2.5D packaging structure and method for preparing 2.5D packaging structure

Abstract

The present invention provides a 2.5D packaging structure and a method for preparing the 2.5D packaging structure, relating to the field of chip packaging technology. The 2.5D packaging structure includes a base assembly wiring layer, a first chip, a coating layer, a second chip, and a plastic encapsulation layer. The base assembly wiring layer is provided with a first solder pad and a second solder pad, and an alignment groove is provided in the middle of the second solder pad; the first chip is attached to the first solder pad; the coating layer covers at least the sidewall of the first chip, and the coating layer partially covers the second solder pad, and is provided with an opening exposing the alignment groove; the second chip is attached to the second solder pad; and the plastic encapsulation layer is provided on the coating layer. Compared with the prior art, the present invention can coat the first chip separately and simultaneously punch a hole exposing the alignment groove, facilitating the alignment and mounting of the second chip with the second solder pad, and allowing the second conductive protrusion of the second chip to engage with the alignment groove to achieve electrical connection. This avoids the negative problems caused by coating multiple chips at the same time.

Description

Technical Field

[0001] The present invention relates to the field of chip packaging technology, and in particular to a 2.5D packaging structure and a method for preparing the 2.5D packaging structure. Background Art

[0002] In the field of chip packaging technology, chiplet technology uses a new design approach to package small chips with different functions together, thus forming a heterogeneous integrated chip packaging structure. As the input / output density of chips increases and the number of chips integrated in a single package increases significantly, 2.5D packaging technology is used as a multi-chip packaging solution to improve its performance through multi-layer wiring layer processes. 2.5D packaging technology usually requires the layout of multiple layers of redistribution layers to connect the functional pads and ground pads on the chip to the outside world.

[0003] Sawfilters are widely used in receiver front-ends, duplexers, and receive filters. Sawfilter chips are typically made of lithium tantalate (LiTaO3) or lithium niobate (LiNbO3). They utilize the piezoelectric properties of piezoelectric materials and input and output transducers to convert radio wave input signals into mechanical energy. After processing, this mechanical energy is converted back into an electrical signal, filtering out unnecessary signals and noise, improving reception quality. To ensure that the functional area of ​​the filter chip is free from contact with any material, a cavity structure is required at the bottom of the filter chip.

[0004] In the prior art, multiple chips are usually flipped and then vacuum-laminated as a whole. Multiple chips are placed in a cavity at the same time. The cavity is too large, and the mutual interference between the chips will be greater. Summary of the Invention

[0005] The object of the present invention is to provide a 2.5D packaging structure and a method for preparing the 2.5D packaging structure, which can realize the individual lamination of sawfilter chips and avoid laminating multiple chips at the same time, thereby effectively reducing the mutual interference between different chips.

[0006] In a first aspect, the present invention provides a 2.5D packaging structure, comprising:

[0007] A substrate assembly wiring layer, wherein a first mounting area and a second mounting area are provided on one side surface of the substrate assembly wiring layer, the second mounting area is located on at least one side of the first mounting area, the first mounting area is provided with a first solder pad, the second mounting area is provided with a second solder pad, and an alignment groove is provided in the middle of the second solder pad;

[0008] A first chip, the first chip is attached to the first mounting area, and a first conductive protrusion is provided on the bottom side of the first chip, and the first conductive protrusion is correspondingly attached to the first pad;

[0009] a covering layer, the covering layer being disposed on a side surface of the base built-up wiring layer and covering at least a side wall of the first chip, so as to form a cavity between the first chip and the surface of the base built-up wiring layer, and the covering layer partially covering the second pad and being provided with an opening exposing the alignment groove;

[0010] a second chip, the second chip being attached to the second mounting area, and a second conductive protrusion being provided on a bottom side of the second chip, the second conductive protrusion being attached to the second pad and passing through the opening to be joined to the alignment groove;

[0011] A plastic sealing layer is provided on the covering layer and covers the first chip and the second chip.

[0012] In an optional embodiment, the first chip includes a filter chip, the coating layer covers the side wall of the filter chip, and the coating layer is flush with the side of the filter chip away from the base combination wiring layer, so that the side of the filter chip away from the base combination wiring layer is exposed to the coating layer.

[0013] In an optional embodiment, the base combined wiring layer includes a multi-layer dielectric layer and a multi-layer wiring layer, the multi-layer wiring layers are stacked in sequence, the multi-layer wiring layers are correspondingly arranged in the multi-layer dielectric layer and are electrically connected to each other, the first solder pad and the second solder pad are arranged on the dielectric layer close to the first chip and are electrically connected to the wiring layer, and a conductive layer is also arranged on the dielectric layer away from the first chip, and the solder balls are correspondingly arranged on the conductive layer.

[0014] In an optional embodiment, the base combined wiring layer includes a transfer intermediary layer, a dielectric layer and a wiring layer, the dielectric layer is arranged on both sides of the transfer intermediary layer, the wiring layer is correspondingly arranged in the dielectric layer, and a conductive through-hole is provided on the transfer intermediary layer, the wiring layers located on both sides of the transfer intermediary layer are electrically connected through the conductive through-holes, the first solder pad and the second solder pad are arranged on the dielectric layer located on the side of the transfer intermediary layer close to the first chip, and are electrically connected to the wiring layer, a conductive layer is also provided on the dielectric layer on the other side of the transfer intermediary layer, and the solder balls are correspondingly arranged on the conductive layer.

[0015] In an optional embodiment, the 2.5D packaging structure also includes an inductor structure, and a third mounting area is further provided on one side surface of the base combined wiring layer. The third mounting area and the second mounting area are respectively located on both sides of the first mounting area, and the coating layer covers the third mounting area. The inductor structure is at least partially located in the third mounting area and is electrically connected to the second chip.

[0016] In an optional embodiment, the inductor structure includes a first metal layer, a second metal layer, a magnetic material layer and a third metal layer, the first metal layer is arranged in the third mounting area and electrically connected to the base combination wiring layer, the coating layer covers the first metal layer, the magnetic material layer is arranged on the coating layer and corresponds to the first metal layer, the second metal layer is arranged on the side of the magnetic material layer away from the coating layer, the third metal layer is arranged on the coating layer and extends to the second mounting area, the second chip is electrically connected to the third metal layer, and the third metal layer is electrically connected to the second metal layer.

[0017] In an optional embodiment, a connecting wire is provided between the second metal layer and the third metal layer located in the third mounting area, and the second metal layer and the third metal layer are electrically connected through the connecting wire.

[0018] In an optional embodiment, the inductor structure further includes a supporting metal layer, which is arranged on the coating layer and corresponds to the first metal layer, and the magnetic material layer is arranged on the supporting metal layer, and the supporting metal layer is electrically isolated from the first metal layer and the second metal layer.

[0019] In an optional embodiment, the thickness of the supporting metal layer is the same as that of the third metal layer, and the magnetic material layer is partially overlapped on the third metal layer.

[0020] In an optional embodiment, the supporting metal layer is distributed in a ring shape on the coating layer, and an insulating layer is further provided on the inner side of the supporting metal layer. A shielding groove is provided on the insulating layer, and a shielding metal layer is formed on the surface of the shielding groove.

[0021] In an optional embodiment, the shielding groove passes through the insulating layer and extends to the covering layer, so that the shielding metal layer covers the insulating layer and the covering layer.

[0022] In an optional embodiment, a first metal column is further provided on one side of the base combination wiring layer, the plastic encapsulation layer is covered on the first metal column, the height of the first metal column relative to the base combination wiring layer is the same as the height of the first chip relative to the base combination wiring layer, and the coating layer covers the side wall of the first metal column.

[0023] In an optional embodiment, a second metal column is further provided on one side of the base combination wiring layer, the plastic encapsulation layer at least partially covers the second metal column, and the height of the second metal column relative to the base combination wiring layer is greater than the height of the first metal column relative to the base combination wiring layer.

[0024] In an optional embodiment, the first metal pillar is disposed on a side of the first chip away from the second chip, and the second metal pillar is disposed on a side of the first metal pillar away from the first chip.

[0025] In an optional embodiment, a height of the second metal column relative to the base built-up wiring layer is the same as a height of the plastic packaging layer relative to the base built-up wiring layer, so that the second metal column is exposed outside the plastic packaging layer.

[0026] In an optional embodiment, a metal shielding layer is further provided on the plastic packaging layer, and the metal shielding layer is connected to the second metal column.

[0027] In a second aspect, the present invention provides a method for preparing a 2.5D package structure, for preparing the 2.5D package structure according to any one of the aforementioned embodiments, the method comprising:

[0028] providing a vehicle;

[0029] forming a base assembly wiring layer on the carrier;

[0030] Disposing a first pad and a second pad in a first mounting area and a second mounting area of ​​the base combined wiring layer respectively;

[0031] Micro-etching a center portion of the second pad to form an alignment groove;

[0032] Mounting a first chip on the first mounting area, wherein a first conductive protrusion is provided on the bottom side of the first chip, and the first conductive protrusion is correspondingly mounted on the first pad;

[0033] A coating layer is formed on the base built-up wiring layer, wherein the coating layer at least covers the sidewall of the first chip to form a cavity between the first chip and the surface of the base built-up wiring layer, and the coating layer covers the second pad.

[0034] Punching a hole on the coating layer at a position corresponding to the alignment groove to form an opening exposing the alignment groove;

[0035] Mounting a second chip on the second mounting area, wherein a second conductive protrusion is provided on the bottom side of the second chip, the second conductive protrusion is correspondingly attached to the second pad, and passes through the opening to be connected to the alignment groove;

[0036] forming a plastic sealing layer on the covering layer, wherein the plastic sealing layer covers the first chip and the second chip;

[0037] The carrier is peeled off, and solder balls are formed on the base assembly wiring layer.

[0038] The beneficial effects of the embodiments of the present invention include:

[0039] The 2.5D packaging structure and preparation method provided by the embodiment of the present invention are characterized by providing a first solder pad in a first mounting area of ​​a base assembly wiring layer, providing a second solder pad in a second mounting area, and providing an alignment groove in the middle of the second solder pad. First, a first chip is mounted on the first solder pad in the first mounting area, and then a film is applied. The film layer can cover the base assembly wiring layer and at least cover the sidewalls of the first chip, thereby forming a cavity on the bottom side of the first chip. The film layer can be punched through the alignment groove to form an opening, so that the alignment groove is exposed, facilitating the mounting of the second chip on the second solder pad to achieve electrical connection, and finally completing the plastic encapsulation. Compared with the prior art, the embodiment of the present invention provides an additionally designed alignment groove, which enables the film layer to laminate the first chip alone while ensuring that the punching forms an opening exposing the alignment groove, facilitating the alignment mounting of the second chip with the second solder pad, and enabling the second conductive protrusion of the second chip to engage with the alignment groove to achieve electrical connection. Therefore, the embodiment of the present invention can avoid laminating multiple chips at the same time, thereby preventing the mold flow of the plastic package from breaking through the film during plastic packaging and causing chip contamination, and can also avoid the problem of delamination between the plastic package and the film. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0041] Figure 1 A schematic diagram of a first 2.5D packaging structure provided by an embodiment of the present invention;

[0042] Figure 2 for Figure 1 A partial enlarged schematic diagram of point II in the middle;

[0043] Figures 3 to 12 A process flow chart of a method for preparing a first 2.5D packaging structure provided by an embodiment of the present invention;

[0044] Figure 13 A schematic diagram of a third 2.5D packaging structure provided by an embodiment of the present invention;

[0045] Figure 14 for Figure 13 A partial enlarged schematic diagram of IV;

[0046] Figure 15 A schematic diagram of a second 2.5D packaging structure provided by an embodiment of the present invention;

[0047] Figure 16 A partial schematic diagram of a third 2.5D packaging structure provided by an embodiment of the present invention;

[0048] Figures 17 to 20 A process flow chart of a method for preparing a third 2.5D packaging structure provided by an embodiment of the present invention;

[0049] Figure 21 A schematic diagram of a fourth 2.5D packaging structure provided by an embodiment of the present invention;

[0050] Figure 22 A schematic diagram of a fifth 2.5D packaging structure provided by an embodiment of the present invention;

[0051] Figure 23 A schematic diagram of the upper plate structure of a fifth 2.5D packaging structure provided by an embodiment of the present invention;

[0052] Figure 24 This is a schematic diagram of a sixth 2.5D packaging structure provided by an embodiment of the present invention.

[0053] Icons: 100-2.5D package structure; 110-substrate combined wiring layer; 111-dielectric layer; 112-wiring layer; 113-transfer interposer; 114-conductive via; 115-conductive layer; 116-solder ball; 120-first chip; 121-first conductive protrusion; 122-first pad; 123-cavity; 130-film layer; 131-opening; 140-second chip; 141-second conductive protrusion; 142-second pad; 143-alignment recess Slot; 150-plastic sealing layer; 160-inductor structure; 161-first metal layer; 162-second metal layer; 163-magnetic material layer; 164-third metal layer; 165-connecting wire; 166-supporting metal layer; 167-insulating layer; 168-shielding metal layer; 169-shielding groove; 170-first metal column; 180-second metal column; 190-metal shielding layer; 200-carrier; 300-substrate; 310-filling rubber layer; 330-enclosure. DETAILED DESCRIPTION

[0054] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0055] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0056] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0057] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the product of the invention is usually placed when in use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be understood as a limitation on the present invention.

[0058] In addition, the terms "first", "second", etc., if used, are merely used to distinguish and describe, and should not be understood as indicating or implying relative importance.

[0059] As disclosed in the background, conventional sawfilter chips are typically connected using a flip-chip process, with vacuum lamination applied to the back of the chip to create a bottom cavity, followed by plastic encapsulation. However, when using a multi-chip structure with a 2.5D package, vacuum laminating a single sawfilter chip can result in the film covering the pads. Research has found that this electrically isolates the pads, preventing the placement of additional chips.

[0060] Furthermore, existing technologies have also adopted a laser grooving process to open the film and expose the pads. However, this method can easily damage the pads, also affecting the electrical connection. Conventional film punching processes, on the other hand, have poor punching results due to the flat surface of the pads, making it difficult to expose the pads.

[0061] Furthermore, with the rapid development of the communications sector, demand for wafer-level RF chip packaging products is also increasing. To meet the requirements of low loss and high integration, existing technologies utilize wiring layers to design inductor structures. These structures have become crucial elements in communication modules such as voltage-controlled oscillators, low-noise amplifiers, mixers, and filters. However, traditional inductor structures are typically formed using wiring layers on the chip surface, which can lead to problems such as poor heat dissipation.

[0062] In order to solve the above problems, embodiments of the present invention provide a novel 2.5D packaging structure and a method for preparing the 2.5D packaging structure. It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict.

[0063] See also Figure 1 and Figure 2 The embodiment of the present invention provides a 2.5D packaging structure 100, which can realize the individual lamination of the sawfilter chip, avoid laminating multiple chips at the same time, thereby preventing the plastic mold flow from breaking through the film during plastic sealing and causing the chip to be contaminated, and at the same time avoid the problem of delamination between the plastic package and the film.

[0064] An embodiment of the present invention provides a 2.5D package structure 100, including a substrate assembly wiring layer 110, a first chip 120, a coating layer 130, a second chip 140, and a plastic encapsulation layer 150. A first mounting area and a second mounting area are provided on one side surface of the substrate assembly wiring layer 110. The second mounting area is located on at least one side of the first mounting area. The first mounting area is provided with a first solder pad 122, and the second mounting area is provided with a second solder pad 142. An alignment groove 143 is provided in the middle of the second solder pad 142. The first chip 120 is attached to the first mounting area, and a first conductive protrusion 121 is provided on the bottom side of the first chip 120. The first conductive protrusion 121 is correspondingly attached to the first solder pad 122. ; The coating layer 130 is arranged on one side surface of the base combined wiring layer 110 and covers at least the side wall of the first chip 120 to form a cavity 123 between the surface of the first chip 120 and the surface of the base combined wiring layer 110, and the coating layer 130 partially covers the second solder pad 142 and is provided with an opening 131 exposing the alignment groove 143; the second chip 140 is attached to the second mounting area, and a second conductive protrusion 141 is provided on the bottom side of the second chip 140, the second conductive protrusion 141 is correspondingly attached to the second solder pad 142, and is connected to the alignment groove 143 through the opening 131; the plastic encapsulation layer 150 is arranged on the coating layer 130 and covers the first chip 120 and the second chip 140.

[0065] It should be noted that during actual packaging, the first chip 120 is first mounted on the first pad 122 in the first mounting area, and then a film is applied. The film layer 130 can cover the base combined wiring layer 110 and at least cover the side wall of the first chip 120, thereby forming a cavity 123 on the bottom side of the first chip 120, and the film layer 130 can be punched through the alignment groove 143 to form an opening 131, so that the alignment groove 143 is exposed, making it convenient to mount the second chip 140 on the second pad 142 to achieve electrical connection, and finally complete the plastic encapsulation. Here, the film layer 130 can be laminated to the first chip 120 alone. After the film layer 130 covers the second pad 142 in the second mounting area, the alignment groove 143 on the second pad 142 can be used to punch a hole 131 structure that exposes the alignment groove 143, thereby avoiding damage to the pad caused by the laser opening 131 action. This also ensures the feasibility of laminating the first chip 120 individually, avoiding laminating multiple chips simultaneously. This prevents the mold flow of the plastic encapsulation body from breaking through the lamination film during plastic encapsulation, thereby preventing chip contamination and delamination between the plastic encapsulation body and the lamination film. Furthermore, the opening 131 enables effective connection between the second conductive protrusion 141 and the second solder pad 142 of the second chip 140, ensuring the reliability of the electrical connection of the second chip 140.

[0066] Furthermore, the first chip 120 includes a filter chip (sawfilter), and the coating layer 130 covers the side wall of the filter chip, and the coating layer 130 is flush with the side of the filter chip away from the base combination wiring layer 110, so that the side of the filter chip away from the base combination wiring layer 110 is exposed to the coating layer 130. Specifically, after the first chip 120 is coated, the coating layer 130 on the back of the first chip 120 can be ground away using a grinding process, and the back of the first chip 120 can be exposed, so that the coating layer 130 only covers the side wall of the first chip 120, thereby forming a cavity 123 using a sealing structure on all sides. At the same time, the cavity 123 is surrounded by the plastic layer 150, and the first chip 120 is in direct contact with the plastic layer 150, which can improve the bonding force between the first chip 120 and the plastic layer 150 and improve the heat dissipation performance of the first chip 120. Moreover, the delamination phenomenon between the coating layer 130 and the molding layer 150 in the traditional coating structure can be avoided. The thickness of the traditional coating layer 130 is 2-500 μm, which is relatively thin. Once the top film layer is broken during molding, it is easy for the molding material to enter the cavity 123, causing the filter chip to be contaminated and affecting its performance.

[0067] In some embodiments, the substrate combined wiring layer 110 includes a multi-layer dielectric layer 111 and a multi-layer wiring layer 112. The multi-layer wiring layers 112 are stacked in sequence. The multi-layer wiring layers 112 are correspondingly arranged in the multi-layer dielectric layer 111 and are electrically connected to each other. The first solder pad 122 and the second solder pad 142 are arranged on the dielectric layer 111 close to the first chip 120 and are electrically connected to the wiring layer 112. A conductive layer 115 is also provided on the dielectric layer 111 away from the first chip 120, and the solder balls 116 are correspondingly provided on the conductive layer 115. Specifically, the process of the multi-layer dielectric layer 111 and the multi-layer wiring layer 112 can realize 2.5D packaging technology and improve performance. In addition, the multi-layer dielectric layer 111 is stacked from bottom to top, and the first solder pad 122 and the second solder pad 142 are both solder pad structures arranged on the top dielectric layer 111 and are electrically in contact with the top wiring layer 112, thereby achieving electrical connection.

[0068] In some embodiments, the second mounting area can be provided on both sides of the first mounting area, that is, there are two second chips 140, and the two second chips 140 are provided on both sides of the first chip 120, thereby realizing a multi-chip package structure. Of course, here, the first chip 120 can be a filter chip, and the second chip 140 can be another chip such as a SOC chip or a radio frequency chip. The specific types of the first chip 120 and the second chip 140 are not specifically limited here.

[0069] An embodiment of the present invention further provides a method for preparing a 2.5D package structure, which is used to prepare the aforementioned 2.5D package structure. The method comprises the following steps:

[0070] S1: Provide a carrier 200.

[0071] Specifically, see Figure 3 First, a carrier 200 is prepared and a liquid adhesive layer is applied using a spin coater. The film is then soft-baked on a hot plate to form a film. The carrier 200 can be made of glass, silicon oxide, or metal, while the adhesive layer can be a material that can be separated by UV light, such as epoxy resin, polyimide, or benzocyclobutene.

[0072] S2 : forming a base build-up wiring layer 110 on the carrier 200 .

[0073] Specifically, see Figure 4 , a multi-layer dielectric layer 111 and a multi-layer dielectric layer 111 can be formed on the carrier 200. First, a photoresist can be coated on the surface thereof using a spin coating process, and a photomask (pattern layer) is again placed over the photoresist layer. An exposure and development process is performed to form an opening in the pattern layer. An electroplating process (sputtering, chemical plating, electroplating, etc.) is then performed to form an electroplated metal layer on the opening in the pattern layer to form the bottom wiring layer 112. A stripping process is then performed again to remove the photoresist layer using acidic / alkaline chemicals, thereby forming the bottom wiring layer 112. Then, a spin coating process (e.g., spin coating, spray coating, printing, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD) is again used to coat the wiring layer 112 with a dielectric material. The dielectric material may be silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, or the like. A photomask (pattern layer) is again placed over the dielectric layer 111, and an exposure and development process is performed to form an opening in the pattern layer. Then, an electroplating process, such as sputtering, electroless plating, electroplating, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or any equivalent process, is again used to form an electroplated metal layer over the opening in the pattern layer to form the wiring layer 112. The preparation of the dielectric layer 111 and the wiring layer 112 is then repeated until all dielectric layers 111 and wiring layers 112 are arranged.

[0074] S3 : Dispose the first pad 122 and the second pad 142 in the first mounting area and the second mounting area of ​​the base built-up wiring layer 110 , respectively.

[0075] Specifically, see Figure 5 , an opening can be formed at a preset position of the top dielectric layer 111 , and a conductive column and a metal layer on the surface of the metal column can be formed by electroplating in the opening, thereby forming the first pad 122 and the second pad 142 .

[0076] S4 : forming an alignment groove 143 by micro-etching in the middle of the second pad 142 .

[0077] Specifically, see Figure 6 The alignment groove 143 can be formed by micro-etching the center area of ​​the second pad 142 using a plasma dry etching process using a mixture of O2 and SF6 plasma gas. The width of the alignment groove 143 can be half the width of the second pad 142.

[0078] S5: Mounting the first chip 120 in the first mounting area.

[0079] See also Figure 7 The bottom side of the first chip 120 is provided with a first conductive protrusion 121, which is correspondingly attached to the first pad 122. Specifically, the first chip 120 can be mounted using a flip-chip process and soldered using a flow soldering process. Here, the first chip 120 is a filter chip.

[0080] S6 : forming a cover layer 130 on the base built-up wiring layer 110 by coating.

[0081] See also Figure 8 , wherein the coating layer 130 at least covers the sidewalls of the first chip 120, so that a cavity 123 is formed between the first chip 120 and the surface of the substrate assembly wiring layer 110, and the coating layer 130 covers the second pad 142. Specifically, during the actual coating, the coating can be performed as a whole, so that the coating layer 130 covers the first mounting area and the second mounting area at the same time, and covers the first chip 120 and the second pad 142, so that a cavity 123 is formed at the bottom of the first chip 120. Then, a grinding process is used to grind the back side of the first chip 120 with a diamond grinding wheel to perform a thinning process, thereby removing the top coating layer 130, so that the coating layer 130 covers the sidewalls of the first chip 120 and exposes the back side of the first chip 120.

[0082] The coating layer 130 may be made of silicon dioxide, silicon nitride, silicon carbide, or the like.

[0083] S7 : Punching holes 131 at positions corresponding to the alignment grooves 143 on the film layer 130 to expose the alignment grooves 143 .

[0084] See also Figure 9 Specifically, a stamping process is used to stamp the position of the alignment groove 143 on the coating layer 130 through a stamping head to form an opening. During the stamping process, the alignment groove 143 can support the coating layer 130 and make way for the stamping head, thereby facilitating the stamping head to pierce the coating layer 130 and form an opening 131.

[0085] S8: Mount the second chip 140 in the second mounting area.

[0086] See also Figure 10 The bottom side of the second chip 140 is provided with a second conductive protrusion 141. The second conductive protrusion 141 is correspondingly attached to the second pad 142 and is connected to the alignment groove 143 through the opening 131. Specifically, the second chip 140 is flip-chip mounted on the second pad 142. The second chip 140 can be a SOC chip or a radio frequency chip.

[0087] S9 : forming a plastic encapsulation layer 150 on the coating layer 130 , and the plastic encapsulation layer 150 covers the first chip 120 and the second chip 140 .

[0088] See also Figure 11 Specifically, the first chip 120 and the second chip 140 are protected by plastic packaging using a plastic packaging process to form a plastic packaging layer 150 .

[0089] S10 : peeling off the carrier 200 and forming solder balls 116 on the base build-up wiring layer 110 .

[0090] See also Figure 12 Specifically, the carrier 200 is removed by irradiating the back side with UV light using a debonding process. A dielectric material is then applied to the surface of the base assembly wiring layer 110 using a spin coating process. Then, holes 131 are opened to expose the bottom wiring layer 112. A conductive layer 115 (i.e., metal pillars and a metal layer) is formed using an electroplating process. Finally, solder balls 116 are formed using a ball placement process. The solder balls 116 can be made of materials such as SnAg or SnAgCu. Finally, a cutting process is performed to form the final product.

[0091] The above method is used to prepare a 2.5D package structure, which is used to define an alignment groove 143 on the second pad 142. This allows the film layer 130 to independently coat the first chip 120 while ensuring that the opening 131 is punched to expose the alignment groove 143. This facilitates the alignment and placement of the second chip 140 on the second pad 142, and allows the second conductive protrusion 141 of the second chip 140 to engage with the alignment groove 143 to achieve electrical connection. Therefore, the embodiment of the present invention can avoid laminating multiple chips at the same time, thereby preventing the mold flow of the plastic encapsulation body from breaking through the film during plastic encapsulation, thereby preventing chip contamination. It also avoids the problem of delamination between the plastic encapsulation body and the film.

[0092] See also Figure 13 and Figure 14In other preferred embodiments of the present invention, the 2.5D package structure further includes an inductor structure 160. A third mounting area is further provided on one side of the substrate assembly wiring layer 110. The third mounting area and the second mounting area are located on either side of the first mounting area, respectively. The cover film layer 130 covers the third mounting area. The inductor structure 160 is at least partially located in the third mounting area and is electrically connected to the second chip 140. Specifically, the inductor structure 160 is at least partially protruded from the substrate assembly wiring layer 110, and avoids the conventional design of flattening the inductor pattern on the chip surface wiring layer. This effectively improves heat dissipation and solves the problem of current generated by parasitic inductance in the conventional inductor structure 160 causing short circuits in the chip wiring layer.

[0093] Furthermore, the inductor structure 160 includes a first metal layer 161, a second metal layer 162, a magnetic material layer 163, and a third metal layer 164. The first metal layer 161 is disposed in the third mounting area and electrically connected to the base combined wiring layer 110. The coating layer 130 covers the first metal layer 161. The magnetic material layer 163 is disposed on the coating layer 130 and corresponds to the first metal layer 161. The second metal layer 162 is disposed on a side of the magnetic material layer 163 away from the coating layer 130. The third metal layer 164 is disposed on the coating layer 130 and extends to the second mounting area. The second chip 140 is electrically connected to the third metal layer 164, and the third metal layer 164 is electrically connected to the second metal layer 162. Specifically, the first metal layer 161 can be prepared and formed simultaneously with the first pad 122 and the second pad 142. The first metal layer 161 covers under the coating layer 130 and can serve as a positive metal layer. The third metal layer 164 can be formed by electroplating on the coating layer 130 to form a negative metal layer, while the second metal layer 162 is designed on the magnetic material layer 163 to serve as the inductor coil layer. The magnetic material layer 163 can significantly increase the magnetic flux, thereby increasing the inductor current intensity, thereby forming the inductor structure 160. The operating principle of the inductor structure 160 can be referred to the relevant records in the prior art.

[0094] It should be noted that the third metal layer 164 here can extend to the second mounting area, thereby forming a wiring structure, and the second conductive protrusion 141 at the bottom of the second chip 140 can contact the third metal layer 164 to form an electrical connection, while the first metal layer 161 is electrically connected to the base assembly wiring layer 110. This makes the second chip 140, the base assembly wiring layer 110, and the first metal layer 161 electrically connected as a whole, achieving an overall electrical connection. The design of the magnetic material layer 163 solves the problem that the traditional inductor structure 160 is designed to be flat on the chip surface circuit layer, resulting in the inductor heat being directly conducted to the chip surface, thereby solving the problems of poor heat dissipation performance in traditional technologies and the current generated by the parasitic inductance causing the chip circuit layer to short-circuit.

[0095] In some embodiments, a connecting wire 165 is provided between the second metal layer 162 and the third metal layer 164 located in the third mounting area, and the second metal layer 162 and the third metal layer 164 are electrically connected via the connecting wire 165. Specifically, the second metal layer 162 and the third metal layer 164 are electrically connected by wire bonding, and the magnetic material can be a neodymium magnet or a samarium cobalt magnet.

[0096] In some embodiments, the inductor structure 160 further includes a support metal layer 166 disposed on the coating layer 130 and corresponding to the first metal layer 161. The magnetic material layer 163 is disposed on the support metal layer 166. The support metal layer 166 is electrically isolated from both the first metal layer 161 and the second metal layer 162. Specifically, the support metal layer 166 is electrically isolated from the first metal layer 161 by the coating layer 130 and is also electrically isolated from the second metal layer 162 by a gap. The support metal layer 166 supports the magnetic material layer 163 and also acts as a heat dissipator, thereby improving heat dissipation.

[0097] In some embodiments, the thickness of the supporting metal layer 166 is the same as that of the third metal layer 164, and the magnetic material layer 163 partially overlaps the third metal layer 164. Specifically, the partial overlap between the magnetic material layer 163 and the third metal layer 164 can reduce the leakage of the magnetic field into the surrounding space, thereby reducing electromagnetic interference with external circuits, reducing eddy current loss and hysteresis loss, and improving the electromagnetic compatibility of the circuit.

[0098] In some embodiments, a first metal pillar 170 is further provided on one side of the base assembly wiring layer 110, and the plastic encapsulation layer 150 is coated on the first metal pillar 170. The height of the first metal pillar 170 relative to the base assembly wiring layer 110 is the same as the height of the first chip 120 relative to the base assembly wiring layer 110, and the coating layer 130 covers the sidewalls of the first metal pillar 170. Specifically, the first metal pillar 170 here can serve as an electrostatic conductive pillar to release static electricity. At the same time, when preparing the first metal pillar 170, a metal pillar can be directly electroplated on the base assembly wiring, and the metal pillar can be a copper pillar, thereby forming a copper pillar on the top wiring layer 112. The height of the first metal pillar 170 is consistent with the mounting height of the first chip 120, so that the first metal pillar 170 is used as a stop pillar during grinding to avoid excessive thinning of the first chip 120. In addition, the first metal pillar 170 here is located between the inductor structure 160 and the first chip 120, which can prevent parasitic currents in the inductor area from interfering with the first chip 120.

[0099] It should be noted that the coating layer 130 here can cover the first metal column 170, and the top coating layer 130 is removed during the subsequent grinding process, so that the coating layer 130 only covers the side wall of the first metal column 170, thereby utilizing the coating layer 130 to achieve the insulation effect of the first metal column 170.

[0100] See also Figure 15 In other preferred embodiments of the present invention, the substrate assembly wiring layer 110 includes a transfer interposer 113, a dielectric layer 111, and a wiring layer 112. The dielectric layer 111 is disposed on both sides of the transfer interposer 113, and the wiring layer 112 is correspondingly disposed within the dielectric layer 111. Conductive vias 114 are provided on the transfer interposer 113, and the wiring layers 112 on both sides of the transfer interposer 113 are electrically connected through the conductive vias 114. The first solder pad 122 and the second solder pad 142 are disposed on the dielectric layer 111 on the side of the transfer interposer 113 near the first chip 120 and are electrically connected to the wiring layer 112. A conductive layer 115 is further disposed on the dielectric layer 111 on the other side of the transfer interposer 113, and solder balls 116 are correspondingly disposed on the conductive layer 115. The transfer interposer 113 may be made of materials such as silicon, germanium, or glass, and the conductive vias 114 may be formed using a TSV or TGV process.

[0101] It should be noted that the inductor structure 160 designed here can be used as an active circuit structure.

[0102] See also Figure 16 In other preferred embodiments of the present invention, the support metal layer 166 can be distributed in an annular shape on the coating layer 130, and an insulating layer 167 is further provided on the inner side of the support metal layer 166. The insulating layer 167 is provided with a shielding groove 169. The surface of the shielding groove 169 is formed with a shielding metal layer 168. The shielding metal layer 168 can form a Faraday cage, thereby better eliminating the induced electric field within the inductor. Furthermore, the shielding groove 169 can penetrate the insulating layer 167 and extend to the coating layer 130, so that the shielding metal layer 168 covers the insulating layer 167 and the coating layer 130. In particular, the shielding groove 169 can extend to the middle of the coating layer 130, thereby increasing its accommodation range and, in turn, increasing the coverage of the shielding metal layer 168, thereby better eliminating the induced electric field within the inductor.

[0103] An embodiment of the present invention further provides a method for preparing a 2.5D package structure, which is used to prepare the aforementioned 2.5D package structure. The basic steps and process means are the same as those of the aforementioned preparation method, and reference may be made to the aforementioned preparation method. The method comprises the following steps:

[0104] S1: Provide a carrier 200.

[0105] S2 : forming a base build-up wiring layer 110 on the carrier 200 .

[0106] S3 : Dispose the first pad 122 and the second pad 142 in the first mounting area and the second mounting area of ​​the base built-up wiring layer 110 , respectively.

[0107] S4 : forming an alignment groove 143 by micro-etching in the middle of the second pad 142 .

[0108] Here, steps S1 to S4 are the same as those of the aforementioned method, and the details can be referred to the aforementioned content. In addition, when executing step S3, the first metal layer 161 can be formed at the same time.

[0109] S5: forming the first metal pillar 170 by electroplating.

[0110] See also Figure 17 Specifically, the first metal pillar 170 can be formed by electroplating at a preset position.

[0111] S6: Mounting the first chip 120 in the first mounting area.

[0112] S7 : forming a cover layer 130 on the base built-up wiring layer 110 by coating.

[0113] Specifically, see Figure 18 During the coating process, the first chip 120 and the first metal pillar 170 can be coated together, and then the coating layer 130 on the top side of the first chip 120 and the top side of the first metal pillar 170 can be removed by grinding. At this time, the first metal pillar 170 can serve as a grinding stop pillar to avoid further thinning of the first chip 120.

[0114] Meanwhile, before grinding, a second metal layer 162 and a supporting metal layer 166 may be formed on the coating layer 130 by electroplating through an electroplating process, and the second metal layer 162 may extend from the third mounting area to the second mounting area.

[0115] S8 : Punching holes 131 at positions corresponding to the alignment grooves 143 on the coating layer 130 to expose the alignment grooves 143 .

[0116] S9: Mount the second chip 140 in the second mounting area.

[0117] Specifically, see Figure 19 The second conductive protrusions 141 on the bottom side of the second chip 140 can be connected to the second pads 142 and the second metal layer 162 accordingly, thereby achieving electrical connection.

[0118] S10: Mounting the magnetic material layer 163 and bonding the wires.

[0119] See also Figure 20Specifically, the third metal layer 164 can be prepared in advance, and then the magnetic material layer 163 with the third metal layer 164 is attached to the supporting metal layer 166, and then the third metal layer 164 is connected to the second metal layer 162 through a wire bonding process.

[0120] S11 : forming a plastic encapsulation layer 150 on the coating layer 130 , and the plastic encapsulation layer 150 covers the first chip 120 and the second chip 140 .

[0121] S12 : peeling off the carrier 200 and forming solder balls 116 on the base build-up wiring layer 110 .

[0122] See also Figure 21 In other preferred embodiments of the present invention, a second metal pillar 180 is further disposed on one side of the base assembly wiring layer 110. The plastic encapsulation layer 150 at least partially covers the second metal pillar 180. The height of the second metal pillar 180 relative to the base assembly wiring layer 110 is greater than the height of the first metal pillar 170 relative to the base assembly wiring layer 110. Specifically, the first metal pillar 170 and the second metal pillar 180 can be fabricated separately, and the second metal pillar 180 is taller. During polishing, the polishing head can avoid the second metal pillar 180 and only focus on the first chip 120 and the first metal pillar 170.

[0123] Furthermore, first metal pillar 170 is disposed on the side of first chip 120 away from second chip 140, and second metal pillar 180 is disposed on the side of first metal pillar 170 away from first chip 120. Specifically, the inductive region is prone to forming electromagnetic standing waves, which in turn generates electron flow. Here, second metal pillar 180 acts as a decelerator for the electron flow, providing static electricity dissipation. First metal pillar 170, in turn, provides static electricity dissipation while preventing vortexes (which are easily generated when electron flow is decelerated by second metal pillar 180 during its motion).

[0124] It should be noted that the first metal pillar 170 and the second metal pillar 180 are spaced apart between the first chip 120 and the inductor structure 160, and the plastic layer 150 is coated on the first metal pillar 170 and the second metal pillar 180. Therefore, the plastic layer 150 can extend into the gap between the first metal pillar 170 and the second metal pillar 180, thereby increasing the plastic contact area and thereby increasing the bonding force of the plastic layer 150, thereby preventing the plastic layer 150 from being delaminated.

[0125] See also Figure 22In some embodiments, the height of the second metal pillars 180 relative to the substrate assembly wiring layer 110 is the same as the height of the plastic layer 150 relative to the substrate assembly wiring layer 110, so that the second metal pillars 180 are exposed outside the plastic layer 150. Specifically, the thickness of the plastic layer 150 can be thinned by secondary grinding, so that the second metal pillars 180 can serve as stop posts for the secondary grinding, preventing the secondary grinding from excessively thinning the plastic layer 150 and exposing the first chip 120.

[0126] See also Figure 23 It should be noted that when the product with this 2.5D package structure is soldered and mounted on the substrate 300, a barrier 330 is typically set up around the mounting area of ​​the substrate 300, and a filler layer 310 is formed around the product. This filler can be coated on the plastic layer 150 and in contact with the second metal pillars 180. The second metal pillars 180 can further improve the heat dissipation of the filler, preventing it from melting due to heat and causing voids in the filler layer, which can damage the bump soldering and affect reliability.

[0127] See also Figure 24 In some embodiments, a metal shielding layer 190 is further provided on the plastic encapsulation layer 150, and the metal shielding layer 190 is connected to the second metal pillar 180. Specifically, the metal shielding layer 190 can be formed by sputtering, and the metal shielding layer 190 can provide electromagnetic shielding and improve heat dissipation.

[0128] In summary, the 2.5D packaging structure and preparation method provided by the embodiment of the present invention are characterized in that a first solder pad 122 is arranged in the first mounting area of ​​the base combined wiring layer 110, and a second solder pad 142 is arranged in the second mounting area. An alignment groove 143 is arranged in the middle of the second solder pad 142. First, the first chip 120 is mounted on the first solder pad 122 in the first mounting area, and then coated. The coating layer 130 can cover the base combined wiring layer 110 and at least cover the side wall of the first chip 120, thereby forming a cavity 123 on the bottom side of the first chip 120, and an opening 131 can be punched on the coating layer 130 through the alignment groove 143, so that the alignment groove 143 is exposed, which facilitates the mounting of the second chip 140 on the second solder pad 142 to achieve electrical connection and finally complete the plastic packaging. Compared to the prior art, the embodiments of the present invention provide an additional alignment groove 143, allowing the film layer 130 to coat the first chip 120 independently while ensuring that the opening 131 is punched to expose the alignment groove 143. This facilitates the alignment and placement of the second chip 140 on the second pad 142, and allows the second conductive protrusion 141 of the second chip 140 to engage with the alignment groove 143 to achieve electrical connection. Therefore, the embodiments of the present invention can avoid laminating multiple chips at the same time, thereby preventing the mold flow of the plastic encapsulation body from breaking through the film during plastic encapsulation, thereby contaminating the chips, and also avoids the problem of delamination between the plastic encapsulation body and the film.

[0129] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A 2.5D packaging structure, characterized in that: include: A substrate assembly wiring layer, wherein a first mounting area and a second mounting area are provided on one surface of the substrate assembly wiring layer, and a solder ball is provided on the other surface of the substrate assembly wiring layer, the second mounting area is located on at least one side of the first mounting area, the first mounting area is provided with a first solder pad, the second mounting area is provided with a second solder pad, and an alignment groove is provided in the middle of the second solder pad; A first chip, the first chip is attached to the first mounting area, and a first conductive protrusion is provided on the bottom side of the first chip, and the first conductive protrusion is correspondingly attached to the first pad; a covering layer, the covering layer being disposed on a side surface of the base built-up wiring layer and covering at least a side wall of the first chip, so as to form a cavity between the first chip and the surface of the base built-up wiring layer, and the covering layer partially covering the second pad and being provided with an opening exposing the alignment groove; a second chip, the second chip being attached to the second mounting area, and a second conductive protrusion being provided on a bottom side of the second chip, the second conductive protrusion being attached to the second pad and passing through the opening to be joined to the alignment groove; A plastic sealing layer is provided on the covering layer and covers the first chip and the second chip.

2. The 2.5D packaging structure according to claim 1, wherein: The first chip includes a filter chip, the covering layer covers the side wall of the filter chip, and the covering layer is flush with the side of the filter chip away from the base combination wiring layer, so that the side of the filter chip away from the base combination wiring layer is exposed to the covering layer.

3. The 2.5D packaging structure according to claim 1, wherein: The base combined wiring layer includes a multi-layer dielectric layer and a multi-layer wiring layer, the multi-layer wiring layers are stacked in sequence, the multi-layer wiring layers are correspondingly arranged in the multi-layer dielectric layer and are electrically connected to each other, the first solder pad and the second solder pad are arranged on the dielectric layer close to the first chip and are electrically connected to the wiring layer, and a conductive layer is also provided on the dielectric layer away from the first chip, and the solder balls are correspondingly arranged on the conductive layer.

4. The 2.5D packaging structure according to claim 1, wherein: The base combined wiring layer includes a transfer interposer, a dielectric layer and a wiring layer. The dielectric layer is arranged on both sides of the transfer interposer, and the wiring layer is correspondingly arranged in the dielectric layer. Conductive through-holes are provided on the transfer interposer. The wiring layers located on both sides of the transfer interposer are electrically connected through the conductive through-holes. The first solder pad and the second solder pad are arranged on the dielectric layer located on the side of the transfer interposer close to the first chip and are electrically connected to the wiring layer. A conductive layer is also provided on the dielectric layer on the other side of the transfer interposer, and the solder balls are correspondingly arranged on the conductive layer.

5. The 2.5D packaging structure according to claim 1, wherein: The 2.5D packaging structure also includes an inductor structure. A third mounting area is further provided on one side surface of the substrate combined wiring layer. The third mounting area and the second mounting area are respectively located on both sides of the first mounting area. The covering layer covers the third mounting area. The inductor structure is at least partially located in the third mounting area and is electrically connected to the second chip.

6. The 2.5D packaging structure according to claim 5, wherein: The inductor structure includes a first metal layer, a second metal layer, a magnetic material layer and a third metal layer. The first metal layer is arranged in the third mounting area and is electrically connected to the base combination wiring layer. The film layer covers the first metal layer. The magnetic material layer is arranged on the film layer and corresponds to the first metal layer. The second metal layer is arranged on a side of the magnetic material layer away from the film layer. The third metal layer is arranged on the film layer and extends to the second mounting area. The second chip is electrically connected to the third metal layer, and the third metal layer is electrically connected to the second metal layer.

7. The 2.5D packaging structure according to claim 6, wherein: A connecting wire is provided between the second metal layer and the third metal layer located in the third mounting area, and the second metal layer and the third metal layer are electrically connected through the connecting wire.

8. The 2.5D packaging structure according to claim 6, wherein: The inductor structure further includes a supporting metal layer, which is arranged on the coating layer and corresponds to the first metal layer. The magnetic material layer is arranged on the supporting metal layer, and the supporting metal layer is electrically isolated from both the first metal layer and the second metal layer.

9. The 2.5D packaging structure according to claim 8, wherein: The thickness of the supporting metal layer is the same as that of the third metal layer, and the magnetic material layer is partially overlapped on the third metal layer.

10. The 2.5D packaging structure according to claim 8, wherein: The supporting metal layer is distributed in a ring shape on the coating layer, and an insulating layer is provided inside the supporting metal layer. A shielding groove is provided on the insulating layer, and a shielding metal layer is formed on the surface of the shielding groove.

11. The 2.5D packaging structure according to claim 10, wherein: The shielding groove penetrates the insulating layer and extends to the covering layer, so that the shielding metal layer covers the insulating layer and the covering layer.

12. The 2.5D packaging structure according to claim 1 or 5, characterized in that: A first metal column is also provided on one side of the base combination wiring layer, the plastic encapsulation layer is covered on the first metal column, the height of the first metal column relative to the base combination wiring layer is the same as the height of the first chip relative to the base combination wiring layer, and the coating layer covers the side wall of the first metal column.

13. The 2.5D packaging structure according to claim 12, wherein: A second metal column is further provided on one side of the base combined wiring layer. The plastic encapsulation layer at least partially covers the second metal column. The height of the second metal column relative to the base combined wiring layer is greater than the height of the first metal column relative to the base combined wiring layer.

14. The 2.5D packaging structure according to claim 13, wherein: The first metal pillar is disposed on a side of the first chip away from the second chip, and the second metal pillar is disposed on a side of the first metal pillar away from the first chip.

15. The 2.5D packaging structure according to claim 13, wherein: The height of the second metal column relative to the base built-up wiring layer is the same as the height of the plastic packaging layer relative to the base built-up wiring layer, so that the second metal column is exposed outside the plastic packaging layer.

16. The 2.5D packaging structure according to claim 15, wherein: A metal shielding layer is further provided on the plastic packaging layer, and the metal shielding layer is connected to the second metal column.

17. A method for preparing a 2.5D packaging structure, for preparing the 2.5D packaging structure according to any one of claims 1 to 16, characterized in that: The method comprises: providing a vehicle; forming a base assembly wiring layer on the carrier; Disposing a first pad and a second pad in a first mounting area and a second mounting area of ​​the base combined wiring layer respectively; Micro-etching a center portion of the second pad to form an alignment groove; Mounting a first chip on the first mounting area, wherein a first conductive protrusion is provided on the bottom side of the first chip, and the first conductive protrusion is correspondingly mounted on the first pad; Laminating the substrate built-up wiring layer to form a covering layer, wherein the covering layer at least covers the sidewall of the first chip so as to form a cavity between the first chip and the surface of the substrate built-up wiring layer, and the covering layer covers the second pad; Punching a hole on the coating layer at a position corresponding to the alignment groove to form an opening exposing the alignment groove; Mounting a second chip on the second mounting area, wherein a second conductive protrusion is provided on the bottom side of the second chip, the second conductive protrusion is correspondingly attached to the second pad, and passes through the opening to be connected to the alignment groove; forming a plastic sealing layer on the covering layer, wherein the plastic sealing layer covers the first chip and the second chip; The carrier is peeled off, and solder balls are formed on the base assembly wiring layer.

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