Power converter with stable output voltage

Abstract

The invention discloses a power converter with stable output voltage. The power converter comprises an upper bridge switch, a lower bridge switch, an error amplifier, a lower bridge feedback circuit, a pulse signal generation circuit, a control circuit and a driving circuit. The lower bridge feedback circuit outputs a blank clock signal according to the voltage signal of the second end of the lower bridge switch, the lower bridge driving signal of the control end of the lower bridge switch and the error amplification signal received from the error amplifier. The pulse signal generating circuit sets the frequency of the clock signal according to the blank clock signal. The control circuit outputs a control signal according to a clock signal. The driving circuit outputs an upper bridge driving signal to the control end of the upper bridge switch and outputs a lower bridge driving signal to the control end of the lower bridge switch according to the control signal.

Description

Technical Field

[0001] The present invention relates to a power converter, and more particularly to a power converter with a stable output voltage. Background Art

[0002] For an electronic device, a power converter is an indispensable device for adjusting power and supplying the adjusted power to the electronic device. The upper bridge switch and the lower bridge switch of the power converter need to be switched according to data such as the voltage or current of the circuit components of the power converter so that the power converter can supply power to the load. However, the traditional control circuit of the power converter fails to effectively control the on-time of the upper bridge switch and the lower bridge switch, resulting in an unstable output voltage when the power converter starts up and an inability to adjust the output voltage to an appropriate voltage value when the input voltage of the power converter is too high. Summary of the Invention

[0003] In view of the deficiencies of the prior art, the present invention provides a power converter with a stable output voltage. The power converter with a stable output voltage of the present invention includes an upper bridge switch, a lower bridge switch, an error amplifier, a lower bridge feedback circuit, a pulse signal generation circuit, a control circuit, and a drive circuit. The first end of the upper bridge switch is coupled to an input voltage. The first end of the lower bridge switch is connected to the second end of the upper bridge switch. The second end of the lower bridge switch is grounded. The node between the first end of the lower bridge switch and the second end of the upper bridge switch is connected to the first end of an inductor. The second end of the inductor is connected to the first end of an output capacitor. The second end of the output capacitor is grounded. The first input terminal of the error amplifier is connected to the first end of the output capacitor. The second input terminal of the error amplifier is coupled to a reference voltage. The lower bridge feedback circuit is connected to the second end and the control end of the lower bridge switch and the output end of the error amplifier. The lower bridge feedback circuit is configured to output a blank clock signal based on the voltage signal at the second end of the lower bridge switch, a lower bridge drive signal at the control end of the lower bridge switch, and an error amplification signal received from the output end of the error amplifier. The pulse signal generation circuit is connected to the lower bridge feedback circuit. The pulse signal generation circuit is configured to set the frequency of the clock signal according to the blank clock signal received from the lower bridge feedback circuit and output the clock signal. The control circuit is connected to the pulse signal generation circuit. The control circuit is configured to output a control signal according to the clock signal received from the pulse signal generation circuit. The drive circuit is connected to the control circuit, the control end of the upper bridge switch, and the control end of the lower bridge switch. The drive circuit is configured to output an upper bridge drive signal to the control end of the upper bridge switch and output a lower bridge drive signal to the control end of the lower bridge switch according to the control signal received from the control circuit.

[0004] As described above, the present invention provides a power converter with a stable output voltage. The switching frequencies of the upper-bridge switch and the lower-bridge switch of the power converter of the present invention can be modulated according to the output voltage of the power converter of the present invention, including automatically reducing the switching frequencies of the upper-bridge switch and the lower-bridge switch when the conduction time of the upper-bridge switch reaches the minimum conduction time, so that the output voltage of the power converter of the present invention is maintained at a stable value.

[0005] To enable a further understanding of the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the provided drawings are only for reference and illustration, and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 It is a circuit diagram of a power converter with a stable output voltage according to a first embodiment of the present invention.

[0007] Figure 2 It is a circuit diagram of a power converter with a stable output voltage according to a second embodiment of the present invention.

[0008] Figure 3 It is a circuit diagram of a first pulse signal generator of a power converter with a stable output voltage according to a third embodiment of the present invention.

[0009] Figure 4 It is a circuit diagram of a second pulse signal generator of a power converter with a stable output voltage according to a third embodiment of the present invention.

[0010] Figure 5 It is a waveform diagram of signals of a power converter with a stable output voltage according to a second embodiment of the present invention.

[0011] Figure 6 It is a waveform diagram of signals of a power converter with a stable output voltage according to a second embodiment of the present invention.

[0012] Figure 7 It is a waveform diagram of signals of a power converter with a stable output voltage according to a second embodiment of the present invention.

[0013] Figure 8 It is a waveform diagram of signals of a power converter with a stable output voltage according to a third embodiment of the present invention.

[0014] Figure 9 It is a waveform diagram of signals of a power converter with a stable output voltage according to a third embodiment of the present invention.

[0015] Figure 10 It is a waveform diagram of signals of a power converter with a stable output voltage according to the first to third embodiments of the present invention and a conventional power converter. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] The following are specific embodiments to illustrate the implementation manners of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments. Various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. Additionally, the drawings of the present invention are only simple schematic illustrations and are not drawn according to actual sizes, which is stated in advance. The following embodiments will further detail the related technical content of the present invention, but the disclosed content is not used to limit the protection scope of the present invention. Additionally, the term "or" used herein should, depending on the actual situation, possibly include any one or a combination of multiple of the associated listed items.

[0017] Please refer to Figure 1 , which is a circuit diagram of a power converter with a stable output voltage according to the first embodiment of the present invention.

[0018] In the first embodiment, the power converter of the present invention includes an upper-bridge switch M1, a lower-bridge switch M2, an error amplifier ERR, a lower-bridge feedback circuit LSFB, a pulse signal generation circuit PS, a control circuit CTR, and a drive circuit DRV.

[0019] The first end of the upper-bridge switch M1 is coupled to an input voltage VIN. The first end of the lower-bridge switch M2 is connected to the second end of the upper-bridge switch M1. The second end of the lower-bridge switch M2 is grounded. A node LX between the first end of the lower-bridge switch M2 and the second end of the upper-bridge switch M1 is connected to the first end of an inductor L. The second end of the inductor L is connected to the first end of an output capacitor Co. The second end of the output capacitor Co is grounded. The first end of the output capacitor Co can also be connected to the first end of the inductor L. The second end of an output resistor RL is grounded.

[0020] The node between the first end of the output capacitor Co and the second end of the inductor L serves as the output end of the power converter of the present invention. The voltage at the first end of the output capacitor Co (the node between it and the second end of the inductor L) serves as the output voltage VOUT of the power converter of the present invention.

[0021] The first input terminal of the error amplifier ERR, for example, the inverting input terminal (as Figure 1 shown through a voltage division circuit DV) is connected to the node between the first end of the output capacitor Co and the second end of the inductor L. The second input terminal of the error amplifier ERR, for example, the non-inverting input terminal, is coupled to a reference voltage VREF.

[0022] The voltage dividing circuit DV may include a first voltage dividing resistor Rd1 and a second voltage dividing resistor Rd2. The first end of the first voltage dividing resistor Rd1 serves as the input end of the voltage dividing circuit DV and is connected to the first end of the output capacitor Co. The first end of the second voltage dividing resistor Rd2 serves as the output end of the voltage dividing circuit DV and is connected to the second end of the first voltage dividing resistor Rd1 and the first input end (such as the inverting input end) of the error amplifier ERR. The second end of the second voltage dividing resistor Rd2 is grounded.

[0023] The lower bridge feedback circuit LSFB is connected to the node between the second end of the lower bridge switch M2 and the ground, and is connected to the control end of the lower bridge switch M2 and the output end of the error amplifier ERR.

[0024] The pulse signal generating circuit PS is connected to the lower bridge feedback circuit LSFB. The control circuit CTR is connected to the pulse signal generating circuit PS. The driving circuit DRV is connected to the control circuit CTR, the control end of the upper bridge switch M1, and the control end of the lower bridge switch M2.

[0025] As Figure 1 shown, a divided voltage generated by dividing the output voltage VOUT of the power converter of the present invention (i.e., the voltage of the node between the first end of the output capacitor Co and the second end of the inductor L) by the voltage dividing circuit DV is transmitted as an output feedback voltage VOUTFB to the first input end (such as the inverting input end) of the error amplifier ERR.

[0026] It should be understood that the voltage dividing circuit DV is not an essential component, and the present invention is not limited thereto. In practice, the voltage dividing circuit DV may also be omitted in the power converter of the present invention. In this case, the output voltage VOUT of the power converter of the present invention is transmitted as an output feedback voltage VOUTFB to the first input end (such as the inverting input end) of the error amplifier ERR.

[0027] The error amplifier ERR multiplies the difference between the output voltage VOUT (a divided voltage thereof) of the power converter of the present invention and a reference voltage VREF by a gain to output an error amplified signal EAO.

[0028] It should be noted that the lower bridge feedback circuit LSFB sets the level of the pulse of a blank clock signal BLCLK according to the voltage signal of the second end of the lower bridge switch M2 received each time, a lower bridge driving signal LG of the control end of the lower bridge switch M2, and an error amplified signal EAO received from the output end of the error amplifier ERR, and further sets the width of the pulse of a blank clock signal BLCLK. The lower bridge feedback circuit LSFB outputs a blank clock signal BLCLK.

[0029] The pulse signal generation circuit PS sets the frequency of the clock signal CLK according to a blank clock signal BLCLK received from the lower bridge feedback circuit LSFB, and outputs the clock signal CLK.

[0030] The control circuit CTR outputs a control signal PWM according to the clock signal CLK received from the pulse signal generation circuit PS (and the error amplification signal EAO received from the output terminal of the error amplifier ERR).

[0031] For example, the control circuit CTR can modulate the pulse width of a pulse width modulation signal according to the clock signal CLK received from the pulse signal generation circuit PS (and the error amplification signal EAO received from the output terminal of the error amplifier ERR), and output this pulse width modulation signal as a control signal PWM.

[0032] The drive circuit DRV outputs an upper bridge drive signal HG to the control terminal of the upper bridge switch M1 and outputs a lower bridge drive signal LG to the control terminal of the lower bridge switch M2 according to the control signal PWM received from the control circuit CTR, so as to drive the upper bridge switch M1 and the lower bridge switch M2.

[0033] Please refer to Figure 2 、 Figure 3 、 Figures 5 to 7 where Figure 2 is the circuit diagram of the power converter with a stable output voltage according to the second embodiment of the present invention, Figure 3 is the circuit diagram of the pulse signal generation circuit and the pulse reference input circuit of the power converter with a stable output voltage according to the second embodiment of the present invention, Figures 5 to 7 is the waveform diagram of the signal of the power converter with a stable output voltage according to the second embodiment of the present invention.

[0034] In addition to including the upper bridge switch M1, the lower bridge switch M2, the error amplifier ERR, the lower bridge feedback circuit LSFB, the pulse signal generation circuit PS, the control circuit CTR and the drive circuit DRV, the power converter of the present invention may also include a pulse reference input circuit INS, a compensation circuit SPS or a combination thereof as shown in Figure 2 shown.

[0035] The same parts of the second embodiment of the present invention as those of the first embodiment will not be described in detail below.

[0036] In the second embodiment, as shown in Figure 2 shown, for example, the lower bridge feedback circuit LSFB may include a lower bridge sensor LSN, a lower bridge comparator CMPLS and a frequency modulation determination circuit LSAT. The pulse signal generation circuit PS may include a first pulse signal generator PU1 and a second pulse signal generator PU2.

[0037] The lower-bridge sensor LSN is connected to the node between the second end of the lower-bridge switch M2 and the ground.

[0038] The lower-bridge comparator CMPLS is a comparator. The first input terminal of the lower-bridge comparator CMPLS, such as the non-inverting input terminal, is connected to the lower-bridge sensor LSN. The second input terminal of the lower-bridge comparator CMPLS, such as the inverting input terminal, is connected to the output terminal of the error amplifier ERR.

[0039] The frequency modulation determination circuit LSAT is connected to the output terminal of the lower-bridge comparator CMPLS, the control terminal of the lower-bridge switch M2, and the first pulse signal generator PU1 of the pulse signal generation circuit PS.

[0040] The frequency modulation determination circuit LSAT may include one or more logic components according to actual application requirements. If the non-inverting input terminal of the lower-bridge comparator CMPLS is used as the first input terminal to connect the lower-bridge sensor LSN, the inverting input terminal of the lower-bridge comparator CMPLS is used as the second input terminal to connect the output terminal of the error amplifier ERR, and the lower-bridge switch M2 uses an n-type metal-oxide-semiconductor field-effect transistor (NMOS) and is turned on by a high-level lower-bridge drive signal LG, the frequency modulation determination circuit LSAT may be as Figure 2 shown including an AND gate LSAND, which is only an example here, and the present invention is not limited thereto.

[0041] The first input terminal of the AND gate LSAND is connected to the output terminal of the lower-bridge comparator CMPLS. The second input terminal of the AND gate LSAND is connected to the control terminal of the lower-bridge switch M2. The output terminal of the AND gate LSAND is connected to the first input terminal of the first pulse signal generator PU1 of the pulse signal generation circuit PS.

[0042] The second input terminal of the first pulse signal generator PU1 of the pulse signal generation circuit PS may be connected to the output terminal of the pulse reference input circuit INS.

[0043] The pulse reference input circuit INS may include a comparator as an input comparator CMIN, and may include an input switching switch Min, a ramp signal generation circuit, and an input logic circuit. The ramp signal generation circuit may include a current source CS and an input capacitor Cin. The input logic circuit may include a flip-flop as an input flip-flop ING (such as but not limited to an SR flip-flop).

[0044] In the ramp signal generation circuit, the current source CS is connected to the first end of the input capacitor Cin. The second end of the input capacitor Cin is grounded. The first input terminal of the input comparator CMIN, such as the non-inverting input terminal, is connected to the first end of the input capacitor Cin of the ramp signal generation circuit. The second input terminal of the input comparator CMIN is connected to an oscillation circuit (not shown in the figure).

[0045] The output terminal of the input comparator CMIN is connected to the second input terminal S of the input flip-flop ING. The first input terminal R of the input flip-flop ING is connected to the output terminal of the second pulse signal generator PU2 of the pulse signal generation circuit PS. The inverted output terminal QB of the input flip-flop ING is connected to the input terminal of the first pulse signal generator PU1 of the pulse signal generation circuit PS.

[0046] The output terminal of the first pulse signal generator PU1 of the pulse signal generation circuit PS is connected to the input terminal of the second pulse signal generator PU2 of the pulse signal generation circuit PS and the control terminal of the input switch Min.

[0047] The first terminal of the input switch Min is connected to the first terminal of the input capacitor Cin and the first input terminal of the input comparator CMIN. The second terminal of the input switch Min is grounded.

[0048] The control circuit CTR may include a comparison circuit CMPC and a control logic circuit, wherein the comparison circuit CMPC may include a comparator as an upper-bridge comparator CMPHS, and the control logic circuit includes a flip-flop as a control flip-flop CTLG.

[0049] The input terminal of the upper-bridge sensor HSN is connected to the first terminal (and the second terminal) of the upper-bridge switch M1. The first input terminal, such as the non-inverting input terminal, of the upper-bridge comparator CMPHS of the control circuit CTR is connected to the output terminal of the upper-bridge sensor HSN.

[0050] The second input terminal, such as the inverting input terminal, of the upper-bridge comparator CMPHS of the control circuit CTR is connected to the output terminal of the error amplifier ERR.

[0051] The compensation circuit SPS may be connected to the node between the output terminal of the error amplifier ERR and the second input terminal, such as the inverting input terminal, of the upper-bridge comparator CMPHS of the control circuit CTR.

[0052] The first input terminal R of a control flip-flop CTLG of the control circuit CTR is connected to the output terminal of the upper-bridge comparator CMPHS. The second input terminal S of the control flip-flop CTLG of the control circuit CTR is connected to the output terminal of the second pulse signal generator PU2 of the pulse signal generation circuit PS. The output terminal Q of the control flip-flop CTLG of the control circuit CTR is connected to the input terminal of the drive circuit DRV.

[0053] The drive circuit DRV outputs an upper-bridge drive signal HG to the control terminal of the upper-bridge switch M1 to drive the upper-bridge switch M1, and the drive circuit DRV outputs a lower-bridge drive signal LG to the control terminal of the lower-bridge switch M2 to drive the lower-bridge switch M2.

[0054] The upper bridge sensor HSN senses the current at the first end of the upper bridge switch M1, and converts the sensed current at the first end of the upper bridge switch M1 into a voltage to output an upper bridge sensing voltage signal.

[0055] The error amplifier ERR uses a divided voltage of the output voltage VOUT of the power converter of the present invention as an output feedback voltage VOUTFB, multiplies the difference between this output feedback voltage VOUTFB and a reference voltage VREF by a gain to output an error amplified signal EAO.

[0056] If necessary, the compensation circuit SPS can compensate an error amplified signal EAO output from the output end of the error amplifier ERR, and output the compensated error amplified signal EAO to the second input end, such as the inverting input end, of the upper bridge comparator CMPHS of the control circuit CTR.

[0057] The first input end, such as the non-inverting input end, of the upper bridge comparator CMPHS of the control circuit CTR receives an upper bridge sensing voltage signal VCSHS from the output end of the upper bridge sensor HSN. The second input end, such as the inverting input end, of the upper bridge comparator CMPHS receives an error amplified signal EAO from the output end of the error amplifier ERR or from the compensation circuit SPS.

[0058] The upper bridge comparator CMPHS compares the voltage of an upper bridge sensing voltage signal VCSHS with the voltage of an error amplified signal EAO to output an upper bridge comparison signal.

[0059] The lower bridge sensor LSN senses the current at the second end of the lower bridge switch M2, converts the sensed current at the second end of the lower bridge switch M2 into a voltage to output a lower side sensing voltage signal VCSLS. The first input end, such as the non-inverting input end, of the lower bridge comparator CMPLS receives a lower side sensing voltage signal VCSLS from the lower bridge sensor LSN, and the second input end, such as the inverting input end, of the lower bridge comparator CMPLS receives an error amplified signal EAO from the output end of the error amplifier ERR.

[0060] The lower bridge comparator CMPLS compares the voltage of a lower side sensing voltage signal VCSLS with the voltage of an error amplified signal EAO to output a lower bridge comparison signal.

[0061] The frequency modulation determination circuit LSAT (AND gate LSAND therein) outputs a blank clock signal BLCLK based on a lower bridge comparison signal received from the output end of the lower bridge comparator CMPLS and a lower bridge drive signal LG received from the control end of the lower bridge switch M2 (or the output end of the drive circuit DRV).

[0062] When a lower-bridge comparison signal received at the first input terminal of the AND gate LSAND in the frequency modulation decision circuit LSAT is at a high level, and a lower-bridge drive signal LG received at the second input terminal of the AND gate LSAND is at a high level to turn on the lower-bridge switch M2, the AND gate LSAND outputs a blank clock signal BLCLK at a high level.

[0063] On the other hand, in the pulse reference input circuit INS, a current source CS supplies an input current to an input capacitor Cin to charge the input capacitor Cin. The voltage signal of the input capacitor Cin is transmitted as a ramp signal VRAMP to the first input terminal, such as the non-inverting input terminal, of an input comparator CMIN. The second input terminal, such as the inverting input terminal, of the input comparator CMIN receives an oscillation signal VTHOSC from an oscillation circuit.

[0064] The input comparator CMIN compares the voltage of a received ramp signal VRAMP with the voltage of an oscillation signal VTHOSC to output an input comparison signal.

[0065] The input flip-flop ING in the pulse reference input circuit INS outputs a pulse reference input signal INSS based on an input comparison signal received from the output terminal of an input comparator CMIN and a clock signal CLK received from the second pulse signal generator PU2 of the pulse signal generation circuit PS.

[0066] As Figure 5 shown, during the charging process of the input capacitor Cin, a voltage signal of the input capacitor Cin gradually rises as a ramp signal VRAMP. When the voltage of the ramp signal VRAMP rises to be equal to or higher than the voltage of an oscillation signal VTHOSC, an input comparator CMIN in the pulse reference input circuit INS outputs an input comparison signal at a high level, causing an input inverted logic signal QBS output from an inverted output terminal QB of an input flip-flop ING to transition from a high level to a low level.

[0067] Each time an input inverted logic signal QBS received by the first pulse signal generator PU1 of the pulse signal generation circuit PS from an input flip-flop ING Figure 5 shown transitions from a high level to a low level, the first pulse signal generator PU1 in the pulse signal generation circuit PS generates a pulse in an input switch switching signal DICH output to the control terminal of an input switching switch Min.

[0068] After each completion of the charging of the input capacitor Cin, the first pulse signal generator PU1 of the pulse signal generation circuit PS can output an input switch switching signal DICH at a high level to the control terminal of an input switching switch Min to turn on the input switching switch Min to discharge an input capacitor Cin.

[0069] The first pulse signal generator PU1 of the pulse signal generation circuit PS outputs a first pulse signal PU1SOT based on a pulse reference input signal INSS received from the input flip-flop ING of the pulse reference input circuit INS and a blank clock signal BLCLK received from the AND gate LSAND of the frequency modulation determination circuit LSAT ().

[0070] The second pulse signal generator PU2 of the pulse signal generation circuit PS outputs a clock signal CLK to the second input terminal S of a control flip-flop CTLG of the control circuit CTR based on the first pulse signal PU1SOT received from the first pulse signal generator PU1.

[0071] As Figure 5 shown, each time after an input capacitor Cin is discharged, the second pulse signal generator PU2 of the pulse signal generation circuit PS can output a pulse reset signal to the first input terminal R of an input flip-flop ING (such as but not limited to an SR flip-flop) to reset the input flip-flop ING.

[0072] At the time point of an input switch switching signal DICH (i.e., the end time point of the discharge of an input capacitor Cin), the second pulse signal generator PU2 of the pulse signal generation circuit PS changes a clock signal CLK from a low level state to a high level state, and from this time point, the next pulse starts to be generated in a clock signal CLK. At this time, the frequency of the pulse of the clock signal CLK is calculated by the following equation:

[0073] Feq = I1 / [Cin × (Vosc)];

[0074] Where Feq represents the frequency of the pulse of the clock signal CLK, I1 represents the input current supplied by the current source CS, Cin represents an input capacitor Cin, and Vosc represents the voltage of an oscillation signal VTHOSC.

[0075] A control flip-flop CTLG of the control circuit CTR outputs a control signal PWM based on an upper bridge comparison signal received from the output terminal of the upper bridge comparator CMPHS and a clock signal CLK received from the second pulse signal generator PU2 of the pulse signal generation circuit PS.

[0076] The drive circuit DRV outputs an upper bridge drive signal HG to the control terminal of the upper bridge switch M1 and outputs a lower bridge drive signal LG to the control terminal of the lower bridge switch M2 based on the control signal PWM received from the control circuit CTR.

[0077] In a conduction time signal TON as Figure 6 shown (this is as Figure 2A signal at a node LX between the first end of the lower bridge switch M2 and the second end of the upper bridge switch M1 shown, or practically the upper bridge drive signal of the upper bridge switch M1), during the working cycle of Figure 2 shown, the drive circuit DRV turns on the upper bridge switch M1 and turns off the lower bridge switch M2 at the same time. Conversely, during the non - working cycle of a conduction time signal TON as shown in Figure 6 shown, the drive circuit DRV turns off the upper bridge switch M1 and turns on the lower bridge switch M2 at the same time. Figure 2 shown, the drive circuit DRV turns off the upper bridge switch M1 and turns on the lower bridge switch M2 at the same time.

[0078] As Figure 6 shown, whenever the lower bridge switch M2 turns on during the non - working cycle of a conduction time signal TON and the voltage of the voltage signal at the second end of the lower bridge switch M2 is higher than the voltage of the error amplification signal EAO, the output terminal of the frequency modulation decision circuit LSAT (AND gate LSAND) of the lower bridge feedback circuit LSFB outputs a high - level blank clock signal BLCLK.

[0079] When the working cycle of the conduction time signal TON is greater than a minimum conduction time of the upper bridge switch M1, there is no need to reduce the switching frequency FSW of the upper bridge switch M1 and the lower bridge switch M2. At this time, as Figure 6 shown, the clock signal CLK is a fixed - frequency signal, and the frequency of each of the multiple pulses of the clock signal CLK is fixed at a default reference frequency.

[0080] As Figure 6 and Figure 7 shown, when the input voltage VIN gradually rises, the working cycle of the conduction time signal TON gradually shortens. When the working cycle of the conduction time signal TON shortens to be equal to a minimum conduction time, an error amplification signal EAO output by the error amplifier ERR gradually decreases. As a result, the width of the pulses generated later among the multiple pulses of a blank clock signal BLCLK output by the frequency modulation decision circuit LSAT (AND gate LSAND) of the lower bridge feedback circuit LSFB becomes larger.

[0081] When the lower bridge switch M2 turns on and the voltage of the voltage signal at the second end of the lower bridge switch M2 is higher than the voltage of the error amplification signal EAO, the frequency modulation decision circuit LSAT (AND gate LSAND) of the lower bridge feedback circuit LSFB outputs a high - level blank clock signal BLCLK. Conversely, when the lower bridge switch M2 turns off or the voltage of the voltage signal at the second end of the lower bridge switch M2 is not higher than the voltage of the error amplification signal EAO, the frequency modulation decision circuit LSAT (AND gate LSAND) of the lower bridge feedback circuit LSFB outputs a low - level blank clock signal BLCLK.

[0082] When the time point at which the pulse of the clock signal CLK is default generated falls within a time interval during which the blank clock signal BLCLK is at a high level, the pulse signal generation circuit PS delays the generation of the pulse of the clock signal CLK to reduce the frequency of the pulse in the clock signal CLK, thereby reducing the switching frequency FSW of the upper bridge switch M1 and the lower bridge switch M2.

[0083] As Figure 6 and Figure 7 shown, when the input voltage VIN coupled to the first end of the upper bridge switch M1 of the output voltage VOUT of the power converter of the present invention gradually rises and the duty cycle of the conduction time signal TON of the power converter of the present invention (i.e., the conduction time of the upper bridge switch M1) is shortened to be equal to a minimum conduction time of the upper bridge switch M1 of the power converter of the present invention, the switching frequency FSW of the upper bridge switch M1 and the lower bridge switch M2 linearly decreases, so that the output voltage VOUT of the power converter of the present invention is maintained at a constant voltage value without overvoltage occurring.

[0084] Please refer to Figure 3 , Figure 4 , Figure 8 and Figure 9 , where Figure 3 is the circuit diagram of the first pulse signal generator of the power converter with a stable output voltage according to the third embodiment of the present invention, Figure 4 is the circuit diagram of the second pulse signal generator of the power converter with a stable output voltage according to the third embodiment of the present invention, Figure 8 and Figure 9 are the waveform diagrams of the signals of the power converter with a stable output voltage according to the third embodiment of the present invention.

[0085] For example, as Figure 2 shown, the first pulse signal generator PU1 of the pulse signal generation circuit PS may include a first transistor T1, a first resistor R1, a second transistor T2, a third transistor T3, a first Schmitt Trigger SHT1, a first NOR gate NOR1, a second NOR gate NOR2, a first NOT gate NOT1, and a first capacitor Cp1 as Figure 3 shown.

[0086] As Figure 3 shown, the first end of the first transistor T1 is coupled to a common voltage VCC. The second end of the first transistor T1 is connected to the first end of the first resistor R1. The second end of the first resistor R1 is connected to the first end of the second transistor T2. The second end of the second transistor T2 is grounded.

[0087] The control terminals of the first transistor T1 and the second transistor T2 are connected to the output terminal Q of an input flip-flop ING of a pulse reference input circuit INS, so as to receive a pulse reference input signal INSS from the output terminal Q of the input flip-flop ING of the pulse reference input circuit INS.

[0088] The first terminal of the third transistor T3 is coupled to a common voltage VCC.

[0089] The input terminal of the first Schmitt trigger SHT1 is connected to a node NE1 between the first terminal of the second transistor T2 and the second terminal of the first resistor R1, and is also connected to the second terminal of the third transistor T3 and the first terminal of the first capacitor Cp1. The second terminal of the first capacitor Cp1 is grounded.

[0090] The first input terminal of the first NOR gate NOR1 is connected to the output terminal of the first Schmitt trigger SHT1. The second input terminal of the first NOR gate NOR1 is connected to the output terminal Q of an input flip-flop ING of a pulse reference input circuit INS, so as to receive a pulse reference input signal INSS from the pulse reference input circuit INS. The third input terminal of the first NOR gate NOR1 is connected to a frequency modulation decision circuit LSAT (AND gate LSAND) of a lower bridge feedback circuit LSFB, so as to receive a blank clock signal BLCLK from the frequency modulation decision circuit LSAT (AND gate LSAND).

[0091] The first input terminal of the second NOR gate NOR2 is connected to the output terminal of the first NOR gate NOR1. The second input terminal of the second NOR gate NOR2 is connected to the output terminal Q of an input flip-flop ING of a pulse reference input circuit INS, so as to receive a pulse reference input signal INSS from the pulse reference input circuit INS. The output terminal of the second NOR gate NOR2 is connected to the input terminal of a second pulse signal generator PU2 of a pulse signal generation circuit PS.

[0092] The input terminal of the first NOT gate NOT1 is connected to the output terminal of the first NOR gate NOR1. The output terminal of the first NOT gate NOT1 is connected to the control terminal of the third transistor T3.

[0093] For example, as Figure 2 shown, the second pulse signal generator PU2 of the pulse signal generation circuit PS may include a fourth transistor T4, a second resistor R2, a fifth transistor T5, a sixth transistor T6, a second Schmitt trigger SHT2, a third NOR gate NOR3, a fourth NOR gate NOR4, a second NOT gate NOT2, and a second capacitor Cp2 as Figure 4 shown.

[0094] As Figure 4 shown, the first terminal of the fourth transistor T4 is coupled to the common voltage VCC. As Figure 4The control terminal of the fourth transistor T4 shown is connected as Figure 3 to the output terminal of the second NOR gate NOR2 of the first pulse signal generator PU1 shown.

[0095] The second terminal of the fourth transistor T4 is connected to the first terminal of the second resistor R2. The second terminal of the second resistor R2 is connected to the first terminal of the fifth transistor T5. The control terminal of the fifth transistor T5 is connected as Figure 3 to the output terminal of the second NOR gate NOR2 of the first pulse signal generator PU1 shown. The second terminal of the fifth transistor T5 is grounded.

[0096] The first terminal of the sixth transistor T6 is coupled to the common voltage VCC.

[0097] The input terminal of the second Schmidt trigger SHT2 is connected to the node NE2 between the first terminal of the fifth transistor T5 and the second terminal of the second resistor R2 (the second voltage signal NES2 of this node NE2 changes as Figure 7 or Figure 8 shown), and is connected to the second terminal of the sixth transistor T6 and the first terminal of the second capacitor Cp2. The second terminal of the second capacitor Cp2 is grounded.

[0098] The first input terminal of the third NOR gate NOR3 is connected to the output terminal of the second Schmidt trigger SHT2. The second input terminal of the third NOR gate NOR3 is connected as Figure 3 to the output terminal of the second NOR gate NOR2 of the first pulse signal generator PU1 shown.

[0099] The first input terminal of the fourth NOR gate NOR4 is connected to the output terminal of the third NOR gate NOR3. The second input terminal of the fourth NOR gate NOR4 is connected as Figure 3 to the output terminal of the second NOR gate NOR2 of the first pulse signal generator PU1 shown. The output terminal of the fourth NOR gate NOR4 is connected to the second input terminal S of a control flip-flop CTLG of the control circuit CTR.

[0100] The input terminal of the second NOT gate NOT2 is connected to the output terminal of the third NOR gate NOR3. The output terminal of the second NOT gate NOT2 is connected to the control terminal of the sixth transistor T6.

[0101] As Figure 8 shown, when a pulse reference input signal INSS changes from a high level to a low level, since a first voltage signal NES1 of the node NE1 between the first terminal of the second transistor T2 and the second terminal of the first resistor R1 is at a low level, the first Schmidt trigger SHT1 outputs a first Schmidt trigger signal at a high level.

[0102] Next, when the first input terminal of the first NOR gate NOR1 receives a first Schmitt trigger signal with a high level from the output terminal of the first Schmitt trigger SHT1, the second input terminal of the first NOR gate NOR1 receives a pulse reference input signal INSS with a low level, and the third input terminal of the first NOR gate NOR1 receives a blank clock signal BLCLK with a low level, the output terminal of the first NOR gate NOR1 outputs a first NOR gate signal with a low level.

[0103] Next, when the first input terminal of the second NOR gate NOR2 receives the first NOR gate signal with a low level from the output terminal of the first NOR gate NOR1 and the second input terminal of the second NOR gate NOR2 receives a pulse reference input signal INSS with a low level from a pulse reference input circuit INS, the output terminal of the second NOR gate NOR2 outputs a first pulse signal PU1SOT with a high level.

[0104] Next, when the voltage of the first voltage signal NES1 is higher than a Schmitt voltage threshold SMTH of the first Schmitt trigger SHT1, a first NOR gate signal output by the output terminal of the first NOR gate NOR1 transitions from a low level to a high level, and a first pulse signal PU1SOT output by the output terminal of the second NOR gate NOR2 transitions from a high level to a low level.

[0105] Or, as Figure 9 shown, when the first input terminal of the first NOR gate NOR1 receives a first Schmitt trigger signal with a low level from the output terminal of the first Schmitt trigger SHT1, the second input terminal of the first NOR gate NOR1 receives a pulse reference input signal INSS with a low level, and the third input terminal of the first NOR gate NOR1 receives a blank clock signal BLCLK with a high level, the output terminal of the first NOR gate NOR1 outputs a first NOR gate signal with a low level.

[0106] Until when the first input terminal of the first NOR gate NOR1 receives a first Schmitt trigger signal with a low level from the output terminal of the first Schmitt trigger SHT1, the second input terminal of the first NOR gate NOR1 receives a pulse reference input signal INSS with a low level, and the third input terminal of the first NOR gate NOR1 receives a blank clock signal BLCLK that transitions from a high level to a low level, a first pulse signal PU1SOT output by the output terminal of the second NOR gate NOR2 transitions from a high level to a low level. Accordingly, the pulse width of a first pulse signal PU1SOT output by the output terminal of the second NOR gate NOR2 is controlled by a blank clock signal BLCLK, thereby controlling the pulse width of a clock signal CLK output by the second pulse signal generator PU2 to the control circuit CTR.

[0107] Please refer to Figure 10, which is a waveform diagram of signals of the power converter with a stable output voltage and a conventional power converter according to the first to third embodiments of the present invention.

[0108] In the startup condition of the conventional power converter, even with the assistance of a soft start circuit to switch the upper bridge switch and the lower bridge switch, since the initial output voltage of the conventional power converter at startup is zero, the duty cycle of the upper bridge drive signal of the upper bridge switch is a low duty cycle, and the frequency reduction operation is not performed at this time.

[0109] When the conduction time of the upper bridge switch of the conventional power converter is the minimum conduction time, the conventional power converter, such as Figure 10 a normal switching frequency marking line CU30 maintains switching the upper bridge switch and the lower bridge switch at a fixed frequency. As a result, the output voltage VOUT of the conventional power converter will have an overvoltage event at the startup output voltage VOUT, such as Figure 10 an output voltage curve CU10 shown, and the output current IL of the conventional power converter will have an overcurrent event at startup, such as Figure 10 an output current curve CU20 shown.

[0110] When the output voltage VOUT of the conventional power converter has an overvoltage, the switching frequency FSW of the conventional power converter, such as Figure 10 a switching frequency curve CU31 shown, jumps in frequency. At this time, the output voltage VOUT of the conventional power converter is unstable, such as Figure 10 an output voltage curve CU11 shown, and the output current IL is unstable, such as Figure 10 an output current curve CU21 shown.

[0111] When the power converter of the present invention starts up, as the duty cycle of the upper bridge drive signal of the upper bridge switch increases, the switching frequency FSW of the power converter of the present invention, such as Figure 10 a switching frequency curve CU32 shown, linearly changes, so that the output voltage VOUT at startup of the power converter of the present invention, such as Figure 10 an output voltage curve CU12 shown, will not have an overvoltage event, and the output current IL at startup of the power converter of the present invention, such as Figure 10 an output current curve CU22 shown, is stable.

[0112] In summary, the present invention provides a power converter with a stable output voltage. The switching frequencies of the upper bridge switch and the lower bridge switch of the power converter of the present invention can be modulated according to the output voltage of the power converter of the present invention, including automatically reducing the switching frequencies of the upper bridge switch and the lower bridge switch when the conduction time of the upper bridge switch reaches the minimum conduction time, so that the output voltage of the power converter of the present invention is maintained at a stable value.

[0113] The above-disclosed content is only the preferred and feasible embodiment of the present invention, and does not limit the claims of the present invention. Therefore, all equivalent technical changes made by using the content of the specification and drawings of the present invention are included in the claims of the present invention.

Claims

1. A power converter with a stable output voltage, characterized in that, The power converter with a stable output voltage includes: An upper bridge switch, the first end of the upper bridge switch is coupled to an input voltage; A lower bridge switch, the first end of the lower bridge switch is connected to the second end of the upper bridge switch, the second end of the lower bridge switch is grounded, and a node between the first end of the lower bridge switch and the second end of the upper bridge switch is connected to the first end of an inductor, and the second end of the inductor is connected to the first end of an output capacitor, and the second end of the output capacitor is grounded; An error amplifier, the first input terminal of the error amplifier is connected to the first end of the output capacitor, and the second input terminal of the error amplifier is coupled to a reference voltage; A lower bridge feedback circuit, connected to the second end and the control terminal of the lower bridge switch and the output terminal of the error amplifier, configured to output a blank clock signal according to a voltage signal at the second end of the lower bridge switch, a lower bridge drive signal at the control terminal of the lower bridge switch, and an error amplification signal received from the output terminal of the error amplifier; A pulse signal generation circuit, connected to the lower bridge feedback circuit, configured to set the frequency of a clock signal according to the blank clock signal received from the lower bridge feedback circuit and output the clock signal; A control circuit, connected to the pulse signal generation circuit, configured to output a control signal according to the clock signal received from the pulse signal generation circuit; And A drive circuit, connected to the control circuit, the control terminal of the upper bridge switch, and the control terminal of the lower bridge switch, configured to output an upper bridge drive signal to the control terminal of the upper bridge switch and output the lower bridge drive signal to the control terminal of the lower bridge switch according to the control signal received from the control circuit.

2. The power converter with a stable output voltage according to claim 1, wherein The power converter with a stable output voltage further includes: A voltage dividing circuit, the input terminal of the voltage dividing circuit is connected to the first end of the output capacitor, and the output terminal of the voltage dividing circuit is connected to the first input terminal of the error amplifier, and the voltage dividing circuit divides the output voltage at the first end of the output capacitor to output a divided voltage to the first input terminal of the error amplifier.

3. The power converter with a stable output voltage according to claim 2, characterized in that, The voltage dividing circuit includes: A first voltage dividing resistor, the first end of the first voltage dividing resistor is connected to the first end of the output capacitor; and A second voltage dividing resistor, the first end of the second voltage dividing resistor is connected to the second end of the first voltage dividing resistor and the first input terminal of the error amplifier, and the second end of the second voltage dividing resistor is grounded.

4. The power converter with a stable output voltage according to claim 1, characterized in that, The lower bridge feedback circuit includes: A lower bridge sensor, connected to the second end of the lower bridge switch, configured to sense a current at the second end of the lower bridge switch, convert the sensed current at the second end of the lower bridge switch into a voltage and output a lower side sensed voltage signal; A lower bridge comparator, the first input terminal of the lower bridge comparator is connected to the lower bridge sensor, the second input terminal of the lower bridge comparator is connected to the output terminal of the error amplifier, and the lower bridge comparator compares the voltage of the lower side sensed voltage signal with the voltage of the error amplification signal to output a lower bridge comparison signal; And A frequency modulation determination circuit is connected to the output terminal of the lower bridge comparator, the control terminal of the lower bridge switch, and the pulse signal generation circuit, and is configured to output the blank clock signal to the pulse signal generation circuit according to the lower bridge comparison signal and the lower bridge drive signal at the control terminal of the lower bridge switch.

5. The power converter with a stable output voltage according to claim 4, wherein Whenever the lower bridge switch is turned on and the voltage converted from the current at the second terminal of the lower bridge switch is higher than the voltage of the error amplification signal, the lower bridge feedback circuit outputs the blank clock signal at a high level; Wherein, when the time point at which the pulse of the clock signal is generated falls within a time interval in which the blank clock signal is at a high level, the pulse signal generation circuit reduces the frequency of the clock signal.

6. The power converter with a stable output voltage according to claim 5, characterized in that, The frequency modulation determination circuit includes an AND gate, a first input terminal of the AND gate is connected to the output terminal of the lower bridge comparator, a second input terminal of the AND gate is connected to the control terminal of the lower bridge switch, and an output terminal of the AND gate is connected to an input terminal of the pulse signal generation circuit.

7. The power converter with a stable output voltage according to claim 1, wherein The power converter with a stable output voltage further includes: An upper bridge sensor, the upper bridge sensor is connected to the first terminal of the upper bridge switch and the control circuit, the upper bridge sensor senses a current at the first terminal of the upper bridge switch and converts the current into a voltage to output an upper bridge sensing voltage signal, and the control circuit controls the drive circuit according to the upper bridge sensing voltage signal received from the upper bridge sensor.

8. The power converter with a stable output voltage according to claim 7, wherein The control circuit includes: An upper bridge comparator, a first input terminal of the upper bridge comparator is connected to the output terminal of the upper bridge sensor, and a second input terminal of the upper bridge comparator is connected to the output terminal of the error amplifier; And A control logic circuit, connected to the output terminal of the upper bridge comparator, the output terminal of the pulse signal generation circuit, and the input terminal of the drive circuit, and configured to control the drive circuit according to an upper bridge comparison signal received from the output terminal of the upper bridge comparator and the clock signal received from the pulse signal generation circuit.

9. The power converter with a stable output voltage according to claim 8, characterized in that, The control logic circuit includes a flip-flop as a control flip-flop, a first input terminal of the control flip-flop is connected to the output terminal of the upper bridge comparator, a second input terminal of the control flip-flop is connected to the output terminal of the pulse signal generation circuit, and an output terminal of the control flip-flop is connected to the input terminal of the drive circuit.

10. The power converter with a stable output voltage according to claim 1, characterized in that, The power converter with a stable output voltage further includes: a pulse reference input circuit, and the pulse reference input circuit includes: An input comparator, a first input terminal of the input comparator receives a ramp signal from a ramp signal generation circuit, a second input terminal of the input comparator receives an oscillation signal from an oscillation circuit, an output terminal of the input comparator is connected to the pulse signal generation circuit, and the input comparator compares the voltage of the ramp signal with the voltage of the oscillation signal to output an input comparison signal; Wherein the pulse signal generation circuit sets the frequency of the clock signal according to the input comparison signal received from the output terminal of the input comparator.

11. The power converter with a stable output voltage according to claim 10, wherein, The ramp signal generation circuit includes: A current source configured to supply an input current; and An input capacitor, a first end of the input capacitor is connected to the current source and a first input terminal of the input comparator, a voltage signal at the first end of the input capacitor serves as the ramp signal, a second end of the input capacitor is grounded, and the input current supplied by the current source flows through the input capacitor.

12. The power converter with a stable output voltage according to claim 11, wherein The pulse reference input circuit further includes: An input logic circuit connected to an output terminal of the input comparator and the pulse signal generation circuit, configured to output a pulse reference input signal according to the input comparison signal received from the input comparator and the clock signal received from the pulse signal generation circuit; Wherein the pulse signal generation circuit sets a frequency of the clock signal according to the pulse reference input signal received from the input logic circuit.

13. The power converter with a stable output voltage according to claim 12, characterized in that, The input logic circuit includes a flip-flop as an input flip-flop, a first input terminal of the input flip-flop is connected to an output terminal of the pulse signal generation circuit, a second input terminal of the input flip-flop is connected to an output terminal of the input comparator, and an inverted output terminal of the input flip-flop is connected to an input terminal of the pulse signal generation circuit.

14. The power converter with a stable output voltage according to claim 12, characterized in that, The pulse reference input circuit further includes: An input switch, a first end of the input switch is connected to the first end of the input capacitor and the first input terminal of the input comparator, a second end of the input switch is grounded, and a control terminal of the input switch is connected to an output terminal of the pulse signal generation circuit.

15. The power converter with a stable output voltage according to claim 14, wherein The pulse signal generation circuit includes a first pulse signal generator, and the first pulse signal generator includes: A first transistor, a first end of the first transistor is coupled to a common voltage, and a control terminal of the first transistor receives a pulse reference input signal from a pulse reference input circuit; A first resistor, a first end of the first resistor is connected to a second end of the first transistor; A second transistor, a first end of the second transistor is connected to a second end of the first resistor, a control terminal of the second transistor receives the pulse reference input signal from the pulse reference input circuit, and a second end of the second transistor is grounded; A third transistor, a first end of the third transistor is coupled to the common voltage; A first Schmitt trigger, an input terminal of the first Schmitt trigger is connected to the first end of the second transistor and a second end of the third transistor; A first NOR gate, a first input terminal of the first NOR gate is connected to an output terminal of the first Schmitt trigger, a second input terminal of the first NOR gate receives the pulse reference input signal from the pulse reference input circuit, and a third input terminal of the first NOR gate is connected to the lower bridge feedback circuit to receive the blank clock signal; A second NOR gate, a first input terminal of the second NOR gate is connected to an output terminal of the first NOR gate, a second input terminal of the second NOR gate receives the pulse reference input signal from the pulse reference input circuit, and an output terminal of the second NOR gate is connected to an input terminal of the control circuit; And A first NOT gate, wherein an input end of the first NOT gate is connected to an output end of the first NOR gate, and an output end of the first NOT gate is connected to a control end of the third transistor.

16. The power converter with a stable output voltage according to claim 15, characterized in that, The first pulse signal generator further includes: A first capacitor, wherein a first end of the first capacitor is connected to an input end of the first Schmitt trigger, and a second end of the first capacitor is grounded.

17. The power converter with a stable output voltage according to claim 16, characterized in that, The pulse signal generating circuit includes a second pulse signal generator, and the second pulse signal generator includes: A fourth transistor, wherein a first end of the fourth transistor is coupled to the common voltage, and a control end of the fourth transistor is connected to an output end of the second NOR gate; A second resistor, wherein a first end of the second resistor is connected to a second end of the fourth transistor; A fifth transistor, wherein a first end of the fifth transistor is connected to a second end of the second resistor, a control end of the fifth transistor is connected to the output end of the second NOR gate, and a second end of the fifth transistor is grounded; A sixth transistor, wherein a first end of the sixth transistor is coupled to the common voltage; A second Schmitt trigger, wherein an input end of the second Schmitt trigger is connected to a first end of the fifth transistor and a second end of the sixth transistor; A third NOR gate, wherein a first input end of the third NOR gate is connected to an output end of the second Schmitt trigger, and a second input end of the third NOR gate is connected to the output end of the second NOR gate; A fourth NOR gate, wherein a first input end of the fourth NOR gate is connected to an output end of the third NOR gate, a second input end of the fourth NOR gate is connected to the output end of the second NOR gate, and an output end of the fourth NOR gate is connected to an input end of the control circuit; And A second NOT gate, wherein an input end of the second NOT gate is connected to the output end of the third NOR gate, and an output end of the second NOT gate is connected to a control end of the sixth transistor.

18. The power converter with a stable output voltage according to claim 17, characterized in that, The second pulse signal generator further includes: A second capacitor, wherein a first end of the second capacitor is connected to an input end of the second Schmitt trigger, and a second end of the second capacitor is grounded.

19. The power converter with a stable output voltage according to claim 1, wherein The power converter with a stable output voltage further includes: A compensation circuit, connected to a node between an output end of the error amplifier and an input end of the control circuit, configured to compensate the error amplification signal output from the output end of the error amplifier to the input end of the control circuit.

20. The power converter with a stable output voltage according to claim 1, characterized in that, The power converter with a stable output voltage further includes: An output resistor, wherein a first end of the output resistor is connected to a second end of the output inductor, and a second end of the output resistor is grounded.

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