Channel estimation device based on power delay spectrum estimation

Abstract

The invention discloses a channel estimation device based on power delay spectrum estimation, which comprises the following steps: firstly, extracting resource particles for placing pilot frequencies in frequency domain resource grids for different physical channels, and carrying out LS (Least Squares) channel estimation on the resource particles and generated local pilot frequencies; secondly, according to different physical channels, transforming the data into a power point number of 2 by adopting two strategies of segmented calculation and edge data inversion, and converting a channel estimation value at a pilot frequency to a time delay domain through a radix-2IFFT (Inverse Fast Fourier Transform) fast algorithm; calculating a power time delay spectrum window in a time delay domain, and performing noise reduction processing on a channel estimation value at a pilot frequency of the time delay domain; and finally, interpolating through a radix-2 FFT fast algorithm to obtain a full-frequency-domain channel estimation value, and integrating and outputting the data according to different physical channels. According to the invention, performance, implementation complexity, processing time delay and hardware resources can be taken into consideration, the universality, compatibility, portability and expandability of the system are improved, and the channel estimation problem realized based on the FPGA or the ASIC is effectively solved.

Description

Technical Field

[0001] The present invention belongs to the field of wireless, and particularly relates to a channel estimation device based on power delay spectrum estimation. Background Art

[0002] The wireless communication environment is quite complex and variable, and is usually affected by factors such as terrain, buildings, weather, etc. These factors bring challenges such as multipath effects, channel fading, time-variability, frequency selectivity, etc., making the signal vulnerable to interference and attenuation during transmission. In such an environment, channel estimation plays a crucial role. Its core lies in accurately understanding the impact on the signal during transmission by estimating the state of the transmission channel. Channel estimation helps the system effectively compensate for signal distortion, track the dynamic changes of the channel in real time, and adjust communication parameters according to the current channel conditions. This ability enables the system to still maintain a low bit error rate and strong anti-interference ability in a complex environment, ensuring stable communication quality.

[0003] Currently, there are relatively few implementation devices for the Minimum Mean Square Error (MMSE) channel estimation algorithm. The existing MMSE channel estimation algorithm needs to be based on the results of the Least Squares (LS) channel estimation, and prior information such as the cross-correlation matrix of the frequency-domain pilot band and the frequency-domain full-band channel, and the autocorrelation matrix of the frequency-domain pilot band is required.

[0004] Since the MMSE channel estimation algorithm involves matrix inversion and matrix multiplication, it is not conducive to the hardware implementation of Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuit (ASIC). It is necessary to approximate and simplify the MMSE channel estimation and deform it to balance the requirements in terms of performance, implementation complexity, computational delay, FPGA or ASIC hardware resource consumption, etc. In addition, in order to use the radix-2 Fast Fourier Transform (FFT), the number of data to be processed needs to be a power of 2. At present, the mainstream algorithm is to pad the data that is not a power of 2 with zeros to a power of 2. However, the spectrum leakage caused by this strategy is more serious, and the performance of the MMSE algorithm drops significantly. Summary of the Invention

[0005] Objective of the Invention: To solve the problems that the current MMSE channel estimation algorithm is computationally complex and not conducive to hardware implementation, and that spectral leakage is severe and the algorithm performance drops significantly when using the radix-2 FFT fast algorithm after padding zeros to data with non-power-of-two numbers, the objective of the present invention is to provide a channel estimation device based on power delay profile estimation, which reduces the hardware implementation complexity on the premise of minimizing algorithm performance loss.

[0006] Technical Solution: To achieve the above objective of the invention, the present invention discloses a channel estimation device based on power delay profile estimation for signal processing at the receiving end of a wireless channel, which specifically includes:

[0007] A resource particle extraction module, which is used for a base station side or a user terminal to extract resource particles where pilots are placed in a frequency-domain resource grid according to the 3GPP protocol for different physical channels; the different physical channels include a Physical Downlink Shared Channel (PDSCH), a Physical Broadcast Channel (PBCH), and a Physical Control Channel (PDCCH);

[0008] An LS channel estimation module, which is used to generate a local pilot sequence and perform LS channel estimation with the received pilot.

[0009] An IFFT operation module, which is used to deform data into a power-of-two number of points according to different physical channels by adopting two strategies of segmented calculation and inverting edge data, and convert the LS channel estimation value at the pilot to the time-delay domain through an Inverse Fast Fourier Transform (IFFT) of radix-2.

[0010] A power delay profile estimation and noise reduction module, which is used to calculate a power delay profile window in the time-delay domain and perform noise reduction processing on the channel estimation value at the pilot in the time-delay domain.

[0011] An FFT operation module, which is used to interpolate through the radix-2 FFT fast algorithm and obtain the channel estimation value in the full frequency domain.

[0012] An integration and output module, which is used to integrate and output data according to different physical channels.

[0013] Furthermore, the device is deployed and implemented on an FPGA or ASIC hardware platform, with a unified fixed-point data bit width, and a unified AXI4-Stream interface protocol is used for the top-level module, internal sub-modules, and called IPs. All IPs inside the module adopt a pipelined structure, and parallel processing is used for data processing.

[0014] Further, the local pilot sequence is generated according to a protocol, specifically: the gold pseudo-random sequence is modulated by Quadrature Phase Shift Keying (QPSK). In the physical shared channel, the generation of the gold sequence is related to factors such as the serial number of the time slot in the radio frame, the scrambling ID, the number of Orthogonal Frequency Division Multiplexing (OFDM) symbols contained in one time slot, and the OFDM symbol index where the DMRS is placed in one time slot. In the physical broadcast channel, the generation of the gold sequence is related to factors such as the SS / PBCH block index, the cell ID, and the half-frame indication. In the physical control channel, the generation of the gold sequence is related to factors such as the serial number of the time slot in the radio frame, the scrambling ID, the number of OFDM symbols contained in one time slot, and the OFDM symbol index where the DMRS is placed in one time slot.

[0015] Further, in the physical shared channel, different BandWidth Part (BWP) configurations are supported. Therefore, according to the configuration information, such as the input RB size, the number of input frequency-domain data is calculated, and then the largest power-of-two number less than the number of input frequency-domain data is obtained by looking up a table, and the input data is segmented according to the lookup result. The specific method is to divide the data into two segments: the first power-of-two number of data is the first half segment, and the second power-of-two number of data is the second half segment. The first half segment is taken from the top of the complete frequency-domain data, and the second half segment is taken from the end of the complete frequency-domain data. There is partial overlap between the two ends of the data in the middle. If the size of the input frequency-domain data is exactly a power of two, then both segments of data are the size of the input frequency-domain data itself, that is, the original data is not segmented, which can improve the generality of the entire module. Then, the IFFT fast operation is performed on the two segments of data respectively.

[0016] Further, in the physical broadcast channel, the pilot signals on the complete OFDM symbols in the 2nd and 4th columns of the physical broadcast block are used for estimation. Since the OFDM symbols in the 2nd and 4th columns of the synchronization broadcast block fixedly occupy 240 subcarriers in the frequency domain, and the pilots are placed four times sparsely, there are 60 pilot data on one column. The last 4 data are inverted, the total data is filled to 64 points, and then the 64-point IFFT fast operation is performed.

[0017] Further, in the physical control channel, due to its resource mapping characteristics, pilot symbols are distributed over 1 - 3 OFDM symbols and are placed in a quadruple - sparse manner in the frequency domain. Therefore, according to configuration information such as the input RB size, the number of input frequency - domain data is calculated, and then the largest power - of - two point number less than the input data volume is obtained by looking up a table. Then, the input data is segmented according to the lookup result. The specific method is to divide the data into two segments: the first 2 - power - of - two point number of data is the first half - segment, and the second 2 - power - of - two point number of data is the second half - segment. The first half - segment is taken from the top of the complete frequency - domain data, and the second half - segment is taken from the end of the complete frequency - domain data. There is some overlap between the two - end data in the middle. If the size of the input frequency - domain data volume is exactly a power of two, then both segments of data are the size of the input frequency - domain data itself, that is, the original data is not segmented, which can improve the generality of the entire module. Then, the IFFT fast operation is performed on the two segments of data respectively.

[0018] Further, the power - delay profile estimation includes the following steps:

[0019] (a) Truncate the time - delay domain LS channel estimation value and perform the first noise reduction. The noise - reduction window length is configured externally to the module.

[0020] (b) Calculate the power of the LS channel estimation value at the pilot in the time - delay domain.

[0021] (c) Calculate the average value of the power values of the LS channel estimation values on the same sub - carrier within the same time slot or multiple time slots.

[0022] (d) Combine the noise power to calculate the soft window of the time - delay domain power spectrum. The noise power is input externally to the module, and then it is compared with the average value of the time - delay domain power obtained on the same sub - carrier to obtain the numerator and denominator of the power - delay profile window. If the time - delay domain power is less than the noise power and the noise power is 0, then the denominator of the power - delay profile window is 1. If the time - delay domain power is less than the noise power and the noise power is not 0, then the denominator of the power - delay profile window is the noise power. Otherwise, the denominator of the power - delay profile window is the time - delay domain power. If the time - delay domain power is not less than the noise power, then the numerator of the power - delay profile window is the time - delay domain power minus the noise power, otherwise it is 0.

[0023] (e) Perform secondary noise reduction on the LS channel estimation value at the pilot in the time - delay domain by adding a soft window.

[0024] Further, in the physical shared channel, due to the pilot being placed in a double - sparse manner, first, zero padding is performed on the time - delay domain noise - reduced LS channel estimation value to make the data volume after zero padding reach twice the data volume of the segmented pilot data. Then, the FFT fast operation of the corresponding number of points is performed to complete the frequency - domain interpolation. Finally, the overlapping parts of the two interpolated frequency - domain channel estimation values are merged, and the complete frequency - domain full - channel estimation value is output.

[0025] Further, in the physical broadcast channel, since the pilots are placed in a quadruple sparse manner, first, zero-padding is performed on the LS channel estimation value after noise reduction in the time delay domain, so that the data volume after zero-padding reaches 4 times the pilot data volume after segmentation. Then, a fast FFT operation with the corresponding number of points is performed to complete frequency domain interpolation. Finally, the data is truncated to 240 points. The channel estimation value on the third column OFDM symbol of the SSB block can be obtained by averaging or interpolation from the channel estimation values on the second and fourth column OFDM symbols.

[0026] Further, in the physical control channel, since the pilots are placed in a quadruple sparse manner, first, zero-padding is performed on the LS channel estimation value after noise reduction in the time delay domain, so that the data volume after zero-padding reaches 4 times the pilot data volume after segmentation. Then, a fast FFT operation with the corresponding number of points is performed to complete frequency domain interpolation. Finally, the overlapping parts of the frequency domain channel estimation values obtained by interpolating the two segments are merged, and a complete frequency domain full channel estimation value is output.

[0027] Beneficial effects: Compared with the prior art, the present invention has the following advantages:

[0028] 1. The architecture can support the receiver channel estimation processing of multiple physical channels including the physical shared channel, physical broadcast channel, physical control channel, etc., and has good channel estimation performance under channel conditions such as additive white Gaussian noise (AWGN) channels and multipath channels, improving the versatility of the module;

[0029] 2. By using the method of segmenting and inverting edge data, the data volume is controlled to a power of 2 number of points, which is more convenient for hardware implementation using the fast FFT algorithm, optimizes the spectrum leakage caused by zero-padding, and solves the problem of serious performance degradation caused by spectrum leakage;

[0030] 3. The data processing adopts a pipelined parallel processing method, effectively reducing the data processing time delay;

[0031] 4. For the physical shared channel, different partial bandwidth configurations can be supported; for the physical control channel, channel estimation can be supported when the resource grid is discontinuous in the frequency domain due to interleaving, improving the compatibility of the system;

[0032] 5. Through the rational design of the calculation structure, the fixed-point data bit width is unified, thus saving hardware implementation resources;

[0033] 6. Using the unified AXI4-Stream interface protocol improves the portability of the module;

[0034] 7. Optimize the hardware implementation logic of the data processing module to improve the scalability of the module: When taking the average of the power values of the time-delay domain signals, the average can be taken for multiple groups of additional pilots within one time slot or multiple groups of pilots and additional pilots within multiple time slots to improve the overall performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 FIG. is a schematic structural diagram of a channel estimation device based on power delay profile estimation according to a specific embodiment of the present invention.

[0036] Figure 2 FIG. is a schematic diagram of the frequency domain resource grid structure of the PDSCH channel.

[0037] Figure 3 FIG. is a schematic structural diagram of the implementation structure of the LS channel estimation module according to a specific embodiment of the present invention.

[0038] Figure 4 FIG. is a schematic structural diagram of the data segmentation implementation according to a specific embodiment of the present invention.

[0039] Figure 5 FIG. is a schematic structural diagram of the implementation of the power delay profile window according to a specific embodiment of the present invention.

[0040] Figure 6 FIG. is a schematic structural diagram of the implementation of the power accumulation average module according to a specific embodiment of the present invention.

[0041] Figure 7 FIG. is a flowchart of the calculation of the power delay profile window according to a specific embodiment of the present invention.

[0042] Figure 8 FIG. is a schematic structural diagram of the implementation of the zero-padding module according to a specific embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] The technical solutions of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0044] An embodiment of the present invention discloses a structure of a channel estimation device based on power delay profile estimation, and the channel estimation device can be deployed and implemented on an FPGA or ASIC hardware platform.

[0045] As Figure 1As shown in the figure, the channel estimation device based on power delay spectrum estimation includes a resource particle extraction module, an LS channel estimation module, an IFFT operation module, a power delay spectrum estimation and noise reduction module, an FFT operation module, and an integration and output module. The resource particle extraction module is used for the base station side or the user terminal to extract the resource particles where pilots are placed in the frequency-domain resource grid according to the 3GPP protocol for different physical channels; the different physical channels include the PDSCH channel, the PBCH channel, and the PDCCH channel; the LS channel estimation module is used to generate a local pilot sequence through the protocol and perform LS channel estimation with the received pilot; the IFFT operation module is used to deform the data into a power of 2 number of points according to different physical channels and convert the LS channel estimation value at the pilot to the time-delay domain through the radix-2 IFFT fast algorithm; the power delay spectrum estimation and noise reduction module is used to calculate the power delay spectrum window in the time-delay domain and perform noise reduction processing on the channel estimation value at the pilot in the time-delay domain; the FFT operation module is used to interpolate through the radix-2 FFT fast algorithm and obtain the channel estimation value in the full frequency domain; the integration and output module is used to integrate and output the data according to different physical channels.

[0046] The working process of the channel estimation device based on power delay spectrum estimation is as follows: At the receiving end, the frequency-domain data, the noise variance, and the system configuration information are input by the upper-level module, such as: the size of the RB to be processed, the frame timing information including the subcarrier index, the OFDM symbol index, the time slot number index, and the frame number index. After the frequency-domain data is processed through the above process, the frequency-domain channel coefficient estimation value is output in units of time slots.

[0047] In this embodiment, in the PDSCH, the time-frequency resource position of the Demodulation reference signal (DMRS) is related to factors such as the duration of the physical channel in a time slot, the mapping method of the DMRS, and the additional pilot configuration. In the PBCH, the time-frequency resource position of the DMRS is placed on the 2nd, 3rd, and 4th symbols of the SynchronizationSignal / PBCH (SSB). In each Resource Block (RB), the specific mapping position of the DMRS is related to the cell ID configuration. In the PDCCH, the position of the DMRS on the resource grid is: the 1st, 5th, and 9th resource particles in each resource block.

[0048] Figure 2 It is a schematic diagram of the frequency-domain resource grid structure of the PDSCH channel. Taking the PDSCH channel as an example, in the resource particle extraction module, first, the pilot symbols are extracted according to the frequency-domain position of the physical shared channel indicated in the physical control channel and the pilot mapping method for subsequent channel estimation. In the physical shared channel, there are various pilot mapping methods, such as Figure 2As shown, the pilot is mapped on the 3rd and 10th OFDM symbols in the time domain, and a 2-fold sparse mapping method is adopted in the frequency domain.

[0049] For the PBCH channel, it is necessary to first find the resource grid where the SSB is located, and then extract the complete pilot symbols in the 2nd and 4th columns of the PBCH for subsequent channel estimation.

[0050] For the PDCCH channel, blind detection is required, and then the pilot symbols in the continuous frequency domain on the control resource set (CORESET) are extracted for subsequent channel estimation.

[0051] Figure 3 It is a schematic diagram of the implementation structure of the LS channel estimation module. The main functions implemented by the LS channel estimation module are: performing LS channel estimation on the extracted received pilots and locally generated pilot sequences. Due to the particularity of the local pilot sequence, its modulus value is 1, and there is only a phase difference between different pilot symbols. The local pilot sequence is generated according to the protocol. Specifically: performing quadrature phase shift encoding QPSK modulation on the gold pseudo-random sequence. In the PDSCH channel, the generation of the gold sequence is related to factors such as the serial number of the time slot in the radio frame, the scrambling ID, the number of orthogonal frequency division multiplexing (OFDM) symbols contained in a time slot, and the OFDM symbol index where the DMRS is placed in a time slot. In the PBCH channel, the generation of the gold sequence is related to factors such as the SS / PBCH block index, the cell ID, and the half-frame indication. In the PDCCH channel, the generation of the gold sequence is related to factors such as the serial number of the time slot in the radio frame, the scrambling ID, the number of OFDM symbols contained in a time slot, and the OFDM symbol index where the DMRS is placed in a time slot.

[0052] Specifically, the specific generation method of the local pilot in the PDSCH channel is: performing QPSK modulation on the gold pseudo-random sequence, that is:

[0053]

[0054] where r represents the generated demodulation reference signal, m represents the symbol serial number after modulation, c represents the pseudo-random sequence, and its specific generation method is:

[0055] c(n) = [x1(n + N c ) + x2(n + N c )] mod 2

[0056] where N c = 1600, and the sequences x1(n) and x2(n) are defined as:

[0057] x1(n + 31) = [x1(n + 3) + x1(n)] mod 2

[0058] x2(n + 31) = [x2(n + 3) + x2(n + 2) + x2(n + 1) + x2(n)] mod 2

[0059] The initial values of x1(n) and x2(n) are respectively:

[0060]

[0061] Among them, Among them, is the number of OFDM symbols in a time slot, is the time slot sequence number within a frame, l is the OFDM symbol index for placing DMRS within a time slot, n SCID is the scrambling ID, n SCID ∈ {0, 1} is given by the DMRS initialization field, represents the identifier related to the reference signal, is given by the relevant parameters in the DMRS-DownlinkConfig IE. If the DMRS-DownlinkConfig IE is not provided, then Among them is the physical cell ID of the serving cell.

[0062] In the PBCH channel, the generation methods of the reference sequence and the pseudo-random sequence are the same as those of the PDSCH. The generation method of the initial value is:

[0063]

[0064] Among them, n hf is the half-frame indication of the PBCH, i SSB is the index of the SS / PBCH block, is the physical cell ID of the serving cell.

[0065] In the PDCCH channel, the generation methods of the reference sequence and the pseudo-random sequence are the same as those of the PDSCH. The generation method of the initial value is:

[0066]

[0067] Among them, is the number of OFDM symbols in a time slot, is the time slot sequence number within a frame, l is the OFDM symbol index within a time slot, N ID is the scrambling ID, N ID ∈ {0, 1} is given by the DMRS initialization field, N ID∈{0,1,…,65535} is given by the relevant parameters in pdcch-DMRS-ScramblingID. If pdcch-DMRS-ScramblingID is not provided, then in The physical cell ID of the serving cell.

[0068] Due to the particularity of the local pilot sequence, the hardware implementation of the LS channel estimation algorithm can use the CORDIC algorithm to convert the division into a phase rotation of the local pilot, which can reduce the hardware resource consumption of the FPGA or ASIC and reduce the processing delay. The module outputs the LS channel estimation value at the pilot symbol.

[0069] The IFFT operation module mainly segments the frequency domain LS channel estimation value into powers of 2, and then performs fast IFFT operation to convert it into the LS channel estimation value in the delay domain. In the physical shared channel, different partial bandwidth configurations are supported. Therefore, it is necessary to calculate the number of input frequency domain data according to the configuration information, such as the input RB size, and then look up the table to find the largest number of power of 2 points that is less than the number of input frequency domain data, and segment the input data according to the table lookup result. The specific method is to divide the data into two segments: the data of the first 2 power points is the first half, and the data of the second 2 power points is the second half. The first half starts from the top of the complete frequency domain data, and the second half starts from the end of the complete frequency domain data. The data at both ends overlap partially in the middle. If the amount of input frequency domain data is exactly a power of 2, the two segments of data are the same as the amount of input frequency domain data itself, that is, the original data is not segmented, which can improve the versatility of the entire module. Then perform fast IFFT operation on the two segments of data respectively.

[0070] In the physical broadcast channel, the pilot signals on the 2nd and 4th complete OFDM symbols in the physical broadcast block are used for estimation. Since the 2nd and 4th OFDM symbols in the synchronous broadcast block occupy 240 subcarriers in the frequency domain, and the pilots are placed four times sparsely, 60 pilot data are fixed in one column. The last 4 data are inverted, the overall data is padded to 64 points, and then a 64-point IFFT fast operation is performed.

[0071] In the physical control channel, due to its resource mapping characteristics, pilot symbols are distributed over 1 - 3 OFDM symbols and are placed in a quadruple - sparse manner in the frequency domain. Therefore, according to configuration information such as the input RB size, the number of input frequency - domain data is calculated, then the largest power - of - 2 number less than the input data volume is obtained by looking up a table, and the input data is segmented according to the lookup result. The specific method is to divide the data into two segments: the first 2 - power - of - 2 number of data is the first half - segment, and the second 2 - power - of - 2 number of data is the second half - segment. The first half - segment is taken from the top of the complete frequency - domain data, and the second half - segment is taken from the end of the complete frequency - domain data. There is partial overlap between the two - end data in the middle. If the size of the input frequency - domain data volume is exactly a power of 2, then both segments of data are the size of the input frequency - domain data itself, that is, the original data is not segmented, which can improve the generality of the entire module. Then, the IFFT fast operation is performed on the two segments of data respectively.

[0072] Exemplarily, Figure 4 is a schematic diagram of the implementation structure for data segmentation. As Figure 4 shown in (a) of, for the LS channel estimation values with non - power - of - 2 numbers in PDCCH and PDSCH, the data is divided into two segments of power - of - 2 data, and there is partial overlap between the two segments. If the data volume of the LS channel estimation value itself is exactly a power of 2, then the two segments of segmented data are both the original data, which improves the generality of the module. The lengths of the two segments of data with the number of points of power - of - 2 intercepted can be obtained by looking up a table according to the input system configuration information such as the RB size and other configuration information.

[0073] As Figure 4 shown in (b) of, for PBCH, the LS channel estimation value is fixed at 60 data. Therefore, the last 4 bits of the data are reversed, that is, the 56 - 59th bits are directly reversed and concatenated after the 60th data, directly forming 64 - bit data, which is the smallest power - of - 2 data greater than 60. This approach has better algorithm performance compared to segmenting into two 32 - point data.

[0074] As Figure 4 shown in (c) of, the hardware implementation method of the IFFT operation is to use the FFTIP core in the FPGA or ASIC hardware platform to complete the corresponding serial IFFT operation of the power - of - 2 number of points. Through the counting of frame timing information, the input time - delay domain channel estimation value is divided into two segments of data with the number of points of power - of - 2. Then, for the PDSCH and PDCCH channels, a FIFO IP is used for caching; for the PBCH channel, a module with a stack function is used to reverse the data, and finally the two segments of data are serially input into the FFT IP core. According to the external input system configuration information such as the resource block size, etc., information such as the number of operation points of the FFT IP, the flag bit of the last data, and the data valid flag bit are configured for the FFT IP to perform dynamic FFT operation point configuration.

[0075] Since the data at the receiving end may be affected by noise, a first noise reduction operation needs to be performed on the data in the time delay domain here: The noise reduction window length is configured externally by the module. Here, a window can be configured at the front and back of the entire data segment to cope with frequency domain leakage. The output data of the FFT IP is truncated according to the window length, the data within the front and back windows is retained, and the data outside the windows is set to zero. The window length can be configured externally, which improves the versatility and flexibility of the system.

[0076] The power delay spectrum estimation and noise reduction module mainly completes the calculation of the power delay spectrum window in the time delay domain and performs noise reduction on the channel estimation values at the pilots in the time delay domain. The power delay spectrum estimation includes the following steps: (a) Truncate the LS channel estimation values in the time delay domain and perform the first noise reduction; (b) Calculate the power of the LS channel estimation values at the pilots in the time delay domain; (c) Calculate the average value of the power values of the LS channel estimation values on the same subcarrier within the same time slot or multiple time slots; (d) Calculate the soft window of the time delay domain power spectrum in combination with the noise power; (e) Perform secondary noise reduction on the LS channel estimation values at the pilots in the time delay domain by adding the soft window.

[0077] Figure 5 It is a schematic diagram of the implementation structure of the power delay spectrum window. This module is mainly composed of a power accumulation and averaging module, a power delay spectrum window module, a secondary window adding module, and a zero-padding module. The module calculates the power of the input complex-valued signal data and takes the average power on the same subcarrier of multiple OFDM symbols within the same time slot or on the same subcarrier of multiple OFDM symbols in multiple time slots. The module supports the calculation of the window length for single time slot and multiple time slots, which improves the scalability and versatility of the module.

[0078] The schematic diagram of the implementation structure of the power accumulation and averaging module is as Figure 6As shown, it mainly consists of two DSPIPs. The time-delay domain data after the first noise reduction is in complex form. The real and imaginary parts of the data are separated. First, the square of the real part is calculated using the function A*B + C of DSPIP. Among them, both ports A and B input the real part of the data, and port C selects to input the output data of the subsequent DSPIP or 0. Since this module also implements the accumulation function, when the input data is the data on the first column of OFDM symbols for accumulation, 0 is selected by the selector for input; if it is the data on other columns of OFDM symbols within the same time slot, or the data on OFDM symbols in subsequent time slots, then the output of the second DSPIP is selected. The second DSPIP selects the function A*B + C to calculate the square of the imaginary part and sums it with the square of the real part. Among them, both ports A and B input the imaginary part of the data, and port C selects to input the output result of the first DSPIP. The output result of the second-level DSPIP needs to be selectively processed: if the accumulated values on the same subcarrier for multiple OFDM symbols within the same time slot are calculated, or the accumulated values on the same subcarrier for multiple OFDM symbols in multiple time slots are calculated, then the power value is averaged for output; if the accumulation calculation has not been completed, the calculation result is stored in the FIFO and waits for the input of data within the next set of OFDM symbols.

[0079] The power delay profile window generation module mainly consists of DIV IP. The generation methods of the numerator and denominator of the power delay profile window are as Figure 7 shown in the power delay profile calculation flowchart. The external input noise power is compared with the average value of the time-delay domain power obtained on the same subcarrier to obtain the numerator and denominator of the power delay profile window. The specific method is as follows: if the time-delay domain power is less than the noise power and the noise power is 0, the denominator of the power delay profile window is 1; if the time-delay domain power is less than the noise power and the noise power is not 0, the denominator of the power delay profile window is the noise power; otherwise, the denominator of the power delay profile window is the time-delay domain power; if the time-delay domain power is not less than the noise power, the numerator of the power delay profile window is the time-delay domain power minus the noise power; otherwise, it is 0. Finally, the DIV IP core in the FPGA or ASIC hardware platform is used for division operation and the power delay profile window is output. Here, through the rational design of the calculation structure, in the designed soft window, the orders of magnitude of the numerator and denominator are close, so the data can be scaled in a unified format, avoiding the problem of increasing the fixed-point data bit width due to the result of the divider being too large or too small, thus saving hardware implementation resources.

[0080] In the secondary windowing module, the time-delay domain LS channel estimation data after the first noise reduction is multiplied by the generated soft window result, which can be implemented through the MULT IP in the FPGA or ASIC. The module completes the secondary noise reduction in the time-delay domain.

[0081] As Figure 8As shown in the schematic diagram of the zero-padding module implementation structure, in the zero-padding module, it is necessary to perform zero-padding on the data after the second windowing and then output it. The specific method is as follows: For the PDSCH channel, assuming the length of each segment of data with a power of 2 is N, since its pilots are twice as sparse in the frequency domain, N zeros need to be padded in the middle of the valid data in the front and back windows to make the total data length 2N; for the PBCH and PDCCH channels, assuming the length of each segment of data with a power of 2 is N, since its pilots are four times as sparse in the frequency domain, 3N zeros need to be padded in the middle of the valid data in the front and back windows to make the total data length 4N. The module outputs the LS channel estimation data after zero-padding in the time delay domain after the second noise reduction.

[0082] Input the time delay domain data after the second noise reduction into the FFT operation module, and configure the corresponding information such as the number of FFT operation points, the flag bit of the last data, and the data valid flag bit of the FFT IP. The number of FFT operation points can be obtained by looking up a table according to the input system configuration information, such as resource block size and other configuration information.

[0083] The main function of the integrated output module is to finally integrate and output the segmented frequency domain data. For the PDSCH and PDCCH channels, the overlapping parts of the segmented full-frequency domain channel estimations are averaged and output. For the PBCH channel, the first 240 points of the frequency domain channel estimation value are intercepted and output as the channel estimation value of the PBCH frequency domain channel. For the channel estimation value of the PBCH on the incomplete OFDM symbol in the 3rd column within the SSB, it can be obtained by averaging or interpolation using the channel estimation values on the OFDM symbols in the 2nd and 4th columns.

[0084] In the channel estimation device based on power delay spectrum estimation, the top-level module, internal sub-modules, and called IPs all use the unified AXI4-Stream interface protocol to improve the portability of the module. The IPs inside the module all adopt a pipelined structure, and data processing adopts a parallel processing method, effectively reducing the data processing time delay.

Claims

1. A channel estimation device based on power delay spectrum estimation, characterized in that Including: A resource particle extraction module, which is used to extract the resource particles where pilots are placed in the frequency-domain resource grid for different physical channels; the different physical channels include the physical shared channel, the physical broadcast channel, and the physical control channel; An LS channel estimation module, which is used to generate a local pilot sequence and perform LS channel estimation with the received pilot; An IFFT operation module, which is used to deform the data into a power-of-2 number of points according to different physical channels by adopting two strategies of segmented calculation and reversing edge data, and convert the LS channel estimation value at the pilot to the time-delay domain through the radix-2 IFFT fast algorithm; A power delay spectrum estimation and noise reduction module, which is used to calculate the power delay spectrum window in the time-delay domain and perform noise reduction processing on the channel estimation value at the pilot in the time-delay domain; An FFT operation module, which is used to interpolate through the radix-2 FFT fast algorithm and obtain the channel estimation value in the full frequency domain; An integration and output module, which is used to integrate and output the data according to different physical channels.

2. The channel estimation device based on power delay profile estimation according to claim 1, wherein The device is deployed and implemented on an FPGA or ASIC hardware platform, with a unified fixed-point data bit width. The top-level module, internal sub-modules, and called IP all use the unified AXI4-Stream interface protocol. The IP inside the module all adopts a pipelined structure, and the data processing adopts a parallel processing method.

3. The channel estimation device based on power delay spectrum estimation according to claim 1, characterized in that, The local pilot is generated according to the protocol and modulated by QPSK through the gold sequence; in the physical shared channel, the generation of the gold sequence is related to the sequence number of the time slot in the radio frame, the scrambling ID, the number of OFDM symbols contained in a time slot, and the OFDM symbol index where the DMRS is placed in a time slot; In the physical broadcast channel, the generation of the gold sequence is related to the SS / PBCH block index, the cell ID, and the half-frame indication; in the physical control channel, the generation of the gold sequence is related to the sequence number of the time slot in the radio frame, the scrambling ID, the number of OFDM symbols contained in a time slot, and the OFDM symbol index where the DMRS is placed in a time slot.

4. The channel estimation device based on power delay profile estimation according to claim 1, characterized in that, In the physical shared channel, the segmented calculation strategy is adopted to support different partial bandwidth configurations. According to the configuration information, the number of input frequency-domain data is calculated, and then the largest power-of-2 number of points less than the number of input frequency-domain data is obtained by looking up a table. The input data is segmented according to the lookup result: the data of the first power-of-2 number of points is the first half segment, and the data of the second power-of-2 number of points is the second half segment. The first half segment is taken from the top of the complete frequency-domain data, and the second half segment is taken from the end of the complete frequency-domain data. There is partial overlap between the two ends of the data. If the size of the input frequency-domain data amount is exactly a power of 2, both segments of data are the size of the input frequency-domain data itself; then, the IFFT fast operation is performed on the two segments of data respectively.

5. The channel estimation device based on power delay profile estimation according to claim 1, characterized in that, In the physical broadcast channel, the strategy of reversing edge data is adopted to reverse the last few data, fill the overall data to the smallest power-of-2 number of points, and then perform the IFFT fast operation.

6. The channel estimation device based on power delay profile estimation according to claim 1, characterized in that In the physical control channel, a segmented calculation strategy is adopted. According to the configuration information, the number of input frequency-domain data is calculated. Then, the largest power-of-two number less than the input data volume is obtained by looking up a table, and the input data is segmented according to the lookup result: the data of the first power-of-two points is the first half segment, and the data of the second power-of-two points is the second half segment. The first half segment is taken from the top of the complete frequency-domain data, and the second half segment is taken from the end of the complete frequency-domain data. There is partial overlap between the two ends of the data in the middle. If the size of the input frequency-domain data volume is exactly a power of two, the data volumes of both segments are the same as the size of the input frequency-domain data itself. Then, the IFFT fast operation is performed on the two segments of data respectively.

7. The channel estimation device based on power delay spectrum estimation according to claim 1, characterized in that The power delay profile estimation includes the following steps: (a) Truncate the time-delay domain LS channel estimation value and perform the first noise reduction, where the noise reduction window length is configured externally by the module; (b) Calculate the power of the LS channel estimation value at the pilot in the time-delay domain; (c) Calculate the average value of the power values of the LS channel estimation values on the same subcarrier within the same time slot or multiple time slots; (d) Combine the noise power to calculate the soft window of the time-delay domain power spectrum. The noise power is input externally by the module, and then it is compared with the average value of the time-delay domain power obtained on the same subcarrier to obtain the numerator and denominator of the power delay profile window. If the time-delay domain power is less than the noise power and the noise power is 0, the denominator of the power delay profile window is 1. If the time-delay domain power is less than the noise power and the noise power is not 0, the denominator of the power delay profile window is the noise power. Otherwise, the denominator of the power delay profile window is the time-delay domain power. If the time-delay domain power is not less than the noise power, the numerator of the power delay profile window is the time-delay domain power minus the noise power, otherwise it is 0; (e) Perform secondary noise reduction on the LS channel estimation value at the pilot in the time-delay domain by adding a soft window.

8. The channel estimation device based on power delay spectrum estimation according to claim 1, characterized in that, In the physical shared channel, the pilots are placed with a two-fold sparse separation. First, zero-padding is performed on the time-delay domain noise-reduced LS channel estimation value to make the data volume after zero-padding reach twice the data volume of the segmented pilots. Then, the FFT fast operation of the corresponding number of points is performed to complete the frequency-domain interpolation. Finally, the overlapping parts of the frequency-domain channel estimation values interpolated from the two segments are merged, and the complete frequency-domain full channel estimation value is output.

9. The channel estimation device based on power delay spectrum estimation according to claim 1, characterized in that In the physical broadcast channel, the pilots are placed with a four-fold sparse separation. First, zero-padding is performed on the time-delay domain noise-reduced LS channel estimation value to make the data volume after zero-padding reach four times the data volume of the segmented pilots. Then, the FFT fast operation of the corresponding number of points is performed to complete the frequency-domain interpolation. Finally, the data is truncated to the original number of points. The channel estimation value on the third column OFDM symbol of the SSB block can be obtained by averaging or interpolating the channel estimation values on the second and fourth column OFDM symbols.

10. The channel estimation device based on power delay profile estimation according to claim 1, characterized in that, In the physical control channel, the pilots are placed with a four-fold sparse separation. First, zero-padding is performed on the time-delay domain noise-reduced LS channel estimation value to make the data volume after zero-padding reach four times the data volume of the segmented pilots. Then, the FFT fast operation of the corresponding number of points is performed to complete the frequency-domain interpolation. Finally, the overlapping parts of the frequency-domain channel estimation values interpolated from the two segments are merged, and the complete frequency-domain full channel estimation value is output.

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