Semiconductor memory device

Abstract

A semiconductor memory device is provided, the semiconductor memory device including: a peripheral gate structure on a substrate; a bit line; and an active pattern including a first surface and a second surface opposite to each other, and a first sidewall and a second sidewall opposite to each other, and the first surface of the active pattern contacts the bit line. The semiconductor memory device includes a word line on a first sidewall of an active pattern; a contact structure including an upper surface and a bottom surface opposite to each other, where the bottom surface of the contact structure contacts the second surface of the active pattern; and a data storage pattern on an upper surface of the contact structure and including a lower electrode and a capacitor dielectric film. The capacitor dielectric film is in contact with a sidewall of the contact structure.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0006070, filed with the Korean Intellectual Property Office on January 15, 2024, and all rights arising therefrom, the content of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present invention relates to a semiconductor memory device and a method of manufacturing the same. Background Art

[0003] There is a need to increase the integration degree of semiconductor memory devices to meet the excellent performance and low price desired by consumers. In the case of semiconductor memory devices, since the integration degree is an important factor determining the price of products, an increased integration degree is particularly desired.

[0004] In the case of two-dimensional or planar semiconductor memory devices, the integration degree is mainly determined by the area occupied by a unit memory cell and is thus greatly affected by fine pattern formation technology. However, since ultra-expensive equipment is required to miniaturize patterns, the integration degree of two-dimensional semiconductor memory devices is increasing but still limited. Accordingly, semiconductor memory devices including vertical channel transistors whose channels extend in the vertical direction have been proposed. Summary of the Invention

[0005] Embodiments of the present invention provide a semiconductor memory device having improved integration degree and electrical characteristics.

[0006] Embodiments of the present invention also provide a method of manufacturing a semiconductor memory device having improved integration degree and electrical characteristics.

[0007] However, embodiments of the present invention are not limited to the embodiments set forth herein. The above and other embodiments of the present invention will become more apparent to those of ordinary skill in the art to which the present invention pertains by referring to the detailed description of the present invention given below.

[0008] According to some embodiments of the present disclosure, a semiconductor device is provided. The semiconductor device includes: a peripheral gate structure on a substrate; a bit line on the peripheral gate structure and extending in a first direction; an active pattern on the bit line and including a first surface and a second surface opposite to each other in a second direction, and a first sidewall and a second sidewall opposite to each other in the first direction. The first surface of the active pattern contacts the bit line; a word line on the first sidewall of the active pattern and extending in a third direction intersecting the first direction and the second direction; a contact structure on the active pattern and including a top surface and a bottom surface opposite to each other in the second direction. The bottom surface of the contact structure contacts the second surface of the active pattern; and a data storage pattern on the top surface of the contact structure and including a lower electrode and a capacitor dielectric film. Wherein, the contact structure includes a sidewall between the top surface and the bottom surface of the contact structure, and the capacitor dielectric film extends along and contacts the sidewall of the contact structure.

[0009] According to some embodiments of the present disclosure, a semiconductor device is provided. The semiconductor device includes: a peripheral gate structure on a substrate; a bit line on the peripheral gate structure and extending in a first direction; an active pattern on the bit line and including a first surface and a second surface opposite to each other in a second direction, and a first sidewall and a second sidewall opposite to each other in the first direction. The first surface of the active pattern contacts the bit line; a word line on the first sidewall of the active pattern on the bit line and extending in a third direction intersecting the first direction and the second direction; a contact structure on the active pattern and including a top surface and a bottom surface opposite to each other in the second direction. The bottom surface of the contact structure contacts the second surface of the active pattern; and a data storage pattern on the top surface of the contact structure. The data storage pattern includes a lower electrode contacting the top surface of the contact structure, a capacitor dielectric film on the lower electrode, and an upper electrode on the capacitor dielectric film. The upper electrode includes a bottom surface facing the bit line, and the distance from the top surface of the bit line to the top surface of the contact structure is greater than the distance from the top surface of the bit line to the bottom surface of the upper electrode.

[0010] According to some embodiments of the present disclosure, there is provided a semiconductor device, the semiconductor device including: a peripheral gate structure on a substrate; a bit line on the peripheral gate structure and extending in a first direction; a shielding conductive pattern on the peripheral gate structure, and the shielding conductive pattern includes a shielding wire pattern extending in the first direction along a sidewall of the bit line; a word line on the bit line and the shielding conductive pattern, extending in a second direction, and including an upper surface and a bottom surface facing each other in a third direction, the bottom surface of the word line facing the bit line; a back gate electrode on the bit line and the shielding conductive pattern, extending in the second direction, and including an upper surface and a bottom surface facing each other in a third direction, the bottom surface of the back gate electrode facing the bit line; a word line covering pattern on the upper surface of the word line; a back gate covering pattern on the upper surface of the back gate electrode; an active pattern between the word line and the back gate electrode, and including a first surface and a second surface facing each other in the third direction, the first surface of the active pattern contacting the bit line; a contact structure on the active pattern and connected to a second side of the active pattern; and a data storage pattern on the contact structure, and including a lower electrode and a capacitor dielectric film, and the capacitor dielectric film contacting the word line covering pattern and the back gate covering pattern.

[0011] According to some embodiments of the present disclosure, there is provided a method for manufacturing a semiconductor memory device, the method including: providing a first substrate including a semiconductor substrate, a buried insulating layer, and an active layer; forming a back gate electrode extending in a first direction in the active layer; patterning the active layer to form a first active pattern and a second active pattern on the buried insulating layer on a first side and a second side of the back gate electrode; forming a first word line and a second word line on the buried insulating layer on the first side and the second side of the back gate electrode, the first active pattern being between the first word line and the back gate electrode, and the second active pattern being between the second word line and the back gate electrode; forming a bit line extending in a second direction across the first word line and the second word line on the first active pattern and the second active pattern; forming a peripheral gate structure on a second substrate; bonding the first substrate and the second substrate together such that the bit line and the peripheral gate structure face each other; forming a metal mask pattern on the semiconductor substrate of the first substrate; forming a semiconductor molding pattern on the buried insulating layer by removing the semiconductor substrate overlapping with the metal mask pattern in a third direction intersecting the first direction and the second direction; forming a sacrificial molding film surrounding the semiconductor molding pattern on the buried insulating layer; forming a lower electrode hole exposing the first active pattern and the second active pattern in the sacrificial molding film by removing a part of the buried insulating layer and the semiconductor molding pattern; sequentially forming a contact structure and a lower electrode in the lower electrode hole; after forming the lower electrode, removing the sacrificial molding film to expose sidewalls of the lower electrode and the contact structure; and forming a capacitor dielectric film and an upper electrode on the lower electrode and the contact structure. Description of the Drawings

[0012] The above and other embodiments and features of the present disclosure will become clearer by describing exemplary embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0013] Figure 1 is a layout diagram for explaining a semiconductor memory device according to some embodiments.

[0014] Figure 2 is along Figure 1 Cross-sectional views taken along lines A-A and B-B of.

[0015] Figure 3 is along Figure 1 Cross-sectional views taken along lines C-C and D-D of.

[0016] Figure 4 is Figure 2 An enlarged view of part P of.

[0017] Figures 5 to 9 is Figure 2 An enlarged view of part Q of.

[0018] Figures 10 to 14 are respectively diagrams for explaining a semiconductor memory device according to some embodiments.

[0019] Figure 15 and Figure 16 are diagrams for explaining a semiconductor memory device according to some embodiments.

[0020] Figure 17 and Figure 18 are diagrams for explaining a semiconductor memory device according to some embodiments.

[0021] Figure 19 and Figure 20 are respectively diagrams for explaining a semiconductor memory device according to some embodiments.

[0022] Figures 21 to 57 is a diagram for explaining a method for manufacturing a semiconductor memory device according to some embodiments. Detailed Description of the Embodiments

[0023] Figure 1 is a layout diagram for explaining a semiconductor memory device according to some embodiments. Figure 2 is along Figure 1 Cross-sectional views taken along lines A-A and B-B of. Figure 3 is along Figure 1 Cross-sectional views taken along lines C-C and D-D of. Figure 4 is Figure 2 An enlarged view of part P of. Figures 5 to 9 is Figure 2 An enlarged view of part Q of.

[0024] A semiconductor memory device according to an embodiment of the present invention may include a memory cell including a vertical channel transistor (VCT).

[0025] Referring to Figures 1 to 9 , a semiconductor memory device according to some embodiments may include a bit line BL, word lines WL1 and WL2, a back gate electrode BG, a shielding conductive pattern SL, active patterns AP1 and AP2, a contact structure (or contact pattern) BC, and a data storage pattern DSP.

[0026] The substrate 100 may be a silicon substrate or may include other materials (such as, but not limited to, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide).

[0027] The substrate 100 may include an upper side 100US. An element isolation film 101 may be disposed inside the substrate 100. The element isolation film 101 may define an active region inside the substrate 100. The element isolation film 101 includes an insulating material.

[0028] The substrate 100 may include a cell array region in which the data storage pattern DSP is disposed, and a peripheral circuit region defined around the cell array region.

[0029] A peripheral gate structure PG may be disposed on the substrate 100. For example, the peripheral gate structure PG may be disposed on the upper side 100US of the substrate. The peripheral gate structure PG may be disposed over the cell array region and the peripheral circuit region. In other words, a part of the peripheral gate structure PG may be disposed in the cell array region of the substrate 100, and the remaining part of the peripheral gate structure PG may be disposed in the peripheral circuit region of the substrate 100.

[0030] The peripheral gate structure PG may be included in a sense transistor, a transfer transistor, a driving transistor, etc. For example, the peripheral gate structure PG included in the sense transistor may be disposed on the cell array region of the substrate 100, but is not limited thereto. Obviously, the type of transistor in the peripheral circuit disposed on the cell array region of the substrate 100 may vary according to the design and layout of the semiconductor memory device.

[0031] The peripheral gate structure PG may include a peripheral gate insulating film 215, a peripheral lower conductive pattern 223, and a peripheral upper conductive pattern 225. The peripheral gate insulating film 215 may include a silicon oxide film, a silicon oxynitride film, a high-k dielectric insulating film having a higher dielectric constant than the silicon oxide film, or a combination thereof. The high-k dielectric insulating film may include, for example, but not limited to, at least one of metal oxides, metal oxynitrides, metal silicon oxides, and / or metal silicon oxynitrides.

[0032] Both the peripheral lower conductive pattern 223 and the peripheral upper conductive pattern 225 include a conductive material. For example, the peripheral lower conductive pattern 223 and the peripheral upper conductive pattern 225 may each include at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional (2D) material, and a metal. In a semiconductor device according to some embodiments, the 2D material may be a metal material and / or a semiconductor material. The 2D material may include 2D allotropes or 2D compounds, and may include, but is not limited to, at least one of graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), and / or tungsten disulfide (WS2). That is, since the above-mentioned 2D materials are only listed as examples, the 2D materials that can be included in the semiconductor memory device of the present invention are not limited to the above-mentioned materials. Although the peripheral gate structure PG is shown as including a plurality of conductive patterns, the embodiments are not limited thereto.

[0033] Although not shown, the peripheral gate structure PG may further include a peripheral gate mask pattern disposed on the peripheral upper conductive pattern 225. The gate peripheral mask pattern is made of an insulating material.

[0034] The first peripheral lower insulating film 227 and the second peripheral lower insulating film 228 are disposed on the upper side 100US of the substrate. Both the first peripheral lower insulating film 227 and the second peripheral lower insulating film 228 include an insulating material.

[0035] The peripheral contact plug 241a and the peripheral wiring line 241b may be disposed in or extend into the first peripheral lower insulating film 227 and the second peripheral lower insulating film 228. The peripheral contact plug 241a and the peripheral wiring line 241b may be connected to the peripheral lower conductive pattern 223 and the peripheral upper conductive pattern 225 of the peripheral gate structure PG. Although not shown, the peripheral contact plug 241a and the peripheral wiring line 241b may be connected to source / drain regions disposed on at least one side of the peripheral gate structure PG.

[0036] Although the peripheral contact plug 241a and the peripheral wiring line 241b are shown as different films from each other, the present invention is not limited thereto. The boundary between the peripheral contact plug 241a and the peripheral wiring line 241b may not be distinguished. Both the peripheral contact plug 241a and the peripheral wiring line 241b include a conductive material.

[0037] The first peripheral upper insulating film 261 and the second peripheral upper insulating film 262 may be disposed on the peripheral contact plug 241a and the peripheral wiring line 241b. Both the first peripheral upper insulating film 261 and the second peripheral upper insulating film 262 include insulating materials. Obviously, different from the illustrated example, an insulating film formed of a single film may be disposed on the peripheral contact plug 241a and the peripheral wiring line 241b.

[0038] The peripheral connection structures 242a and 242b may be connected to the peripheral wiring line 241b. The peripheral connection structures 242a and 242b may include a peripheral connection via 242a and a peripheral connection wiring 242b. Both the peripheral connection via 242a and the peripheral connection wiring 242b include conductive materials.

[0039] Although the peripheral connection via 242a and the peripheral connection wiring 242b are shown as being different films from each other, the present invention is not limited thereto. Although the peripheral connection structures 242a and 242b are shown as including one peripheral connection wiring 242b provided on one metal level, this is only for convenience of explanation, and the embodiments are not limited thereto. The peripheral connection structures 242a and 242b may include a plurality of peripheral connection wirings 242b provided on different metal levels from each other.

[0040] The third peripheral upper insulating film 265 may be disposed on the peripheral connection structures 242a and 242b. The third peripheral upper insulating film 265 includes an insulating material.

[0041] The shielding structures 171, SL, and 175 may be disposed on the peripheral gate structure PG on the substrate 100. For example, the shielding structures 171, SL, and 175 may be disposed on the peripheral connection structures 242a and 242b.

[0042] The shielding structures 171, SL, and 175 may include a shielding conductive pattern SL and shielding insulating films 171 and 175. For example, the shielding insulating films 171 and 175 may include a shielding insulating liner 171 and a shielding insulating cover film 175.

[0043] The shielding conductive pattern SL may include a plurality of shielding wire patterns SLp. Each shielding wire pattern SLp may extend in the second direction D2. Each shielding wire pattern SLp may be adjacent to each other in the first direction D1. For example, the first direction D1 and the second direction D2 may be horizontal directions horizontal to the substrate 100.

[0044] Each shielding wire pattern SLp may extend from the cell array region to the peripheral circuit region. The end of the shielding wire SL may be disposed on the peripheral circuit region.

[0045] The shielding conductive pattern SL includes a conductive material. The shielding conductive pattern SL may include at least one of, for example, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, and / or a metal.

[0046] The shielding insulating cover film 175 may be disposed on the peripheral connection structures 242a and 242b. The shielding insulating cover film 175 may be disposed between the peripheral gate structure PG and the shielding conductive pattern SL.

[0047] The shielding insulating cover film 175 may be in contact with the shielding conductive pattern SL. In a semiconductor memory device according to some embodiments, the shielding insulating cover film 175 may be in contact with the shielding wire pattern SLp.

[0048] The shielding insulating cover film 175 may have a linear shape extending along the shielding wire pattern SLp in the second direction D2. Different from the illustrated example, the shielding insulating cover film 175 may have a flat plate shape. In other words, the shielding insulating cover film 175 may be stacked with the shielding wire pattern SLp and the bit line BL in the third direction D3. For example, the third direction D3 may be a vertical direction perpendicular to the substrate 100.

[0049] The shielding insulating pad 171 may be disposed on the shielding conductive pattern SL. The shielding insulating pad 171 may extend along the contour of the shielding wire pattern SLp.

[0050] The shielding insulating pad 171 may be disposed on the bit line BL and the third peripheral upper insulating film 265. Different from the illustrated example, the shielding insulating pad 171 may not be disposed between the bit line BL and the third peripheral upper insulating film 265. In this case, the bit line BL may be in contact with the third peripheral upper insulating film 265.

[0051] Both the shielding insulating pad 171 and the shielding insulating cover film 175 may be made of an insulating material. When the shielding insulating pad 171 and the shielding insulating cover film 175 include the same material, the boundary between the shielding insulating pad 171 and the shielding insulating cover film 175 may not be distinguishable.

[0052] Since the shielding structures 171, SL, and 175 are disposed between the bit lines BL adjacent in the first direction D1, the coupling noise between the bit lines BL may be reduced.

[0053] The bit line BL may be disposed on the peripheral gate structure PG on the substrate 100. For example, the bit line BL may be disposed on the peripheral connection structures 242a and 242b.

[0054] The bit line BL can extend long in the second direction D2. Adjacent bit lines BL can be spaced apart in the first direction D1. The bit line BL includes a long sidewall extending in the second direction D2 and a short sidewall extending in the first direction D1.

[0055] The bit line BL can be arranged adjacent to the shield wire pattern SLp. The bit line BL can be arranged adjacent to the shield wire pattern SLp in the first direction D1. In other words, the shield wire pattern SLp can extend along the long sidewall of the bit line BL in the second direction D2.

[0056] The bit line BL can be arranged between adjacent shield wire patterns SLp along the first direction D1. The bit line BL can be arranged on the shield insulating pad 171. For example, the shield insulating pad 171 can be in contact with the bit line BL.

[0057] Although not shown, each bit line BL can extend from the cell array region to the peripheral circuit region. The end of each bit line BL can be arranged on the peripheral circuit region.

[0058] Each bit line BL can include a semiconductor pattern 161, a metal pattern 163, and a bit line mask pattern 165 stacked in sequence. Different from the illustrated example, the bit line BL can include one of the semiconductor pattern 161 and / or the metal pattern 163.

[0059] The bit line BL can include a conductive bit line. The conductive bit line includes a film made of a conductive material among the bit lines BL. The conductive bit line can include the semiconductor pattern 161 and the metal pattern 163.

[0060] The semiconductor pattern 161 can include a conductive semiconductor material. The conductive semiconductor material can be, for example, a semiconductor material doped with impurities. The semiconductor pattern 161 can include at least one of polysilicon, polycrystalline silicon germanium, polygermanium, amorphous silicon, amorphous silicon germanium, and / or amorphous germanium.

[0061] The metal pattern 163 can include a conductive material containing a metal. The metal pattern 163 can include at least one of, for example, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, and / or a metal.

[0062] The bit line mask pattern 165 can include an insulating material. The bit line mask pattern 165 can include, but is not limited to, silicon nitride, silicon oxynitride, etc.

[0063] The first active pattern AP1 and the second active pattern AP2 can be arranged on each bit line BL. The first active pattern AP1 and the second active pattern AP2 can be alternately arranged along the second direction D2.

[0064] The first active patterns AP1 may be spaced apart from each other in a first direction D1. The first active patterns AP1 may be spaced apart at regular intervals. The second active patterns AP2 may be spaced apart from each other in the first direction D1. The second active patterns AP2 may be spaced apart at regular intervals. The first active patterns AP1 may be spaced apart from the second active patterns AP2 in a second direction D2. The first active patterns AP1 and the second active patterns AP2 may be two-dimensionally arranged along the first direction D1 and the second direction D2 that intersect each other.

[0065] For example, both the first active patterns AP1 and the second active patterns AP2 may be formed of a single-crystal semiconductor material. As an example, both the first active patterns AP1 and the second active patterns AP2 may be formed of single-crystalline silicon.

[0066] Both the first active patterns AP1 and the second active patterns AP2 may have a length in the first direction D1, a width in the second direction D2, and a height in a third direction D3. Each of the first active patterns AP1 and the second active patterns AP2 may have a substantially consistent width. That is, each of the first active patterns AP1 and the second active patterns AP2 may have a substantially the same width on a first surface S1 and a second surface S2. In addition, the width of the first active patterns AP1 may be equal to the width of the second active patterns AP2.

[0067] The width of the first active patterns AP1 and the width of the second active patterns AP2 may be in the range of several nm to several tens of nm. For example, the width of the first active patterns AP1 and the width of the second active patterns AP2 may be, but are not limited to, 1 nm to 30 nm, and more preferably, 1 nm to 10 nm. The length of each of the first active patterns AP1 and the second active patterns AP2 may be greater than the line width of the bit line BL. That is, the length of each of the first active patterns AP1 and the second active patterns AP2 may be greater than the width of the bit line BL in the first direction D1.

[0068] In Figure 4 each of the first active patterns AP1 and the second active patterns AP2 includes a first surface S1 and a second surface S2 that face each other in the third direction D3. For example, the first surface S1 of the first active patterns AP1 and the second active patterns AP2 faces or confronts the bit line BL. The second surface S2 of the first active patterns AP1 and the second active patterns AP2 faces or confronts the contact pattern BC.

[0069] The first surfaces S1 of the first active pattern AP1 and the second active pattern AP2 are electrically connected and / or physically connected to the bit line BL. For example, the first surfaces S1 of the first active pattern AP1 and the second active pattern AP2 may be electrically connected and / or physically connected to the semiconductor pattern 161 of the bit line BL. Different from the illustrated example, when the semiconductor pattern 161 is omitted, the first surfaces S1 of the first active pattern AP1 and the second active pattern AP2 may be electrically connected and / or physically connected to the metal pattern 163. The second surfaces S2 of the first active pattern AP1 and the second active pattern AP2 may be electrically connected and / or physically connected to the contact pattern BC.

[0070] Each of the first active pattern AP1 and the second active pattern AP2 may include a first sidewall SS1 and a second sidewall SS2 that face each other in the second direction D2. The second sidewall SS2 of the first active pattern AP1 may face the first sidewall SS1 of the second active pattern AP2.

[0071] The first sidewall SS1 of the first active pattern AP1 may be adjacent to the first word line WL1. The second sidewall SS2 of the second active pattern AP2 may be adjacent to the second word line WL2.

[0072] Although not shown, as an example, each of the first active pattern AP1 and the second active pattern AP2 may include a first dopant region adjacent to the bit line BL and a second dopant region adjacent to the contact pattern BC. Each of the first active pattern AP1 and the second active pattern AP2 may include a channel region between the first dopant region and the second dopant region. The first dopant region and the second dopant region are regions doped with dopants in the first active pattern AP1 and the second active pattern AP2. Different from the foregoing example, each of the first active pattern AP1 and the second active pattern AP2 may not include at least one of the first dopant region and the second dopant region.

[0073] During the operation of the semiconductor memory device, the channel regions of the first active pattern AP1 and the second active pattern AP2 may be controlled by the first word line WL1, the second word line WL2, and the back gate electrode BG. Since the first active pattern AP1 and the second active pattern AP2 are made of a single crystal semiconductor material, the leakage current characteristics of the semiconductor memory device may be improved.

[0074] The back gate electrodes BG may be disposed on the bit line BL and the shielding conductive pattern SL. The back gate electrodes BG may be spaced apart from each other in the second direction D2. The back gate electrodes BG may be spaced apart at regular intervals. Each back gate electrode BG may extend in the first direction D1 across the bit line BL.

[0075] Each back gate electrode BG may be disposed between a first active pattern AP1 and a second active pattern AP2 adjacent to each other along a second direction D2. That is, the first active pattern AP1 may be disposed on one side of each back gate electrode BG, and the second active pattern AP2 may be disposed on the other side of each back gate electrode BG. The height of the back gate electrode BG in a third direction D3 may be less than or shorter than the heights of the first active pattern AP1 and the second active pattern AP2.

[0076] Each back gate electrode BG may be disposed between a second sidewall SS2 of the first active pattern AP1 and a first sidewall SS1 of the second active pattern AP2. Each back gate electrode BG may be disposed on the second sidewall SS2 of the first active pattern AP1 and the first sidewall SS1 of the second active pattern AP2.

[0077] The first active pattern AP1 may be disposed between a first word line WL1 and the back gate electrode BG. The second active pattern AP2 may be disposed between a second word line WL2 and the back gate electrode BG. A pair of the first word line WL1 and the second word line WL2 may be disposed between back gate electrodes BG adjacent to each other along the second direction D2.

[0078] The back gate electrode BG may include a first surface BG_S1 and a second surface BG_S2 opposite to each other in a third direction D3. The first surface BG_S1 of the back gate electrode is closer to the bit line BL than the second surface BG_S2 of the back gate electrode.

[0079] The back gate electrode BG may include a first surface BG_S1 and a second surface BG_S2 opposite to each other in a third direction D3. The first surface BG_S1 of the back gate electrode is closer to the bit line BL than the second surface BG_S2 of the back gate electrode. The first surface BG_S1 of the back gate electrode may face or look at the bit line BL.

[0080] The back gate electrode BG includes a conductive material and may include at least one of, for example, a conductive semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, and / or a metal.

[0081] A voltage is applied to the back gate electrode BG during operation of the semiconductor memory device, and the threshold voltage of the vertical channel transistor may be adjusted. The threshold voltage of the vertical channel transistor is adjusted, and the leakage current characteristics may be prevented from deteriorating.

[0082] The back gate cover pattern 111 may be disposed between the first active pattern AP1 and the second active pattern AP2 adjacent to each other along the second direction D2. The back gate cover pattern 111 may extend in a first direction D1 together with the back gate electrode BG. The back gate cover pattern 111 may be disposed on the second surface BG_S2 of the back gate electrode.

[0083] The back gate covering pattern 111 may include a bottom surface 111BS and a top surface 111US that face each other in a third direction D3. The bottom surface 111BS of the back gate covering pattern may face or be oriented toward the back gate electrode BG.

[0084] The back gate covering pattern 111 may be made of an insulating material. The back gate covering pattern 111 may include at least one of, for example, a silicon oxide film, a silicon oxynitride film, and / or a silicon nitride film. For example, the back gate covering pattern 111 may have an etching selectivity with respect to the buried insulating layer ( Figure 22 of 201).

[0085] The back gate insulating pattern 113 may be disposed between the back gate electrode BG and the first active pattern AP1, and between the back gate electrode BG and the second active pattern AP2. The back gate insulating pattern 113 may be disposed between the back gate covering pattern 111 and the back gate electrode BG. The back gate insulating pattern 113 may extend along the second surface BG_S2 of the back gate electrode.

[0086] When the back gate insulating pattern 113 is formed earlier than the back gate covering pattern 111, a shape different from the shape of the back gate insulating pattern 113 shown in Figures 2 to 4 may be shown. The back gate insulating pattern 113 may not extend along the second surface BG_S2 of the back gate electrode. The back gate insulating pattern 113 may be disposed between the back gate covering pattern 111 and the first active pattern AP1, and between the back gate covering pattern 111 and the second active pattern AP2.

[0087] The back gate insulating pattern 113 may be made of an insulating material. The back gate insulating pattern 113 may include, for example, a silicon oxide film, a silicon oxynitride film, a high-k insulating film having a higher dielectric constant than the silicon oxide film, or a combination thereof.

[0088] The back gate isolation pattern 115 may be disposed between the bit line BL and the back gate electrode BG. The back gate isolation pattern 115 may be disposed between the first active pattern AP1 and the second active pattern AP2 that are adjacent to each other in a second direction D2.

[0089] In the back gate isolation pattern 115, the bit line BL may extend in a first direction D1 together with the back gate electrode BG. In the back gate isolation pattern 115, the bit line BL may be disposed on the first surface BG_S1 of the back gate electrode. The thickness of the back gate isolation pattern 115 between the bit lines BL may be different from the thickness of the back gate isolation pattern 115 on the bit line BL, but the embodiments are not limited thereto.

[0090] The back gate separation pattern 115 may be made of an insulating material. The back gate separation pattern 115 may include, for example but not limited to, at least one of a silicon oxide film, a silicon oxynitride film, and / or a silicon nitride film.

[0091] The first word line WL1 and the second word line WL2 may be disposed on the bit line BL and the shield conductive pattern SL. Each of the first word line WL1 and the second word line WL2 may extend in the first direction D1. The first word line WL1 and the second word line WL2 may be alternately arranged in the second direction D2.

[0092] The first word line WL1 may be disposed on the first sidewall SS1 of the first active pattern AP1. The second word line WL2 may be disposed on the second sidewall SS2 of the second active pattern AP2. The first active pattern AP1 and the second active pattern AP2 may be disposed between the first word line WL1 and the second word line WL2 adjacent to each other along the second direction D2.

[0093] The first word line WL1 and the second word line WL2 may be spaced apart from the bit line BL and the contact pattern BC in the third direction D3. The first word line WL1 and the second word line WL2 may be located between the bit line BL and the contact pattern BC.

[0094] Each of the first word line WL1 and the second word line WL2 may have a width in the second direction D2. The width of the first word line WL1 on the bit line BL and the width of the second word line WL2 may be different from the width of the first word line WL1 on the shield conductor SL and the width of the second word line WL2.

[0095] For example, each of the first word line WL1 and the second word line WL2 may include a first part WLa of the word line and a second part WLb of the word line. The width of the first part WLa of the word line in the second direction D2 may be less than or smaller than the width of the second part WLb of the word line in the second direction D2. As an example, the first part WLa of the word line may be disposed on the bit line BL. The second part WLb of the word line may be disposed on the shield conductor SL.

[0096] Each of the first word line WL1 and the second word line WL2 may include the first part WLa of the word line and the second part WLb of the word line alternately arranged along the first direction D1. In the first word line WL1, each first active pattern AP1 may be disposed between the second parts WLb of the word line adjacent to each other along the first direction D1. In the second word line WL2, each second active pattern AP2 may be disposed between the second parts WLb of the word line adjacent to each other along the first direction D1.

[0097] Different from the illustrated example, the width of the first part WLa of the word line in the second direction D2 may be the same as the width of the second part WLb of the word line in the second direction D2.

[0098] The first word line WL1 and the second word line WL2 may include a first surface WL_S1 and a second surface WL_S2 that face each other in a third direction D3. The first surface WL_S1 of the first word line and the second word line is closer to the bit line BL than the second surface WL_S2 of the first word line and the second word line. The first surface WL_S1 of the first word line and the second word line faces or looks at the bit line BL.

[0099] The first word line WL1 will be explained as an example. As an example, the height of the first word line WL1 in the third direction D3 may be equal to the height of the back gate electrode BG in the third direction D3. As another example, the height of the first word line WL1 in the third direction D3 may be greater than the height of the back gate electrode BG in the third direction D3. As yet another example, the height of the first word line WL1 in the third direction D3 may be less than or smaller than the height of the back gate electrode BG in the third direction D3.

[0100] In addition, as an example, based on the upper surface BL_US of the bit line, the height of the first surface WL_S1 of the first word line may be equal to the height of the first surface BG_S1 of the back gate electrode. As another example, the first surface WL_S1 of the first word line may be higher than the first surface BG_S1 of the back gate electrode. As yet another example, the first surface WL_S1 of the first word line may be lower than the first surface BG_S1 of the back gate electrode.

[0101] In addition, as an example, based on the upper surface BL_US of the bit line, the height of the second surface WL_S2 of the first word line may be equal to the height of the second surface BG_S2 of the back gate electrode. As another example, the second surface WL_S2 of the first word line may be higher than the second surface BG_S2 of the back gate electrode. As yet another example, the second surface WL_S2 of the first word line may be lower than the second surface BG_S2 of the back gate electrode.

[0102] The first word line WL1 and the second word line WL2 may include a conductive material. The first word line WL1 and the second word line WL2 may include at least one of, for example, doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, and / or metal.

[0103] The first surface WL_S1 of the first word line WL1 and the second word line WL2 may be planar. Different from the illustrated example, as an example, the first surface WL_S1 of the first word line WL1 and the second word line WL2 may be recessed and rounded. As another example, each of the first word line WL1 and the second word line WL2 may have the form of a spacer. In other words, the first surface WL_S1 of the first word line WL1 and the second word line WL2 may be convexly rounded.

[0104] The second surfaces WL_S2 of the first word line WL1 and the second word line WL2 may be planar. Different from the illustrated example, the second surfaces WL_S2 of the first word line WL1 and the second word line WL2 may have a recessed and curved surface. Although the first surface BG_S1 and the second surface BG_S2 of the back gate electrode are shown as planar, the embodiments are not limited thereto.

[0105] The gate insulating pattern GOX may be disposed between the first word line WL1 and the first active pattern AP1 and between the second word line WL2 and the second active pattern AP2. The gate insulating pattern GOX may extend in the first direction D1 together with the first word line WL1 and the second word line WL2.

[0106] The gate insulating pattern GOX may include a silicon oxide film, a silicon oxynitride film, a high-k dielectric insulating film having a higher dielectric constant than the silicon oxide film, or a combination thereof.

[0107] The gate insulating pattern GOX may extend along the first sidewall SS1 of the first active pattern AP1 and may extend along the second sidewall SS2 of the second active pattern AP2. The gate insulating pattern GOX may not be disposed between the first active pattern AP1 and the gate covering pattern 143 and between the second active pattern AP2 and the gate covering pattern 143. From the perspective of the cross-sectional view, the gate insulating pattern GOX between the first active pattern AP1 and the first word line WL1 may be physically connected to the gate insulating pattern GOX between the second active pattern AP2 and the second word line WL2.

[0108] Different from the illustrated example, the gate insulating pattern GOX between the first active pattern AP1 and the first word line WL1 may be separated from the gate insulating pattern GOX between the second active pattern AP2 and the second word line WL2.

[0109] The gate covering pattern 143 may be disposed between the first word line WL1 and the contact pattern BC and between the second word line WL2 and the contact pattern BC. The gate covering pattern 143 may cover the second surface WL_S2 of the first word line WL1 and the second word line WL2, be stacked with the second surface WL_S2 of the first word line WL1 and the second word line WL2, or be on the second surface WL_S2 of the first word line WL1 and the second word line WL2. The gate covering pattern 143 may be a word line covering pattern.

[0110] The gate covering pattern 143 may include a bottom surface 143BS and an upper surface 143US that face each other in the third direction D3. The bottom surface 143BS of the gate covering pattern may be stacked with the first word line WL1 and the second word line WL2.

[0111] The gate insulating pattern GOX may extend along the bottom surface 143BS of the gate covering pattern. The gate insulating pattern GOX may be disposed between the bottom surface 143BS of the gate covering pattern and the second surface WL_S2 of the first word line and between the bottom surface 143BS of the gate covering pattern and the second surface WL_S2 of the second word line.

[0112] When the gate insulating pattern GOX is formed earlier than the gate covering pattern 143, a shape different from the shape of the gate insulating pattern GOX shown in Figures 2 to 4 may be shown. The gate insulating pattern GOX may not extend along the bottom surface 143BS of the gate covering pattern. The gate insulating pattern GOX may be disposed between the first active pattern AP1 and the first word line WL1 and between the second active pattern AP2 and the second word line WL2. The gate insulating pattern GOX may not be disposed between the bottom surface 143BS of the gate covering pattern and the second surface WL_S2 of the first word line and between the bottom surface 143BS of the gate covering pattern and the second surface WL_S2 of the second word line. As an example, the gate insulating pattern GOX may extend along the upper surface 143US of the gate covering pattern. The gate insulating pattern GOX on the upper surface 143US of the gate covering pattern may not be removed during the formation of the contact pattern BC and the storage electrode 251. As another example, the gate insulating pattern GOX may not extend along the upper surface 143US of the gate covering pattern. The gate insulating pattern GOX on the upper surface 143US of the gate covering pattern may be removed during the formation of the contact pattern BC and the storage electrode 251.

[0113] The gate covering pattern 143 may include at least one of, for example, a silicon oxide film, a silicon oxynitride film, and / or a silicon nitride film. Different from the shown example, the gate covering pattern 143 may include a plurality of insulating films.

[0114] The gate separation pattern GSS may be disposed on the bit line BL. The gate separation pattern GSS may be disposed between the bit line BL and the contact pattern BC. The gate separation pattern GSS may be in contact with the bit line BL.

[0115] The gate separation pattern GSS may be disposed between the first word line WL1 and the second word line WL2 adjacent to each other along the second direction D2. The first word line WL1 and the second word line WL2 may be separated by the gate separation pattern GSS. The gate separation pattern GSS may extend in the first direction D1 between the first word line WL1 and the second word line WL2.

[0116] The first word line WL1 may be disposed between the gate separation pattern GSS and the first active pattern AP1. The second word line WL2 may be disposed between the gate separation pattern GSS and the second active pattern AP2.

[0117] The gate separation pattern GSS may include a horizontal portion GSS_H and a protruding portion GSS_P. The protruding portion GSS_P of the gate separation pattern may protrude from the horizontal portion GSS_H of the gate separation pattern in the third direction D3.

[0118] The horizontal portion GSS_H of the gate separation pattern may be closer to the bit line BL than the protruding portion GSS_P of the gate separation pattern. The horizontal portion GSS_H of the gate separation pattern may be in contact with the bit line BL. The width of the horizontal portion GSS_H of the gate separation pattern in the second direction D2 is greater than the width of the protruding portion GSS_P of the gate separation pattern in the second direction D2.

[0119] The protruding portion GSS_P of the gate separation pattern GSS may be disposed between the sidewalls of the first word line WL1 and the second word line WL2 facing each other. The horizontal portion GSS_H of the gate separation pattern GSS may cover, overlap with, or be on the first surface WL_S1 of the first word line WL1 and the second word line WL2.

[0120] The first word line WL1 and the second word line WL2 are disposed on the horizontal portion GSS_H of the gate separation pattern. The first word line WL1 and the second word line WL2 may be in a form sitting on the horizontal portion GSS_H of the gate separation pattern GSS. The first word line WL1 and the second word line WL2 may be disposed between the horizontal portion GSS_H of the gate separation pattern GSS and the contact pattern BC.

[0121] The gate separation pattern GSS may be made of an insulating material. Different from the illustrated example, the gate separation pattern GSS may include a plurality of insulating films.

[0122] The contact structure BC may be disposed on the first active pattern AP1 and the second active pattern AP2. The contact structure BC may be electrically connected and / or physically connected to each of the first active pattern AP1 and the second active pattern AP2. The contact structure BC may be electrically connected and / or physically connected to the second surface S2 of the first active pattern AP1 and the second active pattern AP2.

[0123] The contact structure BC may protrude in the third direction D3 beyond the upper surface 111US of the back gate covering pattern and the upper surface 143US of the gate covering pattern. From the perspective of a plan view, each contact structure BC may have various shapes (such as circular, oval, rectangular, square, rhombus, and / or hexagonal).

[0124] The contact structure BC may include an upper surface BC_US and a bottom surface BC_BS that face each other in the third direction D3. The bottom surface BC_BS of the contact structure may be electrically connected and / or physically connected to or in contact with the first active pattern AP1 and the second active pattern AP2. The bottom surface BC_BS of the contact structure may be electrically connected and / or physically connected to or in contact with the second surface S2 of the first active pattern AP1 and the second active pattern AP2.

[0125] The upper surface BC_US of the contact structure may protrude beyond the back gate covering pattern 111 and the gate covering pattern 143 in the third direction D3. Based on the upper surface BL_US of the bit line, the upper surface BC_US of the contact structure is higher than the upper surface 111US of the back gate covering pattern and the upper surface 143US of the gate covering pattern.

[0126] The contact structure BC may include sidewalls BC_SW, and the sidewalls BC_SW electrically connect and / or physically connect the upper surface BC_US and the bottom surface BC_BS of the contact structure. From the perspective of the cross-sectional view, the sidewalls BC_SW of the contact structure extend in the third direction D3.

[0127] The contact structure BC may include a conductive material. The contact structure BC may include a contact plug pattern BC_PL made of a conductive material. The contact plug pattern BC_PL may include at least one of, for example, a conductive semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, and / or a metal. Although the contact plug pattern BC_PL is shown as a single film, this is only for ease of explanation, and the embodiments are not limited thereto.

[0128] In a semiconductor memory device according to some embodiments, the sidewalls BC_SW of the contact structure may be defined by the contact plug pattern BC_PL. The contact plug pattern BC_PL may include the sidewalls BC_SW of the contact structure. The upper surface BC_US and the bottom surface BC_BS of the contact structure may be defined by the contact plug pattern BC_PL.

[0129] The data storage pattern DSP may be disposed on each contact structure BC. The data storage pattern DSP may be disposed on each of the upper surfaces BC_US of the contact structure.

[0130] The data storage pattern DSP may be electrically connected to each of the first active pattern AP1 and the second active pattern AP2. As Figure 1 shown, the data storage pattern DSP may be arranged in a matrix form along the first direction D1 and the second direction D2.

[0131] As an example, the data storage pattern DSP may be a capacitor. The data storage pattern DSP may include a capacitor dielectric film 253 disposed between the storage electrode 251 and the plate electrode 255. The storage electrode 251 may be the lower electrode of the capacitor. The plate electrode 255 may be the upper electrode of the capacitor.

[0132] The storage electrode 251 may extend long in the third direction D3. The storage electrode 251 may have, for example, a column shape. The storage electrode 251 may be electrically and / or physically connected to the upper surface BC_US of the contact structure.

[0133] The storage electrode 251 may include a bottom surface 251BS that looks at or faces the contact structure BC. The bottom surface 251BS of the storage electrode is electrically and / or physically connected to the upper surface BC_US of the contact structure.

[0134] For example, the width W12 of the bottom surface 251BS of the storage electrode in the second direction D2 may be equal to the width W11 of the upper surface BC_US of the contact structure in the second direction D2. Although not shown, the width of the bottom surface 251BS of the storage electrode in the first direction D1 may be equal to the width of the upper surface BC_US of the contact structure in the first direction D1.

[0135] The capacitor dielectric film 253 may be disposed on the storage electrode 251. The capacitor dielectric film 253 may extend along the sidewall of the storage electrode 251.

[0136] The capacitor dielectric film 253 may extend along the sidewall BC_SW of the contact structure. For example, the capacitor dielectric film 253 may be in contact with the sidewall BC_SW of the contact structure. The capacitor dielectric film 253 may be in contact with the contact plug pattern BC_PL.

[0137] The capacitor dielectric film 253 may extend along the upper surface 111US of the back gate covering pattern 111 and the upper surface 143US of the gate covering pattern. The capacitor dielectric film 253 may be in contact with the back gate covering pattern 111 and the gate covering pattern 143. For example, the capacitor dielectric film 253 may be in contact with the upper surface 111US of the back gate covering pattern and the upper surface 143US of the gate covering pattern.

[0138] Different from the example shown, as an example, when the back gate insulating pattern 113 extends along the upper surface 111US of the back gate covering pattern, the capacitor dielectric film 253 may not be in contact with the upper surface 111US of the back gate covering pattern. As another example, when the gate insulating pattern GOX extends along the upper surface 143US of the gate covering pattern, the capacitor dielectric film 253 may not be in contact with the upper surface 143US of the gate covering pattern.

[0139] The plate electrode 255 may be disposed on the capacitor dielectric film 253. A part of the plate electrode 255 may protrude toward the substrate 100 beyond the upper surface BS_US of the contact structure.

[0140] From the perspective of the cross-sectional view, the plate electrode 255 may include a bottom surface 255BS that looks at or faces the bit line BL. The part of the plate electrode 255 that protrudes toward the substrate 100 beyond the upper surface BS_US of the contact structure may include the bottom surface 255BS of the plate electrode.

[0141] On the upper surface BL_US of the bit line, the bottom surface 255BS of the plate electrode is lower than the upper surface BS_US of the contact structure. The height H12 from the upper surface BL_US of the bit line to the upper surface BS_US of the contact structure is greater than the height H11 from the upper surface BL_US of the bit line to the bottom surface 255BS of the plate electrode.

[0142] The plate electrode 255 may cover at least a part of the side wall BC_SW of the contact structure, overlap with at least a part of the side wall BC_SW of the contact structure, or be on at least a part of the side wall BC_SW of the contact structure. In other words, from the perspective of the cross-sectional view, the plate electrode 255 may overlap with at least a part of the side wall BC_SW of the contact structure in the second direction D2. Although not shown, the plate electrode 255 may overlap with at least a part of the side wall BC_SW of the contact structure in the first direction D1.

[0143] In a semiconductor memory device according to some embodiments, the plate electrode 255 may cover a part of the side wall BC_SW of the contact structure, overlap with a part of the side wall BC_SW of the contact structure, or be on a part of the side wall BC_SW of the contact structure. Based on the upper surface BL_US of the bit line, the bottom surface 255BS of the plate electrode may be higher than the bottom surface BC_BS of the contact structure.

[0144] Both the storage electrode 251 and the plate electrode 255 may include at least one of, for example, a conductive semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbon nitride, a conductive metal silicide, a conductive metal oxide, and / or a metal. The capacitor dielectric film 253 may include at least one of a ferroelectric material, an antiferroelectric material, and / or a paraelectric material. For example, the capacitor dielectric film 253 may include one of a ferroelectric material, an antiferroelectric material, a paraelectric material, a combination of a ferroelectric material and an antiferroelectric material, a combination of a ferroelectric material and a paraelectric material, a combination of a paraelectric material and an antiferroelectric material, and / or a combination of a ferroelectric material, an antiferroelectric material, and a paraelectric material.

[0145] In contrast, the data storage pattern DSP can be a variable resistance pattern that can be switched between two resistance states by applying an electrical pulse to the memory element. For example, the data storage pattern DSP can include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material.

[0146] At least one or more lower electrode supports 257 and 258 can be disposed on the first active pattern AP1 and the second active pattern AP2. At least one or more lower electrode supports 257 and 258 can support the storage electrode 251.

[0147] A plurality of lower electrode supports 257 and 258 can be disposed on the first active pattern AP1 and the second active pattern AP2. The plurality of lower electrode supports 257 and 258 include a first lower electrode support 257 and a second lower electrode support 258 that are sequentially disposed on the first active pattern AP1 and the second active pattern AP2. The first lower electrode support 257 and the second lower electrode support 258 can be spaced apart from each other in the third direction D3.

[0148] Different from the illustrated example, one lower electrode support for supporting the storage electrode 251 can be provided.

[0149] The first lower electrode support 257 will be explained as an example. The first lower electrode support 257 can include an upper surface 257US and a bottom surface 257BS that face each other in the third direction D3. The bottom surface 257BS of the first lower electrode support can face or be opposite to the bit line BL.

[0150] In the following description, the shape of the bottom surface 257BS of the first lower electrode support and the shape of the upper surface 257US of the first lower electrode support can be the shape between adjacent storage electrodes 251.

[0151] In Figure 5 , both the bottom surface 257BS of the first lower electrode support and the upper surface 257US of the first lower electrode support can be flat.

[0152] In Figures 6 to 9 , at least one of the bottom surface 257BS of the first lower electrode support and the upper surface 257US of the first lower electrode support can include a curved surface.

[0153] In Figure 6 and Figure 7 , the upper surface 257US of the first lower electrode support can be flat. The bottom surface 257BS of the first lower electrode support can include a curved surface. Different from the illustrated example, the upper surface 257US of the first lower electrode support can include a curved surface, and the bottom surface 257BS of the first lower electrode support can be flat.

[0154] In Figure 6 , the bottom surface 257BS of the first lower electrode support may include a convexly curved surface. In Figure 7 the bottom surface 257BS of the first lower electrode support may include a concavely curved surface.

[0155] In Figure 8 and Figure 9 the bottom surface 257BS and the upper surface 257US of the first lower electrode support may both include curved surfaces.

[0156] In Figure 8 the upper surface 257US of the first lower electrode support may include a convexly curved surface. The bottom surface 257BS of the first lower electrode support may include a concavely curved surface. Different from the illustrated example, the upper surface 257US of the first lower electrode support may include a concavely curved surface, and the bottom surface 257BS of the first lower electrode support may include a convexly curved surface.

[0157] In Figure 9 the bottom surface 257BS and the upper surface 257US of the first lower electrode support may both include convexly curved surfaces. Different from the illustrated example, the bottom surface 257BS and the upper surface 257US of the first lower electrode support may both include concavely curved surfaces.

[0158] The capacitor dielectric film 253 may be disposed on the first lower electrode support 257 and the second lower electrode support 258. The capacitor dielectric film 253 may extend along the bottom surface 257BS and the upper surface 257US of the first lower electrode support. The capacitor dielectric film 253 may extend along the bottom surface and the upper surface of the second lower electrode support 258.

[0159] Each of the first lower electrode support 257 and the second lower electrode support 258 may include at least one of, for example, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonate, silicon oxynitride, and / or silicon oxycarbonitride.

[0160] Figures 10 to 14 are diagrams for explaining a semiconductor memory device according to some embodiments. For ease of explanation, the explanation will focus on points different from the points explained using Figures 1 to 9 The points explained.

[0161] For reference, Figures 10 to 14 are respectively Figure 2 enlarged views of part P of

[0162] Referring to Figure 10, in a semiconductor memory device according to some embodiments, the plate electrode 255 may cover the entire sidewall BC_SW of the contact structure, be stacked with the entire sidewall BC_SW of the contact structure, or be on the entire sidewall BC_SW of the contact structure.

[0163] Based on the upper surface BL_US of the bit line, the bottom surface 255BS of the plate electrode may be lower than or equal to the lowermost portion of the sidewall BC_SW of the contact structure.

[0164] A part of the capacitor dielectric film 253 may enter or extend into the gate covering pattern 143 and the back gate covering pattern 111.

[0165] Refer to Figures 11 to 13 , in a semiconductor memory device according to some embodiments, the width of the contact structure BC may change as the contact structure BC moves away from the bottom surface BC_BS of the contact structure.

[0166] In Figure 11 , the width of the contact structure BC may increase as it moves away from the bottom surface BC_BS of the contact structure.

[0167] In Figure 12 , the width of the contact structure BC may decrease as it moves away from the bottom surface BC_BS of the contact structure.

[0168] In Figure 13 , the width of the contact structure BC may increase and then decrease as it moves away from the bottom surface BC_BS of the contact structure.

[0169] Refer to Figure 14 , in a semiconductor memory device according to some embodiments, the contact structure BC may include a contact plug pattern BC_PL and a contact insulating spacer BC_SP.

[0170] The contact insulating spacer BC_SP may extend along the sidewall of the contact plug pattern BC_PL. The sidewall BC_SW of the contact structure may be defined by the contact insulating spacer BC_SP. The contact insulating spacer BC_SP may include the sidewall BC_SW of the contact structure. The capacitor dielectric film 253 extending along the sidewall BC_SW of the contact structure may contact the contact insulating spacer BC_SP.

[0171] The upper surface BC_US and the bottom surface BC_BS of the contact structure may be defined by the contact plug pattern BC_PL and the contact insulating spacer BC_SP.

[0172] The contact insulating spacer BC_SP includes an insulating material. The contact insulating spacer BC_SP may include at least one of, for example but not limited to, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonate, silicon oxynitride, and / or silicon oxycarbonitride.

[0173] Figure 15 and Figure 16 are diagrams for explaining a semiconductor memory device according to some embodiments. Figure 17 and Figure 18 are diagrams for explaining a semiconductor memory device according to some embodiments. For ease of explanation, the explanation will focus on points different from those explained using Figures 1 to 9 the points explained.

[0174] Referring to Figure 15 and Figure 16 in a semiconductor memory device according to some embodiments, the shielding conductive pattern SL may include a shielding conductive plate SLh and a plurality of shielding wire patterns SLp.

[0175] The shielding conductive plate SLh may have a flat plate shape. The shielding wire patterns SLp may protrude from the shielding conductive plate SLh in a third direction D3. The shielding wire patterns SLp are directly connected to the shielding conductive plate SLh.

[0176] The shielding insulating gasket 171 may extend along the contours of the shielding conductive plate SLh and the shielding wire patterns SLp.

[0177] The shielding insulating cover film 175 may be disposed between the shielding conductive plate SLh and the peripheral connection structures 242a and 242b. The shielding insulating cover film 175 may be in contact with the shielding conductive plate SLh.

[0178] The bit line BL may be disposed on the shielding conductive pattern SL. The bit line BL may be disposed on the shielding conductive plate SLh.

[0179] Referring to Figure 17 and Figure 18 a semiconductor memory device according to some embodiments may further include a bonding insulating film 264 disposed between the peripheral connection structures 242a and 242b and the shielding structures SL, 171, and 175.

[0180] The bonding insulating film 264 may include, for example, silicon carbonitride (SiCN).

[0181] Unlike the illustrated example, the third peripheral upper insulating film 265 may not be disposed on the peripheral connection wiring 242b.

[0182] Figure 19 and Figure 20 are diagrams for explaining a semiconductor memory device according to some embodiments. For ease of explanation, the explanation will focus on points different from those explained using Figures 1 to 18 the points explained.

[0183] Referring to Figure 19, in a semiconductor memory device according to some embodiments, a first active pattern AP1 and a second active pattern AP2 may be alternately arranged in a diagonal direction with respect to a first direction D1 and a second direction D2.

[0184] From a plan view perspective, each of the first active pattern AP1 and the second active pattern AP2 may have a parallelogram shape or a rhombus shape. Since the first active pattern AP1 and the second active pattern AP2 are arranged in a diagonal direction, the coupling between the first active pattern AP1 and the second active pattern AP2 facing each other along the second direction D2 can be reduced.

[0185] Refer to Figure 20 , in a semiconductor memory device according to some embodiments, from a plan view perspective, a contact structure BC and a data storage pattern DSP may be arranged in a zigzag shape or a honeycomb shape.

[0186] Figures 21 to 57 is a diagram for explaining a method for manufacturing a semiconductor memory device according to some embodiments. Accordingly, the semiconductor memory device described using Figures 1 to 9 can be manufactured.

[0187] As a reference, Figures 21 to 46 the cutting line and the coordinate system shown in Figure 1 are in a state where the cutting line and the coordinate system in

[0188] Refer to Figures 21 to 23 , a sub-substrate structure including a sub-substrate 200, a buried insulating layer 201, and an active layer 202 may be provided.

[0189] The buried insulating layer 201 and the active layer 202 may be provided on the sub-substrate 200. The sub-substrate 200, the buried insulating layer 201, and the active layer 202 may be a silicon-on-insulator substrate (i.e., an SOI substrate). The sub-substrate 200 may be a semiconductor substrate. The sub-substrate 200 may be, for example, a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. In the following description, the sub-substrate 200 will be described as a silicon substrate.

[0190] The buried insulating layer 201 may be a buried oxide (BOX) formed by a SIMOX (separation by implanted oxygen) method or a bonding and layer transfer method. In contrast, the buried insulating layer 201 may be an insulating film formed by chemical vapor deposition. The buried insulating layer 201 may include, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and / or a low dielectric constant insulating film.

[0191] The active layer 202 may be a single-crystalline semiconductor film. The active layer 202 may be, for example, a single-crystalline silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The active layer 202 may have a first surface and a second surface that face each other in the third direction D3, and the second surface of the active layer 202 may be in contact with the buried insulating layer 201.

[0192] Referring Figures 24 to 26 , a mask pattern MP1 may be formed on the active layer 202.

[0193] The mask pattern MP1 may have a linear opening extending along the first direction D1. The mask pattern MP1 may include a first lower mask film 11 and a first upper mask film 12 stacked in sequence. The first upper mask film 12 may be made of a material having an etching selectivity with respect to the first lower mask film 11. As an example, the first lower mask film 11 may include silicon oxide, and the first upper mask film 12 may include silicon nitride, but the embodiments are not limited thereto.

[0194] Subsequently, the active layer 202 may be anisotropically etched by using the mask pattern MP1 as an etching mask. Accordingly, a back gate trench BG_T extending in the first direction D1 may be formed on the active layer 202. The back gate trench BG_T may expose the buried insulating layer 201 and may be spaced apart at regular intervals in the second direction D2.

[0195] Different from the illustrated example, at least a part of the buried insulating layer 201 may be removed while forming the back gate trench BG_T.

[0196] Referring Figures 27 to 29 , a back gate covering pattern 111 may be formed in the back gate trench BG_T.

[0197] The back gate covering pattern 111 may partially fill the back gate trench BG_T. The back gate covering pattern 111 may extend long in the first direction D1.

[0198] Thereafter, a back gate insulating pattern 113 and a back gate electrode BG may be formed in the back gate trench BG_T. The back gate insulating pattern 113 and the back gate electrode BG may be formed on the back gate covering pattern 111.

[0199] More specifically, the back gate insulating pattern 113 may be formed along the sidewalls of the back gate trench BG_T and the upper surface of the mask pattern MP. The back gate insulating pattern 113 may be formed along the exposed surface of the back gate covering pattern 111. A back gate conductive film may be formed on the back gate insulating pattern 113. The back gate conductive film may fill the back gate trench BG_T.

[0200] Subsequently, the back gate conductive film may be etched to form a back gate electrode BG extending in the first direction D1. The back gate electrode BG may partially fill the back gate trench BG_T.

[0201] Meanwhile, according to some embodiments, a gas phase doping (GPD) process or a plasma doping (PLAD) process may be performed before forming the back gate insulating pattern 113. Through the foregoing processes, the active layer 202 exposed by the back gate trench BG_T may be doped with impurities.

[0202] Referring to Figures 30 to 32 , a back gate isolation pattern 115 may be formed on the back gate electrode BG.

[0203] The back gate isolation pattern 115 may fill the remaining portion of the back gate trench BG_T. When the back gate isolation pattern 115 and the back gate insulating pattern 113 are formed of the same material (e.g., silicon oxide), the back gate insulating pattern 113 on the upper surface of the mask pattern MP may be removed while the back gate isolation pattern 115 is being formed.

[0204] Meanwhile, before forming the back gate isolation pattern 115, a gas phase doping (GPD) process or a plasma doping (PLAD) process may be performed. Accordingly, the active layer 202 may be doped with impurities through the back gate trench BG_T in which the back gate electrode BG is formed.

[0205] Referring to Figures 33 to 35 , after forming the back gate isolation pattern 115, the first upper mask film 12 may be removed.

[0206] The back gate isolation pattern 115 may have a shape protruding above the upper surface of the first lower mask film 11.

[0207] Then, a spacer film 120 may be formed along the upper surface of the first lower mask film 11, the sidewalls of the back gate insulating pattern 113, and the upper surface of the back gate isolation pattern 115. The spacer film 120 may be formed to have a uniform thickness. The width of the active pattern of the vertical channel transistor may be determined according to the deposition thickness of the spacer film 120.

[0208] The spacer film 120 may be formed of an insulating material. The spacer film 120 may include, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbide (SiC), silicon carbonitride (SiCN), and / or a combination thereof.

[0209] Referring to Figures 36 to 38 , by performing an anisotropic etching process on the spacer film 120, a pair of spacer patterns 121 may be formed on the sidewalls of the back gate insulating pattern 113.

[0210] An anisotropic etching process can be performed on the active layer 202 by using the spacer pattern 121 as an etching mask. Accordingly, a pair of pre-active patterns PAP separated from each other can be formed on both sides of each back gate insulating pattern 113. When the pre-active patterns PAP are formed, the buried insulating layer 201 can be exposed.

[0211] The pre-active patterns PAP can have a line shape extending in the first direction D1 together with the back gate electrode BG. While the pre-active patterns PAP are being formed, word line trenches WL_T can be formed between the pre-active patterns PAP adjacent to each other in the second direction D2.

[0212] Referring to Figures 36 to 41 , a sacrificial film filling the word line trenches WL_T can be formed. A mask pattern can be formed on the sacrificial film. The mask pattern can have a line shape extending in the second direction D2. As another example, the mask pattern can have a form of lines extending in a diagonal direction with respect to the first direction D1 and the second direction D2. The sacrificial film can be etched by using the mask pattern as an etching mask to form a sacrificial opening inside the sacrificial film.

[0213] By etching the pre-active patterns PAP exposed to the sacrificial opening, a first active pattern AP1 and a second active pattern AP2 can be formed on both sides of the back gate electrode BG. The first active pattern AP1 can be formed on the first sidewall of the back gate electrode BG to be spaced apart from each other in the first direction D1. The second active pattern AP2 can be formed on the second sidewall of the back gate electrode BG to be spaced apart from each other in the first direction D1. Since the first active pattern AP1 and the second active pattern AP2 are formed, a part of the back gate insulating pattern 113 can be exposed by the sacrificial opening.

[0214] Next, the sacrificial film, the mask pattern, the spacer pattern 121, and the first lower mask film 11 can be removed. Accordingly, the first active pattern AP1 and the second active pattern AP2 can be exposed. In addition, the buried insulating layer 201 can be exposed.

[0215] Referring to Figures 42 to 44 , a gate capping pattern 143 can be formed inside the word line trenches ( Figure 37 and Figure 38 WL_T).

[0216] The gate capping pattern 143 can partially fill the word line trenches WL_T. The gate capping pattern 143 can be formed on the buried insulating layer 201.

[0217] Next, a gate insulating pattern GOX can be formed along the sidewalls of the first active pattern AP1, the sidewalls of the second active pattern AP2, and the upper surface of the back gate separation pattern 115. The gate insulating pattern GOX can be formed along the exposed surface of the gate capping pattern 143.

[0218] The gate insulating pattern GOX may be formed, for example but not limited to, by using at least one of physical vapor deposition (PVD), thermal chemical vapor deposition (thermal CVD), low-pressure chemical vapor deposition (LP-CVD), plasma-enhanced chemical vapor deposition (PE-CVD), or atomic layer deposition (ALD) techniques.

[0219] Subsequently, a first word line WL1 and a second word line WL2 may be formed on the gate insulating pattern GOX. The first word line WL1 and the second word line WL2 may be formed on sidewalls of the first active pattern AP1 and the second active pattern AP2.

[0220] The formation of the first word line WL1 and the second word line WL2 may include: depositing a gate conductive film on the gate insulating pattern GOX, and then performing an anisotropic etching process on the gate conductive film. Here, the deposition thickness of the gate conductive film may be less than half of the width of the word line trench ( Figure 36 and Figure 37 WL_T).

[0221] During the anisotropic etching process on the gate conductive film, the gate insulating pattern GOX may be used as an etch stop film. Different from the illustrated example, the exposed gate insulating pattern GOX between the first word line WL1 and the second word line WL2 may be removed by etching.

[0222] The upper surfaces of the first word line WL1 and the second word line WL2 may be located at a height lower than the upper surfaces of the first active pattern AP1 and the second active pattern AP2 (i.e., closer to the sub-substrate 200).

[0223] As an example, after forming the first word line WL1 and the second word line WL2, a gas phase doping (GPD) process or a plasma doping (PLAD) process may be performed. Thus, impurities may be doped into the first active pattern AP1 and the second active pattern AP2 through the gate insulating pattern GOX exposed by the first word line WL1 and the second word line WL2.

[0224] Subsequently, a gate separation pattern GSS may be formed on the first word line WL1 and the second word line WL2.

[0225] For example, the upper surface of the gate separation pattern GSS may be set on the same plane as the upper surface of the back gate separation pattern 115.

[0226] Referring to Figure 45 and Figure 46 , a bit line BL extending in the second direction D2 may be formed on the gate separation pattern GSS and the back gate separation pattern 115.

[0227] The bit line BL may include a bit line mask pattern 165, a metal pattern 163, and a semiconductor pattern 161. During the formation of the bit line BL, a part of the back gate isolation pattern 115 and a part of the gate isolation pattern GSS may be etched.

[0228] Subsequently, a shielding conductive pattern SL may be formed between the bit lines BL adjacent in the first direction D1.

[0229] More specifically, a shielding insulating gasket 171 may be formed along the contour of the bit line BL. The shielding insulating gasket 171 may define a shielding region between the bit lines BL adjacent in the first direction D1. A shielding conductive film may be formed on the shielding insulating gasket 171. The shielding conductive film may fill the shielding region defined by the shielding insulating gasket 171. At least a part of the shielding conductive film may be recessed to form the shielding conductive pattern SL. As an example, when the shielding conductive film formed on the bit line BL is completely removed, the shielding conductive pattern SL may include a plurality of linear shielding wire patterns SLp. As another example, when a part or all of the shielding conductive film formed on the bit line BL is not removed, the shielding conductive pattern SL may include a flat shielding conductive plate ( Figure 15 and Figure 16 SLh) and a plurality of linear shielding wire patterns SLp. A shielding insulating cover film 175 may be formed on the shielding conductive pattern SL.

[0230] Referring to Figure 47 a peripheral gate structure PG may be formed on the substrate 100.

[0231] A sub-substrate 200 on which a back gate electrode BG, word lines WL1 and WL2, active patterns AP1 and AP2, a bit line BL, and a shielding conductive pattern SL are formed may be bonded to the substrate 100. The substrate 100 and the sub-substrate 200 may be bonded such that the bit line BL and the peripheral gate structure PG face each other.

[0232] After bonding the substrate 100 to the sub-substrate 200, a back grinding process of removing a part of the sub-substrate 200 may be performed.

[0233] Then, an electrode mask pattern 20 and a metal mask pattern 15 may be formed on the sub-substrate 200. The electrode mask pattern 20 may be formed at a position corresponding to the storage electrode 251 of Figure 2 . The metal mask pattern 15 may partially or completely fill the space between the electrode mask patterns 20.

[0234] The electrode mask pattern 20 may comprise, for example, an insulating material. The electrode mask pattern 20 may comprise at least one of an inorganic material and an organic material. The metal mask pattern 15 may comprise a metal. For example, the metal mask pattern 15 may comprise a metal that can be used as a catalyst in metal-assisted chemical etching (MACE). The metal mask pattern 15 may comprise at least one of, but not limited to, gold (Au), platinum (Pt), palladium (Pd), silver (Ag), nickel (Ni), aluminum (Al), copper (Cu), and / or iron (Fe).

[0235] Referring Figure 48 , metal-assisted chemical etching (MACE) can be used to etch a portion of the sub-substrate 200 to form a pre-semiconductor molding pattern 251_PMP.

[0236] The pre-semiconductor molding pattern 251_PMP can be formed by removing the sub-substrate 200 that overlaps the metal mask pattern 15 in the third direction D3.

[0237] Referring Figure 49 , a lower sacrificial molding insulating film 259SC, a first lower electrode support film 257L, an upper sacrificial molding insulating film 259SC, and a second lower electrode support film 258L can be sequentially formed on the metal mask pattern 15.

[0238] While the lower sacrificial molding insulating film 259SC, the first lower electrode support film 257L, the upper sacrificial molding insulating film 259SC, and the second lower electrode support film 258L are being formed, the electrode mask pattern 20 can be removed.

[0239] More specifically, the lower sacrificial molding insulating film 259SC can be formed. For example, a lower sacrificial insulating film can be formed on the metal mask pattern 15. The lower sacrificial insulating film can cover the entire sidewall of the pre-semiconductor molding pattern 251_PMP, overlap the entire sidewall of the pre-semiconductor molding pattern 251_PMP, or be on the entire sidewall of the pre-semiconductor molding pattern 251_PMP. The lower sacrificial molding insulating film 259SC can be formed by making a portion of the lower sacrificial insulating film recessed.

[0240] Subsequently, the first lower electrode support film 257L can be formed on the lower sacrificial molding insulating film 259SC. For example, a pre-lower electrode support film can be formed on the lower sacrificial molding insulating film 259SC. The first lower electrode support film 257L can be formed on the lower sacrificial molding insulating film 259SC by making a portion of the pre-lower electrode support film recessed.

[0241] Subsequently, the upper sacrificial molding insulating film 259SC can be formed on the first lower electrode support film 257L. The formation of the upper sacrificial molding insulating film 259SC can be substantially the same as the process of forming the lower sacrificial molding insulating film 259SC.

[0242] Subsequently, a second lower electrode support film 258L can be formed on the upper sacrificial molding insulating film 259SC.

[0243] The upper sacrificial molding insulating film 259SC and the lower sacrificial molding insulating film 259SC can include an insulating material. The upper sacrificial molding insulating film 259SC and the lower sacrificial molding insulating film 259SC can include a material having an etching selectivity with respect to silicon.

[0244] Referring to Figure 49 and Figure 50 , the first lower electrode support 257 and the second lower electrode support 258 can be formed by patterning the first lower electrode support film 257L and the second lower electrode support film 258L.

[0245] While the first lower electrode support 257 and the second lower electrode support 258 are being formed, a part of the upper sacrificial molding insulating film 259SC and a part of the lower sacrificial molding insulating film 259SC can also be removed.

[0246] Referring to Figure 50 and Figure 51 , the upper sacrificial molding insulating film 259SC and the lower sacrificial molding insulating film 259SC are removed.

[0247] The upper sacrificial molding insulating film 259SC and the lower sacrificial molding insulating film 259SC are removed, and a molding space can be formed between the first lower electrode support 257 and the second lower electrode support 258. The molding space can be an empty space not filled with material.

[0248] Referring to Figure 51 and Figure 52 , the remaining portion of the sub-substrate 200 can be etched by using metal-assisted chemical etching (MACE) to form a semiconductor molding pattern 251_MP.

[0249] The remaining portion of the sub-substrate 200 that overlaps with the metal mask pattern 15 in the third direction D3 can be removed to form a semiconductor molding pattern 251_MP. A plurality of semiconductor molding patterns 251_MP can be formed on the buried insulating layer 201.

[0250] By removing the sub-substrate 200 that overlaps with the metal mask pattern 15 in the third direction D3 by using metal-assisted chemical etching (MACE), a semiconductor molding pattern 251_MP can be formed on the buried insulating layer 201.

[0251] When the aspect ratio of the semiconductor molding pattern 251_MP increases, the semiconductor molding pattern 251_MP can be bent. To prevent the semiconductor molding pattern 251_MP from bending, the first lower electrode support 257 and the second lower electrode support 258 explained by using Figures 48 to 51 can be formed.

[0252] When the semiconductor molding pattern 251_MP has an aspect ratio such that the semiconductor molding pattern 251_MP does not bend, the processes of forming the first lower electrode support 257 and the second lower electrode support 258 may be omitted.

[0253] Referring Figure 52 and Figure 53 , the metal mask pattern 15 used in the metal-assisted chemical etching (MACE) process may be removed.

[0254] The metal mask pattern 15 may be removed to expose the buried insulating layer 201.

[0255] Then, a sacrificial molding film 259 may be formed on the buried insulating layer 201. The sacrificial molding film 259 may wrap the semiconductor molding pattern 251_MP. The sacrificial molding film 259 may cover the sidewalls of the semiconductor molding pattern 251_MP, be stacked with the sidewalls of the semiconductor molding pattern 251_MP, or be on the sidewalls of the semiconductor molding pattern 251_MP. The sacrificial molding film 259 may fill the molding space formed by removing the sub-substrate ( Figures 47 to 52 200). The sacrificial molding film 259 may include an insulating material.

[0256] Referring Figure 53 and Figure 54 , the semiconductor molding pattern 251_MP may be removed to form a lower electrode hole 251H inside the sacrificial molding film 259.

[0257] The semiconductor molding pattern 251_MP is removed, and the lower electrode hole 251H may expose the buried insulating layer 201.

[0258] Referring Figure 54 and Figure 55 , by removing a part of the buried insulating layer 201, the lower electrode hole 251H may extend to the first active pattern AP1 and the second active pattern AP2.

[0259] By removing at least a part of the buried insulating layer 201 that overlaps with the lower electrode hole 251H in the third direction D3, a lower electrode hole 251H exposing the first active pattern AP1 and the second active pattern AP2 may be formed. The lower electrode hole 251H may be formed inside the sacrificial molding film 259 and the buried insulating layer 201.

[0260] Referring Figure 56 , a contact structure BC and a storage electrode 251 may be sequentially formed inside the lower electrode hole 251H.

[0261] The contact structure BC and the storage electrode 251 may be formed inside the sacrificial molding film 259 and the buried insulating layer 201.

[0262] Referring to Figure 56 and Figure 57 , by removing the sacrificial molding film 259 and the buried insulating layer 201, the sidewalls of the contact structure BC and the sidewalls of the storage electrode 251 can be exposed.

[0263] The gate covering pattern 143 and the back gate covering pattern 111 can also be exposed.

[0264] Next, referring to Figure 2 and Figure 3 , a capacitor dielectric film 253 and a plate electrode 255 can be formed on the contact structure BC and the storage electrode 251.

[0265] In order to increase the capacitance of the capacitor, it is necessary to increase the height of the storage electrode 251. In the semiconductor memory device of the present invention, since the sub-substrate 200 that is removed after wafer bonding is used for the storage electrode 251, the thickness of the remaining sub-substrate 200 after the grinding process can be freely adjusted. When the thickness of the sub-substrate 200 increases, the height of the semiconductor molding pattern 251_MP used to form the storage electrode 251 also increases. Therefore, when the height of the semiconductor molding pattern 251_MP increases, the height of the storage electrode 251 also increases, and thus, the capacitance of the capacitor can be increased. Therefore, the performance and reliability of the semiconductor memory device can be improved.

[0266] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments and can be implemented in various different forms. Those of ordinary skill in the art to which the present disclosure pertains will be able to understand that the present disclosure can be implemented in other specific forms without changing the technical idea or characteristics of the present disclosure. Therefore, it should be understood that the embodiments described above are illustrative rather than restrictive in all respects.

Claims

1. A semiconductor memory device, comprising: A peripheral gate structure on a substrate; A bit line on the peripheral gate structure, wherein the bit line extends in a first direction; An active pattern on the bit line, wherein the active pattern includes a first surface and a second surface opposite to each other in a second direction, and a first sidewall and a second sidewall opposite to each other in the first direction, and wherein the first surface of the active pattern contacts the bit line; A word line on the first sidewall of the active pattern, wherein the word line extends in a third direction intersecting the first direction and the second direction; A contact structure on the active pattern, wherein the contact structure includes an upper surface and a bottom surface opposite to each other in the second direction, wherein the bottom surface of the contact structure contacts the second surface of the active pattern; and A data storage pattern on the upper surface of the contact structure, and including a lower electrode and a capacitor dielectric film, Wherein the contact structure includes a sidewall between the upper surface and the bottom surface of the contact structure, and Wherein the capacitor dielectric film extends along the sidewall of the contact structure and contacts the sidewall of the contact structure.

2. The semiconductor memory device according to claim 1, Among them, The lower electrode includes a bottom surface facing the bottom surface of the contact structure, and Wherein the width of the bottom surface of the lower electrode in the first direction is equal to the width of the upper surface of the contact structure in the first direction.

3. The semiconductor memory device according to claim 1, Among them, The contact structure includes a contact plug pattern including a conductive material, and Wherein the contact plug pattern contacts the capacitor dielectric film.

4. The semiconductor memory device according to claim 1, Among them, The contact structure includes a contact plug pattern and a contact insulating spacer, the contact plug pattern includes a conductive material, the contact insulating spacer extends along the sidewall of the contact plug pattern, and Wherein the contact insulating spacer contacts the capacitor dielectric film.

5. The semiconductor memory device according to claim 1, Among them, The data storage pattern further includes an upper electrode on the capacitor dielectric film, and Wherein the upper electrode is on the sidewall of the contact structure.

6. The semiconductor memory device according to claim 1, further comprising: A lower electrode support member contacting the sidewall of the lower electrode.

7. The semiconductor memory device according to claim 6, Among them, The lower electrode support member includes an upper surface and a bottom surface opposite to each other in the second direction, Wherein the bottom surface of the lower electrode support member faces the active pattern, and Wherein at least one of the upper surface and the bottom surface of the lower electrode support member includes a curved surface.

8. The semiconductor memory device according to claim 1, further comprising: A shielding conductive pattern on the peripheral gate structure, and including a shielding wire pattern extending in the first direction along the sidewall of the bit line.

9. The semiconductor memory device according to claim 8, Among them, The shielding conductive pattern further includes a shielding conductive plate, Wherein the shielding wire pattern protrudes from the shielding conductive plate in the second direction, Wherein the bit line is on the shielding conductive plate.

10. The semiconductor memory device according to any one of claims 1 to 9, further comprising: A back gate electrode is on the second sidewall of the active pattern on the bit line, wherein the back gate electrode extends in a third direction.

11. A semiconductor memory device, comprising: A peripheral gate structure on a substrate; A bit line on the peripheral gate structure, wherein the bit line extends in a first direction; An active pattern on the bit line, wherein the active pattern includes a first surface and a second surface facing each other in a second direction, and a first sidewall and a second sidewall facing each other in a first direction, and wherein the first surface of the active pattern contacts the bit line; A word line on the first sidewall of the active pattern, wherein the word line extends in a third direction intersecting the first direction and the second direction; A contact structure on the active pattern, wherein the contact structure includes an upper surface and a bottom surface facing each other in a second direction, and wherein the bottom surface of the contact structure contacts the second surface of the active pattern; and A data storage pattern on the upper surface of the contact structure, wherein the data storage pattern includes a lower electrode contacting the upper surface of the contact structure, a capacitor dielectric film on the lower electrode, and an upper electrode on the capacitor dielectric film, wherein the upper electrode includes a bottom surface facing the bit line, and wherein the distance from the upper surface of the bit line to the upper surface of the contact structure is greater than the distance from the upper surface of the bit line to the bottom surface of the upper electrode.

12. The semiconductor memory device according to claim 11, Among them, The upper electrode is on the sidewall of the contact structure.

13. The semiconductor memory device according to claim 11, Among them, The capacitor dielectric film extends along the sidewall of the contact structure and contacts the sidewall of the contact structure.

14. The semiconductor memory device according to claim 11, Among them, The lower electrode includes a bottom surface facing the contact structure, and wherein the width of the bottom surface of the lower electrode in the first direction is equal to the width of the upper surface of the contact structure in the first direction.

15. The semiconductor memory device according to claim 11, Among them, The contact structure includes a contact plug pattern including a conductive material, and wherein the contact plug pattern includes the sidewall of the contact structure.

16. The semiconductor memory device according to claim 11, Among them, The contact structure includes a contact plug pattern and a contact insulating spacer. The contact plug pattern includes a conductive material. The contact insulating spacer extends along the sidewall of the contact plug pattern, and wherein the contact insulating spacer includes the sidewall of the contact structure.

17. The semiconductor memory device according to any one of claims 11 to 16, further comprising: A back gate electrode on the second sidewall of the active pattern on the bit line, wherein the back gate electrode extends in a third direction; and A shielding conductive pattern on the peripheral gate structure and including a shielding wire pattern extending in the first direction along the sidewall of the bit line.

18. A semiconductor memory device, comprising: A peripheral gate structure on a substrate; A bit line on the peripheral gate structure, wherein the bit line extends in a first direction; A shielding conductive pattern on the peripheral gate structure, wherein the shielding conductive pattern includes a shielding wire pattern extending in the first direction along the sidewall of the bit line; A word line is disposed on the bit line and the shielding conductive pattern. The word line extends in a second direction and includes an upper surface and a bottom surface that face each other in a third direction. The bottom surface of the word line faces the bit line; A back gate electrode is disposed on the bit line and the shielding conductive pattern. The back gate electrode extends in a second direction and includes an upper surface and a bottom surface that face each other in a third direction. The bottom surface of the back gate electrode faces the bit line; A word line covering pattern is disposed on the upper surface of the word line; A back gate covering pattern is disposed on the upper surface of the back gate electrode; An active pattern is disposed between the word line and the back gate electrode. The active pattern includes a first surface and a second surface that face each other in a third direction. The first surface of the active pattern contacts the bit line; A contact structure is disposed on the active pattern. The contact structure contacts the second surface of the active pattern; and A data storage pattern is disposed on the contact structure. The data storage pattern includes a lower electrode and a capacitor dielectric film, wherein the capacitor dielectric film contacts the word line covering pattern and the back gate covering pattern.

19. The semiconductor memory device according to claim 18, Among them, The contact structure includes an upper surface and a bottom surface that face each other in a third direction, wherein the bottom surface of the contact structure contacts the active pattern, and wherein the upper surface of the contact structure protrudes in the third direction beyond the word line covering pattern and the back gate covering pattern.

20. The semiconductor memory device according to claim 18 or 19, Among them, The capacitor dielectric film extends along the sidewall of the contact structure and contacts the sidewall of the contact structure.

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