Semiconductor structure and forming method thereof
A three-dimensional semiconductor structure with parallel-connected capacitors in the peripheral area addresses the challenge of large capacity capacitors in DRAM, improving integration density and performance while reducing costs.
Patent Information
- Application Number
- CN202510442675.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-09
- Publication Date
- 2025-07-15
AI Technical Summary
The capacity of the capacitor NICAP in the peripheral area of the existing DRAM chip is insufficient, resulting in insufficient power supply stability and signal processing capabilities.
Using a three-dimensional semiconductor structure, by forming a step contact structure and a connection structure in the peripheral area, multiple capacitors in the same composite layer are connected in parallel, the capacitor capacity is increased, and vertical interconnection is achieved through the step contact structure.
It improves the capacity and signal processing capabilities of the capacitor, reduces the complexity of the connection structure, simplifies the process flow, and reduces signal interference.
Smart Images
Figure CN120321963A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to, but is not limited to, a semiconductor structure and a method for forming the same. Background Art
[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in electronic devices such as computers. The DRAM chip is divided into an array area and a periphery area. Among them, the array area includes a memory cell array for storing data, and the periphery area includes peripheral circuits located outside the memory cell array.
[0003] The capacitors in the periphery area are usually called NICAP. The capacitor NICAP requires a large capacitance to be used as a power supply or for signal processing in the periphery area. Summary of the Invention
[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, which can save costs and improve performance.
[0005] The technical solution of the embodiments of the present disclosure is implemented as follows:
[0006] Embodiments of the present disclosure provide a semiconductor structure, which includes: a semiconductor substrate, a stacked structure, and a stepped contact structure; the stacked structure is located on the semiconductor substrate; the stacked structure includes: a separation layer and a composite layer alternately stacked in the vertical direction; the semiconductor substrate includes: an array area and a periphery area; the stacked structure forms a stepped structure in the periphery area; the stepped contact structure extends along the vertical direction and connects to the corresponding stepped structure; the stacked structure located in the periphery area further includes: a capacitor area; wherein, the composite layer of the capacitor area includes: a first electrode plate; the composite layer located in the periphery area includes: a connection structure; wherein, multiple first electrode plates in the same layer of the composite layer are connected to the corresponding stepped contact structure through the connection structure.
[0007] In some embodiments of the present disclosure, the connection structure extends along a first direction; the capacitor area and the stepped structure are both located on opposite sides of the connection structure along a second direction.
[0008] In some embodiments of the present disclosure, the connection structure is annular, linear, or square.
[0009] In some embodiments of the present disclosure, the first electrode plates are spaced apart and distributed on opposite sides of the composite layer of the capacitor area along the second direction, and protrude outward; the first electrode plates are directly connected to the nearest connection structure.
[0010] In some embodiments of the present disclosure, each of the step contact structures is only connected to the connection structure in the corresponding one of the composite layers.
[0011] In some embodiments of the present disclosure, the stacked structure in the capacitor region further includes: a dielectric layer and a second electrode plate; the second electrode plate is located on a side of the capacitor region away from the first electrode plate; the dielectric layer is located between the first electrode plate and the second electrode plate.
[0012] In some embodiments of the present disclosure, the semiconductor structure further includes: a capacitive contact structure; the capacitive contact structure extends along the vertical direction; the capacitive contact structure is located on a side of the second electrode plate away from the first electrode plate and is connected to the second electrode plates in different composite layers.
[0013] The embodiments of the present disclosure further provide a method for forming a semiconductor structure. The method for forming the semiconductor structure includes: providing a semiconductor substrate; the semiconductor substrate includes: an array region and a peripheral region; forming a stacked structure on the semiconductor substrate; the stacked structure includes: a separation layer and a composite layer alternately stacked along the vertical direction; the stacked structure forms a step structure in the peripheral region; forming a step contact structure; the step contact structure extends along the vertical direction and is connected to the corresponding step structure; forming a capacitor region and a connection structure in the stacked structure in the peripheral region; wherein, the composite layer in the capacitor region includes: a first electrode plate; multiple first electrode plates in the same composite layer are connected to the corresponding step contact structures through the connection structure.
[0014] In some embodiments of the present disclosure, the method for forming the connection structure includes: etching a first trench in the stacked structure; the first trench penetrates the stacked structure along the vertical direction and extends along a first direction; etching the exposed composite layer in the first trench to form a space for the connection structure; filling the first trench with a conductive material to form the connection structure extending along the first direction.
[0015] In some embodiments of the present disclosure, the method of forming the capacitor region includes: etching to form a first cavity in the stacked structure; the first cavity penetrating the stacked structure along the vertical direction; at the intersections of two opposite sides of the first cavity along a second direction with the composite layer, protruding grooves are formed at intervals; depositing a first conductive layer on the inner sidewall of the first cavity; etching in the first cavity to partially remove the first conductive layer, and retaining and exposing the first conductive layer in the protruding grooves to form the first electrode plate; the first electrode plate is distributed at intervals on two opposite sides of the composite layer of the capacitor region along the second direction and protrudes outward; the connection structure is located outside two opposite sides of the composite layer of the capacitor region along the second direction; the first electrode plate is directly connected to the nearest connection structure; depositing a dielectric layer on the inner sidewall of the first cavity; depositing a second conductive layer covering the dielectric layer on the inner sidewall of the first cavity to form a second electrode plate.
[0016] In some embodiments of the present disclosure, after forming the second electrode plate, the method of forming the semiconductor structure further includes: filling a conductive material in the first cavity to form a capacitive contact structure; the capacitive contact structure extends along the vertical direction and penetrates at least part of the stacked structure; the capacitive contact structure is located inside the second electrode plate and connects the second electrode plates in different composite layers.
[0017] It can be understood that the first electrode plates are formed in the composite layer, and the first electrode plates in different composite layers are not connected to each other. Multiple first electrode plates in the same composite layer are connected to the corresponding step contact structures through the connection structure. In this way, the first electrode plates in the same composite layer are led out by the step contact structures, realizing the connection of NICAP in the three-dimensional semiconductor structure. At the same time, multiple first electrode plates in each composite layer are connected through the connection structure. In this way, it is equivalent to connecting multiple capacitors in parallel, and thus, a capacitor with a larger capacity can be realized. Description of the Drawings
[0018] Figure 1 Structural schematic of the semiconductor structure provided by the embodiment of the present disclosure Figure 1 ;
[0019] Figure 2 Structural schematic of the semiconductor structure provided by the embodiment of the present disclosure Figure 2 ;
[0020] Figure 3 Structural schematic of the semiconductor structure provided by the embodiment of the present disclosure Figure 3 ;
[0021] Figure 4A Structural schematic of the method of forming the semiconductor structure provided by the embodiment of the present disclosureFigure 1 ;
[0022] Figure 4B Schematic diagram of the structure of the method for forming a semiconductor structure provided by an embodiment of the present disclosure Figure 2 ;
[0023] Figure 4C Schematic diagram of the structure of the method for forming a semiconductor structure provided by an embodiment of the present disclosure Figure 3 ;
[0024] Figure 4D Schematic diagram four of the structure of the method for forming a semiconductor structure provided by an embodiment of the present disclosure;
[0025] Figure 5A Schematic diagram five of the structure of the method for forming a semiconductor structure provided by an embodiment of the present disclosure;
[0026] Figure 5B Schematic diagram six of the structure of the method for forming a semiconductor structure provided by an embodiment of the present disclosure;
[0027] Figure 5C Schematic diagram seven of the structure of the method for forming a semiconductor structure provided by an embodiment of the present disclosure;
[0028] Figure 6A Schematic diagram eight of the structure of the method for forming a semiconductor structure provided by an embodiment of the present disclosure;
[0029] Figure 6B Schematic diagram nine of the structure of the method for forming a semiconductor structure provided by an embodiment of the present disclosure;
[0030] Figure 6C Schematic diagram ten of the structure of the method for forming a semiconductor structure provided by an embodiment of the present disclosure;
[0031] Figure 7A Schematic diagram eleven of the structure of the method for forming a semiconductor structure provided by an embodiment of the present disclosure;
[0032] Figure 7B Schematic diagram twelve of the structure of the method for forming a semiconductor structure provided by an embodiment of the present disclosure;
[0033] Figure 7C Schematic diagram of the structure of the method for forming a semiconductor structure provided by an embodiment of the present disclosure Figure Thirteen ;
[0034] Figure 8A Schematic diagram fourteen of the structure of the method for forming a semiconductor structure provided by an embodiment of the present disclosure;
[0035] Figure 8B Schematic diagram fifteen of the structure of the method for forming a semiconductor structure provided by an embodiment of the present disclosure;
[0036] Figure 8C Schematic diagram sixteen of the method for forming a semiconductor structure provided by an embodiment of the present disclosure;
[0037] Figure 8D Schematic diagram seventeen of the method for forming a semiconductor structure provided by an embodiment of the present disclosure;
[0038] Figure 8E Schematic diagram eighteen of the method for forming a semiconductor structure provided by an embodiment of the present disclosure;
[0039] Figure 9A Schematic diagram nineteen of the method for forming a semiconductor structure provided by an embodiment of the present disclosure;
[0040] Figure 9B Schematic diagram of the method for forming a semiconductor structure provided by an embodiment of the present disclosure Figure 2 ten;
[0041] Figure 9C Schematic diagram of the method for forming a semiconductor structure provided by an embodiment of the present disclosure Figure 2 eleven;
[0042] Figure 9D Schematic diagram of the method for forming a semiconductor structure provided by an embodiment of the present disclosure Figure 2 twelve;
[0043] Figure 9E Schematic diagram of the method for forming a semiconductor structure provided by an embodiment of the present disclosure Figure 2 thirteen;
[0044] Figure 10A Schematic diagram of the method for forming a semiconductor structure provided by an embodiment of the present disclosure Figure 2 fourteen; Figure 10B Schematic diagram of the method for forming a semiconductor structure provided by an embodiment of the present disclosure Figure 2 fifteen;
[0045] Figure 10C Schematic diagram of the method for forming a semiconductor structure provided by an embodiment of the present disclosure Figure 2 sixteen;
[0046] Figure 11A Schematic diagram of the method for forming a semiconductor structure provided by an embodiment of the present disclosure Figure 2 seventeen; Figure 11B Schematic diagram of the method for forming a semiconductor structure provided by an embodiment of the present disclosure Figure 2 eighteen;
[0047] Figure 11C Schematic diagram of the method for forming a semiconductor structure provided by an embodiment of the present disclosure Figure 2Nineteen;
[0048] Figure 12A Structural schematic of the method for forming a semiconductor structure provided by an embodiment of the present disclosure Figure 3 Ten;
[0049] Figure 12B Structural schematic of the method for forming a semiconductor structure provided by an embodiment of the present disclosure Figure 3 Eleven;
[0050] Figure 12C Structural schematic of the method for forming a semiconductor structure provided by an embodiment of the present disclosure Figure 3 Twelve;
[0051] Figure 13 Structural schematic of the method for forming a semiconductor structure provided by an embodiment of the present disclosure Figure 3 Thirteen. Detailed implementation manners
[0052] In order to make the objectives, technical solutions, and advantages of the present disclosure clearer, the technical solutions of the present disclosure will be further elaborated in detail below in conjunction with the accompanying drawings and embodiments. The described embodiments should not be construed as limitations on the present disclosure. All other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present disclosure.
[0053] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and they can be combined with each other without conflict.
[0054] If similar descriptions such as "first / second" appear in the application documents, the following description is added. In the following description, the terms "first / second / third" only distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.
[0055] In this document, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be intermediate layers / components between them. Additionally, in one orientation, a layer / component is "on" another layer / component, and when the orientation is reversed, the layer / component can be "under" the other layer / component.
[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used herein are for the purpose of describing embodiments of the present disclosure only and are not intended to limit the present disclosure.
[0057] It should be noted that in the schematic structural diagrams of the embodiments of the present disclosure, the drawings with the same numerical reference numerals show the same structure. For example, Figure 4A 、 Figure 4B 、 Figure 4C and Figure 4D show the same structure. Among them, some of the schematic structural diagrams are three-dimensional schematic diagrams, and some of the schematic structural diagrams are cross-sectional views of three-dimensional structural diagrams. For example, Figure 4B is a cross-sectional view along the cutting line A-A1 in Figure 4A .
[0058] In addition, the internal structure of the three-dimensional perspective schematic structural diagram is cut open for the convenience of observation and description; in practice, the cut-open position is filled with the corresponding structure.
[0059] It should also be noted that in the schematic structural diagrams of the embodiments of the present disclosure, the first direction X and the second direction Y are both located in the horizontal plane perpendicular to the vertical direction Z. That is to say, both the first direction X and the second direction Y are perpendicular to the vertical direction Z. At the same time, the first direction X intersects with the second direction Y, and the included angle is not limited.
[0060] The embodiments of the present disclosure provide a semiconductor structure. As Figure 1 shown, the semiconductor structure includes: a semiconductor substrate 10, a stacked structure 20, and a stepped contact structure 30.
[0061] In the embodiments of the present disclosure, the semiconductor substrate 10 may include any feasible semiconductor material. For example, one or more of silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), and gallium nitride (GaN).
[0062] In the embodiments of the present disclosure, referring to Figure 1 , the stacked structure 20 is located on the semiconductor substrate 10. The stacked structure 20 includes: a separation layer and a composite layer stacked alternately in the vertical direction Z; wherein, devices and circuit structures are formed in the composite layer, and the separation layer is used to separate the respective composite layers. In this way, a 3D (three-dimensional) semiconductor structure is formed, thereby improving the integration degree, enhancing the performance, and reducing the cost.
[0063] In the embodiments of the present disclosure, the semiconductor substrate 10 includes: an array region and a peripheral region. Among them, the array region includes a memory cell array for storing data, and the peripheral region includes peripheral circuits located outside the memory cell array.
[0064] In the embodiments of the present disclosure, referring toFigure 1 In Figure 1 , a stacked structure 20 forms a stepped structure 31 in the peripheral region. The stepped contact structure 30 extends along the vertical direction Z and connects the corresponding stepped structures 31.
[0065] It should be noted that the stepped structure (Step Structure, SS) 31 is a stepped geometric form formed at the edge of each composite layer; among them, the lateral dimension of the upper composite layer is slightly smaller than that of the lower composite layer, thus forming "steps" that are gradually exposed laterally. The stepped structure 31 provides physical contact points for the vertical interconnection of the semiconductor structure.
[0066] The stepped contact structure (Step Contact, SC) 30 is a conductive channel that extends along the vertical direction Z from the stepped structure 31, and can lead out the electrical signals of different composite layers, thereby realizing vertical interconnection. The stepped contact structure 30 can be filled with a via with a low-resistance metal such as tungsten (W) or cobalt (Co), thereby forming a conductive path through multiple composite layers.
[0067] In the embodiments of the present disclosure, the stepped contact structure 30 only connects to the stepped structure 31 in the corresponding composite layer. For example, Figure 1 in the exposed composite layer, the stepped structure 31 only connects to the stepped contact structure 301 and does not connect to the stepped contact structure 302. The stepped contact structure 302 connects to the stepped structure 31 in other composite layers. In this way, it can be ensured that the electrical signals in each composite layer are led out separately, avoiding interference between the electrical signals of different composite layers.
[0068] In the embodiments of the present disclosure, referring to Figure 1 , the stacked structure located in the peripheral region further includes: a capacitor region 40. The capacitor region 40 is used to form a capacitor NICAP in the peripheral region.
[0069] It should be noted that in a memory chip (such as a DRAM chip), the capacitor NICAP in the peripheral region serves as a decoupling capacitor, and its main function is to provide a stable power supply, reduce power supply noise, and protect the chip from high-frequency electromagnetic interference. On the one hand, the decoupling capacitor can be set at the power supply terminal as a local source for providing transient current to maintain the stability of the power supply voltage; on the other hand, the decoupling capacitor can also bypass high-frequency noise and reduce high-frequency electromagnetic interference.
[0070] Figure 2 For Figure 1 is a partial structural schematic diagram of the capacitor region 40 in Figure 2 , the composite layer of the capacitor region 40 includes: a first electrode plate 401. The first electrode plate 401 can serve as the lower electrode plate of the capacitor NICAP. The material of the first electrode plate 401 can include titanium (Ti) and / or titanium nitride (TiN).
[0071] Combined with Figure 1 and Figure 2 , the composite layer located in the peripheral region includes: a connection structure 50. The material of the connection structure 50 may include one or more of titanium (Ti), titanium nitride (TiN), and tungsten (W). Among them, multiple first electrode plates 401 in the same composite layer are connected to the corresponding stepped contact structure 301 through the connection structure 50.
[0072] It can be understood that the first electrode plates 401 are formed in the composite layer, and the first electrode plates 401 in different composite layers are not connected to each other. Multiple first electrode plates 401 in the same composite layer are connected to the corresponding stepped contact structure 301 through the connection structure 50. In this way, the first electrode plates 401 in the same composite layer are led out by the stepped contact structure 301, realizing the wiring of NICAP in the three-dimensional semiconductor structure. At the same time, multiple first electrode plates 401 in each composite layer are connected by the connection structure 50. In this way, it is equivalent to connecting multiple capacitors in parallel, and thus, a capacitor with a larger capacity can be realized.
[0073] In the embodiments of the present disclosure, referring to Figure 1 , the connection structure 50 extends along the first direction X. The capacitor region 40 and the stepped structure 31 are both located on opposite sides of the connection structure 50 along the second direction Y. In this way, the connection structure 50 only needs to extend along the first direction X to connect the capacitor region 40 and the stepped structure 31 on both sides of it, without the need for bending. Thus, the complexity of the wiring of the connection structure 50 is reduced, which is beneficial to simplifying the process and reducing the interference between signals.
[0074] It should be noted that Figure 1 the shown connection structure 50 is in a ring shape, which is only an example of the shape of the connection structure 50. In the embodiments of the present disclosure, the connection structure 50 can be in a ring shape, a straight line shape, a square shape, or other feasible shapes.
[0075] Referring to Figure 1 , in the connection structure 50, partial sections extending along the first direction X are respectively connected to the capacitor region 40 and the stepped structure 31. At the same time, partial sections extending along the second direction Y connect the partial sections extending along the first direction X, so that the connection structure 50 is connected into an integral ring shape. Inside the ring-shaped connection structure 50, a dielectric material is filled.
[0076] In the embodiments of the present disclosure, combined with Figure 1 and Figure 2 , each stepped contact structure 301 only connects the connection structure 50 in the corresponding composite layer.
[0077] It can be understood that the stepped contact structure 301 is connected to only the first electrode plate 401 in the corresponding composite layer through the connection structure 50. In this way, the first electrode plate 401 in each composite layer can be controlled individually, and the capacitance characteristics of the capacitor NICAP in each composite layer can be detected individually. Therefore, the capacitor NICAP can be controlled and detected more accurately.
[0078] In some embodiments of the present disclosure, in combination with Figure 1 and Figure 2 , the first electrode plates 401 are spaced apart and protrude outwardly from opposite sides of the composite layer in the capacitor region 40 along the second direction Y. The first electrode plates 401 are directly connected to the nearest connection structure 50.
[0079] It can be understood that the outward protrusion of the first electrode plates 401 facilitates direct connection to the connection structure 50 without the need to connect to the connection structure 50 through other structures. In this way, the number of structures to be formed is reduced, which is beneficial to the processing and manufacturing of the semiconductor structure. At the same time, the outward protrusion of the first electrode plates 401 forms a curved electrode plate shape, which can increase the area between the electrode plates and thus increase the capacitance of the capacitor NICAP.
[0080] In some embodiments of the present disclosure, with reference to Figure 2 , the stacked structure of the capacitor region 40 further includes: a second electrode plate 402 and a dielectric layer 403. The second electrode plate 402 is located on the side of the capacitor region 40 away from the first electrode plate 401, and the dielectric layer 403 is located between the first electrode plate 401 and the second electrode plate 402. The material of the second electrode plate 402 may include titanium (Ti) and / or titanium nitride (TiN). The material of the dielectric layer 403 may include a high-k material, and the use of a high-k material can increase the capacitance of the capacitor.
[0081] In the embodiments of the present disclosure, in the composite layer of each capacitor region 40, the second electrode plate 402 is an integral electrode plate. That is to say, the same second electrode plate 402 and multiple first electrode plates 401 form a capacitor. In this way, it is equivalent to connecting multiple capacitors in parallel, and thus, a capacitor with a larger capacitance can be realized. At the same time, in the composite layer of each capacitor region 40, the second electrode plate 402 is located inside to form a closed structure. In this way, the size occupied by the capacitance can be effectively reduced, which is beneficial to the improvement of the integration degree.
[0082] In the embodiments of the present disclosure, with reference to Figure 2, a capacitive contact structure (Topcapacity plate, TCP) 41 is provided on the inner side of the second plate 402. The capacitive contact structure 41 extends along the vertical direction Z. The capacitive contact structure 41 is located on the side of the second plate 402 away from the first plate 401 and connects the second plates 402 in different composite layers. The material of the capacitive contact structure 41 may include doped polysilicon. The capacitive contact structure 41 can play a supporting role and can lead out the second plate 402.
[0083] Figure 3 is an optional layout of the semiconductor structure provided by the embodiments of the present disclosure. Refer to Figure 3 , in the capacitor region, the shallow trench isolation structure (STI) 60 extends along the second direction Y for isolating different capacitors NICAP in the first direction X. A first cavity is formed in the capacitor hole (Cap Hole) 42 for forming the capacitor NICAP. The capacitive contact structure (TCP) 41 is used to lead out the upper plate of the capacitor NICAP.
[0084] Continue to refer to Figure 3 , the step contact structure (SC) 30 is used to lead out the connection lines (such as the horizontally arranged word line WL or bit line BL) in the composite layer. The connection structure (SCE) 50 extends along the first direction X, and in the same composite layer, the connection structure 50 connects the capacitors NICAP on both sides and the step contact structure 30.
[0085] The embodiments of the present disclosure also provide a method for forming a semiconductor structure, including steps S101 to S103.
[0086] S101. Provide a semiconductor substrate 10.
[0087] In the embodiments of the present disclosure, refer to Figure 1 , the semiconductor substrate 10 may include any feasible semiconductor material, for example, one or more of silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), and gallium nitride (GaN). The semiconductor substrate 10 includes: an array region and a peripheral region. Among them, the array region includes a memory cell array for storing data, and the peripheral region includes peripheral circuits located outside the memory cell array.
[0088] S102. Form a stacked structure 20 on the semiconductor substrate 10.
[0089] In the embodiments of the present disclosure, refer to Figure 1, the stacked structure 20 includes: a separation layer and a composite layer stacked alternately in the vertical direction Z. Among them, devices and circuit structures are formed in the composite layer, and the separation layer is used to separate each composite layer. In this way, a three-dimensional semiconductor structure is formed, thereby improving the integration degree, enhancing the performance, and reducing the cost.
[0090] In the embodiments of the present disclosure, referring to Figure 1 , the stacked structure 20 forms a stepped structure 31 in the peripheral region. The stepped structure 31 is a stepped geometric form formed at the edge of each composite layer; among them, the lateral dimension of the upper composite layer is slightly smaller than that of the lower composite layer, so that "steps" are gradually exposed laterally. The stepped structure 31 provides physical contact points for the vertical interconnection of the semiconductor structure.
[0091] S103. Form a stepped contact structure 30.
[0092] In the embodiments of the present disclosure, referring to Figure 1 , the stepped contact structure 30 extends in the vertical direction Z and is connected to the corresponding stepped structure 31. The stepped contact structure 30 is a conductive channel extending from the stepped structure 31 in the vertical direction Z, which can lead out the electrical signals of different composite layers, thereby realizing vertical interconnection. The stepped contact structure 30 can be filled with a low-resistance metal such as tungsten (W) or cobalt (Co) in the through hole (Via) to form a conduction path penetrating multiple composite layers.
[0093] In the embodiments of the present disclosure, the stepped contact structure 30 is only connected to the stepped structure 31 in the corresponding composite layer. In this way, it can be ensured that the electrical signals in each composite layer are led out separately, avoiding interference between the electrical signals of different composite layers.
[0094] S104. In the stacked structure 20 in the peripheral region, form a capacitor region 40 and a connection structure 50.
[0095] In the embodiments of the present disclosure, referring to Figure 1 and Figure 2 , the stacked structure located in the peripheral region includes: a capacitor region 40, and the capacitor region 40 is used to form a capacitor NICAP in the peripheral region. The composite layer of the capacitor region 40 includes: a first electrode plate 401, and the first electrode plate 401 can be used as the lower electrode plate of the capacitor NICAP. The material of the first electrode plate 401 can include titanium (Ti) and / or titanium nitride (TiN).
[0096] Continuing to refer to Figure 1 and Figure 2 , the composite layer located in the peripheral region includes: a connection structure 50. The material of the connection structure 50 can include one or more of titanium (Ti), titanium nitride (TiN), and tungsten (W). Among them, multiple first electrode plates 401 in the same composite layer are connected to the corresponding stepped contact structure 301 through the connection structure 50.
[0097] It can be understood that the first electrode plate 401 is formed in the composite layer, and the first electrode plates 401 in different composite layers are not connected to each other. Multiple first electrode plates 401 in the same composite layer are connected to the corresponding step contact structure 301 through the connection structure 50. In this way, the first electrode plates 401 in the same composite layer are led out by the step contact structure 301, realizing the connection of NICAP in the three-dimensional semiconductor structure. At the same time, multiple first electrode plates 401 in each composite layer are connected through the connection structure 50. In this way, it is equivalent to connecting multiple capacitors in parallel, and thus, a capacitor with a larger capacity can be realized.
[0098] In the embodiments of the present disclosure, referring to Figure 1 , the connection structure 50 extends along the first direction X. The capacitor region 40 and the step structure 31 are both located on opposite sides of the connection structure 50 along the second direction Y. In this way, the connection structure 50 only needs to extend along the first direction X to connect the capacitor region 40 and the step structure 31 on both sides of it, without the need for bending. Thus, the complexity of the wiring of the connection structure 50 is reduced, which is beneficial to simplifying the process and reducing the interference between signals.
[0099] In the embodiments of the present disclosure, the connection structure 50 can be in a ring shape, a straight line shape, a square shape, or other feasible shapes.
[0100] In the embodiments of the present disclosure, in combination with Figure 1 and Figure 2 , each step contact structure 301 is only connected to the connection structure 50 in the corresponding composite layer.
[0101] It can be understood that the step contact structure 301 is only connected to the first electrode plate 401 in the corresponding composite layer through the connection structure 50. In this way, the first electrode plates 401 in each composite layer can be controlled separately, and the capacitance characteristics of the capacitor NICAP in each composite layer can be detected separately. Thus, the capacitor NICAP can be controlled and detected more precisely.
[0102] In some embodiments of the present disclosure, in combination with Figure 1 and Figure 2 , the first electrode plates 401 are spaced apart and protrude outward on opposite sides of the composite layer of the capacitor region 40 along the second direction Y. The first electrode plates 401 are directly connected to the nearest connection structure 50.
[0103] It can be understood that the first electrode plate 401 protrudes outward, facilitating direct connection with the connection structure 50 without the need to connect to the connection structure 50 through other structures. In this way, the structures to be formed are reduced, which is conducive to the processing and manufacturing of semiconductor structures. At the same time, the first electrode plate 401 protrudes outward, forming a curved electrode plate shape, which can increase the area between the electrode plates and thus increase the capacitance of the capacitor NICAP.
[0104] In some embodiments of the present disclosure, the method for forming the connection structure 50 includes steps S201 to S203. Each step will be described in combination.
[0105] S201. In the stacked structure 20, a first trench 52 is etched and formed.
[0106] In the embodiments of the present disclosure, in combination with Figure 4A 、 Figure 4B and Figure 4C , the initial form of the stacked structure 20 includes: a separation layer 212 and a first sacrificial layer 201 alternately stacked in the vertical direction Z. The material of the separation layer 212 may include silicon oxide (SiO), and the material of the first sacrificial layer 201 may include silicon (Si). Among them, the position where the first sacrificial layer 201 is located will be processed to form a composite layer.
[0107] In the embodiments of the present disclosure, in combination with Figure 4A 、 Figure 4B and Figure 4D , a sacrificial structure 51 can be formed in the stacked structure 20. The sacrificial structure 51 extends along the first direction X and penetrates into the interior of the stacked structure 20 from the top surface of the stacked structure 20. A first dielectric layer 61 is formed outside the sacrificial structure 51. The material of the first dielectric layer 61 may include silicon nitride (SiN). The first dielectric layer 61 coats the sacrificial layer 201. In this way, a triple layer of the first sacrificial layer 201, the first dielectric layer 61, and the separation layer 212 is formed between two segments of the sacrificial structure 51.
[0108] Furthermore, with reference to Figure 6A 、 Figure 6B and Figure 6C , the material of the first sacrificial layer 201 can be replaced, and the first sacrificial layer 201 is replaced with a second sacrificial layer 202, so that the two segments of the sacrificial structure 51 are connected by the second sacrificial layer 202; among them, the material of the second sacrificial layer 202 may include silicon nitride (SiN). And the first dielectric layer 61 outside the sacrificial structure 51 can be replaced with a second dielectric layer 62, and the material of the second dielectric layer 62 may include silicon oxide (SiO).
[0109] With reference to Figure 6B, a part of the first sacrificial layer 201 remains between the sacrificial structure 51 and the first cavity 42 of the capacitor region, which can isolate the sacrificial structure 51 from the first cavity 42, and the remaining first sacrificial layer 201 will be completely removed in subsequent steps.
[0110] In some embodiments of the present disclosure, in combination with Figure 6A and Figure 7A , the stacked structure 20 can be etched on one side of the sacrificial structure 51 along the second direction Y, and a conductive material can be deposited in the etched space to form a stepped contact structure 30. In Figure 7A the exposed composite layer, the stepped structure 31 is only connected to the stepped contact structure 301 and not to the stepped contact structure 302. The stepped contact structure 302 is connected to the stepped structure 31 in other composite layers.
[0111] Furthermore, in combination with Figure 7A and Figure 8A , the sacrificial structure 51 can be etched at the original position of the sacrificial structure 51 to remove the sacrificial structure 51, and a first trench 52 can be formed. The first trench 52 penetrates the stacked structure 20 in the vertical direction Z and extends in the first direction X.
[0112] S202. In the first trench 51, the exposed composite layer is etched to form a space for connecting the structure 50.
[0113] In the embodiments of the present disclosure, in combination with Figure 8A , Figure 8B , Figure 8D and Figure 8E , in the first trench 51, a part of the second sacrificial layer 202 can be etched laterally, so that the remaining first sacrificial layer 201 is exposed.
[0114] Furthermore, the remaining first sacrificial layer 201 can be selectively etched to remove the remaining first sacrificial layer 201. Since the material of the first sacrificial layer 201 includes silicon (Si), and the silicon material is not exposed in other parts of the structure, during the selective etching of the remaining first sacrificial layer 201, the other parts of the structure will not be affected.
[0115] S203. A conductive material is filled in the first trench 51 to form a connection structure 50 extending in the first direction X.
[0116] In the embodiments of the present disclosure, in combination with Figure 8A and Figure 9A , filling a conductive material in the first trench 51 can form a connection structure 50 extending in the first direction X.
[0117] Referring to Figure 9A , Figure 9B ,Figure 9D and Figure 9E In the connection structure 50, partial sections extending along the first direction X are respectively connected to the capacitor region 40 and the step structure 31. Meanwhile, partial sections extending along the second direction Y connect the partial sections extending along the first direction X. Thus, the connection structure 50 is connected into an integral ring shape. Inside the connection structure 50, a dielectric material 53 is filled.
[0118] In some embodiments of the present disclosure, the method for forming the capacitor region 40 includes steps S301 to S305. Each step will be described in combination.
[0119] S301: In the stacked structure 20, etch to form a first cavity 42.
[0120] In the embodiments of the present disclosure, in combination with Figure 5A and Figure 5B , a sacrificial material is filled in the first cavity 42 to protect the first cavity 42 from the influence of other processes. The first cavity 42 penetrates the stacked structure 20 in the vertical direction Z. The first cavity 42 is formed in the gap of the shallow trench isolation structure (STI) 60. That is to say, the shallow trench isolation structure 60 can trim the sacrificial layer 201 to isolate the capacitor region 40.
[0121] In the embodiments of the present disclosure, lateral etching can be performed from the side of the first cavity 42 to form protruding grooves distributed at intervals. In combination with Figure 5B and Figure 5C , at the intersections of the two opposite sides of the first cavity 42 along the first direction X and the composite layer (i.e., the sacrificial layer 201 in Figure 5B ), protruding grooves distributed at intervals are formed; that is to say, on the two opposite sides of the first cavity 42 along the first direction X, several protruding grooves distributed at intervals are formed, and the protruding grooves and the composite layer (i.e., the sacrificial layer 201 in Figure 5B ) are located in the same layer.
[0122] It can be understood that the protruding grooves distributed at intervals can increase the surface area inside the first cavity 42. Thus, the capacitor NICAP formed in the first cavity 42 can have a larger inter-plate area, that is, the capacitance of the capacitor NICAP is increased.
[0123] S302: Deposit a first conductive layer on the inner sidewall of the first cavity 42.
[0124] In the embodiments of the present disclosure, in combination with Figure 9B and Figure 10B , before depositing the first conductive layer, the sacrificial material in the first cavity 42 can be etched and removed.
[0125] Refer to Figure 10B and Figure 10C, after removing the sacrificial material in the first cavity 42, at the position of the protruding groove in the first cavity 42, the connection structure 50 is exposed. Then, a first conductive layer can be deposited on the inner sidewall of the first cavity 42. Thus, at the position of the protruding groove in the first cavity 42, the first conductive layer and the connection structure 50 can form electrical contact. Among them, the material of the first conductive layer may include titanium (Ti) and / or titanium nitride (TiN).
[0126] S303. Etch in the first cavity 42 to partially remove the first conductive layer, retain and expose the first conductive layer in the protruding groove, and form the first electrode plate 401.
[0127] In the embodiment of the present disclosure, referring to Figure 11A , Figure 11B and Figure 11C , the first electrode plate 401 is located in the protruding groove of the first cavity 42. That is to say, the first electrode plate 401 is spaced apart and distributed on the opposite sides of the composite layer of the capacitor region 40 along the second direction Y and protrudes outward. At the same time, the connection structure 50 is located outside the opposite sides of the composite layer of the capacitor region 40 along the second direction Y. Therefore, the first electrode plate 401 is directly connected to the nearest connection structure 50, that is, the first electrode plate 401 forms electrical contact with the connection structure 50 exposed by the protruding groove.
[0128] S304. Deposit a dielectric layer 403 on the inner sidewall of the first cavity 42.
[0129] S305. Deposit a second conductive layer covering the dielectric layer 403 on the inner sidewall of the first cavity 42 to form the second electrode plate 402.
[0130] In the embodiment of the present disclosure, referring to Figure 12A , Figure 12B and Figure 12C , after the first electrode plate 401 is formed in the first cavity 42, a dielectric layer 403 and a second electrode plate 402 can be sequentially deposited in the first cavity 42. Among them, the second electrode plate 402 is located on the side of the capacitor region 40 away from the first electrode plate 401, and the dielectric layer 403 is located between the first electrode plate 401 and the second electrode plate 402. The material of the second electrode plate 402 may include titanium (Ti) and / or titanium nitride (TiN). The material of the dielectric layer 403 may include a high-k material. Using a high-k material can increase the capacitance of the capacitor.
[0131] In the embodiment of the present disclosure, referring to Figure 12A , Figure 12B and Figure 12C, in the composite layer of each capacitor region 40, the second electrode plate 402 is an integral electrode plate. That is to say, the same second electrode plate 402 and multiple first electrode plates 401 form a capacitor. In this way, it is equivalent to connecting multiple capacitors in parallel, thereby enabling a capacitor with a larger capacitance to be realized. At the same time, in the composite layer of each capacitor region 40, the second electrode plate 402 is located inside to form a closed structure. In this way, the size occupied by the capacitance can be effectively reduced, which is conducive to improving the integration degree.
[0132] In some embodiments of the present disclosure, after forming the second electrode plate, the method for forming the semiconductor structure further includes step S306. This will be described in conjunction with each step.
[0133] S306. Fill the first cavity 42 with a conductive material to form a capacitive contact structure 41.
[0134] In the embodiments of the present disclosure, in combination with Figure 12B and Figure 13 , a capacitive contact structure (TCP) 41 is provided on the inner side of the second electrode plate 402. The capacitive contact structure 41 extends along the vertical direction Z. The capacitive contact structure 41 is located on the side of the second electrode plate 402 away from the first electrode plate 401 and connects the second electrode plates 402 in different composite layers. The material of the capacitive contact structure 41 may include doped polysilicon. The capacitive contact structure 41 can play a supporting role and can lead out the second electrode plate 402.
[0135] It should be noted that the semiconductor structure and the method for forming the same provided by the embodiments of the present disclosure can be applied to a dynamic random access memory DRAM, providing a new solution for three-dimensional memory products. Among them, the capacitor NICAP (i.e., the capacitor region 40) in the peripheral region is in the same composite layer as the storage unit. The capacitor NICAP in the peripheral region is used as a power source or for signal processing in the peripheral region, can frequency modulate and reduce noise, increase the capacitance, and realize a separate 1C test structure.
[0136] It should be noted that in this article, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including the element.
[0137] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the superiority or inferiority of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.
[0138] As described above, the above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should be covered within the protection scope of the present disclosure.
Claims
1. A semiconductor structure, characterized in that, The semiconductor structure includes: a semiconductor substrate, a stacked structure, and a stepped contact structure; The stacked structure is located on the semiconductor substrate; the stacked structure includes: a separation layer and a composite layer alternately stacked in the vertical direction; The semiconductor substrate includes: an array region and a peripheral region; the stacked structure forms a stepped structure in the peripheral region; The stepped contact structure extends in the vertical direction and connects to the corresponding stepped structure; The stacked structure located in the peripheral region further includes: a capacitor region; wherein, the composite layer of the capacitor region includes: a first electrode plate; The composite layer located in the peripheral region includes: a connection structure; wherein, multiple first electrode plates in the same layer of the composite layer are connected to the corresponding stepped contact structure through the connection structure.
2. The semiconductor structure according to claim 1, wherein The connection structure extends in a first direction; Both the capacitor region and the stepped structure are located on opposite sides of the connection structure in a second direction.
3. The semiconductor structure according to claim 2, wherein The connection structure is annular, linear, or box-shaped.
4. The semiconductor structure according to claim 2, wherein The first electrode plates are spaced apart and protrude outwardly on opposite sides of the composite layer of the capacitor region in the second direction; The first electrode plates are directly connected to the nearest connection structure.
5. The semiconductor structure according to claim 1, wherein Each stepped contact structure is only connected to the connection structure in the corresponding layer of the composite layer.
6. The semiconductor structure according to claim 2, characterized in that, The stacked structure of the capacitor region further includes: a dielectric layer and a second electrode plate; The second electrode plate is located on the side of the capacitor region away from the first electrode plate; the dielectric layer is located between the first electrode plate and the second electrode plate.
7. The semiconductor structure according to claim 6, wherein The semiconductor structure further includes: a capacitor contact structure; The capacitor contact structure extends in the vertical direction; The capacitor contact structure is located on the side of the second electrode plate away from the first electrode plate and connects the second electrode plates in different composite layers.
8. A method for forming a semiconductor structure, characterized in that The method for forming the semiconductor structure includes: Providing a semiconductor substrate; the semiconductor substrate includes: an array region and a peripheral region; Forming a stacked structure on the semiconductor substrate; the stacked structure includes: a separation layer and a composite layer alternately stacked in the vertical direction; the stacked structure forms a stepped structure in the peripheral region; Forming a stepped contact structure; the stepped contact structure extends in the vertical direction and connects to the corresponding stepped structure; Forming a capacitor region and a connection structure in the stacked structure in the peripheral region; wherein, the composite layer of the capacitor region includes: a first electrode plate; multiple first electrode plates in the same layer of the composite layer are connected to the corresponding stepped contact structure through the connection structure.
9. The method for forming a semiconductor structure according to claim 8, wherein, The method for forming the connection structure includes: Etching a first trench in the stacked structure; the first trench penetrates the stacked structure in the vertical direction and extends in a first direction; In the first trench, the exposed composite layer is etched to form a space for the connection structure; The first trench is filled with a conductive material to form the connection structure extending along the first direction.
10. The method for forming a semiconductor structure according to claim 8, wherein, The method for forming the capacitor region includes: In the stacked structure, a first cavity is etched; the first cavity penetrates the stacked structure along the vertical direction; at the intersections of the two opposite sides of the first cavity along the second direction with the composite layer, protruding grooves are formed at intervals; A first conductive layer is deposited on the inner sidewall of the first cavity; Etching is performed in the first cavity to partially remove the first conductive layer, and the first conductive layer in the protruding grooves is retained and exposed to form the first electrode plate; the first electrode plate is distributed at intervals on the two opposite sides of the composite layer in the capacitor region along the second direction and protrudes outward; the connection structure is located outside the two opposite sides of the composite layer in the capacitor region along the second direction; the first electrode plate is directly connected to the nearest connection structure; A dielectric layer is deposited on the inner sidewall of the first cavity; A second conductive layer covering the dielectric layer is deposited on the inner sidewall of the first cavity to form a second electrode plate.
11. The method for forming a semiconductor structure according to claim 10, wherein After forming the second electrode plate, the method for forming the semiconductor structure further includes: The first cavity is filled with a conductive material to form a capacitive contact structure; the capacitive contact structure extends along the vertical direction and penetrates at least part of the stacked structure; the capacitive contact structure is located inside the second electrode plate and connects the second electrode plates in different composite layers.