Silicon controlled rectifier device and method for realizing I-III quadrant triggering based on buried layer structure

Abstract

The invention relates to the technical field of silicon controlled devices, in particular to a silicon controlled device and method for achieving I-III quadrant triggering based on a buried layer structure. A plurality of buried layer structures are formed in the substrate, and the buried layer structures are located below the front base region electrode of the front base region; the front base region and the substrate further form a conductive channel below the gate electrode to be connected to the depth of the buried layer structure; and when the external current of the silicon controlled device enters the second quadrant, the trigger current is increased through the buried layer structure so as to avoid false triggering. Aiming at the problem that a silicon controlled rectifier device in the prior art may be mistakenly triggered on a two-quadrant in an alternating current system, when the device works on the two-quadrant, charge export is realized through a conduction path from a buried layer structure to a gate electrode, so that a trigger current threshold value is greatly increased, and the reliability of the device is improved. When a first-quadrant trigger value and a third-quadrant trigger value are about 30 mA, a second-quadrant trigger value above 500 mA can be achieved, and the possibility of false triggering is effectively avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of thyristor devices, and particularly relates to a thyristor device and method for realizing I-III quadrant triggering based on a buried layer structure. Background Art

[0002] A silicon controlled rectifier (SCR), also known as a thyristor, is an element composed of four layers of semiconductor materials of PNPN, with three PN junctions and three electrodes, and is a high-power electrical component. A bidirectional thyristor is developed on the basis of an ordinary thyristor, can replace two thyristors connected in antiparallel, and only requires one trigger circuit, making it an ideal AC switch device. Thyristors are widely used in power electronics technology. In an automatic control system, they can be used as high-power drive devices to realize the control of high-power equipment with low-power control components. They are widely used in AC and DC motor speed control systems, power control systems, and servo systems. Thyristors are divided into two types: unidirectional thyristors and bidirectional thyristors. A bidirectional thyristor is also called a triode for alternating current (TRIAC). Structurally, a bidirectional thyristor is equivalent to two unidirectional thyristors connected in reverse. This thyristor has a bidirectional conduction function. Its on-off state is determined by the gate G. T2 electrodes and T1 electrodes are respectively arranged on the front and back sides of the device. Usually, the electrode opposite to the gate is denoted as the T1 electrode, and the electrode on the same side as the gate is denoted as the T2 electrode. The T1 electrode and the T2 electrode will switch back and forth between the cathode and the anode according to the different directions of the applied current. Therefore, a bidirectional thyristor can operate in four quadrants: I-II-III-IV. The four different quadrants are distinguished by the positive and negative voltages applied to the T1 pole, T2 pole, and G pole. When both T1 and G are positive, it is the first quadrant; when T1 is positive and G is negative, it is the second quadrant; when T1 is negative and G is negative, it is the third quadrant; when T1 is negative and G is positive, it is the fourth quadrant.

[0003] Thyristors are mostly used in the control of AC power systems. Alternating current is a current that periodically reverses direction and continuously changes its magnitude.

[0004] When a thyristor device is applied in an AC power system, the device usually only operates in the I-III quadrants, that is, it switches between the first and third quadrants as the positive and negative half-cycles of the alternating current change.

[0005] Due to the limitation of its trigger structure, in a traditional thyristor structure, if triggered in the third quadrant, it will inevitably be triggered in the second quadrant. However, in actual applications, triggering in the second quadrant is not required. Moreover, there will be phenomena of mis-triggering and mis-conduction, resulting in circuit out-of-control. Summary of the Invention

[0006] In view of the above problems existing in the prior art, there is provided a thyristor device for realizing I-III quadrant triggering based on a buried layer structure; On the other hand, a manufacturing method for preparing the thyristor device is also provided.

[0007] The specific technical solution is as follows: A thyristor device that realizes triggering in the I-III quadrants based on a buried layer structure, including a substrate and a front base region formed above the substrate; A plurality of buried layer structures are formed in the substrate, and the buried layer structures are located below the front base region electrodes of the front base region; A conductive channel is further formed between the front base region and the substrate under the gate electrode; The conductive channel extends downward to the depth of the buried layer structure and is connected to the buried layer structure; When the external current of the thyristor device enters the second quadrant, the trigger current is increased through the buried layer structure to avoid mis-triggering.

[0008] On the other hand, the substrate is of the first doping type; The buried layer structure includes an outer shell part of the second doping type and a core part of the first doping type; The upper and lower surfaces of the buried layer structure are both located in the substrate and are in contact with the substrate through the outer shell part; The outer shell part wraps the core part.

[0009] On the other hand, the conductive channel includes a front base region conductive channel; The front base region conductive channel is formed in the front base region, and the front base region conductive channel has a doping type different from that of the front base region; The front base region conductive channel extends downward from the gate electrode, penetrates into the substrate conductive channel, and reaches the position where the buried layer structure is located.

[0010] On the other hand, the conductive channel further includes a substrate conductive channel; The substrate conductive channel is formed in the substrate, and the substrate conductive channel has a doping type different from that of the substrate; The substrate conductive channel is in contact with the buried layer structure closest to the gate electrode in the lateral direction; The substrate conductive channel extends downward from the upper surface of the substrate to below the height where the buried layer structure is located and completely wraps the front base region conductive channel.

[0011] On the other hand, the thyristor device further includes: A plurality of front emitter regions, and the front emitter regions are distributed on one side of the upper layer of the front base region far from the front emitter region electrodes; The front emission region has a doping type different from that of the front base region; A continuous front emission region electrode is formed above the front emission region; A passivation layer, which is formed on the upper surface of the thyristor device and separates the front base region electrode, the gate electrode, and the front emission region electrode; A back base region is formed below the substrate; A back base region electrode is formed below the back base region.

[0012] On the other hand, at least one back emission region is formed below the back base region, and the back emission region is in contact with the back base region electrode.

[0013] On the other hand, the thyristor device further includes: Grooves, which are distributed on both sides of the front base region, and the grooves are filled with a passivation glass layer.

[0014] On the other hand, the thyristor device further includes: A terminal structure, which is distributed on the left and right sides of the front base region; The depth of the terminal structure is greater than the depth of the front base region.

[0015] On the other hand, the thyristor device further includes: A pair of through isolation diffusion regions, which are formed at the two side edges of the thyristor device.

[0016] A preparation method for preparing the above-mentioned thyristor device, including: Step S1: Inject the substrate multiple times to respectively form a buried layer structure and a conductive channel, and then perform epitaxy to obtain a complete substrate; Step S2: Inject the substrate to form a front base region, and inject the front base region to connect the conductive channel; Step S3: Inject the front base region to form a front emission region, and then prepare a front emitter electrode, a gate electrode, and a front base region electrode; Step S4: Prepare a back base region and a back base region electrode on the back surface of the substrate.

[0017] The above technical solution has the following advantages or beneficial effects: In view of the problem that thyristor devices in the prior art may be mis-triggered in the second quadrant in an AC power system, in this solution, a buried layer structure is added in the middle of the substrate and connected to the gate electrode through a conductive channel. When the device operates in the second quadrant, the conduction path from the buried layer structure to the gate electrode enables the export of charges, thereby greatly increasing the trigger current threshold. When the trigger value in the first and third quadrants is about 30 mA, a trigger value above 500 mA in the second quadrant can be achieved, effectively avoiding the possibility of mis-triggering. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Reference is made to the accompanying drawings for a more complete description of the embodiments of the present invention. However, the accompanying drawings are only for illustration and explanation and do not constitute a limitation on the scope of the present invention.

[0019] Figure 1 Schematic diagram of the overall structure of an embodiment of the present invention; Figure 2 Schematic diagram of the overall structure of another embodiment of the present invention; Figure 3 Schematic diagram of the overall structure of another embodiment of the present invention; Figure 4 Schematic diagram of the preparation method of the present invention; Figure 5 Schematic diagram of the through isolation diffusion region in an embodiment of the present invention; Figure 6 Schematic diagram of the substrate implantation in an embodiment of the present invention; Figure 7 Schematic diagram of the buried layer structure implantation in an embodiment of the present invention; Figure 8 Schematic diagram of the substrate epitaxy in an embodiment of the present invention; Figure 9 Schematic diagram of the secondary implantation of the buried layer structure in an embodiment of the present invention; Figure 10 Schematic diagram of the epitaxy above the buried layer in an embodiment of the present invention; Figure 11 Schematic diagram of adding a conductive channel in an embodiment of the present invention; Figure 12 Schematic diagram of further epitaxy in an embodiment of the present invention; Figure 13 Schematic diagram of the base region implantation in an embodiment of the present invention; Figure 14 Schematic diagram of the emitter region implantation in an embodiment of the present invention; Figure 15 Schematic diagram of the passivation in an embodiment of the present invention; Figure 16 Schematic diagram of the trench in an embodiment of the present invention; Figure 17 Schematic diagram of the electrode in an embodiment of the present invention. Detailed implementation mode

[0020] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts belong to the scope of protection of the present invention.

[0021] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0022] Next, the present invention will be further described in conjunction with the accompanying drawings and specific embodiments, but it is not limited to the present invention.

[0023] The present invention includes: A thyristor device that realizes I-III quadrant triggering based on a buried layer structure, as Figure 1 shown, including a substrate 1 and a front base region 2 formed above the substrate; A plurality of buried layer structures 3 are formed in the substrate 1, and the buried layer structures 3 are located below the front base region electrode 4 of the front base region 2; A conductive channel 6 is further formed between the front base region 2 and the substrate 1 under the gate electrode 5; The conductive channel 6 extends downward to the depth of the buried layer structure 3 and is connected to the buried layer structure 3; When the external current of the thyristor device enters the second quadrant, the trigger current is increased through the buried layer structure 3 to avoid mis-triggering.

[0024] Specifically, aiming at the problem that the thyristor device in the prior art may be mis-triggered in the second quadrant in the AC power system, in this solution, a buried layer structure is added in the middle of the substrate and connected to the gate electrode through a conductive channel. When the device operates in the second quadrant, the conduction path from the buried layer structure to the gate electrode realizes the export of charges, thereby greatly increasing the trigger current threshold. When the trigger value in the first and third quadrants is about 30 mA, a trigger value of 500 mA in the second quadrant can be achieved, effectively avoiding the possibility of mis-triggering.

[0025] Specifically, the above technical solution is mainly embodied as a bidirectional thyristor device in the implementation process. The thyristor device includes a substrate 1, and the substrate 1 has a first doping type. Taking an N-type device as an example, the substrate 1 is lightly doped N-type.

[0026] Above the substrate 1, a front base region 2 is formed by ion implantation. The front base region 2 has a second doping type, which is P-type doping in this embodiment.

[0027] A plurality of front emitter regions 7 are formed in the front base region 2 by ion implantation. The front emitter regions 7 have a first doping type, which is N-type heavy doping in this embodiment. There is a certain interval between the plurality of front emitter regions 7, which is achieved by defining an implantation window through a photoresist or a mask during implantation. The junction depth of the front emitter region 7 is shorter than that of the front base region 2.

[0028] A plurality of front emitter regions 7 are distributed on the upper layer of the front base region 2 on a side away from the front base region electrode 4, and a continuous front emitter region electrode 8 is formed above.

[0029] Three electrodes are sequentially formed on the front of the device: a front emitter electrode 8 completely covering the plurality of front emitter regions 7, a gate electrode 5 covering the front base region 2 and connected to the conductive channel 6, and a front base electrode 4 covering the front base region 2. When in use, the gate electrode 5 serves as the control terminal G to connect to an external control signal, and the front emitter electrode 8 and the front base electrode 4 are short-circuited to serve as the T2 electrode on the front of the device to connect to the corresponding circuit.

[0030] A back-side base region 9 is also prepared below the substrate 1 through a back-side process. The back-side base region 9 has a second doping type, which is P-type doping in this embodiment.

[0031] The bottom of the back base region 9 is metallized to form a back base region electrode 10. When in use, the back base region electrode 10 serves as the T1 electrode at the bottom of the device to connect to an external circuit.

[0032] In the application process, the thyristor device will work in different quadrants according to the different directions of the current applied to the T1 electrode, the T2 electrode and the gate electrode 5. The second quadrant refers to the working state where the T1 electrode is positively charged and the gate electrode 5 is negatively charged, that is, the back base electrode 10 is positively charged and the gate electrode 5 is negatively charged.

[0033] In this state, in order to prevent the device from being triggered by mistake, in this embodiment, a corresponding conductive channel is formed through the buried structure 3 and the conductive channel 6. Since the current direction in the second quadrant is from the back base electrode 10 to the gate electrode 5, the additional extraction of charge can be achieved through the buried structure 3, which in disguise reduces the amount of charge applied to the active area, thereby increasing the threshold of the trigger current.

[0034] By regulating the buried structure 3, when the trigger current of the first and third quadrants is about 30mA, the trigger current of the second quadrant can be increased to 500mA by introducing the buried structure 3 and the conductive channel 6, and it can be considered that there is basically no possibility of false triggering.

[0035] The number of buried structures 3 and conductive channels 6 may be adjusted as required, for example, Figure 2In the illustrated embodiment, the number of buried layer structures 3 is reduced from three to one, but the setting position remains unchanged; In Figure 3 the illustrated embodiment, the number of buried layer structures 3 is reduced from three to two.

[0036] The above structural design is the main device structural design in this application. According to the configurations and index requirements of different devices, other structural features can also be combined, such as: The thyristor device further includes: A passivation layer 11, which is formed on the upper surface of the thyristor device and spaces apart the front base region electrode 4, the gate electrode 5, and the front emitter region electrode 8.

[0037] Among them, the passivation layer 11 is mainly a passivation structure formed by sacrificial oxidation after the front emitter region is prepared. It plays a role in protecting the front of the device and preventing water vapor from entering.

[0038] After the passivation layer 11 is formed, preparation windows for the front base region electrode 4, the gate electrode 5, and the front emitter region electrode 8 are defined by photolithography, and then an electrode metal layer is formed by evaporation or deposition.

[0039] Optionally, at least one back emitter region 12 is formed below the back base region 9, and the back emitter region 12 is in contact with the back base region electrode 10.

[0040] Specifically, according to different device designs, in this embodiment, at least one back emitter region 12 is also formed in the back base region 9 by back injection. The back emitter region 12 has a first doping type, which is N-type doping in the N-device embodiment.

[0041] One or more back emitter regions 12 are provided. Their lower bottom surfaces are in direct contact with the back base region electrode 10, and their upper surfaces are located in the back base region 9.

[0042] And, the thyristor device further includes: Grooves 13, which are distributed on both sides of the front base region, and the grooves 13 are filled with a passivation glass layer.

[0043] Specifically, to achieve a better protection effect on the device, in this embodiment, after a front base region 2 with sufficient length is formed, a pair of grooves 13 are formed at the edge positions of the device by etching, and a passivation glass layer is filled in the grooves 13 to achieve good sealing of the device. The bottom of the grooves usually needs to reach the depth of the front base region 2.

[0044] Or, as Figure 3 shown, the thyristor device further includes: The terminal structure 14 is distributed on the left and right sides of the front base region 2; The depth of the terminal structure 14 is greater than the depth of the front base region 2.

[0045] Specifically, to improve the breakdown voltage performance of the device, in this embodiment, the terminal structure 14 is also formed on the left and right sides of the front base region 2 by ion implantation. The terminal structure 14 has a second doping type, thereby improving the breakdown voltage level of the device.

[0046] Considering the device layout problem, usually only one of the above-mentioned trenches 13 and terminal structures 14 is selected for fabrication.

[0047] It also includes: The through isolation diffusion region 15 is formed on both side edges of the thyristor device.

[0048] Specifically, to achieve a better device protection effect, in this embodiment, the through isolation diffusion region 15 is formed on both sides of the thyristor device by the through isolation diffusion process, wrapping the two side edges of the thyristor device to achieve good passivation characteristics.

[0049] In one embodiment, the substrate 1 is of the first doping type; The buried layer structure 3 includes an outer shell portion 31 of the second doping type and a core portion 32 of the first doping type; Both the upper and lower surfaces of the buried layer structure 3 are located in the substrate 1 and are in contact with the substrate 1 through the outer shell portion 31; The outer shell portion 31 wraps the core portion 32.

[0050] Specifically, to further increase the trigger current, in this embodiment, the buried layer structure 3 is adjusted to have an outer shell portion 31 of the second doping type and a core portion 32 of the first doping type. With the above structure, an NPN or PNP structure device can be formed with the substrate 1 of the first doping type, further modulating the electric field distribution of the substrate 1 at a specific depth, thereby effectively increasing the trigger current.

[0051] During implementation, the above-mentioned buried layer structure 3 includes one or more, but is mainly distributed below the front base region electrode 4.

[0052] Wherein, taking the gate electrode 5 and the conductive channel 6 below as the demarcation line, one side of the gate electrode 5 is the distribution region of the front emitter region 7, and the other side is the region with only the front base region 2.

[0053] All the buried layer structures 3 are distributed on one side of the region in the substrate 1 with only the front base region 2.

[0054] When multiple buried layer structures 3 are provided, each buried layer structure 3 has a predetermined length and is distributed at a certain interval in the substrate 1. The outer shell portion 31 presents a rectangular structure in cross-section and is in contact with the substrate 1 on all four sides, top, bottom, left, and right.

[0055] In one embodiment, the conductive channel 6 includes a front base region conductive channel 61; The front base region conductive channel 61 is formed in the front base region, and the front base region conductive channel 61 has a doping type different from that of the front base region 2; The front base region conductive channel 61 extends downward from the gate electrode 5 and penetrates into the substrate 1 to reach the position where the buried layer structure 3 is located.

[0056] Specifically, to achieve better conductive characteristics, in this embodiment, a vertical front base region conductive channel 61 is formed in the front base region 2. The front base region conductive channel 61 is formed by ion implantation and has a doping type different from that of the front base region 2. That is, when the front base region 2 has a second doping type, the front base region conductive channel 61 has a first doping type.

[0057] The front base region conductive channel 61 has a relatively narrow width, with the top connected to the gate electrode 5, the bottom penetrating into the substrate 1 and reaching the position of the buried layer structure 3. At least one edge of the buried layer structure 3 is directly connected to the front base region conductive channel 61 to form a conductive channel, thereby providing a specific potential difference for the NPN or PNP structure.

[0058] At least one front base region conductive channel 61 is provided, and multiple front base region conductive channels 61 may also be provided in parallel according to needs.

[0059] In the embodiment of the N-type device, the front base region conductive channel 61 is of N-type doping type.

[0060] In one embodiment, the conductive channel 6 further includes a substrate conductive channel 62; The substrate conductive channel 61 is formed in the substrate 1, and the substrate conductive channel 62 has a doping type different from that of the substrate 1; The substrate conductive channel 62 is in contact with the buried layer structure 3 closest to the gate electrode 5 in the lateral direction; The substrate conductive channel 62 extends downward from the upper surface of the substrate 1 to a position below the height where the buried layer structure 3 is located and completely wraps the front base region conductive channel 61.

[0061] Specifically, considering that the conductive channel needs to penetrate the front base region 2 and the substrate 1, therefore, to achieve the process of limiting the conductive channel through the heterojunction, in this embodiment, after the front base region conductive channel 61 with the first doping type extends downward into the substrate 1, it is wrapped in the substrate 1 by the substrate conductive channel 62.

[0062] Among them, the substrate conductive channel 62 has a second doping type, which is a heterostructure with respect to the front base region conductive channel 61 of the first doping type, and can also space the substrate 1 of the first doping type.

[0063] The substrate conductive channel 62 is a rectangular region formed in the substrate 1 by ion implantation, reaching the lower surface of the front base region 2 and the part of the substrate 1 below the buried layer structure 3 in the height direction respectively.

[0064] In the lateral width, it is wide enough to wrap the lateral widths of all the front base region conductive channels 61, and contacts the buried layer structure 3 closest to the gate electrode 5 on the side close to the buried layer structure 3. The buried layer structure 3 refers to the first buried layer structure 3 that appears in the direction of extending from the center line of the gate electrode 5 to the edge.

[0065] On the other side of the lateral width, the width should be controlled to wrap all the front base region conductive channels 61 while avoiding affecting the current channels corresponding to the front emitter regions.

[0066] Through the above structural design, a better formation of the conductive channels can be achieved.

[0067] In one embodiment, the thyristor device further includes: A plurality of front emitter regions 7, which are distributed on the upper layer of the front base region 2 on the side far from the front base region electrode 4; The front emitter regions 7 have a doping type different from that of the front base region 2; A continuous front emitter region electrode 8 is formed above the front emitter regions 7; Specifically, a plurality of front emitter regions 7 are formed in the front base region 2 by ion implantation. The front emitter regions 7 have the first doping type, which is N-type heavy doping in this embodiment. There is a certain interval between the plurality of front emitter regions 7, which is achieved by defining the implantation window via a photoresist or a mask during implantation. The junction depth of the front emitter regions 7 is shorter than that of the front base region 2.

[0068] A plurality of front emitter regions 7 are distributed on the upper layer of the front base region 2 on the side far from the front base region electrode 4, and a continuous front emitter region electrode 8 is formed above.

[0069] A passivation layer 11, which is formed on the upper surface of the thyristor device and spaces the front base region electrode 4, the gate electrode 5, and the front emitter region electrode 8; The passivation layer 11 is mainly a passivation structure formed by sacrificial oxidation after the front emitter regions are prepared. It plays a role in protecting the front of the device and preventing water vapor from entering.

[0070] After forming the passivation layer 11, the preparation windows for the front base region electrode 4, the gate electrode 5, and the front emitter region electrode 8 are defined by photolithography, and then the electrode metal layer is formed by evaporation or deposition.

[0071] A back base region 9 is formed below the substrate 1; A back base region electrode 10 is formed below the back base region 9.

[0072] The back base region 9 is also prepared below the substrate 1 by a back process. The back base region 9 has a second doping type, which is P-type doping in this embodiment.

[0073] Metallization is performed below the back base region 9 to form the back base region electrode 10. The back base region electrode 10 serves as the T1 electrode at the bottom of the device to connect to an external circuit during use.

[0074] In one embodiment, at least one back emitter region 12 is formed below the back base region 9, and the back emitter region is in contact with the back base region electrode.

[0075] In one embodiment, the thyristor device further includes: Grooves 13, which are distributed on both sides of the front base region. The grooves 13 are filled with a passivation glass layer.

[0076] Specifically, to achieve a better protection effect on the device, in this embodiment, after forming the front base region 2 with a sufficient length, a pair of grooves 13 are formed at the edge positions of the device by etching, and a passivation glass layer is filled in the grooves 13 to achieve good sealing of the device. The bottom of the grooves generally needs to reach the depth of the front base region 2.

[0077] In one embodiment, the thyristor device further includes: Terminal structures 14, which are distributed on the left and right sides of the front base region 2; The depth of the terminal structures 14 is greater than the depth of the front base region 2.

[0078] Specifically, to improve the breakdown voltage performance of the device, in this embodiment, the terminal structures 14 are also formed on the left and right sides of the front base region 2 by ion implantation. The terminal structures 14 have a second doping type, thereby improving the breakdown voltage rating of the device.

[0079] In one embodiment, the thyristor device further includes: An anode-cathode isolation diffusion region 15, which is formed at the two side edges of the thyristor device.

[0080] Specifically, to achieve a better device protection effect, in this embodiment, a through-connection isolation diffusion region 15 is formed on both sides of the thyristor device through a through-connection isolation diffusion process to wrap the two side edges of the thyristor device, thereby achieving good passivation characteristics.

[0081] A preparation method for preparing the above-mentioned thyristor device, as Figure 4 shown, includes: Step S1: Inject the substrate multiple times to respectively form a buried layer structure and a conductive channel, and then perform epitaxy to obtain a complete substrate; Step S2: Inject the substrate to form a front base region, and inject the front base region to connect the conductive channels; Step S3: Inject the front base region to form a front emitter region, and then prepare a front emitter electrode, a gate electrode, and a front base region electrode; Step S4: Prepare a back base region and a back base region electrode on the back of the substrate.

[0082] Specifically, to achieve a better preparation effect, in this embodiment, during the preparation of the device, first, a buried layer structure is grown by injecting and epitaxying the substrate multiple times.

[0083] Specifically, the buried layer structure includes a central part of the outer shell part with different doping types, and the buried layer structure is wrapped in the substrate.

[0084] Then, during the preparation of the buried layer structure, the outer shell part can be formed by first injecting the second doping type into the substrate, and then the central part can be formed by injecting the first type into the outer shell part respectively. Then, the substrate is epitaxied to a certain height, and the second doping type is injected into the position corresponding to the outer shell part to form the top of the outer shell part to wrap the central part, and finally, epitaxy is performed again to form a complete substrate.

[0085] The specific preparation process is as follows: Taking the embodiment of an N-type bidirectional thyristor device with a back emitter region, a through-connection isolation diffusion region, and a trench structure as an example.

[0086] During preparation, as Figure 5 shown, first, an N-type doped substrate A1 is taken. The specification of the substrate A1 is a 6-inch wafer, the chip thickness is 300 microns, the N-type doping resistivity is 15 ΩCM, and it is a polished wafer.

[0087] Subsequently, the substrate A1 is doped by lithography to form a through-connection isolation diffusion region A2. The doping process includes AL injection doping, and then diffusion at 1250 °C. Diffusion connection isolation is performed from both sides of the substrate A1 to form the through-connection isolation diffusion region A2.

[0088] Then, as Figure 6As shown, implantation windows are defined on the front side of substrate A1 through photoresist, and P-type doping is performed through ion implantation process respectively, so as to form partial substrate conductive channels A3 and the shell part of buried layer structure A4.

[0089] The shell part here includes the bottom and the side of the shell part. Three buried layer structures A4 are prepared respectively. The buried layer structure A4 closest to the center is directly connected to the substrate conductive channel A3.

[0090] Subsequently, as Figure 7 shown, photolithography and development are carried out, and then N-type implantation is performed, so as to form a central part with a certain thickness in the central area of the shell part of the buried layer structure A4. The bottom of the central part does not reach the bottom of the shell part.

[0091] Then, as Figure 8 shown, epitaxy is carried out on substrate A1, and then as Figure 9 shown, implantation continues to complete the substrate conductive channels A3 in the epitaxial part, the top cover of the shell part of the buried layer structure A4, and the through-connection isolation diffusion regions on both sides; On this basis, as Figure 9 shown, N-type implantation is performed on the substrate conductive channel A3 to form a pair of front base region conductive channels A5.

[0092] Subsequently, as Figure 10 shown, further epitaxy is carried out on substrate A1 to completely wrap the buried layer structure in substrate A1. At the same time, as Figure 11 shown, implantation is used to complete the substrate conductive channels A3, the front base region conductive channels A5 and the through-connection isolation diffusion regions A2 in the epitaxial part. As Figure 12 shown, the complete substrate A1 is prepared by a gradually stretching method and the position of the front base region A6 above is reserved.

[0093] When the partial preparation of substrate A1 is completed, as Figure 13 shown, double-sided photolithography etching and P-type doping implantation are carried out to form the front base region A6 and the back base region A7 respectively. And N-type doping implantation is used to complete the front base region conductive channels A5 in the front base region A6.

[0094] Subsequently, as Figure 14 shown, N-type implantation is carried out on the front and back sides of the device respectively to form the front emitter region A8 and the back emitter region A9.

[0095] As Figure 15 shown, thermal oxidation is carried out on the front side of the device to grow the passivation layer A10.

[0096] And, as Figure 16As shown, grooves A11 are formed by etching on the left and right sides of the front base region A6, and a glass passivation layer is filled.

[0097] On this basis, as Figure 17 shown, multiple electrode windows are defined by etching the front of the device, and then evaporation is performed on the front and back to form the front emitter electrode A12, the gate electrode A13, the front base electrode A14, and the back base electrode A15 to complete the preparation process.

[0098] The above are only preferred embodiments of the present invention, and do not limit the implementation manners and protection scope of the present invention. For those skilled in the art, it should be realized that all equivalent replacements and obvious changes made by using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A thyristor device that realizes triggering in the I-III quadrants based on a buried layer structure, characterized in that, It includes a substrate and a front base region formed above the substrate; A plurality of buried layer structures are formed in the substrate, and the buried layer structures are located below the front base region electrodes of the front base region; A conductive channel is further formed between the front base region and the substrate below the gate electrode; The conductive channel extends downward to the depth of the buried layer structure and is connected to the buried layer structure; When the external current of the thyristor device enters the second quadrant, the trigger current is increased through the buried layer structure to avoid mis-triggering.

2. The thyristor device according to claim 1, characterized in that, The substrate is of the first doping type; The buried layer structure includes an outer shell part of the second doping type and a core part of the first doping type; Both the upper and lower surfaces of the buried layer structure are located in the substrate and are in contact with the substrate through the outer shell part; The outer shell part wraps the core part.

3. The thyristor device according to claim 1, characterized in that, The conductive channel includes a front base region conductive channel; The front base region conductive channel is formed in the front base region, and the front base region conductive channel has a doping type different from that of the front base region; The front base region conductive channel extends downward from the gate electrode and penetrates into the substrate to reach the position where the buried layer structure is located.

4. The thyristor device according to claim 3, characterized in that, The conductive channel further includes a substrate conductive channel; The substrate conductive channel is formed in the substrate, and the substrate conductive channel has a doping type different from that of the substrate; The substrate conductive channel is in contact with the buried layer structure closest to the gate electrode in the lateral direction; The substrate conductive channel extends downward from the upper surface of the substrate to below the height where the buried layer structure is located and completely wraps the front base region conductive channel.

5. The thyristor device according to claim 1, wherein, The thyristor device further includes: A plurality of front emitter regions, which are distributed on one side of the upper layer of the front base region away from the front base region electrode; The front emitter region has a doping type different from that of the front base region; A continuous front emitter region electrode is formed above the front emitter region; A passivation layer, which is formed on the upper surface of the thyristor device and spaces the front base region electrode, the gate electrode, and the front emitter region electrode; A back base region is formed below the substrate; A back base region electrode is formed below the back base region; 6. The thyristor device according to claim 5, characterized in that At least one back emitter region is formed below the back base region, and the back emitter region is in contact with the back base region electrode; 7. The thyristor device according to claim 1, characterized in that, The thyristor device further includes: Grooves, which are distributed on both sides of the front base region, and the grooves are filled with a passivation glass layer; 8. The thyristor device according to claim 1, characterized in that The thyristor device further includes: Terminal structures, which are distributed on the left and right sides of the front base region; The depth of the terminal structure is greater than the depth of the front base region; 9. The thyristor device according to claim 1, characterized in that, The thyristor device further includes: A pair of through isolation diffusion regions, which are formed on both side edges of the thyristor device; 10. A preparation method, characterized in that, For preparing the thyristor device according to any one of claims 1-9, including: Step S1: Inject the substrate multiple times to respectively form a buried layer structure and a conductive channel, and then perform epitaxy to obtain a complete substrate; Step S2: Inject the substrate to form a front base region, and inject the front base region to connect the conductive channels; Step S3: Inject the front base region to form a front emitter region, and then fabricate a front emitter electrode, a gate electrode, and a front base region electrode; Step S4: Fabricate a back base region and a back base region electrode on the back surface of the substrate.

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