HEMT device and manufacturing method thereof
The described manufacturing method for HEMT devices addresses the challenge of high ohmic contact resistance by ion implantation and temperature-activated growth of III-V compounds, resulting in improved conductivity and reduced power loss for GaN transistors.
Patent Information
- Application Number
- CN202510472187.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-15
- Publication Date
- 2025-07-15
AI Technical Summary
In the prior art, the ohmic contact resistance of GaN transistors is large, which affects device performance and is difficult to effectively reduce.
An n-type doped layer is formed by implanting ions in a predetermined region of the barrier layer structure, and the ion layer is activated at the growth temperature when forming the III-V compound of the gate structure and/or barrier layer structure to reduce the ohmic contact resistance of the source and drain metal.
Effectively reduce the ohmic contact resistance of the source and drain metal, improve the performance of GaN transistors, and does not require additional heat treatment processes.
Smart Images
Figure CN120321977A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of semiconductor technology, and relates to a HEMT device and a manufacturing method thereof. Background Art
[0002] With the increasing requirements of the market for the volume and energy efficiency of power devices, wide bandgap semiconductor GaN devices have been widely used in high-frequency power conversion systems due to lower power losses and faster switching capabilities. Compared with silicon metal oxide semiconductor field effect transistors (MOSFETs), GaN high electron mobility transistors (HEMTs) have better figure of merit and more promising performance in high-power and high-frequency applications.
[0003] In order to further improve the performance of GaN transistors, reducing the on-resistance of the device is an effective method, among which, reducing the ohmic contact (source-drain contact) resistance is crucial. Summary of the Invention
[0004] In view of the above-mentioned disadvantages of the prior art, the object of the present invention is to provide a HEMT device and a manufacturing method thereof to solve the problems existing in the prior art.
[0005] According to a first aspect of the present invention, there is provided a manufacturing method of a HEMT device, including: forming a stack including at least a base layer and a channel layer; forming a barrier layer structure step by step or in one step on the upper surface of the stack, wherein the barrier layer structure includes a first predetermined region and a second predetermined region arranged at intervals; forming an n-type doped ion layer by implanting ions in the first predetermined region of the barrier layer structure; forming a gate structure on the second predetermined region of the barrier layer structure, and forming source-drain metals on the first predetermined region of the barrier layer structure, wherein the ion layer is activated by the growth temperature when forming the gate structure and / or the III-V compound in the second predetermined region of the barrier layer structure to reduce the ohmic contact resistance of the source-drain metals.
[0006] Preferably, the method of forming the barrier layer structure includes: forming a first barrier layer covering the upper surface of the stack on the stack to form the barrier layer structure.
[0007] Preferably, the barrier layer structure includes at least a first barrier layer located in the first predetermined region and at least a second barrier layer located in the second predetermined region, wherein the thickness of the second barrier layer is less than the thickness of the first barrier layer.
[0008] Preferably, the step of forming the gate structure includes: growing p-type gallium nitride on the second predetermined region of the first barrier layer, and forming a gate metal on the p-type gallium nitride.
[0009] Preferably, the steps of forming the barrier layer structure include: forming the first barrier layer covering the upper surface of the stack; after forming the n-type doped ion layer in a first predetermined area of the first barrier layer, etching part of the first barrier layer to expose the upper surface of part of the channel layer, and regrowing the second barrier layer on the exposed channel layer, wherein the second barrier layer comprises a III-V compound.
[0010] Preferably, the steps of forming the gate structure include: growing p-type gallium nitride on the second barrier layer, and forming gate metal on the p-type gallium nitride.
[0011] Preferably, the steps of forming the gate structure include: forming a gate dielectric layer on the second barrier layer, and forming gate metal on the gate dielectric layer.
[0012] Preferably, the ions include silicon ions or oxygen ions or germanium ions or nitrogen ions.
[0013] Preferably, it further includes forming a capping layer covering the first barrier layer.
[0014] Preferably, the method of forming the n-type doped ion layer includes: forming a patterned photoresist layer on the capping layer; using the photoresist layer as a mask to etch part of the capping layer to expose the first barrier layer; and using the photoresist layer and the capping layer as masks to perform ion implantation to form the ion layer.
[0015] Preferably, after forming the n-type doped ion layer, it further includes forming a first dielectric layer on the capping layer.
[0016] Preferably, the method of forming source / drain metal on the first predetermined area includes: forming an interlayer dielectric layer covering the gate structure and the barrier layer structure; etching the interlayer dielectric layer to form an opening exposing the first predetermined area of the barrier layer structure; and depositing metal in the opening to form the source / drain metal.
[0017] Preferably, it further includes: forming a first passivation layer on the upper surfaces of the interlayer dielectric layer and the source / drain metal; etching part of the first passivation layer to form a first via exposing the source / drain metal; etching part of the first passivation layer and part of the interlayer dielectric layer to form a second via exposing the gate structure; and depositing metal in the first via and the second via to form a first interconnect metal.
[0018] According to a second aspect of the present invention, there is provided a HEMT device, characterized in that it includes: a base layer, a channel layer located on the upper surface of the base layer; a barrier layer located on the upper surface of the channel layer; source-drain metals located on a first predetermined area of the barrier layer, and a gate structure located on a second predetermined area of the barrier layer; wherein, the surface of the first predetermined area of the barrier layer is set to be n-type doped.
[0019] Preferably, the barrier layer includes a first barrier layer at least located in the first predetermined area and a second barrier layer at least located in the second predetermined area, wherein the thickness of the second barrier layer is less than the thickness of the first barrier layer.
[0020] According to a third aspect of the present invention, there is provided a manufacturing method of a HEMT device including a depletion-type structure and an enhancement-type structure, characterized in that it includes: forming a stack including a base layer, a channel layer and a first barrier layer, the stack including a first structure and a second structure; forming an n-type doped ion layer by implanting ions in a first predetermined area of the first barrier layer in the first structure and a second predetermined area of the first barrier layer in the second structure; etching part of the first barrier layer in the first gate area of the first structure to expose the channel layer, the first gate area being spaced from the first predetermined area; regrowing a second barrier layer on the exposed channel layer, the second barrier layer including a material layer of a III-V compound; forming a first gate structure on the second barrier layer; forming source-drain metals on the first predetermined area and the second predetermined area, and forming a second gate structure in a second gate area of the second structure, wherein the ion layer is activated by the growth temperature during the process of forming the second barrier layer to reduce the ohmic contact resistance of the source-drain.
[0021] Preferably, the step of forming the first gate structure includes: growing p-type gallium nitride on the second barrier layer, and forming a first gate metal located on the p-type gallium nitride.
[0022] Preferably, the thickness of the second barrier layer is less than the thickness of the first barrier layer.
[0023] Preferably, the method of forming the second gate structure includes: forming a gate dielectric layer on a second gate area of the first barrier layer, and forming a second gate metal located on the gate dielectric layer.
[0024] The present invention provides a method for manufacturing a HEMT. N-type ions are formed in a first predetermined region of the barrier layer structure by ion implantation doping, and then the ion layer is activated by the growth temperature when forming a III-V compound in a second predetermined region of the gate structure and / or the barrier layer structure, so as to reduce the ohmic contact resistance of the source-drain metal. The method provided by the present invention solves the problem that it is difficult to activate ions in the barrier layer structure, and does not require additional heat treatment in the process, and does not introduce additional process heat budget. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 It is a flowchart showing the manufacturing method of the HEMT device provided by the present invention;
[0026] Figures 2a - 2h It is a structural diagram showing each step of manufacturing the HEMT device according to the first embodiment of the present invention;
[0027] Figures 3a - 3b It is a structural diagram showing each step of manufacturing the HEMT device according to the second embodiment of the present invention;
[0028] Figures 4a - 4e It is a structural diagram showing each step of manufacturing the HEMT device according to the third embodiment of the present invention;
[0029] Figure 5 It is a flowchart showing the manufacturing method of the HEMT device provided by the present invention, including a depletion type structure and an enhancement type structure;
[0030] Figures 6a - 6g It is a structural diagram showing each step of manufacturing the HEMT device according to the fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0031] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0032] Such as Figure 1As shown in the figure, the present invention provides a manufacturing method of a HEMT device, including: S1: forming a stack layer including at least a base layer and a channel layer; S2: forming a barrier layer structure step by step or at one time on the upper surface of the stack layer, wherein the barrier layer structure includes a first predetermined region and a second predetermined region arranged at intervals; S3: forming an n-type doped ion layer by implanting ions into the first predetermined region of the barrier layer structure; S4: forming a gate structure on the second predetermined region of the barrier layer structure, and S5: forming source and drain metals on the first predetermined region of the barrier layer structure, wherein the ion layer is activated by the growth temperature when forming the III-V compound (such as GaN, AlGaN, AlN, etc.) in the gate structure and / or the second predetermined region of the barrier layer structure to reduce the ohmic contact resistance of the source and drain metals.
[0033] In one embodiment, the method of forming the barrier layer structure includes: forming a first barrier layer covering the upper surface of the stack layer on the stack layer. Wherein, the gate structure is located on the second predetermined region of the first barrier layer.
[0034] In another embodiment, the barrier layer structure includes at least a first barrier layer located in the first predetermined region and at least a second barrier layer located in the second predetermined region, wherein the thickness of the second barrier layer is less than that of the first barrier layer. The steps of forming the barrier layer structure include: forming a first barrier layer covering the upper surface of the stack layer; etching part of the first barrier layer to expose the upper surface of part of the channel layer, and regrowing a second barrier layer on the exposed channel layer, wherein the second barrier layer includes III-V compound base materials such as AlN, GaN or AlGaN, and the gate structure is located on the second barrier layer.
[0035] Please refer to Figures 2a - 2h , which is the manufacturing method of the HEMT device according to the first embodiment of the present application. In this embodiment, the HEMT is taken as an enhancement structure for illustration. In this embodiment, the barrier layer structure is formed step by step. The barrier layer structure includes at least a first barrier layer located in the first predetermined region and at least a second barrier layer located in the second predetermined region, wherein the thickness of the second barrier layer is less than that of the first barrier layer. The specific steps are as follows:
[0036] Step S1: forming a stack layer including at least a base layer and a channel layer. Specifically, as Figure 2aAs shown, a base layer is grown successively, and a channel layer 103 located on the base layer. The base layer includes a substrate 101. In an optional embodiment, the base layer includes a substrate 101 and a buffer layer 102. The buffer layer 102 is disposed between the substrate 101 and the channel layer 103 to reduce the problem of lattice mismatch between the substrate 101 and the channel layer 103. The substrate 101 can be a silicon substrate, a sapphire substrate, a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, or silicon on insulator (SOI), etc. The buffer layer 102 can be a group III-V compound such as AlN, GaN, or AlGaN, etc.
[0037] Step S2: Form a barrier layer structure on the upper surface of the stack. Among them, the barrier layer structure includes a first predetermined region and a second predetermined region arranged at intervals. Specifically, in this embodiment, the barrier layer structure includes at least a first barrier layer located in the first predetermined region and at least a second barrier layer located in the second predetermined region. Among them, the thickness of the second barrier layer is less than the thickness of the first barrier layer.
[0038] First, as Figure 2a shown, a first barrier layer 104 is formed on the channel layer 103. Among them, the channel layer 103 has a (relatively) small bandgap layer (such as a GaN semiconductor layer), and the first barrier layer 104 has a (relatively) large bandgap layer (such as semiconductor layers such as AlGaN, InAlN, AlN, etc.). The two-dimensional electron gas is formed at the interface between the channel layer 103 and the first barrier layer 104. Specifically, it is located at the top of the channel layer 103. Among them, the second barrier layer is formed in a subsequent process.
[0039] In an optional embodiment, it may further include a cap layer 105 located on the first barrier layer 104. The cap layer 105 is used to protect the surface of the first barrier layer 104 to prevent the first barrier layer 104 from being oxidized. The cap layer 105 can include group III-V compounds such as GaN, AlGaN, etc.
[0040] Step S3: Form an n-type doped ion layer by implanting ions into the first predetermined region of the barrier layer structure (the first barrier layer 104). Specifically, as Figure 2bAs shown, first, a patterned photoresist layer 200 is formed on the capping layer 105. The patterned photoresist layer 200 exposes a predetermined area of the capping layer 105. Further, the exposed capping layer 105 is etched to expose a first predetermined area of the first barrier layer 104. Finally, ions are implanted into the first predetermined area of the first barrier layer 104 to form an n-type doped ion layer. Among them, the source and drain electrodes are formed on the first predetermined area subsequently. The ions may include silicon ions, oxygen ions, germanium ions, nitrogen ions, etc. Among them, the silicon ions replace the gallium ions in the first barrier layer (AlGaN) to form n-type doping; or the oxygen ions replace the nitrogen ions in the first barrier layer (AlGaN) to form n-type doping. Finally, the photoresist layer 200 is removed.
[0041] In an alternative embodiment, if the HEMT device does not include a capping layer, then the method includes forming a mask layer on the first barrier layer. The mask layer exposes the upper surface of a first predetermined area of the first barrier layer, and then ions are implanted into the first predetermined area of the first barrier layer 104 to form an n-type doped ion layer.
[0042] After forming the n-type doped ions, continue with the method of step S2 to form the second barrier layer in the barrier layer structure. Specifically, as Figure 2c shown, first, a first dielectric layer 106 is formed on the capping layer 105 and the exposed first barrier layer (the step of forming the first dielectric layer 106 can also be omitted) to protect the capping layer 105. Then, by etching a part of the first dielectric layer 106, a part of the capping layer 105, and a part of the first barrier layer 104, the upper surface of a part of the channel layer 103 is exposed. The exposed area of the trench layer 103 is set as the gate region 300, and the gate region 300 is spaced from the first predetermined area. Finally, as Figure 2d shown, a regrown barrier layer 400 is formed on the upper surface of the structure shown in 2c, that is, the regrown barrier layer 400 covers the first dielectric layer 106 and the upper surface of the exposed channel layer 103. The second barrier layer includes a III-V compound material. In this embodiment, the second barrier layer includes an AlGaN material.
[0043] Furthermore, setting the thickness of the second barrier layer to be less than the thickness of the first barrier layer makes it easier to form an enhancement-mode high electron mobility transistor; and the growth temperature (for example, the growth temperature is greater than 1000 °C) during the process of regrowing the second barrier layer can well activate the ion layer.
[0044] Step S4: Form a gate structure on the second predetermined area of the barrier layer structure.
[0045] As Figure 2eAs shown in the figure, continue to grow a P-type GaN or P-type AlGaN layer 210 on the regrowth barrier layer 400 and form a gate metal 220 on the P-type GaN or P-type AlGaN layer 210. Among them, the growth temperature of the P-type GaN or P-type AlGaN layer 210 is also greater than 1000 °C, which can further activate the ion layer. The gate metal is formed by a deposition process, and the metal may include titanium, nickel, titanium nitride, gold, etc.
[0046] Furthermore, as Figure 2f shown in the figure, sequentially etch part of the gate metal 220, part of the P-type GaN or P-type AlGaN layer 210, and part of the regrowth barrier layer 400 to form a gate structure and a second barrier layer 107 in the gate structure. The gate structure includes a P-type GaN or P-type AlGaN layer 108 covering the upper surface of the second barrier layer 107, and a gate metal 109 covering the upper surface of the P-type GaN or P-type AlGaN layer 108.
[0047] Step S4: Form source / drain metals 111 on the first predetermined region. Specifically, as Figure 2g shown in the figure, first form an interlayer dielectric layer 110 covering the upper surfaces of the first dielectric layer 106 and the gate metal 109, then etch part of the interlayer dielectric layer 110 and the first dielectric layer 106 to expose the first predetermined region of the first barrier layer 104, and finally form source / drain metals 111 in the first predetermined region. Since the first predetermined region of the first barrier layer has been ion-implanted to be n-type doped, and the ion layer is activated by the growth temperature of the III-V compound material to reduce the ohmic contact resistance of the source / drain region.
[0048] Furthermore, as Figure 2h shown in the figure, it further includes forming a passivation layer 112 covering the upper surfaces of the interlayer dielectric layer 110 and the source / drain metals 111, which also includes a first opening passing through the passivation layer 112 and exposing the upper surface of part of the source / drain metals, and a second opening starting from the upper surface of the passivation layer, passing through the passivation layer and part of the interlayer dielectric layer 110 and exposing the upper surface of the gate metal; form a first interconnect metal layer 113 in the first opening and the second opening respectively.
[0049] Please refer to Figures 3a - 3b, A manufacturing method of a HEMT device according to the second embodiment of the present application. In this embodiment, taking the HEMT as an enhancement-mode structure as an example for illustration. The difference from the first embodiment is that in this embodiment, the barrier layer structure is formed in one step without regrowing the second barrier layer, that is, the specific method included in step S2 is different, and other steps are exactly the same as those in the first embodiment, which will not be elaborated here. Among them, step S2 specifically includes: forming a first barrier layer 104 on the channel layer 103 to form the barrier layer structure. Subsequently, after forming n-type doping ions in a first predetermined region of the first barrier layer, the first barrier layer 104 is no longer etched to expose the channel layer 103.
[0050] Specifically, as Figure 3a shown, first form a first dielectric layer 106 on the capping layer 105 and the exposed first barrier layer to protect the capping layer 105; then etch part of the first dielectric layer 106 and part of the capping layer 105 to expose the upper surface of part of the first barrier layer 104. The exposed region of the first barrier layer 104 is set as the gate region 500, and the gate region 500 is spaced from the first predetermined region.
[0051] Further, as Figure 3b shown, form a P-type GaN or P-type AlGaN layer and a gate metal in the gate region. Specifically, grow a P-type GaN or P-type AlGaN layer on the first barrier layer 104 and the first dielectric layer 106 and form a gate metal on the P-type GaN or P-type AlGaN layer. Among them, the growth temperature of the P-type GaN or P-type AlGaN layer 108 is greater than 1000 °C, which can effectively activate the ion layer. The gate metal is formed by a deposition process, and the gate metal may include titanium, nickel, titanium nitride, gold, etc.
[0052] Further, sequentially etch part of the gate metal and part of the P-type GaN or P-type AlGaN layer to form a gate structure. The gate structure includes a P-type GaN or P-type AlGaN layer 108 covering the upper surface of the exposed first barrier layer and a gate metal 109 covering the upper surface of the P-type GaN or P-type AlGaN layer 108.
[0053] This embodiment saves the step of regrowing the barrier layer. Under the same effect of activating the ion layer, the process steps are reduced and the process cost is saved.
[0054] Please refer to Figures 4a - 4e, which is a manufacturing method of a HEMT device according to the third embodiment of the present application. In this embodiment, the HEMT is taken as an example of a depletion type structure for illustration. The difference from the first embodiment is that due to the different structures, the specific methods included in step S4 are also different, and the other steps are exactly the same as those in the first embodiment, which will not be elaborated here. Among them, step S4 specifically includes:
[0055] As Figure 4a shown, first, a first dielectric layer 106 is formed on the capping layer 105 and the exposed first barrier layer to protect the capping layer 105; then, by etching part of the first dielectric layer 106, part of the capping layer 105, and part of the first barrier layer 104 to expose the upper surface of part of the channel layer 103, the exposed area of the trench layer 103 is set as the gate region 300, and the gate region 300 is spaced from the first predetermined region; finally, on Figure 4a the upper surface of the structure, a second barrier layer 410 is formed, that is, the second barrier layer 410 covers the first dielectric layer 106 and the upper surface of the exposed channel layer, as Figure 4b shown, wherein the second barrier layer includes III-V materials such as AlGaN, AlN, InAlN, etc. The growth temperature (the growth temperature is greater than 1000 °C) during the process of regrowing the second barrier layer can well activate the ion layer.
[0056] Further, as Figure 4c shown, a gate dielectric layer 420 is continuously formed on the second barrier layer 410, and the gate dielectric layer 420 covers the upper surface of the second barrier layer 410. Among them, the gate dielectric layer 400 includes silicon oxide, silicon nitride, etc.
[0057] Further, as Figure 4d shown, part of the gate dielectric layer 420 and part of the second barrier layer 410 are etched in sequence to form the second barrier layer 307 and the gate dielectric layer 308 retained in the gate region 300.
[0058] Step S5: Form source / drain metals 111 on the first predetermined region. Specifically, as Figure 4e shown, first, an interlayer dielectric layer 110 covering the upper surfaces of the first dielectric layer 106 and the gate dielectric layer 308 is formed, then part of the interlayer dielectric layer 110 and the first dielectric layer 106 are etched to expose the first predetermined region of the first barrier layer 104, and finally source / drain metals 111 are formed on the first predetermined region.
[0059] Further, it further includes a passivation layer 112 formed to cover the upper surfaces of the interlayer dielectric layer 110 and the source / drain metal 111, wherein it further includes a first opening passing through the passivation layer 112 and exposing the upper surface of a part of the source / drain metal, and a second opening opened from the upper surface of the passivation layer, passing through the passivation layer and a part of the interlayer dielectric layer 110 and exposing the upper surface of the gate dielectric layer 308; a first interconnect metal layer 113 is formed in the first opening and a gate electrode 114 is formed in the second opening respectively.
[0060] Please refer to Figure 5 and Figures 6a - 6g , Figure 5 is a flowchart of a manufacturing method of a HEMT device including a depletion-type structure and an enhancement-type structure provided by the present invention. Figures 6a - 6g It is a manufacturing method of a HEMT device according to the fourth embodiment of the present application. In this embodiment, taking the HEMT including an enhancement-type and a depletion-type structure as an example for illustration. In this embodiment, a thermal process of regrowing the barrier layer of the enhancement-type structure is used to activate the ion layer in the enhancement-type and depletion-type structures. The method specifically includes:
[0061] Step S1: Form a stack including a base layer, a channel layer and a first barrier layer, the stack including a first structure and a second structure;
[0062] Specifically, as Figure 6a shown, a base layer, a channel layer 403 located on the base layer, and a first barrier layer 404 located on the channel layer 403 are sequentially grown to form a first stack 600. The channel layer 403 has a (relatively) small bandgap layer (such as a GaN semiconductor layer), the first barrier layer 404 has a (relatively) large bandgap layer (such as an AlGaN semiconductor layer), and the two-dimensional electron gas is formed at the interface between the channel layer 403 and the first barrier layer 404, specifically, at the top of the channel layer 403. The base layer includes a substrate 401. In an alternative embodiment, the base layer includes a substrate 401 and a buffer layer 402, and the buffer layer 402 is disposed between the substrate 401 and the channel layer 403 to reduce the degree of lattice mismatch between the substrate 401 and the channel layer 403. The substrate 401 can be a silicon substrate, a sapphire substrate, a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, or silicon on insulator (SOI), etc. The buffer layer 402 can be a group III-V compound such as AlN, GaN or AlGaN.
[0063] In an alternative embodiment, a capping layer 405 may further be included on the first barrier layer 404. The capping layer 405 is used to protect the surface of the first barrier layer 404 to prevent oxidation of the first barrier layer 404. The capping layer 405 may include group III-V compounds such as GaN and AlGaN. Figure 6a The dashed line in Figure 6a divides the first stack 600 into a first structure 510 and a second structure 520. An enhancement-mode structure is formed on the first structure 510, and a depletion-mode structure is formed on the second structure 520.
[0064] Step S2: Form an n-type doped ion layer by implanting ions into a first predetermined region of the first barrier layer in the first structure and a second predetermined region of the first barrier layer in the second structure.
[0065] An n-type doped ion layer is formed by implanting ions into a predetermined region of the first barrier layer 404. Specifically, as shown in Figure 6b , first, a patterned photoresist layer 530 is formed on the capping layer 405. The patterned photoresist layer 530 exposes a predetermined region of the capping layer 405. Further, the exposed capping layer 405 is etched to expose a predetermined region of the first barrier layer. Finally, ions are implanted into the predetermined region of the first barrier layer 404 to form an n-type doped ion layer. The predetermined region is set as the region for subsequently forming source and drain electrodes. The ions may include silicon ions, oxygen ions, germanium ions, nitrogen ions, etc. Among them, the silicon ions replace gallium ions in the first barrier layer to form n-type doping; or the oxygen ions replace nitrogen ions in the first barrier layer to form n-type doping. Finally, the photoresist layer 530 is removed. The predetermined region of the first barrier layer of the first structure 510 is set as the first predetermined region, and the predetermined region of the second barrier layer of the structure 520 is set as the second predetermined region. Figure 6b
[0066] Step S3: Etch part of the first barrier layer in the first gate region of the first structure to expose the channel layer. The first gate region is spaced apart from the first predetermined region.
[0067] Specifically, as shown in Figure 6c , first, a first dielectric layer 406 is formed on the capping layer 405 and the exposed first barrier layer 404 to protect the capping layer 405. Then, by etching part of the first dielectric layer 406, part of the capping layer 405, and part of the first barrier layer 404 in the first structure, the upper surface of part of the channel layer 403 is exposed. The exposed region of the trench layer 403 is set as the first gate region. The first gate region is spaced apart from the first predetermined region. Figure 6c
[0068] It should be noted that in this step, only the upper surface of a part of the channel layer of the first structure 510 is exposed, that is, only the gate region on the first structure 510 is formed.
[0069] Step S4: Regrow a second barrier layer on the exposed channel layer, and the second barrier layer includes a material layer of a III-V compound.
[0070] Further, a second barrier layer 700 is formed on the upper surface of the above structure, that is, the second barrier layer 700 covers the upper surface of the first dielectric layer 406 and the exposed channel layer 403. Among them, the second barrier layer includes III-V compounds (such as GaN, AlGaN, AlN, etc.). In this embodiment, the second barrier layer includes an AlGaN material. Setting the thickness of the second barrier layer 700 to be less than the thickness of the first barrier layer 404 makes it easier to form an enhancement-mode high electron mobility transistor; and the growth temperature (greater than 1000 °C) during the process of regrowing the second barrier layer 700 can well activate the ion layer.
[0071] Step S5: Form a first gate structure on the second barrier layer.
[0072] Further, continue to grow a P-type GaN or P-type AlGaN layer on the second barrier layer 700 and form gate metal on the P-type GaN or P-type AlGaN layer 800. Among them, the growth temperature for growing the P-type GaN or P-type AlGaN layer is also greater than 1000 °C, which can further activate the ion layer. The gate metal is formed by a deposition process, and the metal can include nickel, titanium, titanium nitride, gold, etc.
[0073] Further, sequentially etch part of the gate metal, part of the P-type GaN or P-type AlGaN layer, and part of the second barrier layer to form a first gate structure above the first structure. The first gate structure includes a P-type GaN or P-type AlGaN layer 408 covering the upper surface of the second barrier layer 407, and a gate metal 409 covering the upper surface of the P-type GaN or P-type AlGaN layer 408, as Figure 6d shown.
[0074] Step S6: Form source and drain metals on the first predetermined region and the second predetermined region.
[0075] Specifically, as Figure 6eAs shown, an interlayer dielectric layer 411 covering the upper surfaces of the first dielectric layer 406 and the gate metal 409 is first formed, and then a part of the interlayer dielectric layer 411 and the first dielectric layer 406 are etched to expose the predetermined region of the first barrier layer 404. Finally, source-drain metals 412 are formed in the predetermined regions. Specifically, a first source-drain metal is formed in the first predetermined region, and a second source-drain metal is formed in the second predetermined region.
[0076] Optionally, it further includes forming an isolation layer 540 between the first structure and the second structure, wherein the isolation layer extends downward at least from the lower surface of the first dielectric layer 406 to the buffer layer 402. Further, it also includes an isolation layer at the edge of the HEMT device to isolate it from other devices. The isolation layer can be formed by ion implantation or by forming trenches through an etching process.
[0077] Step S7: Form a second gate structure in the second gate region of the second structure.
[0078] Further, as Figure 6f shown, a gate dielectric layer and a gate metal are formed on the second gate region of the first barrier layer 404 of the second structure. Specifically, a first passivation layer 413 is first formed on the interlayer dielectric layer 411; then a part of the first passivation layer 413, a part of the interlayer dielectric layer 411, a part of the first dielectric layer 406, and a part of the capping layer 405 are sequentially etched to form a second gate opening to expose the second gate region of the first barrier layer 404; a gate dielectric layer 414 is continuously formed on the second gate region and the first passivation layer 413, wherein the gate dielectric layer 414 covers the bottom surface and side surfaces of the second gate opening, and the upper surface of the first passivation layer; finally, a gate metal 415 is formed to fill the second gate opening including the gate dielectric layer 414. The gate dielectric layer 414 includes silicon oxide, silicon nitride, etc.
[0079] Further, as Figure 6g shown, it further includes forming a second passivation layer 416 covering the upper surfaces of the gate dielectric layer 414 and the gate metal 415, and it also includes a first opening passing through the second passivation layer 416, the gate dielectric layer 414, and the first passivation layer 413 and exposing the upper surfaces of the first and second source-drain metals, a second opening passing through the second passivation layer 416, the gate dielectric layer 414, the first passivation layer 413, and a part of the interlayer dielectric layer 411 and exposing the upper surface of the first gate metal, and a third opening passing through the second passivation layer 416 and exposing the upper surface of the second gate metal 415; first interconnect metal layers 417 are respectively formed in the first opening, the second opening, and the third opening.
[0080] The manufacturing method of depletion-type and enhancement-type HEMT devices provided by the present invention activates the ion layers of the enhancement-type and depletion-type structures by re-growing the growth temperature of the barrier layer in the first gate region of the enhancement-type structure, so as to simultaneously reduce the ohmic contact resistance of the source-drain metals of the enhancement-type and depletion-type structures.
[0081] The present invention also provides a HEMT device formed according to the above method. The HEMT device includes a base layer, a channel layer located on the upper surface of the base layer; a barrier layer located on the upper surface of the channel layer; source-drain metals located on a predetermined area of the barrier layer; and a gate structure located on the gate region of the barrier layer; wherein, the surface of the predetermined area of the barrier layer is set to be n-type doped.
[0082] Preferably, as Figure 2h shown, it is a HEMT device formed according to the method of the first embodiment. The device includes a base layer, a channel layer 103 located on the upper surface of the base layer; a barrier layer located on the upper surface of the channel layer; source-drain metals 111 located on a predetermined area of the barrier layer; and a gate structure located on the gate region of the barrier layer; wherein, the surface of the predetermined area of the barrier layer is set to be n-type doped. The base layer includes a substrate 101 and a buffer layer 102. The buffer layer 102 is disposed between the substrate 101 and the channel layer 103 to reduce the problem of lattice mismatch between the substrate 101 and the channel layer 103.
[0083] Furthermore, the barrier layer includes a first barrier layer 104 and a second barrier layer 107. Among them, the first barrier layer 104 is located above the channel layer 103 and includes a first opening exposing a part of the upper surface of the channel layer 103. The second barrier layer 107 is located in the first opening, and the second barrier layer is located in the gate region of the HEMT device. The thickness of the second barrier layer 107 is less than the thickness of the first barrier layer 104.
[0084] Optionally, as Figure 3b shown, the barrier layer only includes a first barrier layer 104. The first barrier layer 104 completely covers the upper surface of the channel layer 103, and the gate structure is located on the first barrier layer 104.
[0085] Furthermore, it also includes a capping layer 105 located on the first barrier layer 104 to prevent the oxidation of the first barrier layer. Among them, the capping layer includes a second opening having the same width as the first opening and penetrating through the first opening.
[0086] Further, it further includes a first dielectric layer 106 located on the capping layer 105 to protect the capping layer 105. Wherein, the first dielectric layer includes a third opening having the same width as the second opening and penetrating through the second opening to accommodate the second barrier layer and the gate structure.
[0087] Further, the gate structure includes a p-type gallium nitride 108 located on the second barrier layer 107, and a gate metal 109 located on the p-type gallium nitride.
[0088] Optionally, as Figure 4e shown, the gate structure includes a gate dielectric layer 308 located on the second barrier layer 307, and a gate metal 114 located on the gate dielectric layer 308.
[0089] Further, it further includes an interlayer dielectric layer 110 covering the first dielectric layer 106 and the gate metal 109. Wherein, the source-drain metal 111 extends from the upper surface of the interlayer dielectric layer to the upper surface of the first barrier layer 104.
[0090] Further, it further includes a passivation layer 112 located on the interlayer dielectric layer 110 and an interconnect metal 113 extending from the upper surface of the passivation layer to the upper surfaces of the gate metal 109 / gate metal 114 and the source-drain metal 111.
[0091] The above embodiments merely illustrate the principles and effects of the present invention and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A manufacturing method of a HEMT device, characterized in that, Comprising: Forming a stack including at least a base layer and a channel layer; Forming a barrier layer structure stepwise or in one step on the upper surface of the stack, wherein the barrier layer structure includes a first predetermined region and a second predetermined region arranged at intervals; Forming an n-type doped ion layer by implanting ions in the first predetermined region of the barrier layer structure; Forming a gate structure on the second predetermined region of the barrier layer structure, and Forming source / drain metals on the first predetermined region of the barrier layer structure, Wherein, the ion layer is activated by the growth temperature when forming the III-V compound in the second predetermined region of the gate structure and / or the barrier layer structure to reduce the ohmic contact resistance of the source / drain metals.
2. The method according to claim 1, wherein The method of forming the barrier layer structure in one step includes: forming a first barrier layer covering the upper surface of the stack on the stack to form the barrier layer structure, wherein the ion layer is activated by the growth temperature when forming the III-V compound in the gate structure.
3. The method according to claim 1, wherein When the barrier layer structure is formed stepwise, the barrier layer structure includes at least a first barrier layer located in the first predetermined region and at least a second barrier layer located in the second predetermined region, wherein the thickness of the second barrier layer is less than that of the first barrier layer.
4. The method according to claim 2, wherein The step of forming the gate structure includes: Growing p-type gallium nitride on the second predetermined region of the first barrier layer, and Forming a gate metal on the p-type gallium nitride.
5. The method according to claim 3, characterized in that The step of forming the barrier layer structure includes: Forming the first barrier layer covering the upper surface of the stack; After forming the n-type doped ion layer in the first predetermined region of the first barrier layer, etching part of the first barrier layer to expose the upper surface of part of the channel layer, and Regrowing the second barrier layer on the exposed channel layer, wherein the second barrier layer includes a III-V compound.
6. The method according to claim 3, wherein The step of forming the gate structure includes: growing p-type gallium nitride on the second barrier layer and forming a gate metal on the p-type gallium nitride, wherein the ion layer is activated by the growth temperature when forming the III-V compound in the gate structure and the second barrier layer.
7. The method according to claim 3, characterized in that, The step of forming the gate structure includes: forming a gate dielectric layer on the second barrier layer and forming a gate metal on the gate dielectric layer, wherein the ion layer is activated by the growth temperature when forming the III-V compound in the second barrier layer.
8. The method according to claim 1, wherein The ions include silicon ions or oxygen ions or germanium ions or nitrogen ions.
9. The method according to claim 2 or 5, characterized in that, It further includes forming a capping layer covering the first barrier layer.
10. The method according to claim 9, wherein The method of forming the n-type doped ion layer includes: Forming a patterned photoresist layer on the capping layer; Using the photoresist layer as a mask to etch part of the capping layer to expose the first barrier layer; and Using the photoresist layer and the capping layer as a mask to perform ion implantation to form the ion layer.
11. The method according to claim 9, wherein After forming the n-type doped ion layer, it further includes forming a first dielectric layer on the capping layer.
12. The method according to claim 1, wherein The method of forming source / drain metals on the first predetermined region includes: Form an interlayer dielectric layer covering the gate structure and the barrier layer structure; Etch the interlayer dielectric layer to form an opening exposing a first predetermined area of the barrier layer structure; and Deposit metal in the opening to form the source / drain metal.
13. The method according to claim 12, wherein Further includes: Form a first passivation layer on the upper surfaces of the interlayer dielectric layer and the source / drain metal; Etch part of the first passivation layer to form a first via exposing the source / drain metal; Etch part of the first passivation layer and part of the interlayer dielectric layer to form a second via exposing the gate structure; And Deposit metal in the first via and the second via to form a first interconnect metal.
14. A HEMT device, characterized in that, Includes: A base layer, A channel layer located on the upper surface of the base layer; A barrier layer located on the upper surface of the channel layer; Source / drain metal located on a first predetermined area of the barrier layer, and A gate structure located on a second predetermined area of the barrier layer; Wherein, the surface of the first predetermined area of the barrier layer is set to be n-type doped.
15. The HEMT device according to claim 14, wherein The barrier layer includes at least a first barrier layer located in the first predetermined area and at least a second barrier layer located in the second predetermined area, wherein the thickness of the second barrier layer is less than the thickness of the first barrier layer.
16. A manufacturing method of a HEMT device including a depletion-type structure and an enhancement-type structure, characterized in that, Includes: Form a stack including a base layer, a channel layer and a first barrier layer, the stack including a first structure and a second structure; Inject ions into a first predetermined area of the first barrier layer in the first structure and a second predetermined area of the first barrier layer in the second structure to form an n-type doped ion layer; Etch the first barrier layer in a first gate region of the first structure to expose the channel layer, the first gate region being spaced from the first predetermined area; Regrow a second barrier layer on the exposed channel layer, the second barrier layer including a material layer of a III-V compound; Form a first gate structure on the second barrier layer; Form source / drain metal on the first predetermined area and the second predetermined area, and Form a second gate structure in a second gate region of the second structure, Wherein, the ion layer is activated by the growth temperature during the process of forming the second barrier layer to reduce the ohmic contact resistance of the source / drain.
17. The method according to claim 16, characterized in that The step of forming the first gate structure includes: growing p-type gallium nitride on the second barrier layer, and forming a first gate metal located on the p-type gallium nitride.
18. The method according to claim 16, wherein The thickness of the second barrier layer is less than the thickness of the first barrier layer.
19. The method according to claim 16, wherein The method of forming the second gate structure includes: Form a gate dielectric layer on a second gate region of the first barrier layer, and Form a second gate metal located on the gate dielectric layer.