Manufacturing method of Si-based depletion mode HEMT epitaxial wafer
By employing precise etching and controlled layer formation in separate chambers, the method addresses contamination issues in GaN-based HEMT wafers on silicon substrates, improving crystal quality and device performance.
Patent Information
- Application Number
- CN202510515902.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-23
- Publication Date
- 2025-07-15
AI Technical Summary
During the production process of GaN-based HEMT epitaxial sheets, residues on the silicon substrate affect the growth quality of the nucleation layer and buffer layer, resulting in a decline in device performance, and the residue of doped elements is not good for the channel layer and barrier layer, reducing device performance.
The SiMOS device area and GaN HEMT device area are formed on the silicon-based substrate by etching technology, and the nucleation layer, buffer layer and residual film layer are gradually formed in the separated reaction chamber. Different etching and deposition techniques are used to control the mass and structure of each layer to avoid the influence of residues.
It improves the crystal quality of the HEMT epitaxial layer, reduces the current collapse effect and leakage current, improves the performance of the channel layer and barrier layer, and is suitable for high-performance GaN HEMT switching circuits.
Abstract
Description
Technical Field
[0001] The present invention relates to a method for fabricating a Si-based depletion-mode HEMT epitaxial wafer. Background Art
[0002] With the advent of the 5G era, terminal products have higher requirements for the radio frequency systems of devices: high integration, miniaturization, high performance, etc. Si CMOS switch control circuits have advantages such as low power consumption, wide voltage range, and strong anti-interference ability, and have been widely used in manufacturing due to high integration and low cost. The gallium nitride-based high electron mobility transistor GaN HEMT has advantages such as high output power, high efficiency, high switching frequency, and high breakdown voltage. Therefore, the GaN HEMT switch circuit has advantages such as fast switching speed, high operating voltage, and low drive loss, and has become the core switch circuit in the current wireless communication field and power electronics application field.
[0003] Although using a silicon substrate can have advantages such as good thermal conductivity, low price, and suitability for large-size production, the silicon substrate still has a series of problems. Currently, during the production process of GaN-based HEMT epitaxial wafers, the nucleation layer (usually AlN), buffer layer (doped GaN), channel layer (GaN), and barrier layer (AlGaN) are successively grown in the same reaction chamber. However, a small amount of Ga or GaN will remain in the reaction chamber that has grown GaN material. Since the existing GaN-based HEMT epitaxial wafers use a silicon substrate instead of a sapphire substrate, the remaining Ga or GaN will volatilize and remelt onto the surface of the silicon substrate during the formation of the nucleation layer in subsequent batches and react with the silicon substrate. This not only affects the growth of the nucleation layer and buffer layer, but also causes a decrease in the crystal quality of the channel layer and barrier layer, thereby affecting the yield of GaN-based HEMT devices; in addition, since the buffer layer needs to be doped to form an insulating layer, after doping is completed, a small amount of doping elements such as carbon or iron will remain in the reaction chamber. The remaining doping elements are extremely unfavorable for the growth of the channel layer and barrier layer, and will seriously reduce the performance of GaN-based HEMT devices. Summary of the Invention
[0004] The purpose of the present invention is to provide a method for fabricating a Si-based depletion-mode HEMT epitaxial wafer to solve the problems raised in the above background art.
[0005] To solve the above technical problems, the technical solution provided by the present invention is: A method for fabricating a Si-based depletion-mode HEMT epitaxial wafer, specifically including the following steps:
[0006] Provide a silicon-based GaN wafer, the silicon-based GaN wafer includes a silicon-based substrate and a GaN epitaxial layer disposed on the upper end surface of the silicon-based substrate, and the GaN epitaxial layer includes a first GaN epitaxial layer in a target area and a second GaN epitaxial layer in a non-target area;
[0007] The non-target region of the second GaN epitaxial layer is removed by an etching process, so that a SiMOS device region is formed on the upper end surface of the silicon substrate, and the SiMOS device region is used to fabricate a SiMOS switch control circuit;
[0008] A GaN HEMT device region is formed on the first GaN epitaxial layer in the target region by an etching process;
[0009] A support substrate is provided, placed in the first reaction chamber, and a nucleation layer is formed in the first reaction chamber;
[0010] The support substrate with the nucleation layer formed thereon is transferred to the second reaction chamber, and a buffer layer containing Ga element is formed in the second reaction chamber, and the buffer layer is doped;
[0011] The support substrate with the nucleation layer and the buffer layer formed thereon is transferred to the remaining reaction chambers, and the remaining thin film layers are formed in the remaining reaction chambers;
[0012] A layer of photoresist is coated on the surface of the remaining thin film layer, the MESA photomask is covered on the photoresist for exposure, the shape of the photoresist changes after exposure, and the excess photoresist is removed through the development and photoresist removal processes; the same pattern as on the MESA photomask is formed on the photoresist; then an ICP etching machine is used to perform ICP etching on the epitaxial wafer covered with the photoresist, and the areas not protected by the photoresist are etched to a set depth, which is below 2DEG, to obtain a Si-based depletion-mode HEMT epitaxial wafer.
[0013] Preferably, the first GaN epitaxial layer in the target region and the second GaN epitaxial layer in the non-target region are adjacent to each other.
[0014] Preferably, the GaN HEMT device region is used to fabricate a GaN HEMT switch circuit.
[0015] The advantages of the present invention are as follows: It can effectively prevent the residues in the reaction chamber from volatilizing and remelting to affect the quality of other thin film layers, thereby improving the crystal quality of the HEMT epitaxial layer, further reducing the current collapse effect and leakage current effect existing in the HEMT device. It can also avoid the doping element from remelting into the channel layer and barrier layer during the doping of the buffer layer, reducing the conductivity of the channel layer and barrier layer, improving the performance of the channel layer and barrier layer, and having good popularization prospects. Specific embodiments
[0016] The following specific examples are used to illustrate the present invention, and are not intended to limit the present invention.
[0017] Example 1:
[0018] A method for fabricating a Si-based depletion-mode HEMT epitaxial wafer specifically includes the following steps:
[0019] Select a silicon-based GaN wafer. On the upper surface of the silicon-based substrate of this wafer, there are a first GaN epitaxial layer in the target area and a second GaN epitaxial layer in the non-target area that are adjacent to each other.
[0020] Remove the second GaN epitaxial layer in the non-target area by a high-precision etching process, and precisely form a SiMOS device area on the upper surface of the silicon-based substrate. This area is specifically used to fabricate a SiMOS switch control circuit. The process parameters are strictly controlled during the etching process to ensure the flatness and edge regularity of the area.
[0021] On the first GaN epitaxial layer in the target area, form a GaN HEMT device area by using an advanced etching process. This area will be used to construct a high-performance GaN HEMT switch circuit, and the etching depth and shape precisely meet the design requirements.
[0022] Prepare a high-quality support substrate, carefully place it in the first reaction chamber, and form a uniform and dense nucleation layer under specific temperature, pressure, and gas flow conditions, ensuring that the quality of the nucleation layer meets the requirements for subsequent growth.
[0023] Steadily transfer the support substrate with the nucleation layer to the second reaction chamber, form a buffer layer containing Ga elements in a precisely controlled environment, and dope the buffer layer with a suitable dopant and doping process to make the doping concentration uniform and reach the predetermined value.
[0024] Continue to transfer the support substrate with the nucleation layer and the buffer layer to the remaining reaction chambers, and form the remaining thin film layers under strictly controlled reaction conditions, ensuring that the thickness, composition, and crystal structure of the thin film layers all meet the design standards.
[0025] Uniformly coat a layer of photoresist on the surface of the remaining thin film layer, accurately cover a high-precision MESA photomask on the photoresist for exposure. After exposure, strictly remove the excess photoresist according to the standard developing and photoresist-removing processes, so that the same pattern as on the MESA photomask is perfectly formed on the photoresist. Finally, use a high-precision ICP etching machine to perform ICP etching on the epitaxial wafer covered with the photoresist, and precisely control the etching depth to be below 2DEG, thus successfully fabricating a high-quality Si-based depletion-mode HEMT epitaxial wafer.
[0026] Example 2:
[0027] A method for fabricating a Si-based depletion-mode HEMT epitaxial wafer specifically includes the following steps:
[0028] Provide a silicon-based GaN wafer. The first GaN epitaxial layer in the target area and the second GaN epitaxial layer in the non-target area on the upper surface of its silicon-based substrate are adjacent to each other, and the wafer has undergone strict surface pretreatment to improve the quality of the epitaxial layer.
[0029] Adopt a pulsed etching process to remove the second GaN epitaxial layer in the non-target area. This process can effectively reduce the damage to the silicon-based substrate, make the surface of the formed SiMOS device area smoother, and is conducive to subsequent circuit fabrication.
[0030] Use an ion beam etching process to form a GaN HEMT device area on the first GaN epitaxial layer in the target area, which can accurately control the etching shape and contour, laying a foundation for fabricating a high-performance GaN HEMT switching circuit.
[0031] Select a support substrate with high thermal conductivity, place it in the first reaction chamber, and form a nucleation layer in the chamber by optimizing the ratio of reaction gases. The grain size of the nucleation layer is uniform and the compactness is good.
[0032] Quickly transfer the support substrate with the nucleation layer to the second reaction chamber, and use metal organic chemical vapor deposition (MOCVD) technology to form a buffer layer containing Ga element in this chamber, and adopt a special doping source during the doping process to improve the doping efficiency and uniformity.
[0033] Transfer the support substrate with the formed specific layer structure to the remaining reaction chamber, and use atomic layer deposition (ALD) technology to form the remaining thin film layer in this chamber, which can accurately control the thickness and flatness of the thin film layer.
[0034] Apply photoresist on the surface of the remaining thin film layer, cover the MESA photomask with a special anti-reflection coating on the photoresist for exposure, and use advanced developing and photoresist removal processes to remove the excess photoresist after exposure, making the photoresist pattern clear and accurate. Then use a high-power ICP etching machine to perform ICP etching on the epitaxial wafer covered with photoresist, ensuring that the etching depth of the area not protected by the photoresist is below 2DEG, and obtain a Si-based depletion-mode HEMT epitaxial wafer with excellent performance.
[0035] Example 3:
[0036] A method for fabricating a Si-based depletion-mode HEMT epitaxial wafer specifically includes the following steps:
[0037] Prepare a silicon-based GaN wafer. The first GaN epitaxial layer in the target area and the second GaN epitaxial layer in the non-target area are adjacent on the upper end surface of the silicon-based substrate, and the wafer has been subjected to defect detection and repair processing.
[0038] Use a plasma etching process to remove the second GaN epitaxial layer in the non-target area, and monitor the parameters of the plasma in real time during the etching process to ensure that the SiMOS device area formed on the upper end surface of the silicon-based substrate has good electrical properties and meets the requirements for fabricating a SiMOS switching control circuit.
[0039] The GaN HEMT device region is formed on the first GaN epitaxial layer in the target area by using an electron beam lithography process. Through the precise control of the electron beam, the nanometer-level processing accuracy of the device region is achieved, which helps to improve the performance of the GaN HEMT switching circuit.
[0040] A support substrate with extremely low surface roughness is provided and placed in the first reaction chamber. A nucleation layer is formed in an ultra-high vacuum environment, and the purity and crystallinity of the nucleation layer are extremely high.
[0041] The support substrate with the nucleation layer formed is slowly transferred to the second reaction chamber. A buffer layer containing Ga element is formed in this chamber, and the buffer layer is doped by using a laser-assisted doping process, which can achieve a non-uniform doping distribution and meet the special device design requirements.
[0042] The support substrate with the nucleation layer and the buffer layer is transferred to the remaining reaction chamber. The remaining thin film layer is formed in this chamber by using magnetron sputtering technology, and the composition and structure of the thin film layer can be precisely controlled.
[0043] A layer of photoresist is coated on the surface of the remaining thin film layer. The MESA photomask with a micro-nano structure is covered on the photoresist for exposure. After exposure, the excess photoresist is removed through wet development and photoresist stripping processes, so that a unique pattern is formed on the photoresist. Then, an inductively coupled plasma (ICP) etcher with ultra-high resolution is used to perform ICP etching on the epitaxial wafer covered with the photoresist. The area not protected by the photoresist is etched to a depth below 2DEG, and a Si-based depletion-mode HEMT epitaxial wafer with a special structure is fabricated.
[0044] Example 4:
[0045] A method for fabricating a Si-based depletion-mode HEMT epitaxial wafer specifically includes the following steps:
[0046] A silicon-based GaN wafer is taken. The first GaN epitaxial layer in the target area on the upper end face of the silicon-based substrate and the second GaN epitaxial layer in the non-target area are arranged adjacent to each other, and the wafer is subjected to a special cleaning process to remove surface impurities.
[0047] The second GaN epitaxial layer in the non-target area is removed by using a reactive ion etching process. During the etching process, the flow rate and pressure of the reaction gas are adjusted to make the edge of the SiMOS device area formed on the upper end face of the silicon-based substrate steep and without residue, which is beneficial to the subsequent integrated circuit fabrication.
[0048] The GaN HEMT device region is formed on the first GaN epitaxial layer in the target area by using a deep reactive ion etching process, which can achieve an etching structure with a high aspect ratio and provide a good structural basis for fabricating a high-performance GaN HEMT switching circuit.
[0049] Place the support substrate in the first reaction chamber, introduce a special precursor gas into the chamber, and form a nucleation layer under a specific temperature gradient. The growth rate of the nucleation layer is uniform and controllable.
[0050] Transfer the support substrate with the nucleation layer formed thereon to the second reaction chamber, and form a buffer layer containing Ga element in this chamber by using chemical beam epitaxy (CBE) technology, and combine ion implantation technology during the doping process to achieve precise control of depth and concentration.
[0051] Transfer the support substrate with the specific layer structure formed thereon to the remaining reaction chamber, and form the remaining thin film layer in this chamber by using pulsed laser deposition (PLD) technology, and a thin film layer with a special crystal orientation can be obtained.
[0052] Apply photoresist on the surface of the remaining thin film layer, cover the MESA photomask with a multi-layer structure on the photoresist for exposure, and use dry development and photoresist removal processes to remove the excess photoresist after exposure, so as to form a complex pattern on the photoresist. Then use a high-stability ICP etcher to perform ICP etching on the epitaxial wafer covered with photoresist, and etch the area not protected by the photoresist to a depth below 2DEG to obtain a Si-based depletion-mode HEMT epitaxial wafer with a complex structure and excellent performance.
[0053] Example 5:
[0054] A method for fabricating a Si-based depletion-mode HEMT epitaxial wafer specifically includes the following steps:
[0055] Provide a silicon-based GaN wafer, in which a first GaN epitaxial layer in a target area and a second GaN epitaxial layer in a non-target area exist adjacent to each other on the upper end surface of the silicon-based substrate, and stress regulation treatment is performed on the wafer.
[0056] Use a laser-induced etching process to remove the second GaN epitaxial layer in the non-target area. This process can reduce the thermal effect during etching, make the lattice integrity of the SiMOS device area formed on the upper end surface of the silicon-based substrate better, and is beneficial to improving the reliability of the circuit.
[0057] Adopt a focused ion beam etching process to form a GaN HEMT device area on the first GaN epitaxial layer in the target area, which can achieve fixed-point and quantitative microfabrication and is of great significance for fabricating a high-precision GaN HEMT switching circuit.
[0058] Select a support substrate with high flatness, place it in the first reaction chamber, and form a nucleation layer under the assistance of a magnetic field. The magnetic and electrical properties of the nucleation layer are optimized.
[0059] Transfer the support substrate with the nucleation layer formed thereon to the second reaction chamber, where a buffer layer containing Ga element is formed by molecular beam epitaxy (MBE) technology, and in-situ monitoring technology is adopted during the doping process to adjust the doping parameters in real time to ensure the accuracy of doping.
[0060] Transfer the support substrate with the nucleation layer and the buffer layer to the remaining reaction chamber, where the remaining thin film layer is formed by sol-gel method, which can realize the low-temperature preparation of the thin film layer and reduce the thermal stress.
[0061] Coat a layer of photoresist on the surface of the remaining thin film layer, cover the MESA photomask with a self-aligned structure on the photoresist for exposure, and after exposure, remove the excess photoresist through a mixed development and stripping process to form a self-aligned pattern on the photoresist. Then use a high-precision ICP etcher to perform ICP etching on the epitaxial wafer covered with photoresist, and etch the area not protected by the photoresist to a depth below 2DEG to obtain a Si-based depletion-mode HEMT epitaxial wafer with self-aligned characteristics.
[0062] Example 6:
[0063] A method for fabricating a Si-based depletion-mode HEMT epitaxial wafer specifically includes the following steps:
[0064] Prepare a silicon-based GaN wafer, where the first GaN epitaxial layer in the target area and the second GaN epitaxial layer in the non-target area are adjacent to each other on the upper end face of the silicon-based substrate, and the crystal orientation of the wafer is precisely adjusted.
[0065] Adopt a wet etching process to remove the second GaN epitaxial layer in the non-target area, and add a special complexing agent to the etching solution, which can effectively prevent the side etching phenomenon during the etching process, make the size accuracy of the SiMOS device area formed on the upper end face of the silicon-based substrate higher, and is suitable for fabricating a miniaturized SiMOS switch control circuit.
[0066] Use gray-scale lithography and etching processes to form a GaN HEMT device area with a gradient structure on the first GaN epitaxial layer in the target area, which can realize the gradient change of device performance and meet the requirements of special application scenarios.
[0067] Place the support substrate in the first reaction chamber, and form a nucleation layer in the chamber by alternating pulse deposition technology. The structure of the nucleation layer has a periodic change, which can enhance the adhesion of the subsequent layers.
[0068] Transfer the support substrate with the nucleation layer formed thereon to the second reaction chamber, where a buffer layer containing Ga element is formed by hydride vapor phase epitaxy (HVPE) technology, and a double-layer doping structure is adopted during the doping process to improve the electrical properties of the buffer layer.
[0069] Transfer the support substrate with a specific layer structure formed to the remaining reaction chamber, and form the remaining thin film layer in this chamber by electrochemcial deposition method, so that the growth rate and thickness uniformity of the thin film layer can be precisely controlled.
[0070] Apply photoresist on the surface of the remaining thin film layer, cover the MESA photomask with a three-dimensional structure on the photoresist for exposure. After exposure, use the three-dimensional photoresist development and stripping process to remove the excess photoresist, so that a three-dimensional pattern is formed on the photoresist. Then use a multi-beam ICP etcher to perform ICP etching on the epitaxial wafer covered with photoresist, and etch the area not protected by the photoresist to a depth below 2DEG to obtain a Si-based depletion-mode HEMT epitaxial wafer with three-dimensional structural characteristics.
[0071] Example 7:
[0072] A method for fabricating a Si-based depletion-mode HEMT epitaxial wafer specifically includes the following steps:
[0073] Fetch a silicon-based GaN wafer, where the first GaN epitaxial layer in the target area and the second GaN epitaxial layer in the non-target area are adjacent to each other on the upper end face of the silicon-based substrate, and the wafer has been subjected to an antioxidant treatment.
[0074] Use the microwave plasma etching process to remove the second GaN epitaxial layer in the non-target area. During the etching process, utilize the characteristics of microwaves to improve the activity of the plasma, so that the surface energy of the SiMOS device area formed on the upper end face of the silicon-based substrate is lower, which is beneficial to the subsequent deposition of materials and circuit fabrication.
[0075] Adopt nanoimprint lithography and etching processes to form a GaN HEMT device area with nanoscale feature sizes on the first GaN epitaxial layer in the target area, which can achieve large-scale and low-cost nano-device manufacturing and improve the integration of GaN HEMT switching circuits.
[0076] Provide a support substrate with special electrical properties, place it in the first reaction chamber, and form a nucleation layer under light assistance, and the optoelectronic properties of the nucleation layer are improved.
[0077] Transfer the support substrate with the nucleation layer formed to the second reaction chamber, and form a buffer layer containing Ga element in this chamber by metalorganic vapor phase epitaxy (OMVPE) technology, and adopt quantum dot doping technology during the doping process to bring special quantum effects to the device.
[0078] Transfer the support substrate with the nucleation layer and the buffer layer to the remaining reaction chamber, and form the remaining thin film layer in this chamber by hot filament chemical vapor deposition (HFCVD) technology, which can achieve the growth of high-quality thin film layers at a lower temperature.
[0079] Apply a layer of photoresist on the surface of the remaining thin film layer, cover the MESA photomask with a biocompatible structure on the photoresist for exposure, and remove the excess photoresist through a bio-friendly development and photoresist removal process after exposure, so as to form a special structure pattern on the photoresist. Then use a low-damage ICP etcher to perform ICP etching on the epitaxial wafer covered with photoresist, and etch the area not protected by the photoresist to a depth below 2DEG to obtain a Si-based depletion-mode HEMT epitaxial wafer with special functions.
[0080] As described above, the above is only the preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, according to the technical solution and inventive concept of the present invention, makes equivalent substitutions or changes, and should be covered within the protection scope of the present invention.
Claims
1. A method for fabricating a Si-based depletion-mode HEMT epitaxial wafer, characterized in that, Specifically, it includes the following steps: Provide a silicon-based GaN wafer, which includes a silicon-based substrate and a GaN epitaxial layer disposed on the upper end surface of the silicon-based substrate. The GaN epitaxial layer includes a first GaN epitaxial layer in the target area and a second GaN epitaxial layer in the non-target area; Use an etching process to remove the second GaN epitaxial layer in the non-target area, so as to form a SiMOS device area on the upper end surface of the silicon-based substrate. The SiMOS device area is used to fabricate a SiMOS switch control circuit; Use an etching process to form a GaN HEMT device area on the first GaN epitaxial layer in the target area; Provide a support substrate, place the support substrate in the first reaction chamber, and form a nucleation layer in the first reaction chamber; Transfer the support substrate with the nucleation layer formed thereon to the second reaction chamber, and form a buffer layer containing Ga elements in the second reaction chamber, and dope the buffer layer; Transfer the support substrate with the nucleation layer and the buffer layer formed thereon to the remaining reaction chamber, and form the remaining thin film layer in the remaining reaction chamber; Coat a layer of photoresist on the surface of the remaining thin film layer, cover the MESA photomask on the photoresist for exposure. After the photoresist is exposed, its properties change, and the excess photoresist is removed through the development and photoresist removal processes; The same pattern as on the MESA photomask is formed on the photoresist; Then use an ICP etcher to perform ICP etching on the epitaxial wafer covered with the photoresist. The area not protected by the photoresist will be etched to a set depth, which is below 2DEG, to obtain a Si-based depletion-mode HEMT epitaxial wafer.
2. The manufacturing method of the Si-based depletion-mode HEMT epitaxial wafer according to claim 1, characterized in that: The first GaN epitaxial layer in the target area and the second GaN epitaxial layer in the non-target area are adjacent to each other.
3. The manufacturing method of the Si-based depletion-mode HEMT epitaxial wafer according to claim 2, characterized in that: The GaN HEMT device area is used to fabricate a GaN HEMT switch circuit.