Semiconductor device and method of manufacturing the same

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. According to various embodiments of the present disclosure, a semiconductor device is provided. In some embodiments, the semiconductor device includes a substrate made of a semiconductor material, a gate structure disposed on the substrate, a passivation layer disposed on the substrate and a portion of the gate structure, a sealing oxide layer disposed on the passivation layer, a first field plate disposed on a portion of the sealing oxide layer, and a second field plate disposed on a portion of the sealing oxide layer. A dielectric layer disposed on the first field plate and on the encapsulation oxide layer, a second field plate disposed on a portion of the layer, and a source contact metallization and a drain contact metallization. The sealing oxide layer is thicker than the passivation layer.

Description

Technical Field

[0001] Example embodiments of the present disclosure generally relate to the structure of semiconductor devices, and more particularly to the structure of gallium nitride (GaN) high electron mobility transistor (HEMT) devices. Background Art

[0002] Gallium nitride (GaN) high electron mobility transistors (HEMTs) are increasingly used in power electronic devices, especially for some high-power applications. The applicant has identified many technical challenges and difficulties associated with manufacturing semiconductor devices such as GaN HEMTs. Through applied effort, ingenuity, and innovation, the applicant has solved the problems associated with manufacturing semiconductor devices such as GaN HEMTs by developing the solutions implemented in the present disclosure, which are described in detail below. Summary of the Invention

[0003] Various embodiments described herein relate to semiconductor devices and methods of manufacturing semiconductor devices.

[0004] According to various embodiments of the present disclosure, a semiconductor device is provided. In some embodiments, the semiconductor device includes a substrate made of a semiconductor material, a gate structure placed on the substrate, a passivation layer placed on the substrate and on a part of the gate structure, a sealing oxide layer placed on the passivation layer, a first field plate placed on a part of the sealing oxide layer, a dielectric layer placed on the first field plate and on the sealing oxide layer, a second field plate placed on a part of the layer, and source contact metallization and drain contact metallization. The sealing oxide layer is thicker than the passivation layer.

[0005] In some embodiments, the dielectric layer includes a nitride layer or an oxide layer.

[0006] In some embodiments, the source contact metallization and the drain contact metallization are formed on corresponding portions in corresponding voids in the substrate in the passivation layer, the sealing oxide layer, and the dielectric layer.

[0007] In some embodiments, the dielectric layer includes a first dielectric sub-layer and a second dielectric sub-layer.

[0008] In some embodiments, the first dielectric sub-layer partially overlaps with the source contact metallization and the drain contact metallization.

[0009] In some embodiments, the second dielectric sub-layer overlaps with the source contact metallization and the drain contact metallization.

[0010] In some embodiments, the dielectric layer is a first dielectric layer, and the semiconductor device further includes a second dielectric layer placed on the second field plate and on a part of the first dielectric layer.

[0011] In some embodiments, the semiconductor device further includes a gate contact metallization that is placed in a void in the second dielectric layer, the first dielectric layer, the seal oxide layer, and the passivation layer over the gate structure.

[0012] In some embodiments, the gate structure is made of gallium nitride (GaN), and the semiconductor device includes a GaN high electron mobility transistor.

[0013] In some embodiments, a second field plate is in partial contact with the first field plate through an additional void in the dielectric layer.

[0014] According to various embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided. In some embodiments, the method includes forming a gate structure on a substrate made of a semiconductor material; forming a passivation layer on the substrate and on a portion of the gate structure; forming a seal oxide layer on the passivation layer, wherein the seal oxide layer is thicker than the passivation layer; forming a first field plate on a portion of the seal oxide layer; forming a dielectric layer on the first field plate and on the seal oxide layer; forming a second field plate on a portion of the dielectric layer; and forming source contact metallization and drain contact metallization.

[0015] The foregoing summary is provided only to summarize some example embodiments to provide a basic understanding of some aspects of the present disclosure. Accordingly, it will be recognized that the above embodiments are merely examples and should not be construed as narrowing the scope or spirit of the present disclosure in any way. It will also be recognized that the scope of the present disclosure covers many potential embodiments in addition to the embodiments summarized herein, some of which will be further described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The description of the illustrative embodiments may be read in conjunction with the accompanying drawings. It will be appreciated that for simplicity and clarity of illustration, the elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements unless otherwise described. Embodiments in accordance with the teachings of the present disclosure are shown and described with reference to the figures herein:

[0017] Figures 1 - 13 is a schematic cross-sectional view illustrating the steps of an example method of manufacturing a semiconductor device in accordance with some embodiments of the present disclosure;

[0018] Figure 14 is a schematic cross-sectional view of an example semiconductor device in accordance with some embodiments of the present disclosure; and

[0019] Figure 15 is a schematic cross-sectional view illustrating the steps of an example method of manufacturing a semiconductor device in accordance with some alternative embodiments of the present disclosure. Detailed Implementation Modes

[0020] Some embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all, embodiments of the present disclosure are shown. In fact, these disclosures may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like reference numerals refer to like elements throughout.

[0021] As used herein, terms such as "front", "rear", "top", etc. are used for illustrative purposes in the examples provided below to describe the relative positions of certain components or portions of components. In addition, according to the present disclosure, as will be apparent to those of ordinary skill in the art, the terms "substantially" and "approximately" indicate that the referenced element or associated description is accurate within the applicable engineering tolerances.

[0022] As used herein, the term "comprising" means including but not limited to and should be interpreted in the manner commonly used in the patent context. The use of broader terms such as including, containing, and having should be understood to provide support for more narrow terms such as consisting of, consisting essentially of, and consisting substantially of.

[0023] Phrases such as "in one embodiment", "according to one embodiment", etc. generally mean that the particular feature, structure, or characteristic following such phrase may be included in at least one embodiment of the present disclosure and may be included in more than one embodiment of the present disclosure (importantly, such phrases do not necessarily refer to the same embodiment).

[0024] The word "example" or "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0025] If the specification states that a component or feature "may", "is capable of", "can", "should", "will", "preferably", "possibly", "ordinarily", "optionally", "for example", "frequently", or "may" (or other such language) be included or have a certain characteristic, then the particular component or feature is not required to be included or have that characteristic. Such a component or feature may optionally be included in some embodiments or it may be excluded.

[0026] A GaN HEMT typically includes one or more field plates. A field plate is a metal electrode biased to a certain voltage (which can be made of titanium nitride (TiN), aluminum copper (AlCu), or any other suitable material) for modifying and controlling the voltage and electric field peaks along the conductive channel of the transistor. The voltage between the conductive channel and the field plate can be maintained by a capacitor-like structure having a dielectric medium (usually silicon oxide or silicon nitride).

[0027] Some problems may occur during the formation (definition) of the field plate, which may cause some residues (which can be referred to as stringers) to remain in some unwanted areas, such as at the vertical or recessed walls of the ohmic (drain and source) metallization. These residues may cause unwanted electrical effects and / or loss of the electrical performance of the HEMT. In other cases, when etching the silicon nitride (SiN) passivation layer around the gate to create an opening that enables the formation of the field plate, the mask for creating the SiN opening may not be accurately positioned, thereby removing too much SiN and / or too much silicon oxide (SiO) (in the layer below SiN) and forming holes. Unwanted materials (such as TiN) may fill the holes, thereby causing unwanted electrical effects and / or loss of the electrical performance of the HEMT.

[0028] Various embodiments of the present disclosure overcome the above technical challenges and difficulties and provide various technical improvements and advantages based on, for example, but not limited to, the semiconductor devices and methods of manufacturing semiconductor devices described herein.

[0029] Various embodiments of the present disclosure provide semiconductor devices and methods of manufacturing semiconductor devices, wherein a passivation layer is applied before creating the first of two separate field plates, and then a gate passivation layer is applied. Various embodiments of the present disclosure provide semiconductor devices and methods of manufacturing semiconductor devices, wherein creating the first of two separate field plates is performed separately from the gate metallization. Various embodiments of the present disclosure provide semiconductor devices and methods of manufacturing semiconductor devices, wherein the passivation nitride layer is not etched for field plate creation. Various embodiments of the present disclosure provide semiconductor devices and methods of manufacturing semiconductor devices, wherein a three-step gate contact etching is performed.

[0030] Figures 1 - 13 is a schematic cross-sectional view illustrating the steps of an exemplary method of manufacturing a semiconductor device such as a GaN HEMT according to some embodiments of the present disclosure. Now refer to Figure 1, a gate structure 104 is formed on a substrate 102. The substrate 102 can include, for example, silicon carbide (SiC) or silicon (Si), which are commonly used substrates for GaN HEMTs. Alternatively, the substrate can include a stack of aluminum gallium nitride (AlGaN) and GaN. The gate structure 104 can include, for example, p-type gallium nitride (p-GaN) doped with magnesium (Mg). A passivation layer 106 is formed on top of the substrate 102 and the gate structure 104. The passivation layer 106 can include materials such as, for example, silicon dioxide (SiO2), aluminum oxide (e.g., alumina, Al2O3), aluminum nitride (AlN), or gallium oxide (Ga2O3) (or other similar non-stoichiometric oxides). A sealing dielectric layer (which can also be referred to as a gate-sealing dielectric layer) is deposited on top of the passivation layer 106. Generally, the sealing dielectric layer is made of an oxide material (such as the following referred to as a sealing oxide layer 108). Alternatively, the sealing dielectric layer can be made of a nitride material.

[0031] The sealing oxide layer 108 can include, for example, SiO2. In various embodiments, having the passivation layer in contact with the gate structure and the gate-sealing oxide layer located on top of the passivation layer allows the gate-sealing oxide layer to be thinner than other methods that have been used. In various embodiments, having a thinner gate-sealing oxide layer can provide better reduction of the peak of the electric field and control of hot carriers compared to other methods that have been used, thereby having a beneficial effect on the electrical properties of the device. In various embodiments, the sealing oxide layer 108 is thicker than the passivation layer 106. For example, in some embodiments, the sealing oxide layer is about eight to twelve times thicker than the passivation layer (the passivation layer is typically about 5 - 10 nanometers thick, while the sealing oxide layer is typically about 30 - 120 nm thick, and preferably about 40 - 100 nm thick). For example, in some embodiments, the sealing oxide layer is about ten times thicker than the passivation layer. In various embodiments, since the sealing oxide layer serves as the dielectric of a field plate "capacitor-like" structure, the sealing oxide layer should match a target value. In various embodiments, too low a thickness of the sealing oxide layer results in poor control of the residual sealing layer after the first field plate patterning, while too high a thickness of the sealing oxide layer results in too low a capacitance value and channel coupling with the first field plate.

[0032] Now referring to Figure 2 , a metal layer 110 is deposited on top of the sealing oxide layer 108. The metal layer 110 can include, for example, TiN. In various embodiments, the thickness of the sealing oxide layer can be better controlled because the only source of thickness variation of the sealing oxide layer is the sealing oxide deposition itself.

[0033] Now referring to Figure 3 , the metal layer is patterned and etched to create a first field plate 112 by removing all of the metal layer 110 except for the portion that forms the first field plate 112. Now referring toFigure 4 The sealed oxide layer 108 is patterned and etched to remove unwanted material on opposite sides of the gate structure 104. In various embodiments, the sealed oxide layer 108 is protected by the first field plate 112, and thus better overall electrical behavior of the HEMT can be achieved.

[0034] Now referring Figure 5 to, a dielectric layer including a first dielectric sublayer such as a contact nitride layer 114 (which may be an oxide layer in various alternative embodiments) is deposited over the first field plate 112, a portion of the sealed oxide layer 108, and a portion of the passivation layer 106. The contact nitride layer 114 may include, for example, silicon nitride (SiN or Si3N4) or other dielectrics such as silicon dioxide (SiO2). This layer is referred to as a contact nitride layer because this layer is etched to form source and drain contacts. Now referring Figure 6 to, the contact nitride layer 114 is patterned and etched to remove corresponding portions of the contact nitride layer 114 and the passivation layer 106 to create a source void 116 to allow deposition of a source contact on the substrate 102 and create a drain void 118 to allow deposition of a drain contact on the substrate 102. (Alternatively, the drain contact may be deposited in the void 116 and the source contact may be deposited in the void 118.) In various alternative embodiments, there may be a second passivation layer (not shown) (which may be made of the same or different material as the passivation layer 106, for example). In various embodiments, the second passivation layer may be deposited after defining the gate-sealed oxide layer 108, and the second passivation layer will be conformal with the underlying structure. In various embodiments, the second passivation layer may be etched together with the dielectric layer 114 when defining the voids for contact metallization. In various embodiments, after defining the voids described above, the second passivation layer will remain below the dielectric layer 114.

[0035] Now referring Figure 7 to, a contact layer 120 and another metal layer 122 have been deposited. In various embodiments, the contact layer 120 and the metal layer 122 are a metal stack deposited in a single deposition step and may include, for example, titanium (Ti), titanium nitride (TiN), aluminum copper (AlCu), and / or other materials used in conventional aluminum interconnects. Now referring Figure 8 to, the contact layer 120 and the metal layer 122 have been patterned and etched to expose the areas around the gate structure 104 and form a source contact 124 and a drain contact 126. (Alternatively, the contact 124 may be the drain contact and the contact 126 may be the source contact.)

[0036] Now referring Figure 9, the dielectric layer further includes a second dielectric sub-layer deposited on the source / drain metallization layers 124 and 126 and on the first dielectric sub-layer, such as a sealing nitride layer 128. The sealing nitride layer 128 may include, for example, SiN. This layer protects the metal layer on top of the source contact 124 and the drain contact 126. In various embodiments, different from other methods that have been used, the sealing nitride layer is not directly etched to enable the formation of the field plate. Therefore, the necessity of accurately placing the mask and the implicit and related problems of controlling the lithography process to create the SiN opening are avoided. In an alternative embodiment (not shown), the dielectric layer consists of the first dielectric sub-layer (i.e., does not include the second dielectric sub-layer).

[0037] Now referring to Figure 10 , a metal layer 130 is deposited on top of the sealing nitride layer 128. The metal layer 130 may include, for example, TiN. In various embodiments, the problem of the above-mentioned residue remaining at the vertical or concave walls of the ohmic (drain and source) metallization can be reduced or avoided by applying a metal layer 130 with a small thickness (e.g., about 20 - 60 nanometers) and / or by applying a process that provides low step coverage, such as physical vapor deposition. Now referring to Figure 11 , the metal layer is patterned and etched to create the second field plate 132 by removing all of the metal layer 130 except for the portion that forms the second field plate 132. In various embodiments, the problem of the above-mentioned residue remaining at the vertical or concave walls of the ohmic (drain and source) metallization can be further reduced or avoided by using an isotropic etching process to remove the unwanted portions of the metal layer 130. In various embodiments, it may be possible to bias the two field plates at two different voltages. In various embodiments, the thickness of the first and second field plates ranges from 20 nm to 100 nm. In some cases, it is thinner than in the case of a single field plate. In the illustrated embodiment, the first and second field plates do not overlap. In various alternative embodiments, the first and second field plates may partially overlap. In various embodiments, additional portions of the metal material from which the first and second field plates are derived may be left. These additional portions can be used as passive components, for example, can be used as electrodes for a MIM (metal-insulator-metal) capacitor structure (e.g., the dielectric layer serves as the insulating layer between the two metal plates). In the case of the MIM capacitor, the additional portions overlap each other.

[0038] Now referring to Figure 12 , a gate contact dielectric layer (usually made of an oxide material, and thus hereinafter referred to as the gate contact dielectric oxide layer 134) is deposited on top of the second field plate 132 and a portion of the sealing nitride layer 128. The gate contact dielectric oxide layer 134 may include, for example, SiO. Now referring to Figure 13, a three-step etching process is performed to remove the gate contact dielectric oxide layer 134, the seal nitride layer 128, the seal oxide layer 108, and the passivation layer 106 over the gate structure 104, thereby creating a gate void 136. In various embodiments, the selectivity of etching oxide instead of SiN and etching SiN instead of oxide enables better control of the final etching step.

[0039] Subsequently, a gate contact is formed on top of the gate structure 104 to form Figure 14 the completed device as shown in Figure 14 FIG. 7 illustrates a GaN semiconductor device 100 according to an embodiment of the present disclosure. In Figure 14 device 100 of

[0040] Figure 15 FIG. 13 is a schematic cross-sectional view of steps of an example method of fabricating a semiconductor device according to some alternative embodiments of the present disclosure. Similar to the steps described above with respect to Figures 1 - 9 FIG. Figure 15 FIG. 13 shows the following formed on a substrate 202: a gate structure 204, a passivation layer 206, a seal oxide layer 208, a first field plate 212, a contact nitride layer 214, a source contact 224, a drain contact 226, and a seal nitride layer 228. After depositing the seal nitride layer 228, the seal nitride layer 228 is patterned and etched to remove portions of the seal nitride layer 228 to create a second field plate void 233. A metal layer (not shown) is deposited and then patterned and etched to create a second field plate 232 by removing all of the metal layer except for the portion that forms the second field plate 232. In Figure 15 an alternative embodiment of Figure 15 FIG. 13, the second field plate 232 has an (exemplary center) portion that contacts the first field plate 212. By directly connecting the first and second field plates as shown in

[0041] Layers of the semiconductor devices described herein (e.g., passivation layers, sealing oxide layers, metal layers, contact nitride layers, gate contact dielectric oxide layers) can be formed using any technique suitable for forming layers on semiconductor devices, such as but not limited to physical vapor deposition or chemical vapor deposition.

[0042] Various embodiments of the present invention provide a semiconductor device and a method of manufacturing a semiconductor device for a 100-volt integrated circuit. Various alternative embodiments of the present invention provide a semiconductor device and a method of manufacturing a semiconductor device for a higher voltage rating.

[0043] Conclusion

[0044] Many modifications and other embodiments of the disclosure described herein will come to mind to those skilled in the art having the benefit of the foregoing description and the teachings presented in the associated drawings. Although the figures only show certain components of the devices and systems described herein, it should be understood that various other components can be used in conjunction with the systems. Accordingly, it should be understood that the disclosure is not limited to the specific embodiments disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Additionally, the steps in the foregoing methods need not occur in the order depicted in the figures, and in some instances, one or more of the depicted steps may occur substantially simultaneously or may involve additional steps. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

[0045] Although various embodiments in accordance with the principles disclosed herein have been shown and described above, those skilled in the art can modify them without departing from the spirit and teachings of the disclosure. The embodiments described herein are merely representative and not intended to be limiting. Many variations, combinations, and modifications are possible and within the scope of the disclosure. The disclosed embodiments primarily relate to the structure for GaN HEMT devices, however, those skilled in the art can recognize that these principles can be applied to other semiconductor devices. Alternative embodiments resulting from combining, integrating, and / or omitting features of (one or more) embodiments are also within the scope of the disclosure. Accordingly, the scope of protection is not limited by the above description.

[0046] In addition, the section headings used herein are provided for consistency with the recommendations of 37 C.F.R. 1.77 or to otherwise provide organizational cues. These headings should not limit or characterize the disclosure(s) listed in any claim(s) that may issue from this disclosure.

[0047] Although this detailed description has set forth some embodiments of the present disclosure, the appended claims cover other embodiments of the present disclosure that differ from the described embodiments in various modifications and improvements. For example, the appended claims may cover other forms of semiconductor devices, such as, in some applications, power LDMOS (lateral diffused metal oxide semiconductor) devices in a BCD (bipolar-CMOS-DMOS) platform where dual field plates are used.

[0048] Within the appended claims, unless a specific term "means for" or "step for" is used in a given claim, the claim is not intended to be construed under 35 U.S.C. 112, paragraph 6.

Claims

1. A semiconductor device (100), comprising: a substrate (102; 202), made of a semiconductor material; a gate structure (104; 204), placed on the substrate (102; 202); a passivation layer (106; 206), placed on the substrate (102; 202) and on a part of the gate structure (104; 204); a sealing dielectric layer (108; 208), placed on the passivation layer (106; 206), wherein the sealing dielectric layer (108; 208) is thicker than the passivation layer (106; 206); a first field plate (112; 212), placed on a part of the sealing dielectric layer (108; 208); dielectric layers (114, 128; 214, 228), placed on the first field plate (112; 212) and on the sealing dielectric layer (108; 208); a second field plate (132; 232), placed on a part of the dielectric layers (114, 128; 214, 228); and a source contact metallization (124; 224) and a drain contact metallization (126; 226).

2. The semiconductor device according to claim 1, wherein, The sealing dielectric layer (108; 208) and the dielectric layers (114, 128; 214, 228) are made of a nitride or oxide material.

3. The semiconductor device according to claim 1 or 2, wherein, The source contact metallization (124; 224) and the drain contact metallization (126; 226) are formed on corresponding parts of the substrate (102; 202) in corresponding voids in the passivation layer (106; 206), the sealing dielectric layer (108; 208), and the dielectric layers (114, 128; 214, 228).

4. The semiconductor device according to claims 1-3, wherein, The dielectric layers (114, 128; 214, 228) include a first dielectric sub-layer (114; 214) that partially overlaps with the source contact metallization (124; 224) and the drain contact metallization (126; 226), and a second dielectric sub-layer (128; 228) that overlaps with the source contact metallization (124; 224) and the drain contact metallization (126; 226).

5. The semiconductor device according to claims 1-4, wherein, The passivation layer (106; 206) has a thickness in the range from 5 nm to 10 nm, and the sealing dielectric layer (108; 208) has a thickness in the range from 30 nm to 120 nm.

6. The semiconductor device according to claims 1 - 5, further comprising a gate contact dielectric layer (134) placed on the second field plate (132; 232) and on a part of the dielectric layers (114, 128; 214, 228), and a gate contact metallization (138) placed on the gate structure (104; 204) in a void (136) in the gate contact dielectric layer (134), the dielectric layers (114, 128; 214, 228), the sealing dielectric layer (108; 208), and the passivation layer (106; 206).

7. The semiconductor device according to claims 1-6, wherein, The gate structure (104; 204) is made of gallium nitride (GaN); and wherein the semiconductor device (100) includes a GaN high electron mobility transistor.

8. The semiconductor device according to claims 1-7, wherein, The second field plate (232) partially contacts the first field plate (212) through additional voids (233) in the dielectric layers (114, 128; 214, 228).

9. A method of manufacturing a semiconductor device (100), the method comprising: forming a gate structure (104; 204) on a substrate (102; 204)； 202) made of semiconductor material; forming a passivation layer (106; 206) on the substrate (102; 202) and on a portion of the gate structure (104; 204); forming a sealing dielectric layer (108; 208) on the passivation layer (106; 206), wherein the sealing dielectric layer (108; 208) is thicker than the passivation layer (106; 206); forming a first field plate (112; 212) on a portion of the sealing dielectric layer (108; 208); forming dielectric layers (114, 128; 214, 228) on the first field plate (112; 212) and on the sealing dielectric layer (108; 208); forming a second field plate (132; 232) on a portion of the dielectric layers (114, 128; 214, 228); and 10. The method according to claim 9, wherein, forming source contact metallization (124; 224) and drain contact metallization (126; 226).

11. The method according to claims 9-10, wherein, The sealing dielectric layer (108; 208) and the dielectric layers (114, 128; 214, 228) are made of nitride or oxide materials.

12. The method according to claims 9-11, wherein, The source contact metallization (124; 224) and the drain contact metallization (126; 226) are formed on corresponding portions in corresponding voids in the substrate (102; 202) in the passivation layer (106; 206), the sealing dielectric layer (108; 208), and the dielectric layers (114, 128; 214, 228).

13. The method of claims 9-12, further comprising a gate contact dielectric layer (134) placed on the second field plate (132; 232) and on a portion of the dielectric layers (114, 128; 214, 228), and a gate contact metallization (138) placed on the gate structure (104; 204) in a void (136) in the gate contact dielectric layer (134), the dielectric layers (114, 128; 214, 228), the sealing dielectric layer (108; 208), and the passivation layer (106; 206).

14. The method of claim 13, wherein the gate contact metallization (138) is formed after the first field plate (112; 212) is formed.

15. The method according to any one of claims 9-14, wherein The second field plate (232) partially contacts the first field plate (212) through additional voids (233) in the dielectric layers (114, 128; 214, 228).

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