Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The method comprises the steps that a substrate is a VDMOS drain region; forming an epitaxial layer on the surface of the substrate, wherein the epitaxial layer comprises a first region, a second region and a third region which are adjacent; forming a first body region in the second region, wherein the first body region further extends to a part of the third region; forming a first Diode channel region in a part of the third region, and taking the third region outside the first body region and the first Diode channel region as a first Diode source region; forming a first Diode gate structure on the surface of a part of the third region; forming a VDMOS gate structure in the first region or on the surface of the first region; forming a first Diode drain region in the third region and in the first body region on one side of the first Diode gate structure; forming a first VDMOS source region in the first body region on one side of the VDMOS gate structure; and a first body lead-out region is formed in the first body region, so that the channel diode is compatible with the VDMOS device process, and the reverse recovery characteristic is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] Vertical double-diffused metal oxide semiconductor (VDMOS) is applied to very large scale integrated circuit devices of power devices, and has advantages such as small switching loss, high input impedance, small driving power, and good frequency characteristics.

[0003] However, the long recovery time of the body Diode in the VDMOS device during the reverse recovery process will result in significant switching losses and current spikes, increasing electromagnetic interference (EMI). Especially in silicon carbide and gallium nitride-based VDMOS devices, the wide bandgap material endows the device with excellent high-voltage and high-temperature performance. At the same time, the relatively wide bandgap makes it difficult for the body Diode to conduct during the reverse recovery process.

[0004] In summary, the performance of the existing VDMOS devices still needs to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate having a first conduction type and a first doping concentration, and serving as a VDMOS drain region; an epitaxial layer on the surface of the substrate, having the same conduction type as the substrate and a second doping concentration smaller than the first doping concentration, the epitaxial layer including adjacent first, second, and third regions arranged in a first direction parallel to the substrate surface, with the second region located between the first and third regions; a first body region in the second region and extending into part of the third region, having a second conduction type different from the first conduction type; a first Diode channel region in part of the third region, having the second conduction type and in contact with the first body region, and using the third region other than the first body region and the first Diode channel region as a first Diode source region; a first Diode gate structure on the surface of part of the third region, at least covering the surface of the first Diode channel region; a VDMOS gate structure in or on the surface of the first region; a first Diode drain region formed in the first body region in the third region and on one side of the first Diode gate structure, in contact with the first Diode channel region and having the first conduction type; a first VDMOS source region in the first body region on one side of the VDMOS gate structure; a first body lead-out region in the first body region, located between the first VDMOS source region and the first Diode drain region; a first conductive layer on the surfaces of the first Diode drain region, the first body lead-out region, the first VDMOS source region, and the first Diode gate structure; and a second conductive layer on the surface of the VDMOS gate structure.

[0007] Optionally, the first body region has a third doping concentration, and the first Diode channel region has a fourth doping concentration, with the fourth doping concentration less than or equal to the third doping concentration.

[0008] Optionally, the first Diode gate structure covers all or part of the surface of the first Diode source region.

[0009] Optionally, the first Diode gate structure further extends to part of the surface of the first body region and exposes another part of the surface of the first body region.

[0010] Optionally, the VDMOS gate structure is located in the first region, and the bottom of the VDMOS gate structure is deeper than the bottom edge of the first body region.

[0011] Optionally, the VDMOS gate structure includes a VDMOS gate oxide layer and a VDMOS gate layer on the surface of the VDMOS gate oxide layer; the first Diode gate structure includes a first Diode gate oxide layer and a first Diode gate layer on the surface of the first Diode gate oxide layer; the thickness of the first Diode gate oxide layer is equal to or less than the thickness of the VDMOS gate oxide layer.

[0012] Optionally, the VDMOS gate structure is located on the surface of the first region, and the first body region also extends to a part of the first region.

[0013] Optionally, the substrate includes opposite first and second surfaces, and the epitaxial layer is located on the first surface; further included is: a third conductive layer on the second surface.

[0014] Optionally, the epitaxial layer further includes: a fourth region and a fifth region arranged along the first direction, with the fourth region adjacent to the first region and the fifth region on both sides respectively; the semiconductor structure further includes: a second body region in the fourth region, the second body region also extending to a part of the fifth region, the second body region having the second conductivity type; a second Diode channel region in a part of the fifth region, the second Diode channel region having the second conductivity type, and the second Diode channel region being in contact with the second body region, with the fifth region outside the second body region and the second Diode channel region being the second Diode source region; a second Diode gate structure on the surface of a part of the fifth region, the second Diode gate structure at least covering the surface of the second Diode channel region; a second Diode drain region in the second body region in the fifth region and on one side of the second Diode gate structure, the second Diode drain region being in contact with the second Diode channel region, the second Diode drain region having the first conductivity type; a second VDMOS source region in the second body region on the other side of the VDMOS gate structure; a second body lead-out region in the second body region, the second body lead-out region being located between the second VDMOS source region and the second Diode drain region; a fourth conductive layer on the surfaces of the second Diode drain region, the second body lead-out region, the second VDMOS source region, and the second Diode gate structure.

[0015] Correspondingly, the technical solution of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, the substrate having a first conductivity type and a first doping concentration, and using the substrate as the drain region of the VDMOS; forming an epitaxial layer on the surface of the substrate, the epitaxial layer having the same conductivity type as the substrate and a second doping concentration, the second doping concentration being less than the first doping concentration, the epitaxial layer including adjacent first, second, and third regions arranged along a first direction parallel to the surface of the substrate, and the second region being located between the first region and the third region; forming a first body region in the second region, the first body region also extending into part of the third region, the first body region having a second conductivity type different from the first conductivity type; forming a first Diode channel region in part of the third region, the first Diode channel region having the second conductivity type and being in contact with the first body region, and using the third region other than the first body region and the first Diode channel region as the first Diode source region; forming a first Diode gate structure on the surface of part of the third region, the first Diode gate structure at least covering the surface of the first Diode channel region; forming a VDMOS gate structure in or on the first region; forming a first Diode drain region in the third region and in the first body region on one side of the first Diode gate structure, the first Diode drain region being in contact with the first Diode channel region and having the first conductivity type; forming a first VDMOS source region in the first body region on one side of the VDMOS gate structure; forming a first body lead-out region in the first body region, the first body lead-out region being located between the first VDMOS source region and the first Diode drain region; forming a first conductive layer on the surfaces of the first Diode drain region, the first body lead-out region, the first VDMOS source region, and the first Diode gate structure; and forming a second conductive layer on the surface of the VDMOS gate structure.

[0016] Optionally, the first body region has a third doping concentration, and the first Diode channel region has a fourth doping concentration, the fourth doping concentration being less than or equal to the third doping concentration.

[0017] Optionally, the fourth doping concentration is equal to the third doping concentration; the forming method of the first body region and the first Diode channel region includes: using a first ion implantation process to implant a first doping ion into the second region and part of the third region to form the first body region and the first Diode channel region.

[0018] Optionally, the fourth doping concentration is less than the third doping concentration; the method for forming the first body region further includes: forming a first mask layer on the surface of the epitaxial layer, the first mask layer exposing the surface of the second region and a portion of the surface of the third region adjacent to the second region; using the first mask layer as a mask, and injecting a first doping ion into the epitaxial layer by a first ion implantation process to form the first body region; the method for forming the first Diode channel region further includes: forming a second mask layer on the surface of the epitaxial layer, the second mask layer exposing a portion of the surface of the third region; using the second mask layer as a mask, and injecting a second doping ion into the epitaxial layer by a second ion implantation process to form the first Diode channel region.

[0019] Optionally, the first Diode gate structure covers all or part of the surface of the first Diode source region.

[0020] Optionally, the first Diode gate structure further extends to a portion of the surface of the first body region and exposes another portion of the surface of the first body region.

[0021] Optionally, the VDMOS gate structure is formed in the first region, and the bottom of the VDMOS gate structure is deeper than the bottom edge of the first body region; the method for forming the VDMOS gate structure includes: etching the first region to form a gate groove in the first region; forming a first gate oxide material layer on the sidewall and bottom surface of the gate groove and on the surface of the epitaxial layer; forming a first gate material layer on the surface of the first gate oxide material layer; planarizing the first gate material layer and the first gate oxide material layer until the surface of the epitaxial layer is exposed to form the VDMOS gate structure, the VDMOS gate structure including a VDMOS gate oxide layer and a VDMOS gate layer, using the first gate oxide material layer to form the VDMOS gate oxide layer, and using the first gate material layer to form the VDMOS gate layer.

[0022] Optionally, the first Diode gate structure includes a first Diode gate oxide layer and a first Diode gate layer located on the surface of the first Diode gate oxide layer; the thickness of the first Diode gate oxide layer is equal to or less than the thickness of the VDMOS gate oxide layer; the method for forming the first Diode gate structure further includes: after forming the VDMOS gate structure, the first body region, and the first Diode channel region, forming a second gate oxide material layer on the surface of the epitaxial layer; forming a second gate material layer on the surface of the second gate oxide material layer; etching the second gate material layer and the second gate oxide material layer, using the second gate material layer to form the first Diode gate layer, and using the second gate oxide material layer to form the first Diode gate oxide layer.

[0023] Optionally, a VDMOS gate structure is formed on the surface of the first region, and the first body region further extends to a part of the first region; the VDMOS gate structure includes a VDMOS gate oxide layer and a VDMOS gate layer located on the surface of the VDMOS gate oxide layer; the first Diode gate structure includes a first Diode gate oxide layer and a first Diode gate layer located on the surface of the first Diode gate oxide layer.

[0024] Optionally, the thickness of the first Diode gate oxide layer is equal to that of the VDMOS gate oxide layer; the first Diode gate structure and the VDMOS gate structure are formed by the same process.

[0025] Optionally, the thickness of the first Diode gate oxide layer is less than that of the VDMOS gate oxide layer; the first Diode gate structure and the VDMOS gate structure are formed in different processes.

[0026] Optionally, the substrate includes opposite first and second surfaces, and the epitaxial layer is formed on the first surface; further included is: forming a third conductive layer on the second surface.

[0027] Optionally, the epitaxial layer further includes a fourth region and a fifth region arranged along the first direction, with the fourth region adjacent to the first region and the fifth region on both sides respectively; the method further includes: forming a second body region in the fourth region, the second body region further extending to a part of the fifth region, the second body region having the second conductivity type; forming a second Diode channel region in a part of the fifth region, the second Diode channel region having the second conductivity type, and the second Diode channel region being in contact with the second body region, using the fifth region outside the second body region and the second Diode channel region as the second Diode source region; forming a second Diode gate structure on the surface of a part of the fifth region, the second Diode gate structure at least covering the surface of the second Diode channel region; forming a second Diode drain region in the fifth region and in the second body region on one side of the second Diode gate structure, the second Diode drain region being in contact with the second Diode channel region, the second Diode drain region having the first conductivity type; forming a second VDMOS source region in the second body region on the other side of the VDMOS gate structure; forming a second body lead-out region in the second body region, the second body lead-out region being located between the second VDMOS source region and the second Diode drain region; forming a fourth conductive layer on the surfaces of the second Diode drain region, the second body lead-out region, the second VDMOS source region, and the second Diode gate structure.

[0028] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0029] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a VDMOS drain region, a first VDMOS source region, a first body region, and a VDMOS gate structure form a VDMOS device, and a first Diode source region, a first Diode channel region, a first Diode drain region, and a first Diode gate structure form a channel diode. The channel diode is connected in parallel with the VDMOS device through a first conductive layer. The channel diode with a lower conduction voltage is used to improve the reverse recovery characteristics of the VDMOS device, shorten the reverse recovery time, and improve the switching efficiency. At the same time, through the compatibility of the VDMOS device process and the channel diode process, the VDMOS device and the channel diode are integrated together. While improving the reverse recovery characteristics of the VDMOS, it is beneficial to improve the integration degree of the chip.

[0030] In the semiconductor structure provided by the technical solution of the present invention, a VDMOS drain region, a first VDMOS source region, a first body region, and a VDMOS gate structure form a VDMOS device, and a first Diode source region, a first Diode channel region, a first Diode drain region, and a first Diode gate structure form a channel diode. The channel diode is connected in parallel with the VDMOS device through a first conductive layer. The channel diode with a lower conduction voltage is used to improve the reverse recovery characteristics of the VDMOS device, shorten the reverse recovery time, and improve the switching efficiency. At the same time, through the compatibility of the VDMOS device process and the channel diode process, the VDMOS device and the channel diode are integrated together. While improving the reverse recovery characteristics of the VDMOS, it is beneficial to improve the integration degree of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figures 1 to 10 are schematic structural diagrams of the steps of the method for forming a semiconductor structure according to an embodiment of the present invention;

[0032] Figures 11 to 17 are schematic structural diagrams of the steps of the method for forming a semiconductor structure according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] It should be noted that in this specification, "surface" and "upper" are used to describe the relative positional relationship in space and do not limit whether there is direct contact.

[0034] As described in the background art, the performance of existing VDMOS devices still needs to be improved. Currently, common solutions for optimizing the reverse recovery performance include: externally paralleling a fast recovery diode (FRD), integrating a hetero-junction diode (HJD), or integrating a Schottky barrier diode (SBD), etc.

[0035] However, the above solutions all have deficiencies: among them, the method of externally paralleling an FRD will increase the chip size and introduce complex parasitic parameters; integrating an HJD will face the problem that it is difficult to perfect the inherent material interface defects of the hetero-junction material; integrating an SBD will face the risk of high-temperature performance degradation.

[0036] To solve the above problems, in a semiconductor structure and its forming method provided by the present invention, a VDMOS drain region, a first VDMOS source region, a first body region, and a VDMOS gate structure form a VDMOS device, and a first diode source region, a first diode channel region, a first diode drain region, and a first diode gate structure form a channel diode. The channel diode is paralleled with the VDMOS device through a first conductive layer. The channel diode with a lower conduction voltage is used to improve the reverse recovery characteristics of the VDMOS device, shorten the reverse recovery time, and improve the switching efficiency. At the same time, through the compatibility of the VDMOS device process and the channel diode process, the VDMOS device and the channel diode are integrated together. While improving the reverse recovery characteristics of the VDMOS, it is beneficial to improve the integration degree of the chip.

[0037] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description will be made on specific embodiments of the present invention with reference to the accompanying drawings.

[0038] Figures 1 to 10 It is a structural schematic diagram of each step of the forming method of the semiconductor structure according to an embodiment of the present invention.

[0039] Please refer to Figure 1, a substrate 100 is provided. The substrate 100 has a first conductivity type and a first doping concentration, and serves as the VDMOS drain region. An epitaxial layer 101 is formed on the surface of the substrate 100. The epitaxial layer 101 has the same conductivity type as the substrate 100 and a second doping concentration, which is less than the first doping concentration. The epitaxial layer 101 includes adjacent first region I, second region II, and third region III. The first region I, the second region II, and the third region III are arranged in a first direction (not shown in the figure), and the first direction is parallel to the surface of the substrate 100. The second region II is located between the first region I and the third region III.

[0040] The first region I and the second region II are used to define the position of the VDMOS device. Specifically, the first region I is used to define the position of the VDMOS gate structure, the second region II is used to define the positions of the first VDMOS source region and the first body lead-out region, and the third region III is used to define the position of the MOS-channel diode.

[0041] In this embodiment, the epitaxial layer 101 further includes a fourth region IV and a fifth region V arranged in the first direction. The two sides of the fourth region IV are adjacent to the first region I and the fifth region V respectively. The fourth region IV is used to define the positions of the second VDMOS source region and the second body lead-out region. The two VDMOS devices share the VDMOS gate structure, and the fifth region V is used to define the position of another MOS-channel diode.

[0042] In another embodiment, the epitaxial layer may not include the fourth region and the fifth region. That is, another VDMOS device and another MOS-channel diode are not formed.

[0043] In this embodiment, the substrate 100 includes an opposite first surface (not shown in the figure) and a second surface (not shown in the figure), and the epitaxial layer 101 is formed on the first surface.

[0044] In this embodiment, the first conductivity type is N-type.

[0045] In another embodiment, the first conductivity type may be P-type.

[0046] In this embodiment, the materials of the substrate 100 and the epitaxial layer 101 are both silicon.

[0047] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI); the material of the epitaxial layer includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0048] Subsequently, a VDMOS gate structure is formed within or on the surface of the first region I.

[0049] In this embodiment, for forming the trench gate structure, that is, forming a VDMOS gate structure within the first region I, for the formation method of the VDMOS gate structure, please refer to Figures 2 to 3 .

[0050] Please refer to Figure 2 , etch the first region I to form a gate groove 102 within the first region I.

[0051] The process of etching the first region I includes one or a combination of a dry etching process and a wet etching process. In this embodiment, the process of etching the first region I is a dry etching process, which is beneficial to improving the morphology of the formed gate groove 102.

[0052] Please refer to Figure 3 , form a first gate oxide material layer (not shown in the figure) on the sidewall and bottom surface of the gate groove 102 and on the surface of the epitaxial layer 101; form a first gate material layer (not shown in the figure) on the surface of the first gate oxide material layer; planarize the first gate material layer and the first gate oxide material layer until the surface of the epitaxial layer 101 is exposed to form the VDMOS gate structure. The VDMOS gate structure includes a VDMOS gate oxide layer 103 and a VDMOS gate layer 104. The VDMOS gate oxide layer 103 is formed with the first gate oxide material layer, and the VDMOS gate layer 104 is formed with the first gate material layer.

[0053] In this embodiment, the material of the VDMOS gate layer 104 is polysilicon; the material of the first gate oxide material layer is silicon oxide.

[0054] Please refer to Figure 4 , form a first body region 105 within the second region II. The first body region 105 also extends to a part of the third region III. The first body region 105 has a second conductivity type, which is different from the first conductivity type.

[0055] In this embodiment, the method for forming the first body region 105 further includes: forming a first mask layer (not shown in the figure) on the surface of the epitaxial layer 101, where the first mask layer exposes the surface of the second region II and a part of the surface of the third region III adjacent to the second region II; using the first mask layer as a mask, and adopting a first ion implantation process to implant a first doping ion into the epitaxial layer 101 to form the first body region 105.

[0056] In this embodiment, the first mask layer also exposes the surface of the first region I, so that the first doping ion is implanted into the VDMOS gate structure.

[0057] In this embodiment, the second conduction type is P-type.

[0058] In another embodiment, the second conduction type is N-type.

[0059] In this embodiment, the bottom of the VDMOS gate structure is deeper than the bottom edge of the first body region 105, that is, the doping depth of the first body region 105 is lower than the depth of the gate groove 102 (as Figure 2 shown).

[0060] In this embodiment, after forming the VDMOS gate structure, the first body region 105 is formed.

[0061] In another embodiment, the formation sequence of the VDMOS gate structure and the first body region may not be limited.

[0062] In this embodiment, a second body region 205 is further formed in the fourth region IV, and the second body region 205 also extends to a part of the fifth region V. The second body region 205 has the second conduction type. Here, the first body region 105 and the second body region 205 are formed simultaneously in the same process, that is, the first mask layer also exposes the surface of the fourth region IV and a part of the surface of the fifth region V, so that the first doping ion is implanted into the fourth region IV and a part of the fifth region V.

[0063] Please refer to Figure 5 , a first Diode channel region 106 is formed in a part of the third region III. The first Diode channel region 106 has the second conduction type, and the first Diode channel region 106 is in contact with the first body region 105. The third region III outside the first body region 105 and the first Diode channel region 106 is used as a first Diode source region 121.

[0064] It should be noted here that the region with the first conductivity type in the epitaxial layer 101 is actually shared by the channel diode and the VDMOS device, serving as the drain of the channel diode and the drift region of the VDMOS device respectively. For the convenience of description, the third region III outside the first body region 105 and the first Diode channel region 106 is defined as the first Diode source region 121, and further, the first region I and the second region I outside the first body region 105 and at the bottom of the VDMOS gate structure are defined as the offset regions of the VDMOS device.

[0065] The first body region 105 has a third doping concentration, and the first Diode channel region 106 has a fourth doping concentration, and the fourth doping concentration is less than or equal to the third doping concentration. The purpose of making the fourth doping concentration less than or equal to the third doping concentration is to make the channel diode have a lower conduction voltage relative to the VDMOS device, so as to optimize the reverse recovery performance of the VDMOS device.

[0066] In this embodiment, the fourth doping concentration is less than the third doping concentration.

[0067] In this embodiment, the forming method of the first Diode channel region 106 includes: forming a second mask layer (not shown in the figure) on the surface of the epitaxial layer 101, and the second mask layer exposes part of the surface of the third region III; using the second mask layer as a mask, and adopting a second ion implantation process to implant a second doping ion into the epitaxial layer 101 to form the first Diode channel region 106.

[0068] In this embodiment, the first body region 105 is formed first, and then the first Diode channel region 106 is formed.

[0069] Here, it should be noted that Figure 5 the first body region 105 and the first Diode channel region 106 shown in have the same doping depth. In other embodiments, the first body region and the first Diode channel region may have different doping depths.

[0070] In another embodiment, the formation sequence of the first body region and the first Diode channel region may not be restricted.

[0071] In still another embodiment, the fourth doping concentration is equal to the third doping concentration, and the first body region and the first Diode channel region are formed by the same process. Specifically, the forming method of the first body region and the first Diode channel region includes: adopting a first ion implantation process to implant a first doping ion into the second region and part of the third region to form the first body region and the first Diode channel region.

[0072] In this embodiment, a second Diode channel region 206 is further formed in part of the fifth region V. The second Diode channel region 206 has the second conductivity type, and the second Diode channel region 206 is in contact with the second body region 205. The fifth region V outside the second body region 205 and the second Diode channel region 206 serves as the second Diode source region 221. Here, the second Diode channel region 206 and the first Diode channel region 106 are formed simultaneously in the same process.

[0073] Please refer to Figure 6 , a first Diode gate structure is formed on the surface of part of the third region III, and the first Diode gate structure covers at least the surface of the first Diode channel region 106.

[0074] The first Diode gate structure includes a first Diode gate oxide layer 107 and a first Diode gate layer 108 located on the surface of the first Diode gate oxide layer 107.

[0075] The thickness of the first Diode gate oxide layer 107 is equal to or less than the thickness of the VDMOS gate oxide layer 103. Here, the purpose of making the thickness of the first Diode gate oxide layer 107 equal to or less than the thickness of the VDMOS gate oxide layer 103 is to make the channel diode have a lower turn-on voltage relative to the VDMOS device, so as to optimize the reverse recovery performance of the VDMOS device.

[0076] It should be noted here that whether the first body region and the first Diode channel region can be formed by the same process depends on the material of the epitaxial layer. The specific reasons are as follows:

[0077] Since the channel diode is used to turn on faster than the body diode in the VDMOS device during reverse recovery, so as to optimize the reverse recovery loss, the channel diode needs to have a lower turn-on voltage, and the turn-on voltage of the channel diode is related to the doping concentration of the channel region (i.e., the fourth doping concentration) and the thickness of the gate oxide layer (i.e., the thickness of the first Diode gate oxide layer 107).

[0078] For example, for a VDMOS device and a channel diode based on silicon (i.e., the material of the epitaxial layer is silicon), since the turn-on voltage of the body diode in the VDMOS device is relatively low (about 0.76 V), for the channel diode, to achieve the above purposes, a thinner gate oxide layer and / or a lower doping concentration in the channel region are required, that is, "the thickness of the first Diode gate oxide layer 107 is less than the thickness of the VDMOS gate oxide layer 103", and / or "the fourth doping concentration is less than the third doping concentration". For a VDMOS device and a channel diode based on silicon carbide (i.e., the material of the epitaxial layer is silicon carbide), since the turn-on voltage of the body diode in the VDMOS device is relatively low (about 3.2 V), for the channel diode, a thicker gate oxide layer and a higher doping concentration in the channel region can achieve a turn-on voltage lower than that of the body diode. At this time, the first body region and the first Diode channel region can be formed by the same process. For a planar gate structure, the first Diode gate oxide layer and the VDMOS gate oxide layer can also be formed simultaneously by the same process (see the description of the next embodiment).

[0079] In this embodiment, the method for forming the first Diode gate structure includes: after forming the VDMOS gate structure, the first body region 105 and the first Diode channel region 106, forming a second gate oxide material layer (not shown in the figure) on the surface of the epitaxial layer 101; forming a second gate material layer (not shown in the figure) on the surface of the second gate oxide material layer; etching the second gate material layer and the second gate oxide material layer to form the first Diode gate layer 108 with the second gate material layer and form the first Diode gate oxide layer 107 with the second gate oxide material layer.

[0080] In this embodiment, a second Diode gate structure is further formed on the surface of a part of the fifth region V, and the second Diode gate structure covers at least the surface of the second Diode channel region 206.

[0081] The second Diode gate structure includes a second Diode gate oxide layer 207 and a second Diode gate layer 208 located on the surface of the second Diode gate oxide layer 207. Here, the second Diode gate structure and the first Diode gate structure are formed simultaneously by the same process.

[0082] In this embodiment, the first Diode gate structure covers the entire surface of the first Diode source region 121.

[0083] In another embodiment, the first Diode gate structure covers a part of the surface of the first Diode source region.

[0084] In this embodiment, the second Diode gate structure covers the entire surface of the second Diode source region 221.

[0085] In another embodiment, the second Diode gate structure covers a part of the surface of the second Diode source region.

[0086] In this embodiment, the first Diode gate structure also extends to a part of the surface of the first body region 105 and exposes another part of the surface of the first body region 105; the second Diode gate structure also extends to a part of the surface of the second body region 205 and exposes another part of the surface of the second body region 205.

[0087] Please refer to Figure 7 , in the third region III, a first Diode drain region 109 is formed in the first body region 105 on one side of the first Diode gate structure. The first Diode drain region 109 is in contact with the first Diode channel region 106, and the first Diode drain region 109 has the first conduction type; a first VDMOS source region 110 is formed in the first body region 105 on one side of the VDMOS gate structure.

[0088] In this embodiment, the first Diode drain region 109 and the first VDMOS source region 110 are formed simultaneously in the same ion implantation process.

[0089] In this embodiment, a second Diode drain region 209 is also formed in the second body region 205 on one side of the second Diode gate structure in the fifth region V. The second Diode drain region 209 is in contact with the second Diode channel region 206, and the second Diode drain region 209 has the first conduction type; a second VDMOS source region 210 is formed in the second body region 205 on the other side of the VDMOS gate structure.

[0090] In this embodiment, the second Diode drain region 209 and the second VDMOS source region 210 are also formed simultaneously in the same ion implantation process as the first Diode drain region 109 and the first VDMOS source region 110.

[0091] In this embodiment, the first Diode drain region 109 also extends to the bottom of a part of the first Diode gate structure.

[0092] In this embodiment, the second Diode drain region 209 also extends to the bottom of a part of the second Diode gate structure.

[0093] Please refer to Figure 8, a first body lead-out region 111 is formed within the first body region 105, and the first body lead-out region 111 is located between the first VDMOS source region 110 and the first Diode drain region 109.

[0094] In this embodiment, the first body lead-out region 111 has the same conductivity type as the first body region 105, and the doping concentration of the first body lead-out region 111 is greater than that of the first body region 105.

[0095] In this embodiment, both sides of the first body lead-out region 111 are in contact with the first VDMOS source region 110 and the first Diode drain region 109 respectively.

[0096] In another embodiment, the first body lead-out region may not be in contact with the first VDMOS source region and the first Diode drain region.

[0097] In this embodiment, a second body lead-out region 211 is further formed within the second body region 205, and the second body lead-out region 211 is located between the second VDMOS source region 210 and the second Diode drain region 209.

[0098] Please refer to Figure 9 , a first conductive layer 112 is formed on the surfaces of the first Diode drain region 109, the first body lead-out region 111, the first VDMOS source region 110, and the first Diode gate structure; a second conductive layer 113 is formed on the surface of the VDMOS gate structure.

[0099] So far, the VDMOS drain region, the first VDMOS source region 110, the first body region 105, and the VDMOS gate structure constitute a VDMOS device, and the first Diode source region 121, the first Diode channel region 106, the first Diode drain region 109, and the first Diode gate structure constitute a channel diode. The channel diode is connected in parallel with the VDMOS device through the first conductive layer 112. By using the channel diode with a lower conduction voltage, the reverse recovery characteristic of the VDMOS device is improved, the reverse recovery time is shortened, and the switching efficiency is increased. At the same time, through the compatibility of the VDMOS device process and the channel diode process, the VDMOS device and the channel diode are integrated together. While improving the reverse recovery characteristic of the VDMOS, it is beneficial to improve the integration degree of the chip.

[0100] In addition, by improving the reverse recovery characteristic of the VDMOS device through the channel diode, not only the energy loss is reduced, but also it helps to meet the strict requirements for device performance in fields such as modern electric vehicles, renewable energy, and high-frequency switching power supplies, thereby enhancing the overall reliability and competitiveness of the system.

[0101] In this embodiment, a fourth conductive layer 212 is further formed on the surfaces of the second Diode drain region 209, the second body lead-out region 211, the second VDMOS source region 210, and the second Diode gate structure. Here, the first conductive layer 112, the second conductive layer 113, and the fourth conductive layer 212 are formed by the same process.

[0102] Here, the VDMOS drain region, the second VDMOS source region 210, the second body region 205, and the VDMOS gate structure constitute another VDMOS device, and the second Diode source region 221, the first Diode channel region 106, the first Diode drain region 109, and the first Diode gate structure constitute another channel diode. The fourth conductive layer 212 is used to connect the other channel diode in parallel with the corresponding VDMOS device, which is also used to improve the reverse recovery characteristics of the VDMOS device, shorten the reverse recovery time, and improve the switching efficiency.

[0103] The materials of the first conductive layer 112, the second conductive layer 113, and the fourth conductive layer 212 include metal, and the metal can be copper, aluminum, gold, tungsten, etc.

[0104] Please refer to Figure 10 , and a third conductive layer 114 is formed on the second surface.

[0105] In this embodiment, the material of the third conductive layer 114 includes metal, and the metal can be copper, aluminum, gold, tungsten, etc.

[0106] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method. Please continue to refer to Figure 10, the semiconductor structure includes: a substrate 100 having a first conductivity type and a first doping concentration, and serving as the VDMOS drain region; an epitaxial layer 101 on the surface of the substrate 100, having the same conductivity type as the substrate 100 and a second doping concentration less than the first doping concentration. The epitaxial layer 101 includes adjacent first region I, second region II, and third region III, which are arranged in a first direction (not shown in the figure) parallel to the surface of the substrate 100, and the second region II is located between the first region I and the third region III; a first body region 105 within the second region II and extending into part of the third region III, having a second conductivity type different from the first conductivity type; a first Diode channel region 106 within part of the third region III, having the second conductivity type and in contact with the first body region 105, and using the third region III outside the first body region 105 and the first Diode channel region 106 as the first Diode source region 121; a first Diode gate structure on the surface of part of the third region III, at least covering the surface of the first Diode channel region 106; a VDMOS gate structure within or on the surface of the first region I; a first Diode drain region 109 formed within the first body region 105 within the third region III and on one side of the first Diode gate structure, in contact with the first Diode channel region 106 and having the first conductivity type; a first VDMOS source region 110 within the first body region 105 on one side of the VDMOS gate structure; a first body lead-out region 111 within the first body region 105, located between the first VDMOS source region 110 and the first Diode drain region 109; a first conductive layer 112 on the surfaces of the first Diode drain region 109, the first body lead-out region 111, the first VDMOS source region 110, and the first Diode gate structure; and a second conductive layer 113 on the surface of the VDMOS gate structure.

[0107] So far, the VDMOS drain region, the first VDMOS source region 110, the first body region 105, and the VDMOS gate structure constitute a VDMOS device. The first Diode source region 121, the first Diode channel region 106, the first Diode drain region 109, and the first Diode gate structure constitute a channel diode. The channel diode is connected in parallel with the VDMOS device through the first conductive layer 112. The channel diode with a lower conduction voltage is adopted to improve the reverse recovery characteristic of the VDMOS device, shorten the reverse recovery time, and improve the switching efficiency. At the same time, through the compatibility of the VDMOS device process and the channel diode process, the VDMOS device and the channel diode are integrated together. While improving the reverse recovery characteristic of the VDMOS, it is beneficial to improve the integration degree of the chip.

[0108] In addition, the reverse recovery characteristic of the VDMOS device is improved by the channel diode, which not only reduces the energy loss, but also helps to meet the strict requirements for device performance in fields such as modern electric vehicles, renewable energy, and high-frequency switching power supplies, thereby improving the overall reliability and competitiveness of the system.

[0109] The first body region 105 has a third doping concentration, and the first Diode channel region 106 has a fourth doping concentration, and the fourth doping concentration is less than or equal to the third doping concentration.

[0110] The first Diode gate structure covers all or part of the surface of the first Diode source region 121.

[0111] In this embodiment, the first Diode gate structure covers the entire surface of the first Diode source region 121.

[0112] In another embodiment, the first Diode gate structure covers part of the surface of the first Diode source region.

[0113] In this embodiment, the first Diode gate structure further extends to part of the surface of the first body region 105 and exposes another part of the surface of the first body region 105.

[0114] In this embodiment, the VDMOS gate structure is located in the first region I, and the bottom of the VDMOS gate structure is deeper than the bottom edge of the first body region 105.

[0115] In another embodiment, the VDMOS gate structure is located on the surface of the first region, and the first body region further extends to part of the first region.

[0116] The VDMOS gate structure includes a VDMOS gate oxide layer 103 and a VDMOS gate layer 104 located on the surface of the VDMOS gate oxide layer 103.

[0117] The first Diode gate structure includes a first Diode gate oxide layer 107 and a first Diode gate layer 108 located on the surface of the first Diode gate oxide layer 107.

[0118] The thickness of the first Diode gate oxide layer 107 is equal to or less than the thickness of the VDMOS gate oxide layer 103.

[0119] The substrate 100 includes opposite first and second surfaces (not shown in the figure), and the epitaxial layer 101 is located on the first surface.

[0120] In this embodiment, it further includes: a third conductive layer 114 located on the second surface.

[0121] In this embodiment, the epitaxial layer further includes: a fourth region IV and a fifth region V arranged along the first direction, and the fourth region IV is adjacent to the first region I and the fifth region V on both sides respectively.

[0122] In this embodiment, the semiconductor structure further includes: a second body region 205 located in the fourth region IV, the second body region 205 also extending to a part of the fifth region V, the second body region 205 having the second conductivity type; a second Diode channel region 206 located in a part of the fifth region V, the second Diode channel region 206 having the second conductivity type, and the second Diode channel region 206 being in contact with the second body region 205, with the fifth region V other than the second body region 205 and the second Diode channel region 206 being the second Diode source region 221; a second Diode gate structure located on the surface of a part of the fifth region V, the second Diode gate structure at least covering the surface of the second Diode channel region 206; a second Diode drain region 209 located in the second body region 205 within the fifth region V and on one side of the second Diode gate structure, the second Diode drain region 209 being in contact with the second Diode channel region 206, the second Diode drain region 209 having the first conductivity type; a second VDMOS source region 210 located in the second body region 205 on the other side of the VDMOS gate structure; a second body lead-out region 211 located in the second body region 205, the second body lead-out region 211 being located between the second VDMOS source region 210 and the second Diode drain region 209; a fourth conductive layer 212 located on the surfaces of the second Diode drain region 209, the second body lead-out region 211, the second VDMOS source region 210, and the second Diode gate structure.

[0123] In this embodiment, the second Diode gate structure includes a second Diode gate oxide layer 207 and a second Diode gate layer 208 located on the surface of the second Diode gate oxide layer 207.

[0124] Figures 11 to 17 It is a schematic structural diagram of each step of a method for forming a semiconductor structure according to another embodiment of the present invention.

[0125] The main difference between this embodiment and the previous embodiment is as follows:

[0126] In this embodiment, a VDMOS gate structure is formed on the surface of the first region, that is, a planar gate structure is formed. In the previous embodiment, the VDMOS gate structure was formed within the first region, that is, a trench gate structure was formed.

[0127] In this embodiment, for the method of forming the semiconductor structure, please refer to Figures 11 to 17 .

[0128] Please refer to Figure 11, a substrate 300 is provided. The substrate 300 has a first conductivity type and a first doping concentration, and the substrate 300 serves as the drain region of the VDMOS. An epitaxial layer 301 is formed on the surface of the substrate 300. The epitaxial layer 301 has the same conductivity type as the substrate 300 and a second doping concentration, and the second doping concentration is less than the first doping concentration. The epitaxial layer 301 includes adjacent first region I, second region II, and third region III, which are arranged in a first direction (not shown in the figure). The first direction is parallel to the surface of the substrate 300, and the second region II is located between the first region I and the third region III.

[0129] Please refer to Figure 12 , a first body region 302 is formed in the second region II, and the first body region 302 also extends to a part of the third region III. The first body region 302 has a second conductivity type, which is different from the first conductivity type. A first Diode channel region 303 is formed in a part of the third region III. The first Diode channel region 303 has the second conductivity type, and the first Diode channel region 303 is in contact with the first body region 302. The third region III outside the first body region 302 and the first Diode channel region 303 serves as the first Diode source region 304.

[0130] In this embodiment, the first body region 302 also extends to a part of the first region I, that is, to the bottom of the VDMOS gate structure formed subsequently.

[0131] In this embodiment, a second body region 402 is further formed in the fourth region IV, and the second body region 402 also extends to a part of the fifth region V. The second body region 402 has the second conductivity type.

[0132] In this embodiment, the second body region 402 also extends to a part of the first region I, that is, to the bottom of the VDMOS gate structure formed subsequently.

[0133] In this embodiment, a second Diode channel region 403 is further formed in a part of the fifth region V. The second Diode channel region 403 has the second conductivity type, and the second Diode channel region 403 is in contact with the second body region 402. The fifth region V outside the second body region 402 and the second Diode channel region 403 serves as the second Diode source region 404.

[0134] Please refer to Figure 13, a first Diode gate structure is formed on the surface of a part of the third region III, and the first Diode gate structure covers at least the surface of the first Diode channel region 303; a VDMOS gate structure is formed on the surface of the first region I.

[0135] The first Diode gate structure includes a first Diode gate oxide layer 305 and a first Diode gate layer 306 located on the surface of the first Diode gate oxide layer 305.

[0136] The VDMOS gate structure includes a VDMOS gate oxide layer 307 and a VDMOS gate layer 308 located on the surface of the VDMOS gate oxide layer 307.

[0137] The thickness of the first Diode gate oxide layer 305 is equal to or less than the thickness of the VDMOS gate oxide layer 307.

[0138] In this embodiment, the thickness of the first Diode gate oxide layer 305 is equal to the thickness of the VDMOS gate oxide layer 307; the first Diode gate structure and the VDMOS gate structure are formed by the same process.

[0139] Specifically, the forming methods of the first Diode gate structure and the VDMOS gate structure include: forming a gate oxide material layer (not shown in the figure) on the surface of the epitaxial layer 301; forming a gate material layer (not shown in the figure) on the surface of the gate oxide material layer; etching the gate material layer and the gate oxide material layer to form the first Diode gate oxide layer 305 and the VDMOS gate oxide layer 307 with the gate oxide material layer, and forming the first Diode gate layer 306 and the VDMOS gate layer 308 with the gate material layer.

[0140] In another embodiment, the thickness of the first Diode gate oxide layer is less than that of the VDMOS gate oxide layer; the first Diode gate structure and the VDMOS gate structure are formed in different processes.

[0141] In this embodiment, a second Diode gate structure is further formed on the surface of a part of the fifth region V, and the second Diode gate structure covers at least the surface of the second Diode channel region 403.

[0142] The second Diode gate structure includes a second Diode gate oxide layer 405 and a second Diode gate layer 406 located on the surface of the second Diode gate oxide layer 405. Here, the second Diode gate structure and the first Diode gate structure are formed simultaneously by the same process.

[0143] Please refer to Figure 14, in the third region III, a first Diode drain region 309 is formed in the first body region 302 on one side of the first Diode gate structure. The first Diode drain region 309 is in contact with the first Diode channel region 303, and the first Diode drain region 309 has the first conductivity type; a first VDMOS source region 310 is formed in the first body region 302 on one side of the VDMOS gate structure.

[0144] In this embodiment, a second Diode drain region 409 is further formed in the fifth region V and in the second body region 402 on one side of the second Diode gate structure. The second Diode drain region 409 is in contact with the second Diode channel region 403, and the second Diode drain region 409 has the first conductivity type; a second VDMOS source region 410 is formed in the second body region 402 on the other side of the VDMOS gate structure.

[0145] Please refer to Figure 15 , a first body lead-out region 311 is formed in the first body region 302, and the first body lead-out region 311 is located between the first VDMOS source region 310 and the first Diode drain region 309.

[0146] In this embodiment, a second body lead-out region 411 is further formed in the second body region 402, and the second body lead-out region 411 is located between the second VDMOS source region 410 and the second Diode drain region 409.

[0147] Please refer to Figure 16 , a first conductive layer 312 is formed on the surfaces of the first Diode drain region 309, the first body lead-out region 311, the first VDMOS source region 310, and the first Diode gate structure; a second conductive layer 313 is formed on the surface of the VDMOS gate structure.

[0148] In this embodiment, a fourth conductive layer 314 is further formed on the surfaces of the second Diode drain region 309, the second body lead-out region 311, the second VDMOS source region 310, and the second Diode gate structure.

[0149] Please refer to Figure 17 , a third conductive layer 315 is formed on the second surface.

[0150] So far, the VDMOS drain region, the first VDMOS source region 410, the first body region 302, and the VDMOS gate structure form a VDMOS device. The first Diode source region 304, the first Diode channel region 303, the first Diode drain region 309, and the first Diode gate structure form a channel diode. The channel diode is connected in parallel with the VDMOS device through the first conductive layer 312. The channel diode with a lower conduction voltage is adopted to improve the reverse recovery characteristic of the VDMOS device, shorten the reverse recovery time, and improve the switching efficiency. At the same time, through the compatibility of the VDMOS device process and the channel diode process, the VDMOS device and the channel diode are integrated together, which is beneficial to improving the integration degree of the chip while improving the reverse recovery characteristic of the VDMOS.

[0151] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method. Please continue to refer to Figure 17, the semiconductor structure includes: a substrate 300 having a first conduction type and a first doping concentration, and serving as the VDMOS drain region; an epitaxial layer 301 on the surface of the substrate 300, having the same conduction type as the substrate 300 and a second doping concentration less than the first doping concentration. The epitaxial layer 301 includes adjacent first region I, second region II, and third region III arranged in a first direction (not shown in the figure) parallel to the surface of the substrate 300, and the second region II is located between the first region I and the third region III; a first body region 302 within the second region II and extending into part of the third region III, having a second conduction type different from the first conduction type; a first Diode channel region 303 within part of the third region III, having the second conduction type and in contact with the first body region 302, and the third region III outside the first body region 302 and the first Diode channel region 303 serves as the first Diode source region 304; a first Diode gate structure on the surface of part of the third region III, covering at least the surface of the first Diode channel region 303; a VDMOS gate structure on the surface of the first region I; a first Diode drain region 309 formed within the first body region 302 in the third region III and on one side of the first Diode gate structure, in contact with the first Diode channel region 303 and having the first conduction type; a first VDMOS source region 310 within the first body region 302 on one side of the VDMOS gate structure; a first body lead-out region 311 within the first body region 302, located between the first VDMOS source region 310 and the first Diode drain region 309; a first conductive layer 312 on the surfaces of the first Diode drain region 309, the first body lead-out region 311, the first VDMOS source region 310, and the first Diode gate structure; and a second conductive layer 313 on the surface of the VDMOS gate structure.

[0152] So far, the VDMOS drain region, the first VDMOS source region 410, the first body region 302, and the VDMOS gate structure constitute a VDMOS device, and the first Diode source region 304, the first Diode channel region 303, the first Diode drain region 309, and the first Diode gate structure constitute a channel diode. The channel diode is connected in parallel with the VDMOS device through the first conductive layer 312. The channel diode with a lower conduction voltage is used to improve the reverse recovery characteristic of the VDMOS device, shorten the reverse recovery time, and improve the switching efficiency. At the same time, through the compatibility of the VDMOS device process and the channel diode process, the VDMOS device and the channel diode are integrated together, which is beneficial to improving the integration of the chip while improving the reverse recovery characteristic of the VDMOS.

[0153] In this embodiment, the epitaxial layer further includes a fourth region IV and a fifth region V arranged along the first direction, and the fourth region IV is adjacent to the first region I and the fifth region V on both sides respectively.

[0154] In this embodiment, the semiconductor structure further includes: a second body region 402 located in the fourth region IV, and the second body region 402 also extends to a part of the fifth region V. The second body region 402 has the second conductivity type; a second Diode channel region 403 located in a part of the fifth region V, the second Diode channel region 403 has the second conductivity type, and the second Diode channel region 403 is in contact with the second body region 402. The fifth region V outside the second body region 402 and the second Diode channel region 403 is used as a second Diode source region 404; a second Diode gate structure located on the surface of a part of the fifth region V, and the second Diode gate structure covers at least the surface of the second Diode channel region 403; a second Diode drain region 409 located in the second body region 402 on one side of the second Diode gate structure in the fifth region V, the second Diode drain region 409 is in contact with the second Diode channel region 403, and the second Diode drain region 409 has the first conductivity type; a second VDMOS source region 410 located in the second body region 402 on the other side of the VDMOS gate structure; a second body lead-out region 411 located in the second body region 402, and the second body lead-out region 411 is located between the second VDMOS source region 410 and the second Diode drain region 409; a fourth conductive layer 314 located on the surfaces of the second Diode drain region 409, the second body lead-out region 411, the second VDMOS source region 410, and the second Diode gate structure.

[0155] In this embodiment, the second Diode gate structure includes a second Diode gate oxide layer 405 and a second Diode gate layer 406 located on the surface of the second Diode gate oxide layer 405.

[0156] The main difference between this embodiment and the previous one lies in:

[0157] In this embodiment, the VDMOS gate structure is located on the surface of the first region, which is a planar gate structure. In the previous embodiment, the VDMOS gate structure is located within the first region, which is a trench gate structure.

[0158] In this embodiment, the first body region 402 also extends to the first region I, that is, to the bottom of the VDMOS gate structure.

[0159] Here, except for the VDMOS gate structure and the relative positional relationship between the VDMOS gate structure and the first body region, for other structures, please refer to the description of the previous embodiment and will not be elaborated here.

[0160] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Including: A substrate having a first conductivity type and a first doping concentration, with the substrate serving as the VDMOS drain region; An epitaxial layer located on the surface of the substrate, having the same conductivity type as the substrate and a second doping concentration less than the first doping concentration. The epitaxial layer includes adjacent first, second, and third regions arranged in a first direction parallel to the substrate surface, with the second region located between the first and third regions; A first body region located in the second region and extending into part of the third region, having a second conductivity type different from the first conductivity type; A first Diode channel region located in part of the third region, having the second conductivity type and in contact with the first body region, with the third region outside the first body region and the first Diode channel region serving as the first Diode source region; A first Diode gate structure located on the surface of part of the third region, at least covering the surface of the first Diode channel region; A VDMOS gate structure located in or on the surface of the first region; A first Diode drain region formed in the first body region within the third region and on one side of the first Diode gate structure, in contact with the first Diode channel region and having the first conductivity type; A first VDMOS source region located in the first body region on one side of the VDMOS gate structure; A first body lead-out region located in the first body region between the first VDMOS source region and the first Diode drain region; A first conductive layer located on the surfaces of the first Diode drain region, the first body lead-out region, the first VDMOS source region, and the first Diode gate structure; A second conductive layer located on the surface of the VDMOS gate structure.

2. The semiconductor structure according to claim 1, wherein The first body region has a third doping concentration, and the first Diode channel region has a fourth doping concentration, with the fourth doping concentration less than or equal to the third doping concentration.

3. The semiconductor structure according to claim 1, characterized in that, The first Diode gate structure covers all or part of the surface of the first Diode source region.

4. The semiconductor structure according to claim 1, characterized in that, The first Diode gate structure also extends to part of the surface of the first body region, exposing another part of the surface of the first body region.

5. The semiconductor structure according to claim 1, wherein, The VDMOS gate structure is located in the first region, and the bottom of the VDMOS gate structure is deeper than the bottom edge of the first body region.

6. The semiconductor structure according to claim 1, wherein, The VDMOS gate structure includes a VDMOS gate oxide layer and a VDMOS gate layer on the surface of the VDMOS gate oxide layer; the first Diode gate structure includes a first Diode gate oxide layer and a first Diode gate layer on the surface of the first Diode gate oxide layer; the thickness of the first Diode gate oxide layer is equal to or less than the thickness of the VDMOS gate oxide layer.

7. The semiconductor structure according to claim 1, wherein, The VDMOS gate structure is located on the surface of the first region, and the first body region also extends to part of the first region.

8. The semiconductor structure according to claim 1, wherein The substrate includes opposite first and second surfaces, and the epitaxial layer is located on the first surface; further included is: a third conductive layer located on the second surface.

9. The semiconductor structure according to claim 1, wherein The epitaxial layer further includes: a fourth region and a fifth region arranged along the first direction, with the fourth region adjacent to the first region and the fifth region on both sides respectively; the semiconductor structure further includes: a second body region located in the fourth region, the second body region also extending to part of the fifth region, the second body region having the second conductivity type; a second Diode channel region located in part of the fifth region, the second Diode channel region having the second conductivity type, and the second Diode channel region being in contact with the second body region, with the fifth region outside the second body region and the second Diode channel region being the second Diode source region; a second Diode gate structure located on the surface of part of the fifth region, the second Diode gate structure at least covering the surface of the second Diode channel region; a second Diode drain region located in the second body region within the fifth region and on one side of the second Diode gate structure, the second Diode drain region being in contact with the second Diode channel region, the second Diode drain region having the first conductivity type; a second VDMOS source region located in the second body region on the other side of the VDMOS gate structure; a second body lead-out region located in the second body region, the second body lead-out region being located between the second VDMOS source region and the second Diode drain region; a fourth conductive layer located on the surfaces of the second Diode drain region, the second body lead-out region, the second VDMOS source region, and the second Diode gate structure.

10. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate having a first conductivity type and a first doping concentration, using the substrate as a VDMOS drain region; Forming an epitaxial layer on the surface of the substrate, the epitaxial layer having the same conductivity type as the substrate, the epitaxial layer having a second doping concentration, the second doping concentration being less than the first doping concentration, the epitaxial layer including adjacent first, second, and third regions arranged along a first direction, the first direction being parallel to the surface of the substrate, and the second region being located between the first region and the third region; A first body region is formed in the second region, and the first body region also extends to a part of the third region. The first body region has a second conductivity type, which is different from the first conductivity type. A first Diode channel region is formed in a part of the third region. The first Diode channel region has the second conductivity type, and the first Diode channel region is in contact with the first body region. The third region outside the first body region and the first Diode channel region is the first Diode source region. A first Diode gate structure is formed on the surface of a part of the third region, and the first Diode gate structure covers at least the surface of the first Diode channel region. A VDMOS gate structure is formed in or on the surface of the first region. A first Diode drain region is formed in the third region and in the first body region on one side of the first Diode gate structure. The first Diode drain region is in contact with the first Diode channel region, and the first Diode drain region has the first conductivity type. A first VDMOS source region is formed in the first body region on one side of the VDMOS gate structure. A first body lead-out region is formed in the first body region, and the first body lead-out region is located between the first VDMOS source region and the first Diode drain region. A first conductive layer is formed on the surfaces of the first Diode drain region, the first body lead-out region, the first VDMOS source region, and the first Diode gate structure. A second conductive layer is formed on the surface of the VDMOS gate structure.

11. The method for forming a semiconductor structure according to claim 10, wherein, The first body region has a third doping concentration, and the first Diode channel region has a fourth doping concentration, and the fourth doping concentration is less than or equal to the third doping concentration.

12. The method for forming a semiconductor structure according to claim 11, wherein, The fourth doping concentration is equal to the third doping concentration. The forming method of the first body region and the first Diode channel region includes: using a first ion implantation process to implant first doping ions into the second region and a part of the third region to form the first body region and the first Diode channel region.

13. The method for forming a semiconductor structure according to claim 11, wherein, The fourth doping concentration is less than the third doping concentration. The forming method of the first body region further includes: forming a first mask layer on the surface of the epitaxial layer, and the first mask layer exposes the surface of the second region and a part of the surface of the third region adjacent to the second region; using the first mask layer as a mask, and adopting a first ion implantation process to implant first doping ions into the epitaxial layer to form the first body region; the forming method of the first Diode channel region further includes: forming a second mask layer on the surface of the epitaxial layer, and the second mask layer exposes a part of the surface of the third region; using the second mask layer as a mask, and adopting a second ion implantation process to implant second doping ions into the epitaxial layer to form the first Diode channel region.

14. The method for forming a semiconductor structure according to claim 10, wherein The first Diode gate structure covers all or part of the surface of the first Diode source region.

15. The method for forming a semiconductor structure according to claim 10, wherein, The first Diode gate structure also extends to a part of the surface of the first body region and exposes another part of the surface of the first body region.

16. The method for forming a semiconductor structure according to claim 10, wherein, The VDMOS gate structure is formed in the first region, and the bottom of the VDMOS gate structure is deeper than the bottom edge of the first body region; The method for forming the VDMOS gate structure includes: etching the first region to form a gate groove in the first region; forming a first gate oxide material layer on the sidewall and bottom surface of the gate groove and on the surface of the epitaxial layer; Forming a first gate material layer on the surface of the first gate oxide material layer; planarizing the first gate material layer and the first gate oxide material layer until the surface of the epitaxial layer is exposed to form the VDMOS gate structure, the VDMOS gate structure including a VDMOS gate oxide layer and a VDMOS gate layer, using the first gate oxide material layer to form the VDMOS gate oxide layer and using the first gate material layer to form the VDMOS gate layer.

17. The method for forming a semiconductor structure according to claim 16, wherein, The first Diode gate structure includes a first Diode gate oxide layer and a first Diode gate layer located on the surface of the first Diode gate oxide layer; The thickness of the first Diode gate oxide layer is equal to or less than the thickness of the VDMOS gate oxide layer; The method for forming the first Diode gate structure further includes: after forming the VDMOS gate structure, the first body region, and the first Diode channel region, forming a second gate oxide material layer on the surface of the epitaxial layer; Forming a second gate material layer on the surface of the second gate oxide material layer; etching the second gate material layer and the second gate oxide material layer to form the first Diode gate layer using the second gate material layer and form the first Diode gate oxide layer using the second gate oxide material layer.

18. The method for forming a semiconductor structure according to claim 10, wherein, A VDMOS gate structure is formed on the surface of the first region, and the first body region also extends to a part of the first region; the VDMOS gate structure includes a VDMOS gate oxide layer and a VDMOS gate layer located on the surface of the VDMOS gate oxide layer; the first Diode gate structure includes a first Diode gate oxide layer and a first Diode gate layer located on the surface of the first Diode gate oxide layer.

19. The method for forming a semiconductor structure according to claim 18, wherein, The thickness of the first Diode gate oxide layer is equal to the VDMOS gate oxide layer; the first Diode gate structure and the VDMOS gate structure are formed using the same process.

20. The method for forming a semiconductor structure according to claim 18, wherein The thickness of the first Diode gate oxide layer is less than the VDMOS gate oxide layer; the first Diode gate structure and the VDMOS gate structure are formed in different processes.

21. The method for forming a semiconductor structure according to claim 10, wherein, The substrate includes opposite first and second faces, the epitaxial layer is formed on the first face; further included is: forming a third conductive layer on the second face.

22. The method for forming a semiconductor structure as claimed in claim 10, wherein The epitaxial layer further includes a fourth region and a fifth region arranged along the first direction, with the fourth region adjacent to the first region and the fifth region on both sides respectively; the method further includes: forming a second body region in the fourth region, the second body region also extending into a part of the fifth region, the second body region having the second conductivity type; forming a second Diode channel region in a part of the fifth region, the second Diode channel region having the second conductivity type, and the second Diode channel region being in contact with the second body region, using the fifth region outside the second body region and the second Diode channel region as the second Diode source region; forming a second Diode gate structure on the surface of a part of the fifth region, the second Diode gate structure at least covering the surface of the second Diode channel region; forming a second Diode drain region in the fifth region and in the second body region on one side of the second Diode gate structure, the second Diode drain region being in contact with the second Diode channel region, the second Diode drain region having the first conductivity type; forming a second VDMOS source region in the second body region on the other side of the VDMOS gate structure; forming a second body lead-out region in the second body region, the second body lead-out region being located between the second VDMOS source region and the second Diode drain region; forming a fourth conductive layer on the surfaces of the second Diode drain region, the second body lead-out region, the second VDMOS source region and the second Diode gate structure.

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