A vertical d-mosfet with enhanced breakdown voltage and method of fabrication

Abstract

The application relates to the field of MOS semiconductor technology, and discloses a vertical D-MOSFET with enhanced breakdown voltage and a preparation method, which is composed of a plurality of mutually juxtaposed MOS cells, a single MOS cell comprising a drain, a source, a gate and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P well layer and a P+ layer, and the outer side of the P+ layer in a single MOS cell is further formed with a doped P+ layer and a heavily doped P+ layer in sequence through ion implantation; the doping concentration of the P+ layer, the doped P+ layer and the heavily doped P+ layer gradually increases in stages, and the cross-sectional width gradually expands in sequence. The P+ layer and the heavily doped P+ layer with gradually increasing doping concentration are formed in the outer P+ layer in sequence, and the design of gradually expanding cross-sectional width is combined, so that the slow variation optimization of the electric field distribution near the PN junction is realized, the gradient doping structure effectively reduces the high electric field concentration phenomenon, and the breakdown voltage of the device is significantly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of MOS semiconductor technology, and in particular to a vertical D-MOSFET with enhanced breakdown voltage and a preparation method. BACKGROUND

[0002] As a core structure of power semiconductor devices, vertical D-MOSFET (vertical double-diffused metal-oxide semiconductor field effect transistor) is widely used in high-power scenarios such as new energy, electric vehicles, and industrial power supply due to its advantages of high withstand voltage, low on-resistance, and high frequency performance. The technical core lies in realizing self-aligned short channel design through double diffusion process and optimizing electric field distribution to improve withstand voltage.

[0003] However, the traditional vertical D-MOSFET still has significant problems: first, the electric field concentration near the PN junction easily leads to local breakdown, limiting the further improvement of breakdown voltage; second, the uneven electric field distribution at the edge of the drift region may cause leakage current or parasitic conduction effect, affecting the reliability of the device; third, the trade-off between on-resistance and withstand voltage performance is difficult to break through, restricting the performance optimization in high-power scenarios.

[0004] A high-power planar gate D-MOSFET structure (CN207021266U) is disclosed in the existing patent. The planar gate D-MOSFET is an N-MOS structure or a P-MOS structure, including a P-well or an N-well, a gate, an N+ source region or a P+ source region, a source, an insulating layer, an N-drift region or a P-drift region, and a drain. The P-well structure corner area of the N-MOS structure is a ladder-shaped structure composed of sub-steps; the N-well structure corner area of the P-MOS structure is a ladder-shaped structure composed of sub-steps. In the disclosed technology of this patent, although attempts are made to alleviate the above problems through single doping optimization or simple structure improvement, often one-sidedness is lost, and the coordinated improvement of multiple performance parameters cannot be achieved. For example, the conventional gradient doping design has limited effect on the gradual change of electric field distribution, and the traditional conductive channel structure cannot meet the needs of low-resistance path and electric field dispersion. SUMMARY

[0005] The present application provides a vertical D-MOSFET with enhanced breakdown voltage and a preparation method to solve the existing technical problems, solving the problems in the above background technology.

[0006] To solve the above technical problems, according to one aspect of the present application, more specifically, a vertical D-MOSFET with enhanced breakdown voltage, comprising a plurality of mutually juxtaposed MOS cells, each of the MOS cells comprising a drain, a source, a gate and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprising an N substrate layer, an N drift layer, an N well layer, a P well layer and a P+ layer, and the outside of the P+ layer in each of the MOS cells further comprises a doped P+ layer and a heavily doped P+ layer formed by ion implantation.

[0007] The doping concentration of the P+ layer, the doped P+ layer and the heavily doped P+ layer gradually increases, and the cross-sectional width gradually expands.

[0008] Further, the left and right sides of the N drift layer in each of the MOS cells are provided with side-through N layers, and the cross-sectional profile of the side-through N layer is a vertically placed right-angled trapezoidal shape.

[0009] The top right angle of the side-through N layer directly contacts the P+ layer, the doped P+ layer and the heavily doped P+ layer, and the bottom tip of the side-through N layer extends to the surface of the N substrate layer.

[0010] Further, an upper N+ layer is formed above the N drift layer by ion implantation, the cross-sectional profile of the upper N+ layer is a "U" shape, and the two upper ends of the N+ layer directly contact the P well layer.

[0011] Further, a lower N- layer is formed in the middle region of the bottom of the N drift layer by ion implantation, the lower N- layer directly contacts the N substrate layer, and the cross-sectional profile of the lower N- layer is an isosceles trapezoidal shape.

[0012] Further, an intermediate N+ layer is formed in the middle region of the N drift layer in each of the MOS cells by ion implantation, and an intermediate heavily doped N+ layer is formed inside the intermediate N+ layer by ion implantation.

[0013] Further, side individual N- layers are formed on the left and right sides of the N drift layer in each of the MOS cells by ion implantation, the cross-sectional profile of the side individual N- layer is a rectangular shape, and the top of the side individual N- layer directly contacts the P+ layer, the doped P+ layer and the heavily doped P+ layer.

[0014] A preparation method of a vertical D-MOSFET with enhanced breakdown voltage, comprising:

[0015] S1, sequentially growing an N drift layer and an N well layer on the surface of an N body substrate layer;

[0016] S2, forming a P well layer in the N drift layer by ion implantation, and then sequentially forming a P+ layer, a doped P+ layer and a heavily doped P+ layer by a plurality of masking and ion implantation processes.

[0017] S3, forming a right-angled trapezoidal groove on the left and right sides of the N drift layer by photoetching and etching, and then performing ion implantation to form a side-through N-layer;

[0018] S4, forming a "U" shaped upper N+ layer above the N drift layer by high-energy ion implantation, and the two ends of the "U" shaped upper N+ layer are in contact with the P well layer;

[0019] S5, implanting an isosceles trapezoidal lower N-layer in the middle region of the bottom of the N drift layer to make it in direct contact with the N substrate layer;

[0020] S6, forming an intermediate N+ layer and an intermediate heavily doped N+ layer in the middle region of the N drift layer by twice ion implantation, the intermediate heavily doped N+ layer is located inside the intermediate N+ layer, and the doping concentration of the intermediate heavily doped N+ layer is higher;

[0021] S7, forming a source electrode in the P+ layer region, a drain electrode on the back of the N substrate layer, and depositing polysilicon in the gate region by photoetching and metal deposition process.

[0022] Further, in the step S2, the dose and energy of ion implantation are sequentially increased, so that the doping concentration of the P+ layer, the doped P+ layer and the heavily doped P+ layer gradually increases, and the cross-sectional width gradually expands.

[0023] Further, the doping amount of the P+ layer is not higher than , and the doping amount of the heavily doped P+ layer is not less than .

[0024] The present application provides a vertical D-MOSFET with enhanced breakdown voltage and a preparation method.

[0025] 1. The present application forms P+ layer and heavily doped P+ layer with gradually increasing doping concentration in the outer P+ layer, and combines the design of gradually expanding cross-sectional width, which realizes the optimization of the gradual change of the electric field distribution near the PN junction, and effectively reduces the high electric field concentration phenomenon, significantly improves the breakdown voltage of the device.

[0026] 2. The side-through N-layer in the present application adopts a vertical right-angled trapezoidal design, the top is in contact with the P+ layer, the bottom extends to the N substrate layer, and the trapezoidal structure forms a continuous conductive channel on both sides of the drift region, which reduces the resistance of the current path; at the same time, its geometric shape expands the electric field distribution area, disperses the electric field intensity of the edge of the drift region, avoids the risk of local breakdown, and significantly improves the overall voltage resistance and reliability of the device.

[0027] 3、U shape design of the upper N+ layer in the application makes its two ends directly contact with the P well layer, and the U type structure promotes the uniform distribution of the on-state current near the source, effectively reduces the current crowding effect, and reduces the local heat loss and on-state resistance.

[0028] 4、The lower N- layer in the application adopts isosceles trapezoidal design, and the bottom directly contacts with the N substrate layer. The trapezoidal structure expands the interface contact area, optimizes the electric field distribution between the drift region and the substrate, and prevents premature breakdown caused by concentrated interface electric field.

[0029] 5、The middle N+ layer in the application is embedded with a higher doped middle heavily doped N+ layer, forming a nested structure. The internal high-doped layer significantly reduces the resistance in the on-state by enhancing the carrier injection efficiency, and the outer low-doped layer maintains the high voltage withstand characteristic of the drift region. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a schematic diagram of the embodiment one in the application;

[0031] Figure 2 is a schematic diagram of the embodiment two in the application;

[0032] Figure 3 is a schematic diagram of the embodiment three in the application;

[0033] Figure 4 is a schematic diagram of the embodiment four in the application;

[0034] Figure 5 is a schematic diagram of the embodiment five in the application;

[0035] Figure 6 is a schematic diagram of the embodiment six in the application.

[0036] In the figure: 1, drain; 2, source; 3, gate; 4, N substrate layer; 5, N drift layer; 6, N well layer; 7, P well layer; 8, P+ layer; 9, doped P+ layer; 10, heavily doped P+ layer; 11, side through N- layer; 12, upper N+ layer; 13, lower N- layer; 14, middle heavily doped N+ layer; 15, middle N+ layer; 16, side separate N- layer. DETAILED DESCRIPTION

[0037] In order to make the technical scheme of the application clearer, the application will be further described in detail below in combination with the drawings and specific embodiments.

[0038] Figures 1-6 As shown, according to one aspect of the application, a preparation method of a vertical D-MOSFET with enhanced breakdown voltage is provided, which has:

[0039] Step one, forming the basic epitaxial structure of the device by growing N drift layer 5 and N well layer 6 on the surface of N body substrate layer 4 in sequence; forming the basic epitaxial structure of the device by growing N drift layer 5 and N well layer 6 on the surface of N body substrate layer 4 in sequence.

[0040] N drift layer 5 is a high-voltage region, and its low-doped characteristic can support high electric field intensity; N well layer 6 provides a doped basis for the formation of subsequent P well layer. This step ensures the thickness and doping uniformity of the drift layer by precisely controlling the epitaxial growth process, laying the foundation for subsequent optimization of electric field distribution and voltage resistance performance.

[0041] Step two, forming P well layer 7 in N drift layer 5 by ion implantation, and then forming P+ layer 8, doped P+ layer 9 and heavily doped P+ layer 10 in sequence by multiple masking and ion implantation processes; increasing the dose and energy of ion implantation in sequence to gradually increase the doping concentration of P+ layer 8, doped P+ layer 9 and heavily doped P+ layer 10, and the cross-sectional width is expanded in sequence. The doping amount of P+ layer 8 is not higher than , and the doping amount of heavily doped P+ layer 10 is not less than .

[0042] Forming P well layer 7 in N drift layer 5, and then forming P+ layer 8, doped P+ layer 9 and heavily doped P+ layer 10 in sequence by multiple masking and ion implantation. By gradually increasing the ion implantation dose and energy, the doping concentration and cross-sectional width are gradually increased. This gradient doping structure effectively changes the electric field distribution near the PN junction, reduces the electric field concentration, and significantly improves the breakdown voltage; at the same time, the expanded cross-sectional width enhances the ability of carrier lateral diffusion, and reduces the on-resistance.

[0043] Step three, forming a right trapezoidal groove on the left and right sides of N drift layer 5 by lithography and etching, and then forming a side-through N- layer 11 by ion implantation. Forming a right trapezoidal groove on the left and right sides of N drift layer 5 by lithography and etching, and then implanting to form a side-through N- layer 11.

[0044] The right trapezoidal design makes the top contact with the P+ layer and the bottom extend to the N substrate layer 4, forming a continuous conductive channel. This structure expands the electric field distribution area, disperses the electric field intensity at the edge of the drift region, avoids local breakdown, reduces the resistance of the current path, and improves the overall voltage resistance capability.

[0045] Step four, forming a "U" shaped upper N+ layer 12 above N drift layer 5 by high energy ion implantation, and the two ends of the "U" shaped upper N+ layer 12 contact with P well layer 7; implanting to form a "U" shaped upper N+ layer 12 above N drift layer (5), and the two ends of the "U" shaped upper N+ layer 12 contact with P well layer 7. The U-shaped structure makes the on-current distribute uniformly laterally, reduces the current crowding effect near the source, reduces local heat loss; at the same time, it enhances the control ability of the gate to the channel, improves the switching speed and stability, realizes the balance of low on-resistance and high switching efficiency.

[0046] Step 5: Implanting is performed at the bottom center of the N-drift layer 5 to form an isosceles trapezoidal lower N-layer 13, placing it in direct contact with the N substrate layer 4. The isosceles trapezoidal design expands the bottom contact area, optimizing the electric field distribution at the drift region-substrate interface and preventing premature breakdown caused by interfacial electric field concentration. The symmetrical structure ensures vertical electric field uniformity, further enhancing the reliability of the breakdown voltage.

[0047] Step 6: Form an intermediate N+ layer 15 and an intermediate heavily doped N+ layer 14 in the middle region of the N drift layer 5 by two ion implantations. The latter is located inside the former and has a higher doping concentration. Form an intermediate N+ layer 15 and an intermediate heavily doped N+ layer 14 in the middle region of the N drift layer 5 by two ion implantations.

[0048] The nested structure enhances carrier injection efficiency and reduces on-resistance through the internal high-doping layer (14); the external low-doping layer (15) maintains the high withstand voltage characteristics of the drift region. The synergistic effect of the two achieves an optimized balance between withstand voltage performance and on-resistance.

[0049] Step 7: Form the source 2 in the P+ layer 8 and the drain 1 on the back of the N substrate layer 4 through photolithography and metal deposition processes, and deposit polysilicon in the gate region 3. The source 2, drain 1, and gate 3 are formed through photolithography and metal deposition processes.

[0050] Precise metallization ensures low contact resistance between the electrode and semiconductor layer, improving device conduction efficiency; polysilicon gate deposition optimizes gate control capabilities and enhances device switching characteristics. This step completes device functionality through structural integration, ultimately achieving a high-voltage, low-loss vertical D-MOSFET.

[0051] Example 1

[0052] like Figure 1 As shown, according to one aspect of the present invention, a vertical D-MOSFET with enhanced breakdown voltage is provided, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain 1, a source 2, a gate 3 and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises an N substrate layer 4, an N drift layer 5, an N well layer 6, a P well layer 7 and a P+ layer 8, and a doped P+ layer 9 and a heavily doped P+ layer 10 are sequentially formed on the outer side of the P+ layer 8 in the single MOS cell by ion implantation (wherein, the P+ layer 8, the doped P+ layer 9 and the heavily doped P+ layer 10 in the single MOS cell are arranged from inside to outside); the doping concentrations of the P+ layer 8, the doped P+ layer 9 and the heavily doped P+ layer 10 are gradually increased, and the cross-sectional widths are gradually expanded.

[0053] A P+ layer 9 and a heavily doped P+ layer 10 are formed on the outside of the P+ layer 8, each with a gradually increasing doping concentration, and the cross-sectional width gradually increases. This gradient doping structure effectively optimizes the electric field distribution near the PN junction by forming a slowly varying doping concentration distribution, reducing high electric field concentration and significantly improving the device's breakdown voltage. At the same time, the gradually increasing cross-sectional width enhances the lateral diffusion capability of carriers, further reducing on-resistance and achieving a coordinated optimization of high withstand voltage and low loss.

[0054] Example 2

[0055] like Figure 2 As shown, side-penetrating N-layers 11 are provided on both the left and right sides of the N-drift layer 5 in a single MOS cell. The cross-sectional profile of the side-penetrating N-layer 11 is in the shape of a vertically placed right-angled trapezoid. The top right-angled side of the side-penetrating N-layer 11 directly contacts the P+ layer 8, the doped P+ layer 9, and the heavily doped P+ layer 10, and the bottom tip of the side-penetrating N-layer 11 extends to the surface of the N substrate layer 4. The side-penetrating N-layer 11 is designed as a vertical right-angled trapezoid, with its top right-angled side contacting the P+ layer and its bottom tip extending to the N substrate layer 4.

[0056] The trapezoidal structure forms a continuous conductive channel on both sides of the drift region, reducing the resistance of the current path. At the same time, the right-angled trapezoidal geometry expands the electric field distribution area, dispersing the electric field strength at the edge of the drift region, avoiding the risk of localized breakdown and significantly improving the overall voltage withstand capability of the device.

[0057] Example 3

[0058] like Figure 3 As shown, an upper N+ layer 12 is formed above the N drift layer 5 by ion implantation. The cross-sectional profile of the upper N+ layer 12 is in a “U” shape, and both upper ends of the N+ layer 12 are in direct contact with the P well layer 7 .

[0059] The upper N+ layer 12 is U-shaped, with its ends in direct contact with the P-well layer 7. This U-shaped structure evenly distributes current laterally during conduction, reducing current crowding near the source, thereby lowering local heat loss and on-resistance. Furthermore, this structure enhances the gate's control over the channel, improving the switching speed and stability of the device.

[0060] Example 4

[0061] like Figure 4 As shown, a lower N-layer 13 is formed in the bottom middle area of ​​the N drift layer 5 by ion implantation. The lower N-layer 13 is in direct contact with the N substrate layer 4 , and the cross-sectional profile of the lower N-layer 13 is in an isosceles trapezoidal shape.

[0062] The lower N-layer 13 is an isosceles trapezoid, directly contacting the N substrate layer 4. This trapezoidal design optimizes the electric field distribution at the drift region-substrate interface by expanding the bottom contact area, preventing premature breakdown caused by electric field concentration at the interface. Furthermore, the symmetry of the isosceles trapezoid ensures vertical uniformity of the electric field, further improving the device's breakdown voltage reliability.

[0063] Example 5

[0064] like Figure 5 As shown, an intermediate N+ layer 15 is formed in the middle region of the N drift layer 5 in a single MOS cell by ion implantation, and an intermediate heavily doped N+ layer 14 is formed inside the intermediate N+ layer 15 by ion implantation.

[0065] A more highly doped intermediate N+ layer 14 is embedded within the intermediate N+ layer 15. This nested structure enhances carrier injection efficiency through localized high-doping regions, reducing on-state resistance. The outer intermediate N+ layer maintains the low-doping characteristics of the drift region, ensuring a high breakdown voltage. The combination of these two achieves an optimized balance between on-resistance and withstand voltage performance.

[0066] Example 6

[0067] like Figure 6 As shown, ion implantation forms separate N-layers 16 on the left and right sides of the N-drift layer 5 in a single MOS cell. The cross-sectional profile of the separate N-layer 16 is rectangular, and the top of the separate N-layer 16 is in direct contact with the P+ layer 8, the doped P+ layer 9, and the heavily doped P+ layer 10. The separate N-layer 16 is rectangular, with its top in direct contact with the P+ layer 8 and other layers. This rectangular structure forms stable low-doping regions on both sides of the drift region, effectively suppressing parasitic turn-on effects when the drain voltage increases, reducing leakage current. Furthermore, its geometric symmetry ensures uniform electric field distribution, further enhancing the device's withstand voltage and reliability.

[0068] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A vertical D-MOSFET with enhanced breakdown voltage, comprising a plurality of mutually parallel MOS cells, wherein each MOS cell comprises a drain (1), a source (2), a gate (3) and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises an N substrate layer (4), an N drift layer (5), an N well layer (6), a P well layer (7) and a P+ layer (8), characterized in that: A doped P+ layer (9) and a heavily doped P+ layer (10) are sequentially formed on the outer side of the P+ layer (8) in a single MOS cell by ion implantation; The doping concentrations of the P+ layer (8), the doped P+ layer (9) and the heavily doped P+ layer (10) increase step by step, and the cross-sectional widths expand sequentially; The doped P+ layer (9) and the heavily doped P+ layer (10) are located outside the P+ layer (8) in a horizontal direction.

2. The vertical D-MOSFET with enhanced breakdown voltage according to claim 1, wherein: A side-penetrating N-layer (11) is provided on both the left and right sides of the N-drift layer (5) in a single MOS cell, and the cross-sectional profile of the side-penetrating N-layer (11) is in the shape of a vertically placed right-angled trapezoid; The top right-angled edge of the side-penetrating N-layer (11) is in direct contact with the P+ layer (8), the doped P+ layer (9) and the heavily doped P+ layer (10), and the bottom tip of the side-penetrating N-layer (11) extends to the surface of the N substrate layer (4).

3. The vertical D-MOSFET with enhanced breakdown voltage according to claim 2, wherein: An upper N+ layer (12) is formed above the N drift layer (5) by ion implantation. The cross-sectional profile of the upper N+ layer (12) is in a "U" shape, and both upper ends of the N+ layer (12) are in direct contact with the P well layer (7).

4. The vertical D-MOSFET with enhanced breakdown voltage according to claim 3, wherein: A lower N-layer (13) is formed in the bottom middle region of the N drift layer (5) by ion implantation. The lower N-layer (13) is in direct contact with the N substrate layer (4), and the cross-sectional profile of the lower N-layer (13) is in an isosceles trapezoidal shape.

5. The vertical D-MOSFET with enhanced breakdown voltage according to claim 1, wherein: An intermediate N+ layer (15) is formed in the middle region of the N drift layer (5) in a single MOS cell by ion implantation, and an intermediate heavily doped N+ layer (14) is formed inside the intermediate N+ layer (15) by ion implantation.

6. The vertical D-MOSFET with enhanced breakdown voltage according to claim 1, wherein: A side separate N-layer (16) is formed on the left and right sides of the N drift layer (5) in a single MOS cell by ion implantation. The cross-sectional profile of the side separate N-layer (16) is rectangular, and the top of the side separate N-layer (16) is in direct contact with the P+ layer (8), the doped P+ layer (9) and the heavily doped P+ layer (10).

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