Semiconductor device and manufacturing method of electrode
By employing a polishing stop layer with high selectivity and eddy current monitoring, the CMP process for tungsten electrodes is optimized, addressing over- and under-etching issues and enhancing production yield and efficiency.
Patent Information
- Application Number
- CN202510358873.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-25
- Publication Date
- 2025-07-15
AI Technical Summary
In the prior art, in the process of making tungsten electrodes of metal gate MOS devices, chemical mechanical grinding process is difficult to accurately control, which can easily lead to insufficient or excessive grinding, affecting the production efficiency and yield of tungsten electrodes.
The grinding stop layer and shielding layer are formed on the interlayer dielectric layer, contact holes are formed by patterning, and chemical mechanical grinding is controlled using eddy current signals to selectively remove the electrode material layer to ensure that the grinding stops in appropriate positions.
The production yield and efficiency of tungsten electrodes are improved, the exposure of tungsten seams is avoided, the control capability of the process is improved, and the rework rate is reduced.
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Figure CN120321996A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of semiconductor integrated circuit manufacturing, and relates to a manufacturing method of a semiconductor device and an electrode. Background Art
[0002] Currently, in the process of manufacturing a tungsten electrode of a metal gate MOS device, after forming a tungsten layer that fills the contact hole and covers the upper surface of the wafer, it is necessary to use a chemical mechanical polishing (CMP) process to remove the tungsten layer covering the upper surface of the wafer. As Figure 1 shown, it is a schematic cross-sectional structure diagram of a wafer after forming a tungsten layer, including a wafer 01, an interlayer dielectric layer 011, an interconnect metal layer 012, source / drain doping regions 0121, a metal gate layer 0122, a contact hole 013, a tungsten seam 014, a tungsten electrode 02, a diffusion barrier layer 021, and a tungsten layer 022. When removing the tungsten layer and the diffusion barrier layer on the upper surface of the wafer, usually a fixed polishing duration is set for polishing. This method has poor control ability, is prone to under-polishing or over-polishing, and then causes the risk of rework or exposure of the tungsten seam, affecting the manufacturing efficiency and yield of the tungsten electrode. As Figure 2 shown, it is Figure 1 a statistical result graph of the height of the tungsten electrode after polishing and removing the tungsten layer in the structure of is the thickness of a normal interlayer dielectric layer. When the interlayer dielectric layer exceeds it means under-polishing and rework are required. When the interlayer dielectric layer is lower than it means over-polishing, which will cause the tungsten seam to be exposed.
[0003] Therefore, there is an urgent need to find a manufacturing method of an electrode that can improve the CMP control ability of the metal electrode. Summary of the Invention
[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a manufacturing method of a semiconductor device and an electrode, which is used to solve the problems of easy under-polishing and rework or over-polishing and exposure of the tungsten seam in the CMP process of the tungsten electrode of the semiconductor device in the prior art.
[0005] To achieve the above purpose and other related purposes, the present invention provides a manufacturing method of an electrode, including the following steps:
[0006] Provide a semiconductor structure with an interlayer dielectric layer formed on an upper surface layer, and at least one electrical contact region is provided below the interlayer dielectric layer;
[0007] Form a polishing stop layer and a masking layer covering the upper surface of the interlayer dielectric layer in sequence, and pattern the masking layer;
[0008] Form contact holes penetrating through the grinding stop layer and the interlayer dielectric layer based on the patterned masking layer, remove the masking layer, and the bottom surface of the contact holes exposes the electrical contact regions;
[0009] Form an electrode material layer filling the contact holes and covering the upper surface of the grinding stop layer, and use a chemical mechanical polishing process to remove the electrode material layer directly above the interlayer dielectric layer to obtain metal electrodes filling the contact holes. During the polishing process, control the end of polishing based on eddy current signals and the selectivity of the polishing liquid for the electrode material layer and the grinding stop layer is different.
[0010] Optionally, at least one gate structure is included in the semiconductor structure, the interlayer dielectric layer covers the exposed surface of the gate structure, and at least one of the electrical contact regions is located on the upper surface of the gate structure.
[0011] Optionally, the gate structure includes a gate dielectric layer and a metal gate layer, and the electrical contact region is located on the upper surface of the metal gate layer.
[0012] Optionally, the material of the grinding stop layer includes silicon nitride.
[0013] Optionally, the thickness range of the grinding stop layer is
[0014] Optionally, the masking layer includes a mask layer, an anti-reflection layer, a capping layer, and a photoresist layer.
[0015] Optionally, the electrode material layer includes a buffer conductive layer and a metal conductive layer.
[0016] Optionally, the material of the metal conductive layer includes tungsten.
[0017] Optionally, the selectivity range of the polishing liquid for the electrode material layer and the grinding stop layer is 5:1 to 10:1.
[0018] The present invention also provides a semiconductor device, and at least one metal electrode of the semiconductor device is fabricated by using the method for fabricating the electrodes described above.
[0019] As described above, in the method for manufacturing a semiconductor device and an electrode according to the present invention, a polishing stop layer is formed between the interlayer dielectric layer and the masking layer during the manufacturing process of the electrode of the semiconductor device. A polishing liquid with a high polishing selectivity between the electrode material layer and the polishing stop layer is selected to remove the electrode material layer. During the polishing process, the polishing is stopped based on the eddy current signal, so that only a small thickness of the polishing stop layer is lost during the process of detecting the polishing stop signal and stopping the polishing. This avoids the exposure of the gap in the middle of the metal electrode caused by over-polishing, which affects the reliability of the device. At the same time, it avoids the problem of rework caused by insufficient polishing, improves the control ability of the process of polishing and removing the electrode material layer, and increases the yield and efficiency of manufacturing the metal electrode. In addition, since the thickness of the polishing stop layer is relatively thin, it has no influence on the manufacturing process of the metal electrode and has high industrial utilization value. Description of the Drawings
[0020] Figure 1 It shows a schematic cross-sectional structure diagram of a wafer after forming a tungsten layer.
[0021] Figure 2 It shows Figure 1 The statistical result diagram after polishing and removing the tungsten layer in the structure shown in
[0022] Figure 3 It shows a process flow diagram of the method for manufacturing an electrode according to the present invention.
[0023] Figure 4 It shows a schematic cross-sectional structure diagram of a semiconductor structure of the method for manufacturing an electrode according to the present invention.
[0024] Figure 5 It shows a schematic cross-sectional structure diagram after forming a polishing stop layer in the method for manufacturing an electrode according to the present invention.
[0025] Figure 6 It shows a schematic cross-sectional structure diagram after forming a masking layer in the method for manufacturing an electrode according to the present invention.
[0026] Figure 7 It shows a schematic cross-sectional structure diagram after forming a contact hole in the method for manufacturing an electrode according to the present invention.
[0027] Figure 8 It shows a schematic cross-sectional structure diagram after forming an electrode material layer in the method for manufacturing an electrode according to the present invention.
[0028] Figure 9 It shows a schematic cross-sectional structure diagram after removing the electrode material layer directly above the interlayer dielectric layer in the method for manufacturing an electrode according to the present invention.
[0029] Figure 10 It shows Figure 9 The statistical result diagram of the electrode height of the structure shown in
[0030] Description of the Reference Numerals in the Drawings
[0031] 01 Wafer
[0032] 011 Interlayer Dielectric Layer
[0033] 012 Interconnect Metal Layer
[0034] 0121 Source / Drain Doped Region
[0035] 0122 Metal Gate Layer
[0036] 013 Contact Hole
[0037] 014 Tungsten Plug
[0038] 02 Tungsten Electrode
[0039] 021 Diffusion Barrier Layer
[0040] 022 Tungsten Layer
[0041] 1 Semiconductor Structure
[0042] 11 Interlayer Dielectric Layer
[0043] 12 Interconnect Metal Layer
[0044] 121 Source / Drain Doped Region
[0045] 122 Metal Gate
[0046] 13 Chemical-Mechanical Planarization Stop Layer
[0047] 14 Masking Layer
[0048] 141 Mask Layer
[0049] 142 Anti-Reflection Layer
[0050] 143 Capping Layer
[0051] 144 Photoresist Layer
[0052] 15 Contact Hole
[0053] 16 Electrode Plug
[0054] 2 Electrode Material Layer
[0055] 21 Buffer Conductive Layer
[0056] 22 Metal Conductive Layer
[0057] 3 Metal Electrode Detailed Implementation Manner
[0058] The embodiments of the present invention will be described below through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0059] Please refer to Figures 3 to 10 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0060] Embodiment 1
[0061] This embodiment provides a method for fabricating an electrode. As Figure 3 shown, it is a process flow diagram of the method for fabricating the electrode, including the following steps:
[0062] S1: Provide a semiconductor structure with an interlayer dielectric layer formed on its upper surface, and at least one electrical contact region is provided below the interlayer dielectric layer;
[0063] S2: Sequentially form a polishing stop layer and a masking layer covering the upper surface of the interlayer dielectric layer, and pattern the masking layer;
[0064] S3: Form a contact hole penetrating through the polishing stop layer and the interlayer dielectric layer based on the patterned masking layer, remove the masking layer, and the bottom surface of the contact hole exposes the electrical contact region;
[0065] S4: Form an electrode material layer filling the contact hole and covering the upper surface of the polishing stop layer, and use a chemical mechanical polishing process to remove the electrode material layer directly above the interlayer dielectric layer to obtain a metal electrode filling the contact hole. During the polishing process, the end of the polishing is controlled based on the eddy current signal, and the selectivity of the polishing liquid for the electrode material layer and the polishing stop layer is different.
[0066] Please refer to Figures 4 to 7 , perform step S1, step S2, and step S3: Provide a semiconductor structure 1 with an interlayer dielectric layer 11 formed on its upper surface. At least one electrical contact region is provided below the interlayer dielectric layer 11; Sequentially form a polishing stop layer 13 and a masking layer 14 covering the upper surface of the interlayer dielectric layer 11, and pattern the masking layer 14; Form a contact hole 15 penetrating through the polishing stop layer 13 and the interlayer dielectric layer 11 based on the patterned masking layer 14, remove the masking layer 14, and the bottom surface of the contact hole 15 exposes the electrical contact region.
[0067] Specifically, generally, the semiconductor structure 1 is a structure for fabricating device metal electrodes after forming the interlayer dielectric layer 11. The type of semiconductor device to be fabricated included therein can be selected according to actual circumstances; the size, shape, thickness, and specific structure of the semiconductor structure 1 can be selected according to actual circumstances. Preferably, the semiconductor structure 1 is a wafer structure of the metal electrode of the metal-gate MOS to be fabricated. Subsequently, the wafer structure of the metal electrode of the metal-gate MOS to be fabricated will be taken as an example for illustration, as Figure 4 shown.
[0068] Specifically, the interlayer dielectric layer 11 is generally used for insulation between the metal electrodes of the semiconductor devices in the semiconductor structure 1. Under the condition of ensuring device performance, the thickness of the interlayer dielectric layer 11 can be selected according to actual circumstances.
[0069] Specifically, the material of the interlayer dielectric layer 11 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.
[0070] Specifically, the electrical contact region is generally a region for connecting metal electrodes or for interconnecting and leading out in the semiconductor device. Under the condition of ensuring the performance of the semiconductor device, the size, shape, and structure of the electrical contact region can be selected according to actual circumstances.
[0071] It should be noted that generally, the electrical contact region is located on the surfaces of the interconnecting metal layer 12, the source / drain doping regions 121 in the semiconductor device, and the metal gate 122 in the semiconductor device.
[0072] As an example, the semiconductor structure 1 includes at least one gate structure. The interlayer dielectric layer 11 covers the exposed surface of the gate structure. At least one electrical contact region is located on the upper surface of the gate structure, that is, the device is a MOS device or an IGBT device having a gate structure, and the electrical contact region is located in the region of the gate structure to be electrically connected to the gate electrode.
[0073] As an example, the gate structure includes a gate dielectric layer and a metal gate layer. The electrical contact region is located on the upper surface of the metal gate layer, that is, the gate structure in the semiconductor structure is a metal gate. In this embodiment, the semiconductor structure 1 is a metal-gate MOS device for fabricating a metal electrode.
[0074] Specifically, when the gate structure is a metal gate, generally, the gate dielectric layer is a high-k dielectric film layer. For example, it can be a high-k dielectric film layer such as tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, aluminum oxide, hafnium silicate; the material of the metal gate layer includes titanium nitride, tantalum nitride, tantalum, titanium, gold, silver, copper, aluminum, nickel, cobalt, chromium, tungsten, or other suitable conductive materials.
[0075] It should be noted that when the gate structure is a metal gate, the metal gate layer is usually a composite film layer composed of multiple conductive film layers to prevent the metal in the metal gate layer from diffusing into other regions of the semiconductor structure, which may affect the performance and reliability of the device.
[0076] Specifically, the gate structure can also be a polysilicon gate, that is, the gate structure includes a gate dielectric layer and a polysilicon gate layer stacked in sequence. At this time, the dielectric constant of the gate dielectric layer is usually low. For example, it can be a low-k dielectric film layer such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.
[0077] Specifically, under the condition of ensuring the device performance, the thickness of the gate dielectric layer can be selected according to the actual situation.
[0078] As an example, as Figure 5 shown, it is a schematic cross-sectional structure diagram after forming the polishing stop layer 13. The material of the polishing stop layer 13 includes silicon nitride or other suitable materials.
[0079] Specifically, the method for forming the polishing stop layer 13 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.
[0080] As an example, the thickness range of the polishing stop layer 13 is For example, it can be
[0081] Specifically, by making the thickness of the polishing stop layer 13 within to avoid the thickness of the polishing stop layer 13 affecting the process difficulty of the subsequent formed contact holes.
[0082] Specifically, the masking layer 14 is usually used to form the pattern for making subsequent contact holes and at the same time serves as a masking film layer to protect the non-etching area during the process of making contact holes.
[0083] It should be noted that generally, the masking layer 14 needs to have a large etching selectivity ratio with the polishing stop layer 13 to avoid damaging the polishing stop layer 13 during the subsequent process of removing the masking layer 14 by etching, which may affect the subsequent polishing process.
[0084] As an example, as Figure 6As shown, it is a schematic cross-sectional structure diagram after forming the shielding layer 14. The shielding layer 14 includes a mask layer 141, an anti-reflection layer 142, a capping layer 143, and a photoresist layer 144 or other suitable film layers. Preferably, a stacked structure composed of the mask layer 141, the anti-reflection layer 142, the capping layer 143, and the photoresist layer 144 is used as the shielding layer 14. In the stacked structure, generally, the mask layer 141 is used to transfer the pattern in the photoresist layer 144, and a material with a relatively high etching selectivity (i.e., a high etching selectivity in the longitudinal and transverse directions) is usually selected as the mask layer 141, such as amorphous carbon; the anti-reflection layer 142 is used to reduce the influence of light reflection generated during the exposure of the photoresist layer 144, and improve the accuracy and quality of the pattern formed by lithography. Its specific material can be selected according to the actual situation; the capping layer 143 facilitates the rework of the subsequent photoresist layer 144; the photoresist layer 144 generally forms a pattern for making contact holes through a reaction with the light passing through the photomask and then through a developing process.
[0085] Specifically, on the premise of ensuring the quality of the subsequent formed contact holes, the thickness of the shielding layer 14 can be selected according to the actual situation; the thickness and material of each film layer in the shielding layer 14 can be selected according to the actual situation.
[0086] Specifically, as Figure 7 shown, it is a schematic cross-sectional structure diagram after forming the contact hole 15. The method for forming the contact hole 15 based on the patterned shielding layer 14 includes dry etching, wet etching, or other suitable methods. Preferably, the dry etching process is used to form the contact hole 15, so as to obtain a contact hole 15 with a better hole shape and a relatively high aspect ratio.
[0087] It should be noted that usually, in order to ensure the performance of the semiconductor device, the thickness of the interlayer dielectric layer 11 is relatively thick, and the aspect ratio of the formed contact hole 15 is relatively high.
[0088] Specifically, the method for removing the shielding layer 14 includes ashing, dry etching, wet etching, or other suitable methods.
[0089] Please refer to Figures 8 to 10 , perform step S4: form an electrode material layer 2 that fills the contact hole 15 and covers the upper surface of the polishing stop layer 13, and use a chemical mechanical polishing process to remove the electrode material layer 2 directly above the interlayer dielectric layer 11 to obtain a metal electrode 3 that fills the contact hole 15. During the polishing process, the end of the polishing is controlled based on the eddy current signal, and the selectivity of the polishing liquid for the electrode material layer 2 and the polishing stop layer 13 is different.
[0090] It should be noted that during the formation of the electrode material layer 2, due to the relatively large aspect ratio of the contact hole 15, electrode gaps 16 will be generated in the electrode material layer 2 that fills the contact hole 15.
[0091] As an example, such as Figure 8 shown, it is a schematic cross-sectional structure diagram after forming the electrode material layer 2. The electrode material layer 2 includes a buffer conductive layer 21 and a metal conductive layer 22.
[0092] Specifically, the buffer conductive layer 21 is usually used to improve the bonding force between the metal conductive layer 22 and the interlayer dielectric layer 11 on the inner wall of the contact hole 15, and at the same time, it can prevent the metal conductive layer 22 from diffusing into the interlayer dielectric layer 11 to ensure the reliability of the subsequent formed semiconductor device.
[0093] Specifically, generally, the conductivity of the buffer conductive layer 21 is poorer than that of the metal conductive layer 22, and its properties are relatively stable, not easy to diffuse, and at the same time, it can increase the resistance of the metal conductive layer 22 to diffuse into the interlayer dielectric layer 11. Therefore, in order to ensure the electrical performance of the metal electrode 3, the material of the buffer conductive layer 21 needs to be reasonably selected in the metal electrode 3, and the proportion of the buffer conductive layer 21 cannot be too high, that is, the thickness of the buffer conductive layer 21 is relatively thin. Under the condition of ensuring the performance of the subsequent fabricated semiconductor device, the thickness of the buffer conductive layer 21 can be selected according to the actual situation.
[0094] Specifically, the material of the buffer conductive layer 21 includes tantalum, tantalum nitride, or other suitable conductive materials. Preferably, a laminated film layer composed of a tantalum nitride layer and a tantalum layer is used as the buffer conductive layer 21.
[0095] Specifically, the method for forming the buffer conductive layer 21 includes chemical vapor deposition, physical vapor deposition, magnetron sputtering, metal compound vapor deposition, atomic vapor deposition, atomic layer deposition, evaporation, or other suitable methods.
[0096] As an example, the selectivity range of the polishing liquid for the electrode material layer 2 and the polishing stop layer 13 is 5:1 to 10:1.
[0097] Specifically, the method for forming the metal conductive layer 22 includes chemical vapor deposition, physical vapor deposition, magnetron sputtering, metal compound vapor deposition, atomic vapor deposition, atomic layer deposition, evaporation, or other suitable methods.
[0098] As an example, the selectivity range of the polishing liquid for the electrode material layer 2 and the polishing stop layer 13 is 5:1 to 10:1.
[0099] Specifically, by making the selectivity of the polishing liquid for the electrode material layer 2 and the polishing stop layer 13 between 5:1 and 10:1, the polishing liquid can remove the electrode material layer 2 at a relatively high rate and the polishing stop layer 13 at a relatively low rate. Then, when determining that the electrode material layer 2 directly above the interlayer dielectric layer 11 has been completely removed based on the magnitude of the eddy current signal value and ending the polishing process, the thickness loss of the polishing stop layer 13 is small, reducing the probability of over-polishing and also avoiding the problem of rework caused by insufficient polishing.
[0100] Specifically, during the polishing process of the electrode material layer 2, since the electrode material layer 2 is a conductive material, the removal situation of the electrode material layer 2 directly above the interlayer dielectric layer 11 can be determined by eddy current detection. When the eddy current value decreases to a preset value, it indicates that the electrode material layer 2 on the upper surface of the interlayer dielectric layer 11 has been completely removed, and polishing is stopped. It should be noted that the magnitude of the eddy current value when the electrode material layer 2 on the upper surface of the interlayer dielectric layer 11 is completely removed is related to the arrangement of the metal layers in the semiconductor structure, which is not restricted here.
[0101] Specifically, the material of the abrasive in the polishing liquid includes silicon oxide or other suitable materials. Preferably, colloidal silicon oxide is used as the abrasive in the polishing liquid.
[0102] It should be noted that as Figure 9 shown, it is a schematic cross-sectional structure diagram after removing the electrode material layer 2 directly above the interlayer dielectric layer 11. After polishing, the height of the metal electrode 3 is usually related to the process requirements and is generally between In the case where the device requires, it can also be less than or greater than
[0103] Specifically, as Figure 10 shown, it is a statistical chart of the thickness of the interlayer dielectric layer 11 of several semiconductor structures 1 after polishing. The normal thickness range of the interlayer dielectric layer 11 in the semiconductor structure 1 is It can be seen from the figure that the thicknesses of the interlayer dielectric layers 11 of several semiconductor structures 1 are all within the normal thickness range, improving the polishing yield and reducing the rework rate of polishing.
[0104] Specifically, before forming the shielding layer 14, a polishing stop layer 13 with a high polishing selectivity with respect to the electrode material layer 2 is formed on the upper surface of the interlayer dielectric layer 11. At the same time, based on the eddy current signal, polishing is stopped, so that only the thickness of the polishing stop layer 13 is lost during the process of stopping polishing and the lost thickness is small. Then, polishing stops at the polishing stop layer 13, avoiding excessive polishing that exposes the electrode gap 16 in the middle of the metal electrode 3 and affecting the reliability of the device. At the same time, the problem of rework caused by insufficient polishing is avoided, the control ability of the process of removing the electrode material layer 2 directly above the interlayer dielectric layer 11 is improved, and the yield and efficiency of manufacturing the metal electrode 3 are increased.
[0105] Specifically, since the thickness of the polishing stop layer 13 is relatively thin, the formation of the polishing stop layer 13 has little impact on the manufacturing process of the metal electrode 3.
[0106] The method for manufacturing the electrode in this embodiment improves the process of manufacturing the metal electrode 3. Before forming the shielding layer 14, a polishing stop layer 13 covering the upper surface of the interlayer dielectric layer 11 is formed. There is a high polishing selectivity between the electrode material layer 2 and the polishing stop layer 13, and the eddy current signal is used to determine the time to stop polishing, so that only a small thickness of the polishing stop layer 13 is lost during the process of stopping polishing. This avoids excessive polishing that exposes the electrode gap 16 in the middle of the metal electrode 3 and affects the reliability of the device. At the same time, the problem of rework caused by insufficient polishing is avoided, the control ability of the process of polishing and removing the electrode material layer 2 is improved, and the yield and efficiency of manufacturing the metal electrode 3 are increased.
[0107] Embodiment 2
[0108] This embodiment also provides a semiconductor device, and at least one metal electrode of the semiconductor device is manufactured by using the method for manufacturing the electrode described in Embodiment 1.
[0109] Specifically, by using the method for manufacturing the electrode described in Embodiment 1 to manufacture the metal electrode 3 of the semiconductor device, the yield and efficiency of manufacturing the metal electrode 3 are improved, and the rework rate is reduced.
[0110] The semiconductor device of this embodiment manufactures the metal electrode 3 of the semiconductor device by using the method for manufacturing the electrode described in Embodiment 1, improves the manufacturing yield and efficiency of the metal electrode 3, and reduces the rework rate of manufacturing the metal electrode 3.
[0111] In summary, in the method for manufacturing a semiconductor device and an electrode according to the present invention, by improving the manufacturing process of the metal electrode, a polishing stop layer covering the upper surface of the interlayer dielectric layer is formed before forming the shielding layer. There is a high polishing selectivity between the electrode material layer and the polishing stop layer, and the polishing stop time is determined by the eddy current signal, so that only a small thickness of the polishing stop layer is lost during the polishing stop process, avoiding the exposure of the electrode gap in the middle of the metal electrode caused by over-polishing, which affects the reliability of the device, and at the same time avoiding the problem of rework caused by insufficient polishing, improving the control ability of the process of polishing and removing the electrode material layer, and improving the yield and efficiency of manufacturing the metal electrode. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.
[0112] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A method for manufacturing an electrode, characterized in that, The method includes the following steps: Providing a semiconductor structure with an interlayer dielectric layer formed on an upper surface layer, at least one electrical contact region being provided below the interlayer dielectric layer; Successively forming an etch stop layer and a masking layer covering the upper surface of the interlayer dielectric layer, and patterning the masking layer; Forming a contact hole penetrating through the etch stop layer and the interlayer dielectric layer based on the patterned masking layer, removing the masking layer, and the bottom surface of the contact hole exposing the electrical contact region; Forming an electrode material layer filling the contact hole and covering the upper surface of the etch stop layer, and removing the electrode material layer directly above the interlayer dielectric layer by a chemical mechanical polishing process to obtain a metal electrode filling the contact hole, controlling the end of polishing based on an eddy current signal during the polishing process and the selectivity of the polishing liquid for the electrode material layer and the etch stop layer being different; 2. The method for manufacturing an electrode according to claim 1, wherein: At least one gate structure is included in the semiconductor structure, the interlayer dielectric layer covering the exposed surface of the gate structure, and at least one of the electrical contact regions being located on the upper surface of the gate structure; 3. The manufacturing method of the electrode according to claim 2, characterized in that: The gate structure includes a gate dielectric layer and a metal gate layer, and the electrical contact region is located on the upper surface of the metal gate layer; 4. The method for manufacturing an electrode according to claim 1, wherein: The material of the etch stop layer includes silicon nitride; 5. The manufacturing method of the electrode according to claim 1, characterized in that: The thickness range of the grinding stop layer is 6. The manufacturing method of the electrode according to claim 1, characterized in that: The masking layer includes a mask layer, an anti-reflection layer, a cap layer, and a photoresist layer; 7. The method for manufacturing an electrode according to claim 1, characterized in that: The electrode material layer includes a buffer conductive layer and a metal conductive layer; 8. The method for manufacturing an electrode according to claim 7, wherein: The material of the metal conductive layer includes tungsten; 9. The method for manufacturing the electrode according to claim 1, wherein: The selectivity range of the polishing liquid for the electrode material layer and the etch stop layer is 5:1 to 10:1; 10. A semiconductor device, characterized in that, At least one metal electrode of the semiconductor device is manufactured by using the method for manufacturing an electrode according to any one of claims 1 to 9.