Formation method of semiconductor structure

Abstract

A method for forming a semiconductor structure comprises the following steps: providing a substrate which comprises a field plate region and a non-field plate region; forming a field oxide material layer on the surface of the substrate; forming a photoresist layer on the surface of a part of the field oxide material layer, wherein the photoresist layer is located on the field plate region; etching the field oxide material layer on the non-field plate region by using a dry etching process by taking the photoresist layer as a mask until the field oxide material layer on the non-field plate region reaches a preset thickness; continuously etching the field oxide material layer on the non-field plate region by adopting a first wet etching process by taking the photoresist layer as a mask until the surface of the substrate is exposed, and taking the field oxide material layer on the field plate region as a field plate; and after the first wet etching process, the photoresist layer is removed, so that the morphology and thickness uniformity of the formed field plate can be improved, and the voltage resistance of the device can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and particularly to a method for forming a semiconductor structure. Background Art

[0002] In high-voltage power devices, the lateral double-diffused metal oxide semiconductor field effect transistor (Lateral Double-Diffused Metal Oxide Semiconductor Field Effect Transistor, abbreviated as LDMOS device) has good process compatibility with CMOS devices due to the characteristic that current flows laterally on the device surface. At the same time, compared with traditional power devices, LDMOS devices are widely used because of their good characteristics of high breakdown voltage and low on-resistance.

[0003] Among them, the high-voltage field plate (Field Plate, abbreviated as FP) plays a crucial role in the high-voltage resistance of LDMOS devices.

[0004] However, the performance of LDMOS devices formed by existing high-voltage field plate processes needs to be further improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problem, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a field plate region and a non-field plate region; forming a field oxide material layer on the surface of the substrate; forming a photoresist layer on the surface of a part of the field oxide material layer, the photoresist layer being located on the field plate region; using the photoresist layer as a mask, etching the field oxide material layer on the non-field plate region by a dry etching process until the field oxide material layer on the non-field plate region reaches a preset thickness; continuing to use the photoresist layer as a mask, etching the field oxide material layer on the non-field plate region by a first wet etching process until the surface of the substrate is exposed, and using the field oxide material layer on the field plate region as a field plate; after the first wet etching process, removing the photoresist layer.

[0007] Optionally, the field oxide material layer includes a first oxide material layer and a second oxide material layer.

[0008] Optionally, the forming process of the first oxide material layer includes a wet oxidation process.

[0009] Optionally, the process parameters of the wet oxidation process include: the reaction gas includes hydrogen and oxygen, the ratio range of the hydrogen flow rate to the oxygen flow rate is from 2:1 to 1:2, and the process temperature range is from 700 degrees Celsius to 900 degrees Celsius.

[0010] Optionally, the formation process of the second oxidation material layer includes a chemical vapor deposition process; the chemical vapor deposition process includes a low-pressure vapor deposition process.

[0011] Optionally, the process parameters of the low-pressure vapor deposition process include: the reaction gas includes tetraethoxysilane, the gas flow rate range is from 200 standard milliliters per minute to 400 standard milliliters per minute, and the pressure range is from 400 millitorr to 800 millitorr.

[0012] Optionally, the thickness range of the first oxidation material layer is from 90 angstroms to 110 angstroms; the thickness range of the second oxidation material layer is from 1100 angstroms to 1300 angstroms.

[0013] Optionally, the thickness of the second oxidation material layer is the preset thickness.

[0014] Optionally, the thickness range of the field oxide material layer is from 1170 angstroms to 1430 angstroms; the preset thickness range is from 40 angstroms to 100 angstroms; the ratio range of the preset thickness to the thickness of the oxide material layer is from 1:10 to 1:40.

[0015] Optionally, the process parameters of the dry etching process include: the etching gas includes CF4 and O2, the etching power range is from 200 watts to 300 watts, the pressure range in the etching chamber is from 40 millitorr to 70 millitorr, and the etching gas flow rate range is from 20 standard milliliters per minute to 100 standard milliliters per minute.

[0016] Optionally, the process parameters of the first wet etching process include: the etching solution includes a hydrofluoric acid solution, wherein the volume ratio range of hydrofluoric acid to water is from 1:50 to 1:200, the process temperature range is from 20 degrees Celsius to 30 degrees Celsius, and the process time range is from 0.5 hours to 1.5 hours.

[0017] Optionally, the process of removing the photoresist layer includes a second wet etching process.

[0018] Optionally, the process parameters of the second wet etching process include: the etching solution includes an SPM solution, wherein the concentration range of the sulfuric acid etching solution is from 70% to 90%, and the concentration range of the hydrogen peroxide etching solution is from 0.5% to 2%.

[0019] Optionally, the etching selectivity range of the second wet etching process for the photoresist layer and the field plate is greater than 10000:1.

[0020] Optionally, after forming the field oxide material layer and before forming the photoresist layer, the method further includes: annealing the field oxide material layer.

[0021] Optionally, the process parameters of the annealing process include: the time range is from 10 seconds to 30 seconds, and the temperature range is from 1000 degrees Celsius to 1200 degrees Celsius.

[0022] Optionally, the thickness range of the photoresist layer is from 7000 angstroms to 10000 angstroms.

[0023] Optionally, the size range of the field plate in the direction parallel to the substrate surface is from 0.3 micrometers to 5 micrometers.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0025] In the method for forming a semiconductor structure provided by the technical solution of the present invention, using the photoresist layer as a mask, a dry etching process is used to etch the field oxide material layer on the non-field plate region until the field oxide material layer on the non-field plate region reaches a preset thickness. Then, continuing to use the photoresist layer as a mask, a first wet etching process is used to etch the field oxide material layer on the non-field plate region until the substrate surface is exposed. Using the field oxide material layer on the field plate region as a field plate, therefore, the thickness of the field oxide material layer is the same as the thickness of the field plate. The thickness of the field oxide material layer is small, and the etching stop position in the dry etching process is relatively easy to control. The preset thickness can be controlled to a small thickness, so that the etching time of the first wet etching process will be correspondingly reduced, which is beneficial to reducing the lateral etching of the field plate and optimizing the sidewall morphology of the field plate. In addition, since the field oxide material layer on the field plate region is not thinned by etching, the thickness non-uniformity problem caused by etching is reduced. Overall, it is beneficial to improve the morphology and thickness uniformity of the formed field plate, and further improve the breakdown voltage performance of the device.

[0026] Furthermore, the etching selectivity range of the second wet etching process for the photoresist layer and the field plate is greater than 10000:1. Selecting a larger etching selectivity is beneficial to reducing the etching damage to the surface of the field plate in the second wet etching process. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figures 1 to 4 is a cross-sectional schematic diagram of a semiconductor structure formation process;

[0028] Figures 5 to 9 is a schematic diagram of the structures of the steps of the method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] It should be noted that the "surface" and "upper" in this specification are used to describe the relative positional relationship in space and do not limit whether there is direct contact.

[0030] As described in the background art, the performance of LDMOS devices formed by the existing high-voltage field plate process needs to be further improved. An analysis will be carried out in combination with the formation process of a semiconductor structure.

[0031] Figures 1 to 4 It is a cross-sectional schematic diagram of the formation process of a semiconductor structure.

[0032] Please refer to Figure 1 , a substrate 100 is provided, and the substrate 100 includes a field plate region I and a non-field plate region II; a field oxide material layer is formed on the surface of the substrate 100, and the field oxide material layer includes a first oxide material layer 101 and a second oxide material layer 102 located on the surface of the first oxide material layer 101, with the total thickness of the field oxide material layer being h1.

[0033] Please refer to Figure 2 , a patterned photoresist layer 103 is formed on the surface of the field oxide material layer; using the photoresist layer 103 as a mask, the field oxide material layer on the non-field plate region II is etched by a dry etching process until a preset thickness h2 is reached.

[0034] Please refer to Figure 3 , the photoresist layer 103 is removed.

[0035] Please refer to Figure 4 , the field oxide material layer is etched by a wet etching process until the surface of the non-field plate region II is exposed, and a field plate 103 is formed with the field oxide material layer on the field plate region I, with the thickness of the field plate 103 being h3.

[0036] In the above method for forming a semiconductor structure, the first oxide material layer 101 is formed by a wet oxidation process, and the second oxide material layer 102 is formed by a low-pressure chemical vapor deposition (abbreviated as LPCVD) process. The thickness of the first oxide material layer 101 is relatively thin (about dozens of angstroms) and is used to improve the interface state between the second oxide material layer 102 and the substrate 100 and reduce interface defects.

[0037] However, since the total thickness h1 of the field oxide material layer is relatively large (greater than the target thickness, i.e., the thickness h3 of the field plate 103), in the dry etching process of etching the field oxide material layer on the non-field plate region II, it is difficult to control the etching stop position. To avoid etching damage to the surface of the substrate 100, it is usually required that the preset thickness h2 is relatively large. As a result, during the wet etching process of etching the field oxide material layer, the etching time is relatively long, which easily causes poor thickness uniformity of the finally formed field plate 103 (as shown in region A in Figure 4 ), and side etching problems occur (as shown in region B in Figure 4 ), thus affecting the high-voltage performance of the device.

[0038] To solve the above problems, in a method for forming a semiconductor structure provided by the present invention, using a photoresist layer as a mask, a dry etching process is used to etch the field oxide material layer on the non-field plate region until the field oxide material layer on the non-field plate region reaches a preset thickness. Then, continuing to use the photoresist layer as a mask, a first wet etching process is used to etch the field oxide material layer on the non-field plate region until the surface of the substrate is exposed. Using the field oxide material layer on the field plate region as a field plate, therefore, the thickness of the field oxide material layer is the same as that of the field plate. The thickness of the field oxide material layer is relatively small, and the etching stop position in the dry etching process is relatively easy to control. The preset thickness can be controlled to a relatively small value, so that the etching time of the first wet etching process will be correspondingly reduced, which is beneficial to reducing the lateral etching of the field plate and optimizing the sidewall morphology of the field plate. In addition, since the field oxide material layer on the field plate region is not thinned by etching, the thickness non-uniformity problem caused by etching is reduced. Overall, it is beneficial to improve the morphology and thickness uniformity of the formed field plate, and further improve the breakdown voltage performance of the device.

[0039] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description will be given to specific embodiments of the present invention with reference to the accompanying drawings.

[0040] Figures 5 to 9 FIG. is a schematic structural diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0041] Please refer to Figure 5 , a substrate 200 is provided, and the substrate 200 includes a field plate region i and a non-field plate region ii.

[0042] In this embodiment, the material of the substrate 200 is silicon.

[0043] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0044] Please continue to refer to Figure 5 , and a field oxide material layer 201 is formed on the surface of the substrate 200.

[0045] The material of the field oxide material layer 201 includes silicon oxide.

[0046] In this embodiment, the thickness range of the field oxide material layer 201 is from 1170 angstroms to 1430 angstroms. It should be noted here that the thickness described in this article refers to the dimension in the direction perpendicular to the surface of the substrate 200.

[0047] In this embodiment, the field oxide material layer 201 includes a first oxide material layer 201a and a second oxide material layer 201b.

[0048] In this embodiment, the thickness range of the first oxide material layer 201a is from 90 angstroms to 110 angstroms.

[0049] In this embodiment, the formation process of the first oxide material layer 201a includes a wet oxidation process. The wet oxidation process is obtained by reacting with the surface of the substrate 200. The formed silicon oxide material has good compactness, which is beneficial to optimizing the interface state between the second oxide material layer 201b and the substrate 200, reducing interface defects, and further improving the breakdown voltage performance of the finally formed device.

[0050] The process parameters of the wet oxidation process include: the reaction gases include hydrogen and oxygen, the ratio range of the hydrogen flow rate to the oxygen flow rate is from 2:1 to 1:2, and the process temperature range is from 700 degrees Celsius to 900 degrees Celsius. In this embodiment, the ratio of the hydrogen flow rate to the oxygen flow rate is 1:1.

[0051] The formation process of the second oxide material layer 201b includes a chemical vapor deposition process.

[0052] In this embodiment, the chemical vapor deposition process includes a low-pressure vapor deposition process. Specifically, the low-pressure vapor deposition process is performed in a furnace tube.

[0053] In this embodiment, the process parameters of the low-pressure chemical vapor deposition process include: the reaction gas includes tetraethyl orthosilicate (TEOS), the gas flow rate ranges from 200 standard milliliters per minute to 400 standard milliliters per minute, and the pressure ranges from 400 millitorr to 800 millitorr. In this embodiment, the gas flow rate is 280 standard milliliters per minute, and the pressure is 600 millitorr.

[0054] In this embodiment, the thickness range of the second oxide material layer 201b is from 1100 angstroms to 1300 angstroms.

[0055] In this embodiment, after forming the field oxide material layer 201, an annealing treatment is further performed on the field oxide material layer 201. The annealing treatment is used to reduce the defects generated during the formation of the field oxide material layer 201.

[0056] In this embodiment, the process parameters of the annealing treatment process include: the time range is from 10 seconds to 30 seconds, and the temperature range is from 1000 degrees Celsius to 1200 degrees Celsius.

[0057] Please refer to Figure 6 , a photoresist layer 202 is formed on the surface of a part of the field oxide material layer 201, and the photoresist layer 202 is located on the field plate area i.

[0058] In this embodiment, the method for forming the photoresist layer 202 includes: forming a photoresist material layer (not shown in the figure) on the surface of the field oxide material layer 201; patterning the photoresist material layer to form the photoresist layer 202.

[0059] Specifically, after the annealing treatment, the photoresist layer 202 is formed.

[0060] Here, the photoresist layer 202 needs to have good acid resistance to avoid being etched away in the subsequent first wet etching process and unable to play the role of a mask.

[0061] In this embodiment, the thickness range of the photoresist layer 202 is from 7000 angstroms to 10000 angstroms.

[0062] Please refer to Figure 7 , using the photoresist layer 202 as a mask, the field oxide material layer 201 on the non-field plate area ii is etched by a dry etching process until the field oxide material layer 201 on the non-field plate area i reaches a preset thickness.

[0063] Subsequently, the field oxide material layer 201 on the field plate area i will be used as the field plate 203. Therefore, the thickness of the field oxide material layer 201 is the same as the thickness of the field plate. The thickness of the field oxide material layer 201 is small, and the etching stop position in the dry etching process is relatively easy to control, and the preset thickness can be controlled to a smaller size.

[0064] The preset thickness range is from 40 angstroms to 100 angstroms.

[0065] The ratio range of the preset thickness to the thickness of the field oxide material layer 201 is from 1:10 to 1:40. The ratio range of the preset thickness to the thickness of the field oxide material layer 201 is 1:20.

[0066] In this embodiment, the thickness of the second oxide material layer 201b is used as the preset thickness. Specifically, using the photoresist layer 202 as a mask, the field oxide material layer 201 on the non-field plate region ii is etched by a dry etching process until the second oxide material layer 201b on the non-field plate region i is exposed.

[0067] In this embodiment, the process parameters of the dry etching process include: the etching gas includes CF4 and O2, the etching power range is from 200 watts to 300 watts, the air pressure in the etching chamber range is from 40 millitorr to 70 millitorr, and the etching gas flow rate range is from 20 standard milliliters per minute to 100 standard milliliters per minute.

[0068] Please refer to Figure 8 , and continue to use the photoresist layer 202 as a mask to etch the field oxide material layer 201 on the non-field plate region ii by a first wet etching process until the surface of the substrate 200 is exposed, and use the field oxide material layer 201 on the field plate region i as the field plate 203.

[0069] As described above, since the preset thickness can be controlled to a smaller thickness, therefore, the etching time of the first wet etching process will be correspondingly reduced, which is beneficial to reducing the lateral etching of the field plate 203 and optimizing the sidewall morphology of the field plate 203; in addition, since the field oxide material layer 201 on the field plate region i will not be etched to thin it, the thickness non-uniformity problem caused by etching is reduced. Overall, it is beneficial to improve the morphology and thickness uniformity of the formed field plate 203, thereby improving the breakdown voltage performance of the device.

[0070] In this embodiment, the field plate 203 includes a first oxide layer 203a and a second oxide layer 203b. Specifically, the first oxide layer 203a is formed with the first oxide material layer 201a (as Figure 7 shown), and the second oxide layer 203b is formed with the second oxide material layer 201b (as Figure 7 shown).

[0071] In this embodiment, the process parameters of the first wet etching process include: the etching solution includes a hydrofluoric acid solution, wherein the volume ratio range of hydrofluoric acid to water is from 1:50 to 1:200, the process temperature range is from 20 degrees Celsius to 30 degrees Celsius, and the process time range is from 0.5 hour to 1.5 hours. In this embodiment, the process temperature is 23 degrees Celsius.

[0072] Please refer to Figure 9 , after the first wet etching process, the photoresist layer 202 is removed.

[0073] The etching selectivity of the second wet etching process for the photoresist layer 202 and the field plate 203 is in the range of greater than 10000:1. Selecting a larger etching selectivity is beneficial to reducing the etching damage to the surface of the field plate 203 during the second wet etching process.

[0074] In this embodiment, the process of removing the photoresist layer 202 includes a second wet etching process.

[0075] In this embodiment, the process parameters of the second wet etching process include: the etching solution includes an SPM solution, wherein the concentration range of the sulfuric acid etching solution is from 70% to 90%, and the concentration range of the hydrogen peroxide etching solution is from 0.5% to 2%.

[0076] In this embodiment, the size range of the field plate 203 in the direction parallel to the surface of the substrate 200 is from 0.3 micrometers to 5 micrometers.

[0077] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate including a field plate region and a non-field plate region; Forming a field oxide material layer on the surface of the substrate; Forming a photoresist layer on the surface of a part of the field oxide material layer, the photoresist layer being located on the field plate region; Using the photoresist layer as a mask, etching the field oxide material layer on the non-field plate region by a dry etching process until the field oxide material layer on the non-field plate region reaches a preset thickness; Continuing to use the photoresist layer as a mask, etching the field oxide material layer on the non-field plate region by a first wet etching process until the surface of the substrate is exposed, and using the field oxide material layer on the field plate region as a field plate; After the first wet etching process, removing the photoresist layer.

2. The method for forming a semiconductor structure according to claim 1, wherein, The field oxide material layer includes a first oxide material layer and a second oxide material layer.

3. The method for forming a semiconductor structure according to claim 2, wherein The forming process of the first oxide material layer includes a wet oxidation process.

4. The method for forming a semiconductor structure according to claim 3, wherein, The process parameters of the wet oxidation process include: the reaction gas includes hydrogen and oxygen, the ratio range of the hydrogen flow rate to the oxygen flow rate is from 2:1 to 1:2, and the process temperature range is from 700 degrees Celsius to 900 degrees Celsius.

5. The method for forming a semiconductor structure according to claim 2, wherein The forming process of the second oxide material layer includes a chemical vapor deposition process; the chemical vapor deposition process includes a low-pressure vapor deposition process.

6. The method for forming a semiconductor structure according to claim 5, wherein, The process parameters of the low-pressure vapor deposition process include: the reaction gas includes tetraethoxysilane, the gas flow rate range is from 200 standard milliliters per minute to 400 standard milliliters per minute, and the pressure range is from 400 millitorr to 800 millitorr.

7. The method for forming a semiconductor structure according to claim 2, wherein, The thickness range of the first oxide material layer is from 90 angstroms to 110 angstroms; the thickness range of the second oxide material layer is from 1100 angstroms to 1300 angstroms.

8. The method for forming a semiconductor structure according to claim 2, wherein The thickness of the second oxide material layer is the preset thickness.

9. The method for forming a semiconductor structure according to claim 1, wherein, The thickness range of the field oxide material layer is from 1170 angstroms to 1430 angstroms; the preset thickness range is from 40 angstroms to 100 angstroms; the ratio range of the preset thickness to the thickness of the oxide material layer is from 1:10 to 1:

40.

10. The method for forming a semiconductor structure according to claim 1, characterized in that, The process parameters of the dry etching process include: the etching gas includes CF4 and O2, the etching power range is from 200 watts to 300 watts, the gas pressure range in the etching chamber is from 40 millitorr to 70 millitorr, and the etching gas flow rate range is from 20 standard milliliters per minute to 100 standard milliliters per minute.

11. The method for forming a semiconductor structure according to claim 1, wherein, The process parameters of the first wet etching process include: the etching solution includes a hydrofluoric acid solution, wherein the volume ratio range of hydrofluoric acid to water is from 1:50 to 1:200, the process temperature range is from 20 degrees Celsius to 30 degrees Celsius, and the process time range is from 0.5 hours to 1.5 hours.

12. The method for forming a semiconductor structure according to claim 1, wherein, The process of removing the photoresist layer includes a second wet etching process.

13. The method for forming a semiconductor structure according to claim 12, wherein, The process parameters of the second wet etching process include: the etching solution includes an SPM solution, wherein the concentration range of the sulfuric acid etching solution is from 70% to 90%, and the concentration range of the hydrogen peroxide etching solution is from 0.5% to 2%.

14. The method for forming a semiconductor structure according to claim 12, wherein The etching selectivity range of the second wet etching process for the photoresist layer and the field plate is greater than 10000:

1.

15. The method for forming a semiconductor structure according to claim 1, wherein, After forming the field oxide material layer and before forming the photoresist layer, it further includes: annealing the field oxide material layer.

16. The method for forming a semiconductor structure according to claim 15, wherein, The process parameters of the annealing treatment process include: the time range is from 10 seconds to 30 seconds, and the temperature range is from 1000 degrees Celsius to 1200 degrees Celsius.

17. The method for forming a semiconductor structure as claimed in claim 1, wherein, The thickness range of the photoresist layer is from 7000 angstroms to 10000 angstroms.

18. The method for forming a semiconductor structure according to claim 1, wherein, The size range of the field plate in the direction parallel to the surface of the substrate is from 0.3 micrometers to 5 micrometers.

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