Chip and method for reducing chip load effect
By uniformly forming source and drain regions through controlled etching and epitaxial growth, the method addresses inconsistent growth rates of silicon-germanium in semiconductor chips, enhancing chip yield and electrical reliability.
Patent Information
- Application Number
- CN202510403246.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-01
- Publication Date
- 2025-07-15
AI Technical Summary
The growth rates in different regions of the semiconductor chip are inconsistent, resulting in a load effect, affecting the yield and electrical properties of the chip manufacturing.
The chip is etched to expose the core logic region, standard cell region and input and output region of the PMOS region, the source and drain electrodes are formed on the fin structures of these regions, respectively, and the consistency of the growth rate is controlled by epitaxial growth of silicon germanium.
The source and drain growth rates of different regions of PMOS are achieved consistently, reducing the load effect of the chip and improving the yield and electrical reliability of the chip.
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Figure CN120322005A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly relates to a chip and a method for reducing the load effect of the chip. Background Art
[0002] In order to generate compressive stress in the channel region of a P-type semiconductor (PMOS), silicon germanium epitaxial growth (also known as a silicon germanium stressor) is generally formed in the source and drain regions of the PMOS. Since silicon germanium has a larger lattice constant than silicon, after annealing, silicon germanium will expand and generate compressive stress in the channel region in the source-to-drain direction.
[0003] However, in the same chip (die), due to the different sizes and pattern densities of the fin structures in different regions of the chip, during the subsequent silicon germanium epitaxial growth to form the source and drain, the growth rates in different regions are inconsistent, resulting in inconsistent thicknesses and shapes of the epitaxially grown silicon germanium films, generating a load effect and affecting the overall manufacturing yield of the chip and the electrical properties of the device.
[0004] It should be noted that the information disclosed in the background art section of this invention is only intended to deepen the understanding of the general background art of the present invention, and should not be regarded as an admission or any form of implication that this information constitutes the prior art known to those skilled in the art. Summary of the Invention
[0005] The purpose of the present invention is to provide a chip and a method for reducing the load effect of the chip to solve the problem of generating a load effect due to inconsistent growth rates in different regions during the process of epitaxially growing silicon germanium.
[0006] To solve the above technical problems, the present invention provides a method for reducing the load effect of a chip, including:
[0007] S1: Provide a chip, etch the chip to expose the area where the PMOS is located on the chip. The area where the PMOS is located includes a core logic area, a standard cell area, and an input / output area. The core logic area, the standard cell area, and the input / output area respectively have fin structures where the source and drain are to be formed;
[0008] S2: Expose the fin structures in one of the core logic area, the standard cell area, and the input / output area, and cover the remaining areas;
[0009] S3: Form the source and drain on the fin structures in the exposed area;
[0010] S4: Repeat steps S2 and S3 to form the source and drain on the fin structures in the remaining areas.
[0011] Preferably, the S2 includes:
[0012] Form a hard mask layer and a photoresist layer successively upward from the substrate in the region where the PMOS is located;
[0013] Etch the photoresist in one of the regions, and use the etched photoresist as a mask to etch the hard mask layer to expose the fin structure in one of the regions, and cover the remaining regions with the hard mask layer and the photoresist.
[0014] Preferably, the exposed fin structure in one of the regions is the fin structure in the core logic region.
[0015] Preferably, the exposed fin structure in one of the regions is the fin structure in the standard cell region.
[0016] Preferably, the exposed fin structure in one of the regions is the fin structure in the input / output region.
[0017] Preferably, the S4 includes:
[0018] Expose the fin structure in the standard cell region and cover the remaining regions;
[0019] Form source and drain electrodes in the fin structure in the standard cell region;
[0020] Expose the fin structure in the input / output region and cover the remaining regions;
[0021] Form source and drain electrodes in the fin structure in the input / output region.
[0022] Preferably, the S3 includes:
[0023] Etch the fin structure to form a groove at the top of the fin structure;
[0024] Grow silicon germanium in the groove by epitaxial growth to form source and drain electrodes.
[0025] Preferably, the chip includes PMOS and NMOS. Etching the chip to expose the region where the PMOS is located on the chip includes:
[0026] Form a hard mask layer and a photoresist layer on the surface of the chip;
[0027] Etch the photoresist in the region where the PMOS is located, and use the photoresist as a mask to remove the hard mask layer in the region where the PMOS is located to expose the region where the PMOS is located on the chip.
[0028] Preferably, after the S4, the method further includes:
[0029] Cover the area where the PMOS is located and expose the area where the NMOS is located;
[0030] Form source and drain electrodes in the area where the NMOS is located.
[0031] Based on the same inventive concept, the present invention also provides a chip, comprising:
[0032] Manufactured by using the method for reducing the load effect of the chip described above.
[0033] Compared with the prior art, the method for reducing the load effect of the chip of the present invention has the following advantages:
[0034] By exposing one of the three regions in the PMOS region and covering the fin structures in the other regions, the present invention can form source and drain electrodes by epitaxially growing silicon germanium on the fin structures in the exposed region. Then, in the same way, source and drain electrodes are formed in the other regions, so that the growth rates of the source and drain electrodes in different regions of the PMOS are consistent, and the morphologies of the source and drain electrodes are substantially the same, thereby reducing the load effect of the chip and improving the yield of chip manufacturing and the electrical reliability of the chip.
[0035] The chip provided by the present invention and the method for reducing the load effect of the chip provided by the present invention belong to the same inventive concept. Therefore, the chip provided by the present invention has at least all the advantages of the method for reducing the load effect of the chip provided by the present invention, can reduce the load effect of the chip, and improve the yield of chip manufacturing and the electrical reliability of the chip. Description of the Drawings
[0036] Figure 1 is a schematic structural diagram of etching a chip to expose the area where the PMOS is located in an embodiment;
[0037] Figure 2 is a schematic structural diagram after etching the fin structures for growing source and drain electrodes in the PMOS in an embodiment;
[0038] Figure 3 is a schematic structural diagram after forming source and drain electrodes in the PMOS in an embodiment;
[0039] Figure 4 is a flowchart of the method for reducing the load effect of the chip in an embodiment of the present invention;
[0040] Figure 5 is a schematic structural diagram of only exposing the central logic region in an embodiment of the present invention;
[0041] Figure 6 is a schematic structural diagram of only exposing the standard cell area in an embodiment of the present invention;
[0042] Figure 7 It is a schematic structural diagram of only the input / output area in an embodiment of the present invention;
[0043] Figure 8 It is a schematic structural diagram after forming the source and drain in an embodiment of the present invention;
[0044] In the figure,
[0045] 100 - Substrate; 200 - Shallow trench isolation;
[0046] 300 - Fin structure; 310 - Groove;
[0047] 320 - Source; 330 - Drain;
[0048] 400 - Hard mask layer; 500 - Photoresist. Detailed implementation manners
[0049] To make the objectives, advantages and features of the present invention clearer, the following further describes in detail the chip and the method for reducing the chip loading effect proposed by the present invention with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in very simplified forms and use non-precise scales, only for conveniently and clearly assisting in explaining the objectives of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to explain certain principles of the present invention in the drawings of the specification will also adopt slightly simplified drawing methods. The specific design features of the present invention disclosed herein, such as specific dimensions, directions, positions and shapes, will be partially determined by the specific application and usage environment. Also, in the following described embodiments, sometimes the same reference numerals are used commonly between different drawings to represent the same part or parts having the same functions, and the repeated description thereof is omitted. In this specification, similar reference numerals and letters are used to represent similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.
[0050] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically and clearly defined.
[0051] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.
[0052] As shown Figures 1 to 3 in the figure, the chip includes PMOS and NMOS. During the manufacturing process of the chip, the fin structure 300, shallow trench isolation 200 (i.e., STI), and gate (not shown in the figure) have been fabricated. Next, a hard mask layer and photoresist are sequentially deposited on the chip upward from the substrate 100 to cover the chip. First, the region where the PMOS of the chip is located is etched to remove the hard mask layer 400 and photoresist 500 in the region where the PMOS is located, so as to expose the region where the PMOS is located, and the region where the NMOS is located is covered by the hard mask layer 400 and photoresist 500. When etching the region where the PMOS of the chip is located, the photoresist in the region where the PMOS is located is patterned. After etching the photoresist, the hard mask layer 400 is etched using the photoresist as a mask to expose the region where the PMOS is located. From Figure 2 it can be seen that the PMOS includes a central logic region (i.e., Core region 10a), a standard cell region (i.e., Cell region 10b), and an input / output region (i.e., IO region 10c). Then, the fin structure 300 in the region where the PMOS is located is etched using dry etching to form a groove 310 in the fin structure 300. Finally, silicon germanium is grown in the groove 310 by epitaxial growth to form a source electrode 320 and a drain electrode 330. From Figure 2 it can be seen that the critical dimensions of the fin structures 300 in the Core region 10a, Cell region 10b, and IO region 10c (i.e., the width of the fin structure 300 extending along Figure 2 the direction of arrow a in the figure) are all different. The critical dimension of the fin structure 300 in the Core region 10a is greater than the dimension of the fin structure 300 in the Cell region 10b and less than the dimension of the fin structure 300 in the IO region 10c. From Figure 3It can be seen that since the patterns in the Core region 10a and the Cell region 10b are dense patterns, while the patterns in the IO region 10c are sparse patterns, and the density of the patterns in the Core region 10a and the Cell region 10b is also different. Therefore, when epitaxially growing silicon germanium, the growth rates in the Core region 10a, the Cell region 10b, and the IO region 10c are all different, thus forming the source electrode 320 and the drain electrode 330 as shown in Figure 3 . As can be seen from Figure 3 , the source electrodes 320 and the drain electrodes 330 in different regions have different dimensions in the longitudinal direction (i.e., the direction of the arrow b in Figure 2 ) and the transverse direction (i.e., the direction of the arrow a in Figure 2 ), thereby causing the load effect and affecting the yield of chip manufacturing and the electrical properties of the chip.
[0053] The core idea of the present invention is to provide a chip and a method for reducing the load effect of the chip, which can reduce the load effect of the chip and improve the yield and electrical reliability of the chip.
[0054] To achieve the above idea, the present invention provides a method for reducing the load effect of a chip, referring to Figures 4 to 8 a specific implementation manner of a method for reducing the load effect of a chip. The method for reducing the load effect of the chip includes the following steps S1 to S4.
[0055] Step S1: Provide a chip, etch the chip to expose the region where the PMOS is located on the chip. The region where the PMOS is located includes a core logic region, a standard cell region, and an input / output region. The core logic region, the standard cell region, and the input / output region respectively have fin structures 300 where source electrodes and drain electrodes are to be formed.
[0056] Specifically, referring to Figures 1 to 5 , in Figure 5 , the chip includes a substrate 100, and PMOS and NMOS are formed on the substrate 100. During the manufacturing process of the chip, the manufacturing of the fin structures 300, the shallow trench isolation 200 (i.e., STI), and the gate (not shown in the figure) has been completed. That is, the manufacturing of the fin structures 300, the shallow trench isolation 200, and the gate has been completed on the substrate 100. The STI therein is used for isolation between different fin structures 300.
[0057] Etching the chip to expose the region where the PMOS is located includes:
[0058] First, deposit a hard mask layer 400 and a photoresist 500 on the chip in sequence from the substrate 100 upward to cover the chip.
[0059] Next, etch the photoresist 500 in the region where the PMOS is located, and use the photoresist 500 as a mask to remove the hard mask layer 400 in the region where the PMOS is located, so as to expose the region where the PMOS is located on the chip. Etch the region where the PMOS of the chip is located to remove the hard mask layer 400 and the photoresist 500 in the region where the PMOS is located, so as to expose the region where the PMOS is located, and cover the region where the NMOS is located through the hard mask layer 400 and the photoresist 500. When etching the region where the PMOS of the chip is located, pattern the photoresist 500 in the region where the PMOS is located. After etching the photoresist 500, etch the hard mask layer 400 using the photoresist 500 as a mask to expose the region where the PMOS is located. The material of the hard mask layer can be nitride, silicide, etc. In this embodiment, preferably, the material of the hard mask layer 400 is silicon nitride (SiN).
[0060] The region where the PMOS is located includes a PMOS including a central logic region (i.e., Core region 10a), a standard cell region (i.e., Cell region 10b), and an input / output region (i.e., IO region 10c). The Core region 10a therein performs core logic operations and data processing. The Cell region 10b provides reusable basic logic units. The IO region 10c provides signal interaction and protection between the chip and the external world. In the subsequent chip fabrication, it is necessary to grow silicon germanium epitaxial layers as source and drain electrodes on the fin structures 300 in the Core region 10a, the Cell region 10b, and the IO region 10c.
[0061] Step S2: Expose the fin structure 300 in one of the central logic region, the standard cell region, and the input / output region, and cover the remaining regions.
[0062] Specifically, referring Figure 4 and Figure 5 as shown, the exposing the fin structure 300 in one of the central logic region, the standard cell region, and the input / output region and covering the remaining regions includes:
[0063] First, form a hard mask layer 400 and a photoresist 500 successively upward from the substrate 100 in the region where the PMOS is located.
[0064] Next, etch the photoresist 500 in one of the regions, and use the etched photoresist 500 as a mask to etch the hard mask layer 400 to expose the fin structure 300 in one of the regions, and cover the remaining regions through the hard mask layer 400 and the photoresist 500. That is, expose the fin structure 300 in one of the Core region 10a, the Cell region 10b, and the IO region 10c, cover the remaining regions, and form source and drain electrodes on the exposed fin structure 300. As an example, it can be as Figure 5For the structure shown, first, the fin structure 300 of the Core region 10a is exposed, and the Cell region 10a and the IO region 10c are covered. The photoresist and the hard mask layer cover the Cell region and the IO region, while the fin structure 300 of the Core region 10a is exposed.
[0065] It should be noted that either the fin structure 300 of the Core region 10a can be preferentially exposed, and the Cell region 10b and the IO region 10c are covered. Or the fin structure 300 of the Cell region 10b can be preferentially exposed, and the Core region 10a and the IO region 10c are covered. Or the fin structure 300 of the IO region 10c can be preferentially exposed, and the Core region 10a and the Cell region 10b are covered. That is, the fin structure of the exposed one of the regions can be the fin structure 300 of the Core region 10a, or the fin structure 300 of the Cell region 10b, or the fin structure 300 of the IO region 10c. For the convenience of explanation, hereinafter, still taking Figure 5 the structure shown in
[0066] Step S3: Form source and drain electrodes on the fin structure 300 in the exposed region.
[0067] Specifically, referring to Figure 4 and Figure 5 shown, forming source and drain electrodes on the fin structure 300 in the exposed region includes:
[0068] First, etch the fin structure 300 to form a groove on the top of the fin structure 300. Dry etch the Core region 10a to form a groove 310 on the fin structure 300 of the Core region 10a. The dry etch uses common etch gases, such as one of CHF3, CH2F2, CH3F, SiF4, CF4, NF3, or any combination thereof. Here, there is no specific requirement for the etch gas, as long as it can etch the fin structure 300.
[0069] Then, grow silicon germanium in the groove 310 by epitaxial growth to form the source electrode 320 and the drain electrode 330. Finally, use the epitaxial growth process to grow silicon germanium in the groove to form the source and drain electrodes of the Core region. When growing silicon germanium, place the chip in an epitaxial growth device, and simultaneously introduce a silicon source and a germanium source into the device. The silicon source can be one of silane (SiH4), dichlorosilane (DCS, SiH2Cl2), and trichlorosilane (TCS, SiHCl3), or any combination thereof. The germanium source is mainly germane (GeH4).
[0070] Step S4: Repeat steps S2 and S3 to form source and drain electrodes on the fin structure 300 in the remaining region.
[0071] Specifically, refer to Figure 4 and Figures 6 to 8 As shown, repeat steps S2 and S3 to form the source and drain in the remaining fin structures.
[0072] The steps to form the source 320 and drain 330 in the Cell region 10b are as follows:
[0073] First, cover the Core region 10a and the IO region 10c to expose the fin structures 300 in the Cell region 10b. Deposit a hard mask layer 400 and a photoresist 500 sequentially upward from the substrate 100 in the PMOS region. Etch the Cell region 10b to remove the hard mask layer 400 and the photoresist 500 in the Cell region 10b, exposing the fin structures 300 in the Cell region 10b, while the Core region 10a and the IO region 10c are covered by the hard mask layer 400 and the photoresist 500.
[0074] Next, use dry etching to etch the fin structures 300 in the Cell region 10b to form grooves 310 at the top of the fin structures 300. It should be noted that the dry etching here is the same as the above, and will not be elaborated in detail here.
[0075] Then, grow silicon germanium in the grooves 310 by epitaxial growth to form the source 320 and drain 330 in the Cell region 10b. It should be noted that the epitaxial growth here is the same as that described above, and will not be elaborated in detail here. It should also be noted that in order to reduce the load effect, when growing silicon germanium epitaxially in the Core region 10a and the Cell region 10b, the growth rate of silicon germanium epitaxial growth can be controlled to ensure that the morphologies of the source 320 and drain 330 in the two regions are the same.
[0076] The steps to form the source 320 and drain 330 in the IO region 10c are as follows:
[0077] First, cover the Core region 10a and the Cell region 10b to expose the fin structures 300 in the IO region 10c. Deposit a hard mask layer 400 and a photoresist 500 sequentially upward from the substrate 100 in the PMOS region. Etch the IO region 10c to remove the hard mask layer 400 and the photoresist 500 in the IO region 10c, exposing the fin structures 300 in the IO region 10c, while the Core region 10a and the Cell region 10b are covered by the hard mask layer 400 and the photoresist 500.
[0078] Next, use dry etching to etch the fin structures 300 in the IO region 10c to form grooves 310 at the top of the fin structures 300. It should be noted that the dry etching here is the same as the above, and will not be elaborated in detail here.
[0079] Then, silicon germanium is grown in the groove 310 by epitaxial growth to form the source and drain of the IO region 10c. It should be noted that the epitaxial growth here is the same as that described above and will not be elaborated in detail here. It should also be noted that in order to reduce the load effect, when epitaxially growing silicon germanium in the Core region 10a, the Cell region 10b, and the IO region 10c, the growth rate of the silicon germanium epitaxy can be controlled to ensure that the morphologies of the source 320 and drain 330 in the three regions are the same. From Figure 8 It can be seen that for the PMOS fabricated by the method disclosed in this embodiment, the morphologies of the source 320 and drain 330 formed in the three regions of the PMOS are substantially the same.
[0080] After the epitaxial growth of the source and drain in the region where the PMOS is located is completed, the method further includes:
[0081] Cover the region where the PMOS is located and expose the region where the NMOS is located.
[0082] Form the source and drain in the region where the NMOS is located.
[0083] It should be noted that the method of covering the region where the PMOS is located and exposing the region where the NMOS is located is similar to the method of exposing the region where the PMOS is located and will not be elaborated in detail here. Forming the source and drain in the region where the NMOS is located belongs to the prior art, and those skilled in the art are already familiar with its specific process steps and will not be elaborated in detail here. In this embodiment, by the above method, the morphologies of the silicon germanium epitaxy in the Core region 10a, the Cell region 10b, and the IO region 10c of the PMOS are improved, and the original chip manufacturing process sequence is not changed. It is still to first complete the fabrication of the gate. Then, form the source and drain in the PMOS. Then form the source and drain in the NMOS. Therefore, the difficulty of executing the process steps can be reduced and the cost can be reduced.
[0084] In this embodiment, by exposing one of the three regions in the PMOS region and covering the fin structures in the other regions, the source and drain can be formed by epitaxially growing silicon germanium on the fin structures in the exposed region. Then, in the same way, silicon germanium is epitaxially grown in the other regions to form the source and drain, so that the growth rates of the source and drain in different regions of the PMOS are consistent, the morphologies of the source and drain are substantially the same, the load effect of the chip can be reduced, and the yield of chip manufacturing and the electrical reliability of the chip can be improved.
[0085] To implement the above idea, this embodiment also discloses a chip, including:
[0086] Fabricated by using the method for reducing the load effect of the chip as described above.
[0087] The chip provided in this embodiment and the method for reducing the chip load effect provided in this embodiment belong to the same inventive concept. Therefore, the chip provided in this embodiment has at least all the advantages of the method for reducing the chip load effect provided in this embodiment, can reduce the chip load effect, improve the yield of chip manufacturing and the reliability of the electrical properties of the chip.
[0088] In summary, the above embodiments have described in detail different configurations of the chip and the method for reducing the chip load effect. Of course, the above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences from one instance to another based on the content of the above embodiments. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the protection scope of the claims.
Claims
1. A method for reducing the chip loading effect, characterized in that, Including: S1: Provide a chip, etch the chip to expose the area where PMOS is located on the chip. The area where PMOS is located includes a core logic area, a standard cell area, and an input / output area. The core logic area, the standard cell area, and the input / output area respectively have fin structures where source and drain are to be formed. S2: Expose the fin structures in one of the core logic area, the standard cell area, and the input / output area, and cover the remaining areas. S3: Form source and drain on the fin structures in the exposed area. S4: Repeat steps S2 and S3 to form source and drain on the fin structures in the remaining areas.
2. The method for reducing the chip load effect according to claim 1, wherein S2 includes: Form a hard mask layer and a photoresist on the substrate upward in the area where PMOS is located. Etch the photoresist in one of the areas, and use the etched photoresist as a mask to etch the hard mask layer to expose the fin structures in one of the areas, and cover the remaining areas through the hard mask layer and the photoresist.
3. The method for reducing the chip load effect according to claim 2, wherein Exposing the fin structures in one of the areas is the fin structures in the core logic area.
4. The method for reducing the chip loading effect according to claim 2, wherein Exposing the fin structures in one of the areas is the fin structures in the standard cell area.
5. The method for reducing the chip load effect according to claim 2, wherein Exposing the fin structures in one of the areas is the fin structures in the input / output area.
6. The method for reducing the chip loading effect according to claim 3, wherein S4 includes: Expose the fin structures in the standard cell area and cover the remaining areas. Form source and drain on the fin structures in the standard cell area. Expose the fin structures in the input / output area and cover the remaining areas. Form source and drain on the fin structures in the input / output area.
7. The method for reducing the chip load effect according to claim 1, wherein S3 includes: Etch the fin structures to form grooves on the top of the fin structures. Grow silicon germanium in the grooves by epitaxial growth to form source and drain.
8. The method for reducing the chip load effect according to claim 1, wherein The chip includes PMOS and NMOS. Etching the chip to expose the area where PMOS is located on the chip includes: Form a hard mask layer and a photoresist on the surface of the chip. Etch the photoresist in the area where PMOS is located, and use the photoresist as a mask to remove the hard mask layer in the area where PMOS is located to expose the area where PMOS is located on the chip.
9. The method for reducing the chip load effect according to claim 8, wherein After S4, the method further includes: Cover the area where PMOS is located and expose the area where NMOS is located. Form source and drain in the area where NMOS is located.
10. A chip, characterized in that, Including: Manufactured by using the method for reducing the chip load effect according to any one of claims 1 - 9.