Nanostructure profiles in GAA and methods of forming same

Abstract

The invention discloses a nanostructure profile in GAA and a method of forming the same. A method includes forming a multilayer stack including a plurality of semiconductor layers and a plurality of sacrificial layers placed alternately. The method further includes forming a dummy gate stack on the multilayer stack, etching the multilayer stack to form a trench, epitaxially growing a semiconductor region in the trench to form a source / drain region, and removing the plurality of sacrificial layers from the multilayer stack. After removing the sacrificial layer, an etching process is performed. After the etching process, a gate stack is formed around the plurality of semiconductor layers.

Description

Technical Field

[0001] The present disclosure generally relates to the field of semiconductor technology, and more particularly to nanostructure profiles in gate-all-around (GAA) and methods for forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of materials over a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon.

[0003] The semiconductor industry has continuously improved the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size is reduced, other problems arise that need to be solved. Summary of the Invention

[0004] According to a first aspect of the present disclosure, there is provided a method for forming a semiconductor device, including: forming a multi-layer stack including a plurality of semiconductor layers and a plurality of sacrificial layers alternately disposed; forming a dummy gate stack on the multi-layer stack; etching the multi-layer stack to form trenches; epitaxially growing semiconductor regions in the trenches to form source / drain regions; removing the plurality of sacrificial layers from the multi-layer stack; after removing the sacrificial layers, performing an etching process; and after the etching process, forming a gate stack surrounding the plurality of semiconductor layers.

[0005] According to a second aspect of the present disclosure, there is provided a semiconductor device, including: a dielectric isolation region; a protruding structure higher than the dielectric isolation region, the protruding structure including: a plurality of semiconductor nanostructures, wherein an upper semiconductor nanostructure among the plurality of semiconductor nanostructures overlaps with a corresponding lower semiconductor nanostructure among the plurality of semiconductor nanostructures; a gate spacer located on a first portion of the protruding structure, wherein the plurality of semiconductor nanostructures includes a first portion overlapping with the gate spacer, and the first portion has a first height; and a gate stack including: a top located above the protruding structure; and a lower portion located between a second portion of the plurality of semiconductor nanostructures, wherein the second portion of the plurality of semiconductor nanostructures has a second height smaller than the first height.

[0006] According to a third aspect of the present disclosure, a semiconductor device is provided, including: a nanostructure transistor, including: a semiconductor nanostructure; a gate stack, wherein the gate stack surrounds the semiconductor nanostructure, and the gate stack includes: an upper portion, located above the semiconductor nanostructure and in contact with the semiconductor nanostructure; and a lower portion, located below the semiconductor nanostructure and in contact with the semiconductor nanostructure, wherein the upper portion and the lower portion respectively include a first portion and a second portion of the semiconductor nanostructure; and source / drain regions, located beside the semiconductor nanostructure and in contact with the semiconductor nanostructure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0008] Figures 1 to 4 、 Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figure 15A 、 Figure 15B 、 Figure 16A 、 Figure 16B 、 Figure 16C 、 Figure 17A 、 Figure 17B and Figure 17C show views of intermediate stages in forming a nanostructure transistor according to some embodiments.

[0009] Figures 18 to 20 、 Figure 21A 、 Figure 21B and Figure 21C show cross-sectional views of removing a sacrificial layer and forming an interface layer according to some embodiments.

[0010] Figure 22Illustrates a process flow for forming a nanostructure transistor according to some embodiments. Detailed Description

[0011] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or characters in various examples. Such repetition is for the purpose of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, spatially relative terms (such as "below", "beneath", "under", "overlying", "above", etc.) may be used herein to facilitate describing the relationship of one element or feature shown in the figures to another (one or more) element or (one or more) feature. In addition to the orientation depicted in the figures, spatially relative terms are also intended to encompass different orientations of the device in use or operation. The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0013] According to some embodiments, a gate-all-around (GAA) transistor (also referred to as a nanostructure transistor) and a method of forming the same are provided. Forming a GAA transistor includes: forming a multi-layer stack including semiconductor nanostructures and a sacrificial layer, and forming a dummy gate stack over the multi-layer stack. The dummy gate stack and the sacrificial layer are removed. Then, an etching process may be performed to remove a germanium mixed layer on the surface of the semiconductor nanostructures. The profile of the nanostructures is also shaped by the etching process.

[0014] The purpose of the embodiments discussed herein is to provide examples to enable the making or using of the subject matter of the present disclosure, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the scope of the different embodiments. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0015] Figures 1 to 4 、 Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 Figure 7A 、Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B and Figure 17C illustrate views of intermediate stages in forming a nanostructure transistor in accordance with some embodiments of the present disclosure. Figure 22 The corresponding processes are also schematically reflected in the process flow shown in

[0016] Referring to Figure 1 , a perspective view of a wafer 10 is shown. The wafer 10 includes a multi-layer structure that includes a multi-layer stack 22 on a substrate 20. According to some embodiments, the substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon germanium (SiGe) substrate, etc., but other substrates and / or structures may be used, such as semiconductor-on-insulator (SOI), strained SOI, silicon germanium-on-insulator, etc. The substrate 20 may be doped as a p-type semiconductor, but in other embodiments, it may be doped as an n-type semiconductor.

[0017] According to some embodiments, the multi-layer stack 22 is formed by a series of deposition processes for depositing alternating materials. The corresponding processes are shown as process 202 in the process flow 200 shown in Figure 22 . According to some embodiments, the multi-layer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material, the second semiconductor material being different from the first semiconductor material.

[0018] According to some embodiments, the first semiconductor material of the first layer 22A is formed of or includes: SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, etc. According to some embodiments, the first layer 22A (e.g., SiGe) is deposited by epitaxial growth, and the corresponding deposition method may be vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), etc. According to some embodiments, the first layer 22A is formed to have a first thickness in the range between about and about . However, any suitable thickness may be used while remaining within the scope of the embodiments.

[0019] Once the first layer 22A is deposited on the substrate 20, the second layer 22B is deposited on the first layer 22A. According to some embodiments, the second layer 22B is formed of or includes a second semiconductor material, such as Si, SiGe, Ge, GaAs, InSb, GasB, InAlAs, InGaAs, GasB, GaAsSB, and combinations thereof, etc., and the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments where the first layer 22A is silicon germanium, the second layer 22B may be formed of silicon, and vice versa. It should be understood that any suitable combination of materials may be used for the first layer 22A and the second layer 22B.

[0020] According to some embodiments, the second layer 22B is epitaxially grown on the first layer 22A using a deposition technique similar to that used for forming the first layer 22A. According to some embodiments, the second layer 22B is formed to have a thickness similar to that of the first layer 22A. However, the second layer 22B may also be formed to have a thickness different from that of the first layer 22A. According to some embodiments, the second layer 22B may be formed to have a second thickness, for example, in the range between about and about .

[0021] Once the second layer 22B is formed over the first layer 22A, the deposition process is repeated to form the remaining layers in the multi-layer stack 22 until the desired topmost layer of the multi-layer stack 22 is formed. According to some embodiments, the first layers 22A have the same or similar thicknesses to each other, and the second layers 22B have the same or similar thicknesses to each other. According to alternative embodiments, the first layers 22A may also have the same or different thicknesses as the second layers 22B. According to some embodiments, the first layer 22A is removed in a subsequent process and is alternatively referred to as the sacrificial layer 22A in the specification. According to alternative embodiments, the second layer 22B is removed in a subsequent process.

[0022] According to some embodiments, (some) liner oxide layers and hard mask layers (not shown) are formed over the multi-layer stack 22, and these layers are used for the patterning processes presented in the subsequent figures. These layers are patterned and are used to subsequently pattern the multi-layer stack 22.

[0023] Reference Figure 2 , the multi-layer stack 22 and a portion of the underlying substrate 20 are patterned in (one or more) etching processes such that trenches 23 are formed. The corresponding process is shown as process 204 in the process flow 200 shown in Figure 22 . The trenches 23 extend into the substrate 20. The remaining portion of the multi-layer stack is hereinafter referred to as the multi-layer stack 22'. Some portions of the underlying multi-layer stack 22' and the substrate 20 are left, and these portions of the substrate 20 are hereinafter referred to as the substrate strip 20'. The multi-layer stack 22' includes the semiconductor layer 22A and the semiconductor layer 22B. The semiconductor layer 22A is alternatively referred to as the sacrificial layer, and the semiconductor layer 22B is alternatively referred to as the nanostructure. The portions of the multi-layer stack 22' and the underlying substrate strip 20' are collectively referred to as the semiconductor strip 24.

[0024] In the above embodiments, the gate-all-around (GAA) transistor structures can be patterned by any suitable method. For example, one or more lithography processes (including double patterning processes or multi-patterning processes) can be used to pattern these structures. Generally, double patterning processes or multi-patterning processes combine lithography processes and self-alignment processes, thereby allowing the generation of patterns with, for example, pitches smaller than those achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and is patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. Then the sacrificial layer is removed, and then the remaining spacers can be used to pattern the GAA structure.

[0025] Figure 3 The formation of the isolation regions 26 is shown, and the isolation regions 26 are also referred to as shallow trench isolation (STI) regions in the specification. The corresponding process is shown in Figure 22The process shown in the process flow 200 is shown as process 206. The STI region 26 may include a liner oxide (not shown), which may be a thermal oxide formed by thermally oxidizing the surface layer of the substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, ALD, high-density plasma chemical vapor deposition (HDPCVD), CVD, etc. The STI region 26 may further include a dielectric material on top of the liner oxide, and the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, HDPVCD, etc. Then a planarization process (e.g., a chemical mechanical polishing (CMP) process or a mechanical grinding process) may be performed to make the top surface of the dielectric material flush, and the remaining part of the dielectric material is the STI region 26.

[0026] Then the STI region 26 is recessed such that the top of the semiconductor strip 24 protrudes higher than the top surface 26T of the remaining part of the STI region 26 to form a protruding fin 28. The protruding fin 28 includes the top of the multi-layer stack 22' and the substrate strip 20'. The recessing of the STI region 26 may be performed by a dry etching process, where, for example, NF3 and NH3 are used as etching gases. During the etching process, a plasma may be generated. Argon may also be included. According to an alternative embodiment of the present disclosure, the recessing of the STI region 26 is performed by a wet etching process. For example, the etching chemical may include HF.

[0027] Reference Figure 4 , a dummy gate stack 30 and gate spacers 38 are formed on the top surface and sidewalls of the (protruding) fin 28. The corresponding process is shown as process 208 in the process flow 200 shown in Figure 22 The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 on top of the dummy gate dielectric 32. The dummy gate dielectric 32 may be formed by oxidizing the surface portion of the protruding fin 28 to form an oxide layer. For example, polysilicon or amorphous silicon may be used to form the dummy gate electrode 34, and other materials such as amorphous carbon may also be used. Each dummy gate stack 30 may further include one (or more) hard mask layers 36 on top of the dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or a multi-layer thereof.

[0028] Forming the dummy gate stack 30 includes: forming a dummy gate dielectric layer, depositing a dummy gate electrode layer on top of the dummy gate dielectric layer, depositing one or more hard mask layers and then patterning the formed layers by (one or more) patterning processes.

[0029] Next, a gate spacer 38 is formed on the sidewalls of the dummy gate stack 30. According to some embodiments of the present disclosure, the gate spacer 38 is formed of a dielectric material (e.g., silicon nitride (SiN), silicon dioxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), etc.) and may have a single-layer structure or a multi-layer structure including multiple dielectric layers. The formation process of the gate spacer 38 may include: depositing one or more dielectric layers and then performing one or more anisotropic etching processes on the (one or more) dielectric layers. The remaining portion of the (one or more) dielectric layers is the gate spacer 38.

[0030] Figure 5A and Figure 5B shows Figure 4 a cross-sectional view of the structure shown. Figure 5A shows Figure 4 reference cross-section A1-A1 in, which cuts through the portion of the protruding fin 28 that is not covered by the gate stack 30 and the gate spacer 38 and is parallel to the gate length direction. Figure 5B shows Figure 4 reference cross-section B-B in, which is parallel to the length direction of the protruding fin 28.

[0031] Reference Figure 6A and Figure 6B , the portion of the protruding fin 28 that is not directly below the dummy gate stack 30 and the gate spacer 38 is recessed by an etching process to form a recess 42. The corresponding process is shown as process 210 in the process flow 200 shown in Figure 22 . For example, a dry etching process can be performed using tetramethylammonium hydroxide (TMAH) or the like to etch the multi-layer semiconductor stack 22' and the underlying substrate strip 20'. The bottom of the recess 42 is at least flush with the bottom of the multi-layer semiconductor stack 22' or may be lower than the bottom of the multi-layer semiconductor stack 22' (as shown in Figure 6B ). The etching can be anisotropic such that the sidewalls of the multi-layer semiconductor stack 22' facing the recess 42 are vertical and straight, as shown in Figure 6B .

[0032] Reference Figure 7A and Figure 7B and Figure 8A and Figure 8B , an internal spacer 44 is formed. The corresponding process is shown as process 212 in the process flow 200 shown in Figure 22 . According to some embodiments, forming the internal spacer 44 may include: laterally recessing the sacrificial semiconductor layer 22A to form a recess 41, as shown in Figure 7A and Figure 7B .

[0033] Once the sacrificial semiconductor layer 22A is laterally recessed to form the recess 41, a spacer material is deposited to fill the corresponding recess. The spacer material may be different from the material of the gate spacer 38 and may be a dielectric material including silicon (e.g., silicon oxycarbonitride (SiOCN), silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), etc.), while any other suitable material may also be used, such as a low-k material with a k value less than about 3.5 or a combination thereof. The spacer material may be deposited to a thickness in the range between, for example, about 2 nm and about 10 nm using a conformal deposition process (e.g., CVD, ALD, etc.).

[0034] Then, a dry etching and / or wet etching process is performed to remove the portion of the spacer material located on the sidewalls of the nanostructure 22B, such that the sidewalls of the nanostructure 22B are exposed. As Figure 8A and Figure 8B shown, the remaining portion of the spacer material is the spacer 44. The inner spacer 44 is used to isolate the subsequently formed gate structure from the subsequently formed source / drain regions and prevent damage to the source / drain regions during subsequent etching processes (e.g., the etching of the dummy gate stack 30).

[0035] Reference Figure 9A and Figure 9B , an epitaxial source / drain region 48 is formed in the recess 42. The corresponding process is shown as process 214 in the process flow 200 shown in Figure 22 . According to some embodiments, the source / drain region 48 may apply stress to the nanostructure 22B serving as the channel of the corresponding GAA transistor, thereby improving performance. Depending on whether the resulting transistor is a p-type transistor or an n-type transistor, p-type or n-type impurities may be doped in-situ as the epitaxy proceeds. For example, when the resulting transistor is a p-type transistor, silicon germanium boron (SiGeB), silicon boron (SiB), etc. may be grown.

[0036] Conversely, when the resulting transistor is an n-type transistor, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. may be grown. After the recess 42 is filled with the epitaxial region 48, further epitaxial growth of the epitaxial region 48 causes the epitaxial region 48 to expand horizontally, and facets may be formed. Further growth of the epitaxial region 48 may also cause adjacent epitaxial regions 48 to merge with each other.

[0037] The source / drain region 48 may include multiple sub-layers. For example, Figure 9A and Figure 9B (and Figure 18) shows an example where the source / drain region 48 includes multiple sub-layers 48A (also referred to as L0), 48B (L1), and 48C (L2). The sub-layers may have different compositions, such as different dopant concentrations and / or different percentages of Si, Ge, C atoms, etc. In subsequent figures, the sub-layers may not be shown, but they may still exist.

[0038] After the epitaxial process, the epitaxial region 48 can be further implanted with p-type or n-type impurities to form the source region and the drain region, and the source region and the drain region are also denoted by the reference numeral 48. According to an alternative embodiment of the present disclosure, the implantation process is skipped when the epitaxial region 48 is in-situ doped with p-type or n-type impurities during epitaxy.

[0039] According to some embodiments, the dopant in the source / drain region 48 can diffuse into the portion of the nanostructure 22B that overlaps with the gate spacer 38 to form Figure 18 the shown lightly doped source / drain (LDD) region 48LDD. It can also be formed, for example, Figure 6B during the shown process by performing an angled implantation process to introduce p-type or n-type dopants into the portion of the nanostructure 22B that overlaps with the gate spacer 38 to form the LDD region 48LDD.

[0040] In Figure 10A 、 Figure 10B and Figures 10C to 17A 、 Figure 17B and Figure 17C the subsequent reference numerals may have numbers followed by the letters A, B, or C, where the figures with reference numerals having the letter A represent that the corresponding figure shows the same reference cross-section as the reference cross-section A2 - A2 in Figure 4 ,the figures with reference numerals having the letter B represent that the corresponding figure shows the same reference cross-section as the reference cross-section B - B in Figure 4 ,and the figures with reference numerals having the letter C represent that the corresponding figure shows the same reference cross-section as the reference cross-section A1 - A1 in Figure 4 .

[0041] Figure 10A 、 Figure 10B and Figure 10C show cross-sectional views of the structure after forming the contact etch stop layer (CESL) 50 and the interlayer dielectric (ILD) 52. The corresponding processes are in Figure 22The process shown in FIG. 200 is shown as process 216. The CESL 50 can be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. The ILD 52 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or any other suitable deposition method. The ILD 52 can be formed of an oxygen-containing dielectric material, which can be silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0042] Figure 11A and Figures 11B to 15A and Figure 15B shows a process for forming an alternative gate stack. In Figure 11A and Figure 11B , a planarization process (e.g., a CMP process or a mechanical polishing process) can be performed to make the top surface of the ILD 52 flush. The corresponding process is shown as process 218 in the process flow 200 shown in Figure 22 . According to some embodiments, the planarization process can remove the hard mask 36 to expose the dummy gate electrode 34. According to alternative embodiments, the planarization process can expose the hard mask 36 and be stopped on the hard mask 36. According to some embodiments, after the planarization process, the top surfaces of the dummy gate electrode 34 (or the hard mask 36), the gate spacers 38, and the ILD 52 are horizontal within process variations.

[0043] Next, the dummy gate electrode 34 (and the hard mask 36, if remaining) is removed in one or more etching processes, thereby forming a recess 58, as shown in Figure 12A and 12B . The corresponding process is shown as process 220 in the process flow 200 shown in Figure 22 . Some portions of the dummy gate dielectric 32 in the recess 58 are also removed. According to some embodiments, the dummy gate electrode 34 and the dummy gate dielectric 32 are removed by an anisotropic dry etching process. For example, the etching process can be performed using a (one or more) reactive gas that selectively etches the dummy gate electrode 34 at a faster rate than the ILD 52. Each recess 58 exposes and / or overlies portions of the multilayer stack 22', which include the future channel regions in the subsequently completed nano-FETs. The portions of the multilayer stack 22' that serve as the channel regions are located between adjacent pairs of the epitaxial source / drain regions 48.

[0044] Then the recess 58 is extended downward between the nanostructures 22B, and the resulting structure is shown in Figure 13A and Figure 13B . In Figures 18 to 20 shows a process for formingFigure 13A and Figure 13B The detailed process of the structure shown in Figures 18 to 20 provides a magnified view.

[0045] Referring to Figure 18 , a part of the structure in Figure 13B is shown, in which the dummy gate stack is removed and the top nanostructure 22B is exposed. The sidewalls of the multi-layer stack 22' are exposed to the recess 58, which can be achieved from Figure 12A implementation.

[0046] According to some embodiments, due to interdiffusion, a mixed layer 59 is formed between the nanostructure 22B and the sacrificial layer 22A. According to some embodiments in which the sacrificial layer 22A includes silicon germanium and the nanostructure 22B includes silicon, the mixed layer 59 may further include silicon germanium having a lower percentage of germanium atoms than the sacrificial layer 22A. In addition, the portion of the mixed layer 59 closer to the sacrificial layer 22A has a higher percentage of germanium atoms than the corresponding portion of the mixed layer 59 closer to the nanostructure 22B. The mixed layer 59 may extend into the sacrificial layer 22A and the nanostructure 22B. The portion of the mixed layer 59 in the sacrificial layer 22A has a higher percentage of germanium atoms than the portion of the mixed layer 59 in the nanostructure 22B.

[0047] Next, an isotropic etching process 57A ( Figure 18 ) is performed using an etchant selective to the material of the sacrificial layer 22A to remove the sacrificial layer 22A from the side (refer to Figure 12A and Figure 13A ). Thus, the recess 58 extends into the region between the nanostructures 22B. The nanostructure 22B, the substrate 20, and the STI region 26 remain relatively unetched compared to the sacrificial layer 22A. Figure 19 The resulting structure is shown in Figure 22 . The corresponding process is shown as process 222 in the process flow 200 shown in

[0048] Because the composition of the sacrificial layer 22A (e.g., a higher percentage of germanium atoms) is different from that of the hybrid layer 59, at least some portions of the hybrid layer 59 near the nanostructure 22B are left after etching the sacrificial layer 22A. Depending on the etching duration, the exposed edges of the remaining hybrid layer 59 can be located at positions such as 59E1, 59E2, or 59E3. When the edge of the remaining hybrid layer 59 is at position 59E1, the upper or lower edge of the remaining hybrid layer 59 is coplanar with the interface between the LDD region 48LDD and the inner spacer 44. When the edge of the remaining hybrid layer 59 is at position 59E2 or 59E3, the remaining hybrid layer 59 can protrude beyond the interface between the LDD region 48LDD and the inner spacer 44, or be recessed backward from the interface between the LDD region 48LDD and the inner spacer 44.

[0049] Next, referring to Figure 19 , an etching process 57B is performed to remove the hybrid layer 59. The corresponding process is shown as process 224 in the process flow 200 shown in Figure 22 . The resulting structure is shown in Figure 20 . The etching process 57B can be performed by using an etching chemical different from that used when removing the sacrificial layer 22A. The etching chemical can etch germanium faster than silicon.

[0050] According to some embodiments, the etching process 57B includes a wet etching process, and the etching chemical can include a solution of a mixture of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and H2O. This etching can be performed outdoors at a temperature in the range of about 10 °C to about 90 °C. A high temperature (above room temperature, which can be about 21 °C) can improve the etching efficiency. The etching time can be in the range of about 100 seconds to about 1,000 seconds.

[0051] As a result of the etching process 58B, recesses 61 and 61T extending into the nanostructure 22B are formed, and the nanostructure 22B is thinned. For example, the portion of the nanostructure 22B forming the LDD region 48LDD can have a height H LDD , and the recessed portion of the nanostructure 22B can have a height H LDD less than height H 片 . The difference (H LDD -H 片 ) can be in the range of about 1 nm to about 4 nm. According to some embodiments, the height H 片 can be in the range of about 2 nm to about 8 nm, and can be in the range of about 3 nm to about 7 nm. The inter-chip spacing S 片It can be in the range between about 4 nm and about 12 nm, and can be in the range between about 6 nm and about 10 nm.

[0052] Height H LDD It can be in the range between about 3 nm and about 10 nm, and can be in the range between about 5 nm and about 9 nm. Inter-chip spacing S LDD It can be in the range between about 2 nm and about 13 nm, and can be in the range between about 4 nm and about 8 nm. Length L of the fin portion of nanostructure 22B 片 It can be in the range between about 5 nm and about 30 nm, and can be in the range between about 12 nm and about 24 nm. Length L of the LDD portion of nanostructure 22B LDD It can be in the range between about 2 nm and about 8 nm, and can be in the range between 3 nm and about 7 nm.

[0053] According to some embodiments, the fin portion of nanostructure 22B has a transition portion that connects the LDD region 48LDD to an intermediate fin portion having a height H 片 The transition portion has a gradually decreasing height, while the intermediate portion has a uniform height H 片 . The recess depth D1 of the recess 61 can be greater than 0 nm and less than about 6 nm, for example, in the range between about 1 nm and about 6 nm. Ratio D1 / H 片 , that is, the ratio of the recess depth D1 to the height H 片 can be greater than about 0.05 or greater than about 0.1, and can be in the range between about 0.05 and about 0.2 or in the range between about 0.1 and about 0.2, while smaller or higher values can be adopted. Different recesses 61 can also have the same depth D1, for example, the variation is less than about 10%. The length Lt of the transition portion of nanostructure 22B can also be greater than 0 nm and less than about 6 nm, for example, in the range between about 1 nm and about 6 nm.

[0054] Due to the etching process 57B for removing the mixed layer 59, the top surface of the topmost nanostructure 22B can also be recessed to form a recess 61T. According to some embodiments, since no mixed layer is formed at the top surface of the topmost nanostructure 22B, and also because the etching rate of silicon is lower than the etching rates of germanium and silicon-germanium during the etching process 57B, the recess depth D2 of the recess 61T is less than the depth D1 of the underlying recess 61. According to some embodiments, the ratio D2 / D1 is less than about 2 / 3, and can be less than about 1 / 2, while the recess depths of all the underlying recesses 61 can be equal to or substantially equal to each other, for example, the variation is less than about 10%.

[0055] The exposed surface of the nanostructure 22B can have various profiles. For example, the illustrated surface of the transition portion of the nanostructure 22B has a curved surface. Alternatively, as shown by the dashed line, the surface of the transition portion of the nanostructure 22B can be straight and inclined. The inclination angle θ can be less than about 60°, and can be in the range between about 15° and about 45°.

[0056] According to an alternative embodiment, due to process variations, the recess 61 can extend horizontally to form an undercut portion that overlaps the edge portions of the gate spacer 38 and the inner spacer 44. Accordingly, the top and bottom surfaces of the inner spacer 44 and the gate spacer 38 can be exposed to the edge portions of the overlying and underlying recesses 61 and / or recess 62T.

[0057] Reference Figure 20 , after the etching process 57B, a cleaning process 57C can be performed using a chemical different from the etching chemical used in the etching process 57B. The corresponding process is shown as process 226 in the process flow 200 shown in Figure 22 . According to some embodiments, the cleaning process can be performed by a dry etching process using a mixture of HF gas and NH3 gas. Accordingly, any oxides and other residues (such as nitrogen-containing chemicals and fluorine-containing chemicals) formed on the nanostructure 22B are removed. The cleaning process 57C can be performed non-in-situ with respect to the etching process 57B (e.g., the etching process 57B performed outdoors and the etching process 57C performed in a vacuum chamber). Additionally, the cleaning process 57C can be performed, and the subsequent formation of the gate dielectric can be performed in-situ in the same vacuum environment without a vacuum interruption therebetween.

[0058] After the cleaning process 57C, as Figure 14A and Figure 14B shown, the gate dielectric 66 is formed. The corresponding process is shown as process 228 in the process flow 200 shown in Figure 22 . The gate dielectric 66 can include an interface layer (IL) and a high-k dielectric layer located above the IL. Figure 21A The formation of the interface layer 62 is shown. The interface layer 62 can be formed of or include silicon oxide and is also referred to as the oxide layer 62. If an undercut portion ( Figure 20 ) is formed, the gate dielectric 66 (and possibly the gate electrode) also extends into the undercut portion.

[0059] The formation of the interface layer 62 can include a thermal oxidation process, a chemical oxidation process, a deposition process, etc. When a deposition process is performed, the IL 62 also extends on the surface of the dielectric material. Figure 21A The IL 62 shown has a profile formed by oxidizing the nanostructure 22B.

[0060] Figure 21B shows Figure 21A the cross-section 21B-21B shown, where the IL 62 is formed to surround the nanostructure 22B. Due to the etching process 57B, the corners of the nanostructure 22B are rounded. For example, Figure 21C shows Figure 21B a magnified view of a part of the structure shown. According to some embodiments, the curvature 1 / R of the corners of the nanostructure 22B 片 can be less than about 2 nm -1 , which means that the corners can fit a circle with a radius R 片 , and the radius R 片 can be greater than about 2 nm.

[0061] Returning to reference Figure 14A and Figure 14B , the gate dielectric 66 shown includes Figure 21A the IL 62 shown and a high-k dielectric layer (not shown separately) on the IL 62. The high-k dielectric layer is conformally deposited in the recess 58, where different parts of the high-k dielectric layer have a uniform thickness. The high-k dielectric layer can also be deposited on the top surfaces of the ILD 52, the CESL 50, the gate spacers 38, and the STI regions 26. According to some embodiments, the high-k dielectric layer is formed by a conformal deposition method (such as ALD, CVD, etc.) such that the horizontal parts, the vertical parts, and the corner parts have the same thickness.

[0062] According to some embodiments, the high-k dielectric layer includes one or more dielectric layers, such as one or more metal oxide layers. For example, according to some embodiments, the high-k dielectric layer can be formed of or include a high-k dielectric material that can have a k value greater than about 7.0 and can include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof.

[0063] Referring Figure 15A and Figure 15B , a gate electrode 68 is deposited over the high-k dielectric layer. The corresponding process is shown as process 230 in the process flow 200 shown in Figure 22 . The gate electrode 68 can include a metal-containing material, for example, TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, and combinations and / or multilayers thereof. For example, although a single-layer gate electrode 68 is shown, the gate electrode 68 can include any number of layers, any number of work function layers, and filling materials. The gate electrode 68 can be deposited to fill the space between adjacent nanostructures 22B in the nanostructure 22B and the space between the bottom nanostructure 22B in the nanostructure 22B and the underlying substrate strip 20'.

[0064] After filling the recess 58, a planarization process (e.g., CMP process or mechanical polishing process) is performed to remove the excess portions of the high-k dielectric layer and the gate electrode 68 that are located above the top surface of the ILD 52. The gate electrode 68 and the gate dielectric 66 (including the oxide layer 62 and the high-k dielectric layer) are collectively referred to as the gate stack 70 of the resulting nanometer FET.

[0065] In Figure 16A , Figure 16B and Figure 16C In the processes shown, the gate stack 70 (including the high-k dielectric layer and the corresponding overlying gate electrode 68) is recessed such that a recess is formed between directly above the gate stack 70 and opposite portions of the gate spacers 38. A gate mask 74 including one or more dielectric materials (e.g., silicon nitride, silicon oxynitride, etc.) is filled in each of the recesses, and then a planarization process is performed to remove the excess portions of the dielectric material that extend beyond the first ILD 52.

[0066] As Figure 16A , Figure 16B and Figure 16C Further shown, an ILD 76 is deposited over the ILD 52 and the gate mask 74. The corresponding process is shown as process 232 in the process flow 200 shown in Figure 22 . An etch stop layer (not shown) may or may not be deposited before forming the ILD 76. According to some embodiments, the ILD 76 is formed by FCVD, CVD, PECVD, etc. The ILD 76 is formed of a dielectric material that may be selected from silicon oxide, PSG, BSG, BPSG, USG, etc.

[0067] In Figure 17A , Figure 17B and Figure 17C , the ILD 76, the ILD 52, the CESL 50, and the gate mask 74 are etched to form recesses (occupied by contact plugs 80A and contact plugs 80B) that expose the surface of the epitaxial source / drain regions 48 and / or the gate stack 70. The recesses can be formed by etching using an anisotropic etching process (e.g., RIE, NBE, etc.). According to some embodiments, the recesses can be formed by etching the ILD 76 and the ILD 52 using a first etching process, etching the gate mask 74 using a second etching process, and possibly etching the CESL 50 using a third etching process. Although the contact plugs 80A and the contact plugs 80B are shown as being located in the same cross-section, in various embodiments, the contact plugs 80A and the contact plugs 80B can be formed in different cross-sections to reduce the risk of shorting to each other.

[0068] After forming the recess, a silicide region 78 is formed over the epitaxial source / drain region 48. The corresponding process is shown as process 234 in process flow 200 shown in Figure 22 According to some embodiments, the silicide region 78 is formed by first depositing a metal layer (not shown) that is capable of reacting with the semiconductor material (e.g., silicon, silicon germanium, germanium) of the underlying epitaxial source / drain region 48 to form a silicide region and / or a germanide region, and then performing a thermal annealing process to form the silicide region 78. The metal can include nickel, cobalt, titanium, tantalum, platinum, tungsten, etc. Then, the unreacted portion of the deposited metal is removed, for example, by an etching process.

[0069] Then, a contact plug 80B is formed over the silicide region 78. In addition, a contact plug 80A (which can also be referred to as a gate contact plug) is also formed in the recess, and is located over and in contact with the gate electrode 68. The corresponding process is shown as process 236 in process flow 200 shown in Figure 22 The contact plug 80A and the contact plug 80B can each include one or more layers, such as a barrier layer, a diffusion layer, and a fill material. For example, according to some embodiments, the contact plug 80A and the contact plug 80B each include a barrier layer and a conductive material, and are electrically coupled to the underlying conductive features (e.g., the gate stack 70 and / or the silicide region 78 in the illustrated embodiment). The barrier layer can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process (e.g., a CMP process) can be performed to remove excess material from the surface of the ILD 76. Thereby, the nano-FET 82 is formed.

[0070] Embodiments of the present disclosure have some advantageous features. By etching the hybrid layer, possible degradation of the resulting transistor is avoided. In addition, by adjusting the etching process for etching the hybrid layer, the profile of the nanosheets (channels) is shaped such that the width of the nanosheets gradually decreases from the LDD region to the narrowed nanosheets. Thereby, the current crowding effect is reduced. Since the height of the silicon nanosheets is reduced, the drain-induced barrier lowering (DIBL) effect is reduced.

[0071] According to some embodiments of the present disclosure, a method includes: forming a multi-layer stack including a plurality of semiconductor layers and a plurality of sacrificial layers alternately placed; forming a dummy gate stack over the multi-layer stack; etching the multi-layer stack to form trenches; epitaxially growing semiconductor regions in the trenches to form source / drain regions; removing the plurality of sacrificial layers from the multi-layer stack; after removing the sacrificial layers, performing an etching process; and after the etching process, forming a gate stack surrounding the plurality of semiconductor layers.

[0072] In an embodiment, a first etch chemical is used to remove the plurality of sacrificial layers, and a second etch chemical different from the first etch chemical is used to perform the etch process. In an embodiment, the plurality of semiconductor layers are silicon layers, the plurality of sacrificial layers include germanium, and wherein a remaining silicon and germanium mixed layer is etched by the etch process. In an embodiment, the etch process is performed using an etch chemical that etches germanium at a rate higher than the rate of etching silicon.

[0073] In an embodiment, the plurality of sacrificial layers are removed by a dry etch process, and the etch process is performed by a wet etch process. In an embodiment, the etch process is performed using a mixture of NH4OH, H2O2, and H2O. In an embodiment, the method further includes performing a cleaning process after the etch process.

[0074] In an embodiment, the cleaning process is performed by a dry etch process. In an embodiment, a semiconductor layer among the plurality of semiconductor layers includes a first portion forming a lightly doped source / drain region and a second portion in contact with a gate stack, and wherein the first portion has a first height greater than a second height of the second portion. In an embodiment, the etch process is performed at a high temperature above room temperature.

[0075] According to some embodiments of the present disclosure, a device includes: a dielectric isolation region; a protruding structure, above the dielectric isolation region, the protruding structure includes: a plurality of semiconductor nanostructures, wherein an upper semiconductor nanostructure among the plurality of semiconductor nanostructures overlaps a corresponding lower semiconductor nanostructure among the plurality of semiconductor nanostructures; a gate spacer, located on a first portion of the protruding structure, wherein the plurality of semiconductor nanostructures includes a first portion overlapping the gate spacer, and the first portion has a first height; and a gate stack, including: a top, above the protruding structure; and a lower portion, between a second portion of the plurality of semiconductor nanostructures, wherein the second portion of the plurality of semiconductor nanostructures has a second height less than the first height.

[0076] In an embodiment, a lower portion among the lower portions of the gate stack extends into the plurality of semiconductor nanostructures to a recess depth in a range between about 1 nm and about 6 nm. In an embodiment, the second portion includes a transition portion connected to the first portion, and a height of the transition portion gradually decreases. In an embodiment, the plurality of semiconductor nanostructures includes a topmost semiconductor nanostructure, the gate stack extends from the top into the topmost semiconductor nanostructure to a first recess depth and extends from the bottom into the topmost semiconductor nanostructure to a second recess depth, and the second recess depth is greater than the first recess depth. In an embodiment, a ratio of the first recess depth to the second recess depth is less than about 2 / 3. In an embodiment, the gate stack includes an undercut portion overlapping an edge portion of the gate spacer.

[0077] According to some embodiments of the present disclosure, a device includes: a nanostructure transistor including: a semiconductor nanostructure;

[0078] a gate stack, wherein the gate stack surrounds the semiconductor nanostructure, and the gate stack includes: an upper portion located above and in contact with the semiconductor nanostructure; and a lower portion located below and in contact with the semiconductor nanostructure, wherein the upper and lower portions respectively include a first portion and a second portion of the semiconductor nanostructure; and source / drain regions located beside and in contact with the semiconductor nanostructure.

[0079] In an embodiment, the first portion extends into the semiconductor nanostructure to a first recess depth, while the second portion extends into the semiconductor nanostructure to a second recess depth equal to the first recess depth. In an embodiment, the first portion extends into the semiconductor nanostructure to a first recess depth, while the second portion extends into the semiconductor nanostructure to a second recess depth greater than the first recess depth.

[0080] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

[0081] Example

[0082] Example 1. A method for forming a semiconductor device includes: forming a multi-layer stack including a plurality of alternating semiconductor layers and a plurality of sacrificial layers; forming a dummy gate stack on the multi-layer stack; etching the multi-layer stack to form trenches; epitaxially growing semiconductor regions in the trenches to form source / drain regions; removing the plurality of sacrificial layers from the multi-layer stack; after removing the sacrificial layers, performing an etching process; and after the etching process, forming a gate stack around the plurality of semiconductor layers.

[0083] Example 2. The method according to Example 1, wherein the plurality of sacrificial layers are removed using a first etching chemical, and the etching process is performed using a second etching chemical different from the first etching chemical.

[0084] Example 3. The method according to Example 1, wherein the plurality of semiconductor layers are silicon layers, the plurality of sacrificial layers include germanium, and a mixed layer of the remaining silicon and germanium is etched by the etching process.

[0085] Example 4. The method according to Example 3, wherein the etching process is performed using an etching chemical that etches germanium at a rate higher than the rate of etching silicon.

[0086] Example 5. The method according to Example 1, wherein the plurality of sacrificial layers are removed by a dry etching process and the etching process is performed by a wet etching process.

[0087] Example 6. The method according to Example 1, wherein the etching process is performed using a mixture of NH4OH, H2O2, and H2O.

[0088] Example 7. The method according to Example 1, further comprising: performing a cleaning process after the etching process.

[0089] Example 8. The method according to Example 7, wherein the cleaning process is performed by a dry etching process.

[0090] Example 9. The method according to Example 1, wherein a semiconductor layer in the plurality of semiconductor layers includes a first portion that forms a lightly doped source / drain region and a second portion that contacts the gate stack, and wherein the first portion has a first height greater than a second height of the second portion.

[0091] Example 10. The method according to Example 1, wherein the etching process is performed at a high temperature above room temperature.

[0092] Example 11. A semiconductor device, comprising: a dielectric isolation region; a protruding structure above the dielectric isolation region, the protruding structure comprising: a plurality of semiconductor nanostructures, wherein an upper semiconductor nanostructure among the plurality of semiconductor nanostructures overlaps a corresponding lower semiconductor nanostructure among the plurality of semiconductor nanostructures; a gate spacer on a first portion of the protruding structure, wherein the plurality of semiconductor nanostructures includes a first portion that overlaps the gate spacer and the first portion has a first height; and a gate stack, comprising: a top above the protruding structure; and a lower portion between a second portion of the plurality of semiconductor nanostructures, wherein the second portion of the plurality of semiconductor nanostructures has a second height less than the first height.

[0093] Example 12. The semiconductor device according to Example 11, wherein one of the lower portions of the gate stack extends into the plurality of semiconductor nanostructures to a recess depth in a range between about 1 nm and about 6 nm.

[0094] Example 13. The semiconductor device according to Example 11, wherein one of the lower portions of the gate stack extends into one of the plurality of semiconductor nanostructures to a recess depth, and the ratio of the recess depth to one of the first heights is greater than about 0.1.

[0095] Example 14. The semiconductor device according to Example 11, wherein the second portion includes a transition portion coupled to the first portion, and the height of the transition portion gradually decreases.

[0096] Example 15. The semiconductor device according to Example 11, wherein the plurality of semiconductor nanostructures includes a topmost semiconductor nanostructure, the gate stack extends into the topmost semiconductor nanostructure from the top to a first recess depth and from the bottom to a second recess depth, and the second recess depth is greater than the first recess depth.

[0097] Example 16. The semiconductor device according to Example 15, wherein the ratio of the first recess depth to the second recess depth is less than about 2 / 3.

[0098] Example 17. The semiconductor device according to Example 11, wherein the gate stack includes an undercut portion that overlaps an edge portion of the gate spacer.

[0099] Example 18. A semiconductor device, comprising: a nanostructure transistor, comprising: a semiconductor nanostructure; a gate stack, wherein the gate stack surrounds the semiconductor nanostructure, the gate stack includes: an upper portion, located above the semiconductor nanostructure and in contact with the semiconductor nanostructure; and a lower portion, located below the semiconductor nanostructure and in contact with the semiconductor nanostructure, wherein the upper portion and the lower portion respectively include a first portion and a second portion of the semiconductor nanostructure; and source / drain regions, located beside the semiconductor nanostructure and in contact with the semiconductor nanostructure.

[0100] Example 19. The semiconductor device according to Example 18, wherein the first portion extends into the semiconductor nanostructure to a first recess depth, and the second portion extends into the semiconductor nanostructure to a second recess depth equal to the first recess depth.

[0101] Example 20. The semiconductor device according to Example 18, wherein the first portion extends into the semiconductor nanostructure to a first recess depth, and the second portion extends into the semiconductor nanostructure to a second recess depth greater than the first recess depth.

Claims

1. A method for forming a semiconductor device, comprising: forming a multi-layer stack including a plurality of semiconductor layers and a plurality of sacrificial layers alternately placed; forming a dummy gate stack on the multi-layer stack; etching the multi-layer stack to form trenches; epitaxially growing a semiconductor region in the trenches to form source / drain regions; removing the plurality of sacrificial layers from the multi-layer stack; performing an etching process after the plurality of sacrificial layers are removed; and forming a gate stack surrounding the plurality of semiconductor layers after the etching process.

2. The method according to claim 1, wherein The plurality of sacrificial layers are removed using a first etching chemical, and the etching process is performed using a second etching chemical different from the first etching chemical.

3. The method according to claim 1, wherein The plurality of semiconductor layers are silicon layers, the plurality of sacrificial layers include germanium, and a mixed layer of the remaining silicon and germanium is etched by the etching process.

4. The method according to claim 3, wherein, The etching process is performed using an etching chemical with a higher etching rate for germanium than for silicon.

5. The method according to claim 1, wherein The plurality of sacrificial layers are removed by a dry etching process, and the etching process is performed by a wet etching process.

6. The method according to claim 1, wherein The etching process is performed using a mixture of NH4OH, H2O2, and H2O.

7. The method according to claim 1 further comprises: Performing a cleaning process after the etching process.

8. The method according to claim 7, wherein The cleaning process is performed by a dry etching process.

9. A semiconductor device, comprising: Dielectric isolation regions; Protruding structures, higher than the dielectric isolation regions, the protruding structures comprising: a plurality of semiconductor nanostructures, wherein an upper semiconductor nanostructure among the plurality of semiconductor nanostructures overlaps with a corresponding lower semiconductor nanostructure among the plurality of semiconductor nanostructures; gate spacers, located on a first portion of the protruding structure, wherein the plurality of semiconductor nanostructures include a first portion overlapping with the gate spacers, and the first portion has a first height; and a gate stack, comprising: a top, located above the protruding structure; and a lower portion, located between a second portion of the plurality of semiconductor nanostructures, wherein the second portion of the plurality of semiconductor nanostructures has a second height smaller than the first height.

10. A semiconductor device, comprising: a nanostructure transistor, comprising: semiconductor nanostructures; a gate stack, wherein the gate stack surrounds the semiconductor nanostructures, and the gate stack comprises: an upper portion, located above and in contact with the semiconductor nanostructures; and a lower portion, located below and in contact with the semiconductor nanostructures, wherein the upper and lower portions respectively include a first portion and a second portion of the semiconductor nanostructures; and source / drain regions, located beside and in contact with the semiconductor nanostructures.

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