Integrated circuit and forming method thereof

Abstract

A method of forming an integrated circuit includes forming a source / drain region connected to a channel of a plurality of transistors, and forming a silicide in contact with the source / drain region. The method includes depositing a first metal layer of a source / drain contact of the transistor on the silicide using a first deposition process, and patterning the silicide by performing an etching process using the first metal layer as a mask. A second metal layer of the source / drain contact is then deposited on the first metal layer. The first metal layer is laterally wider than the second metal layer. Embodiments of the invention relate to an integrated circuit and a method of forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated circuits and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit industry has experienced rapid growth. Technological advances in integrated circuit materials and design have produced several generations of integrated circuits, each of which has smaller and more complex circuits than the previous one. During the development of integrated circuits, typically the functional density (i.e., the number of interconnected devices per chip area) has increased while the geometric size (i.e., the smallest component (or wire) that can be produced using the manufacturing process) has decreased. This scaling process generally provides benefits by increasing production efficiency and reducing related costs. This scaling also increases the complexity of processing and manufacturing integrated circuits. Summary of the Invention

[0003] Some embodiments of the present application provide a method of forming an integrated circuit, including: forming source / drain regions connected to channels of a plurality of transistors; forming a silicide layer in contact with the source / drain regions; depositing a first metal layer of source / drain contacts of the transistors on the silicide layer using a first deposition process; and patterning the silicide layer by implementing an etching process using the first metal layer as a mask.

[0004] Some other embodiments of the present application provide an integrated circuit, including: transistors, including: a plurality of stacked channels; source / drain regions in contact with each of the stacked channels and including a concave top surface; a silicide layer on the top surface of the source / drain regions; an etch stop layer on the top surface of the source / drain regions; a first dielectric layer on sidewalls of the etch stop layer; and metal source / drain contacts, including a lower region in contact with the silicide layer below the first dielectric layer, and an upper region laterally adjacent to sidewalls of the first dielectric layer.

[0005] Some other embodiments of the present application provide a method of forming an integrated circuit, including: forming gate metals of the transistors above stacked channels of a plurality of transistors; forming a silicide layer in contact with a top surface of a source / drain region in a trench above the source / drain regions of the transistors; forming a first metal layer of source / drain contacts of the transistors on the silicide layer in the trench; forming a dielectric layer on the first metal layer in the trench; and patterning the dielectric layer to expose the first metal layer in the trench. Brief Description of the Drawings

[0006] As will be best understood from the following detailed description when read in conjunction with the accompanying drawings, it should be noted that the various components are not drawn to scale in accordance with standard practice in the industry. In fact, for the sake of clear discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0007] Figures 1 - 22 are cross-sectional views, top views, and perspective views of an integrated circuit at different processing stages according to some embodiments;

[0008] Figure 23 is a flowchart of a method for operating an integrated circuit according to some embodiments;

[0009] Figure 24 is a flowchart of a method for operating an integrated circuit according to some embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. Additionally, the present invention may repeat reference numerals and / or letters in various instances. This repetition is for the purpose of simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] Moreover, for ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to easily describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientation shown in the figures, spatially relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0012] Terms indicating relative degree, such as "about", "substantially", etc., should be interpreted as terms that would be understood by a person of ordinary skill in the art according to the current technical specifications.

[0013] The present invention generally relates to semiconductor devices, and more particularly to field effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructure devices. Examples of nanostructure devices include gate-all-around (GAA) devices, nanosheet FETs (NSFETs), nanowire FETs (NWFETs), etc. In advanced technology nodes, the active region pitch between nanostructure devices is typically uniform, the source / drain epitaxial structure is symmetric, and the metal gate surrounds the four sides of the nanostructure (e.g., nanosheet).

[0014] Embodiments of the present invention provide an integrated circuit that includes a transistor having source / drain contacts with improved electrical characteristics. A silicide is provided between the semiconductor source / drain region and the source / drain contacts. A first source / drain contact metal is formed on the silicide, and the silicide is patterned in the presence of the first source / drain contact metal. Then, a second source / drain contact metal is deposited on the first source / drain contact metal. The silicide has a relatively large area to help reduce the resistance between the source / drain contacts and the source / drain region. Since the resistance is reduced by increasing the silicide area, the critical dimension of the source / drain contacts can be reduced. This further increases the scalability of the source / drain contacts and reduces the capacitance between the source / drain contacts and the gate metal. This enables the transistor to have an increased processing speed, reduced power consumption, and reduced area consumption. This further enables the integrated circuit to function better.

[0015] Figures 1 - 22 are a cross-sectional view, a top view, and a perspective view of an integrated circuit 100 fabricated according to some embodiments of the present invention. The manufacturing process produces a plurality of transistors 101, as will be described in further detail below.

[0016] Figure 1 is a perspective view of the integrated circuit 100 in an intermediate state of processing. The integrated circuit 100 includes a substrate 102. The substrate 102 can be a semiconductor substrate, such as a bulk semiconductor, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped. The semiconductor material of the substrate 102 can include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates can be used, such as single-layer substrates, multi-layer substrates, or graded substrates.

[0017] Integrated circuit 100 includes a semiconductor stack 103, and the semiconductor stack 103 includes a plurality of semiconductor layers 104 and sacrificial semiconductor layers 106 that alternate with each other. As will be elaborated in further detail below, the semiconductor layers 104 will be patterned to form the channels of a stack of multiple transistors. As will be elaborated in more detail below, the sacrificial semiconductor layers 106 will ultimately be completely removed and are used to form gate metals and other structures around the semiconductor nanostructures. In Figure 1 three semiconductor layers 104 and three sacrificial semiconductor layers 106 are shown. In some embodiments, the multi-layer stack 103 may include fewer or more layers than Figure 1 shown in

[0018] In some embodiments, the semiconductor layer 104 may be formed of a suitable first semiconductor material such as silicon, silicon carbide, etc., and the sacrificial semiconductor layer 106 may be formed of a second semiconductor material such as silicon germanium. Processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. can be used to epitaxially grow each layer of the multi-layer stack 103.

[0019] Due to the high etch selectivity between the materials of the semiconductor layer 104 and the sacrificial semiconductor layer 106, the sacrificial semiconductor layer 106 of the second semiconductor material can be removed without significantly etching the semiconductor layer 104 of the first semiconductor material, thereby allowing the semiconductor layer 104 to be released to form the channel regions of the stack of transistors, as will be elaborated in more detail below.

[0020] In Figure 2A trenches 110 are formed in the stack 103 and the substrate 102. Although not shown in Figure 1 a hard mask layer is first formed and patterned on the stack 103. The trenches 110 can be formed by an anisotropic etching process that etches in a downward direction in the presence of the patterned hard mask. The etching process defines semiconductor fins 112 by forming trenches 110 that pass through the sacrificial semiconductor layer 106, the semiconductor layer 104, and the substrate 102.

[0021] Figure 2B is a top view of the integrated circuit 100 according to some embodiments of Figure 2A Figure 2B The top view shows fins 112 extending in the X direction and trenches 110 between the fins 112. The substrate 102 is visible in the trenches 110. The topmost semiconductor layer 106 is visible on top of the fins 112. As previously elaborated, in practice, the hard mask layer may be located on top of the topmost semiconductor layer 106. Figure 2BCutting lines X and Y are also shown. A cross-sectional view along cutting line Y may be referred to as a "Y view". A cross-sectional view along cutting line X may be referred to as an "X view".

[0022] Figure 3 is a cross-section of the Y view according to some embodiments. In Figure 3 , a shallow trench isolation region 116 is formed by depositing a dielectric material in the trench 110 between the fins 112. The shallow trench isolation region 116 can be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes. In an exemplary embodiment, the shallow trench isolation region includes silicon oxide. However, the shallow trench isolation region can include SiN, SiCN, SiOC, SiOCN, or other dielectric materials without departing from the scope of the present invention. After depositing the dielectric material, an etch-back process is implemented to recess the top of the shallow trench isolation region 116 below the lowest sacrificial semiconductor layer 106.

[0023] Figure 4 is the X view of the integrated circuit 100 according to some embodiments. In Figure 4 , a sacrificial gate structure 118 is formed over the fins 112. The sacrificial gate structure 118 extends in the Y direction perpendicular to the fins 112. Each sacrificial gate structure 118 passes through a plurality of fins 112. The sacrificial gate structure 118 is also formed in the trench 110.

[0024] The sacrificial gate structure 118 includes a dielectric layer 126. In an exemplary embodiment, the dielectric layer 126 includes silicon oxide. However, alternatively, the dielectric layer 126 can include SiN, SiCN, SiOC, SiOCN, or other dielectric materials without departing from the scope of the present invention. In some embodiments, the dielectric layer 126 has a low-K dielectric material. The dielectric layer 126 can be deposited by CVD, ALD, or PVD.

[0025] The sacrificial gate structure includes a sacrificial gate layer 128 on the dielectric layer 126. The sacrificial gate layer 128 can include a material having a high etch selectivity relative to the trench isolation region 116. In an exemplary embodiment, the sacrificial gate layer 128 includes polysilicon. However, the sacrificial gate layer 128 can be a conductor, semiconductor, or non-conductive material and can be or include amorphous silicon, poly-silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The sacrificial gate layer 128 can be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material.

[0026] The sacrificial gate structure 118 includes a dielectric layer 130 on the sacrificial gate layer 128 and a dielectric layer 132 on the dielectric layer 130. The dielectric layers 130 and 132 can correspond to a first mask layer and a second mask layer. The dielectric layer 130 can include silicon nitride, silicon oxynitride, or other suitable dielectric materials. The dielectric layer 132 can include silicon nitride, silicon oxynitride, or other suitable dielectric materials. The dielectric layers 130 and 132 are different materials from each other and can be deposited using CVD, ALD, PVD, or other suitable deposition processes. Other materials and deposition processes can be used for the dielectric layers 130 and 132 without departing from the scope of the present invention.

[0027] A gate spacer layer 134 is formed on the sidewalls of the layers 126, 128, 130, and 132. The gate spacer layer 134 can also be formed on other exposed surfaces of the integrated circuit. The gate spacer layer 134 can be formed by PVD, CVD, ALD, or other suitable deposition processes. After forming the gate spacer layer 134, the horizontal portions (e.g., along the X-Y plane) of the gate spacer layer 134 can be removed by an anisotropic etching process, thereby exposing the fins 112 and the upper surface of the dielectric layer 134. After patterning the gate spacer layer, the vertically thicker portions of the gate spacer layer 134 remain, as Figure 4 shown in the figure. The gate spacer layer 134 can include one or more of SiO, SiN, SiON, SiCN, SiOCN, SiOC, or other suitable dielectric materials.

[0028] After patterning the gate spacer layer 134, an etching process is implemented to form source / drain trenches 120 in the fins 112. One or more etching processes are implemented to form source / drain trenches 120 in the fins 112. Forming the source / drain trenches 120 includes etching through each of the semiconductor layer 104 and the sacrificial semiconductor layer 106, as well as a portion of the substrate 102. Accordingly, the removal operation can include suitable etching operations for removing the materials of the semiconductor layer 104, the sacrificial semiconductor layer 106, and the substrate 102. The etching process can include reactive ion etching (RIE), neutral beam etching (NBE), atomic layer etching (ALE), etc.

[0029] The formation of the source / drain trenches 120 causes the formation of a stack of the channel 105. In particular, the portion of the semiconductor layer 104 after forming the source / drain trenches 120 currently corresponds to the channel of the transistor. The formation of the source / drain trenches 120 also causes the formation of a plurality of sacrificial semiconductor nanostructures 107 from the sacrificial semiconductor layer 106.

[0030] A large number of source / drain trenches 120 are formed in the fin 112. The stack 122 of the channel 105 is located between each source / drain layer. Each stack 122 of the channel 105 corresponds to the stacked channel 105 of the transistor.

[0031] In Figure 5 , an internal spacer 136 is formed. A selective etching process is implemented to recess the exposed ends of the sacrificial semiconductor nanostructures 107, while substantially not etching the sacrificial semiconductor nanostructures 107. Next, the recesses between the channels 105 formed by the previous selective etching process of the sacrificial semiconductor nanostructures 107 are filled by depositing a dielectric material to form the internal spacer 136. The internal spacer 136 can be a suitable dielectric material, such as silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), etc., and is formed by a suitable deposition method, such as physical vapor deposition (PVD), CVD, ALD, etc. An etching process, such as an anisotropic etching process, is implemented to remove the portions of the internal spacer 136 that are outside the recesses provided in the sacrificial semiconductor nanostructures 107. The remaining portion of the dielectric layer corresponds to the internal spacer 136 shown in Figure 5 .

[0032] In Figure 6 , a source / drain region 140 is formed. In the illustrated embodiment, the source / drain region 140 grows epitaxially from the channel 105. The source / drain region 140 grows on the exposed portion of the fin 112 and contacts the channel 105. For each stack 122 of the channel 105, there are two source / drain regions 140. Some stacks 122 of the channel 105 may share the source / drain region 140 with the stacks 122 of the channel 105 adjacent along the X direction.

[0033] Although not shown, dielectric support elements corresponding to the remaining portions of the gate spacer layer 134 on the trench isolation region 116 can laterally limit the growth of the source / drain region 140. In some embodiments, the source / drain region 140 applies stress in the corresponding channel 105, thereby improving performance. The source / drain region 140 is formed such that each sacrificial gate structure 118 is disposed between adjacent pairs of the corresponding source / drain regions 140. In some embodiments, the spacer layer 134 and the internal spacer 136 separate the source / drain region 140 from the sacrificial gate layer 128 by an appropriate lateral distance (e.g., along the X-axis direction) to prevent electrical bridging to the gate of the subsequently formed obtained device.

[0034] The source / drain region 140 may include any acceptable material, such as materials suitable for n-type or p-type devices. For n-type devices, in some embodiments, the source / drain region 140 includes materials that apply tensile strain in the channel region, such as silicon, SiC, SiCP, SiP, etc. According to certain embodiments, when forming a p-type device, the source / drain region 140 includes materials that apply compressive strain in the channel region, such as SiGe, SiGeB, Ge, GeSn, etc. The source / drain region 140 may have a surface that protrudes from the corresponding surface of the fin and may have facets. In some embodiments, adjacent source / drain regions 140 may be merged to form a single source / drain region 140 above two adjacent fins of the fin 112.

[0035] The source / drain region 140 may be implanted with dopants and then subjected to an annealing process. The source / drain region 140 may have an impurity concentration between about 10 19 cm -3 and about 10 21 cm -3 . The n-type and / or p-type impurities used for the source / drain region 140 may be any of the impurities discussed above. In some embodiments, the source / drain region 140 is in-situ doped during growth.

[0036] Figure 7 is an X-view of the integrated circuit 100 according to some embodiments. In Figure 7 , a dielectric layer 144 and an interlayer dielectric (ILD) 146 are formed over the source / drain region. The dielectric layer 144 may correspond to an etch stop layer (ESL). The dielectric layer 144 may include a thin dielectric layer that may be conventionally deposited on the exposed surfaces of the source / drain region 140 and other exposed surfaces. The dielectric layer 144 may include SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. The dielectric 144 may be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0037] The dielectric layer 146 covers the dielectric layer 144. The dielectric layer 146 may include SiO, SiON, SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. The dielectric layer 146 may be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0038] In Figure 7 , the sacrificial gate structure 118 is removed from between the gate spacers 134. In particular, the dielectric layer 126 and the sacrificial gate layer 128 are completely removed from between the gate spacers 134.

[0039] In some embodiments, the sacrificial gate layer 128 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the sacrificial gate layer 128 without etching the spacer layer 134. When etching the sacrificial gate layer 128, if the dielectric layer 126 is present, it can be used as an etch stop layer. Then, the dielectric layer 126 can be removed after the sacrificial gate layer 128 is removed.

[0040] The removal of the sacrificial gate layer 128 and the dielectric layer 126 creates a void between the gate spacer layers 134 above the channel 105. As will be elaborated in more detail below, the upper portion of the gate metal or gate electrode will be formed in the void. Accordingly, the sacrificial gate layer 128 is sacrificial because the upper portion of the gate metal will ultimately be formed in its place.

[0041] In Figure 7 , the channel 105 is released by removing the sacrificial semiconductor nanostructure 107. The sacrificial semiconductor nanostructure 107 can be removed by a selective etching process using an etchant that is selective to the material of the sacrificial semiconductor nanostructure 107, thereby removing the sacrificial semiconductor nanostructure 107 while substantially not etching the channel 105. In some embodiments, the etching process is an isotropic etching process using an etching gas and an optional carrier gas, where the etching gas includes F2 and HF, and the carrier gas can be an inert gas such as Ar, He, N2, combinations thereof, etc. In some embodiments, the sacrificial semiconductor nanostructure 107 is removed and the channel 105 is patterned to form the channel regions of PFETs and NFETs. The removal of the sacrificial semiconductor nanostructure 107 creates a void between the channels 105.

[0042] After releasing the channel 105, an interfacial gate dielectric layer 151 is deposited. The interfacial gate dielectric layer 151 is deposited on all exposed surfaces of the channel 105. The interfacial gate dielectric layer 151 surrounds the channel 105. The interfacial gate dielectric layer 151 can include a dielectric material such as silicon oxide, silicon nitride, or other suitable dielectric materials. The interfacial gate dielectric layer 151 can include a relatively low-K dielectric relative to a high-K dielectric such as hafnium oxide or other high-K dielectric materials that can be used for transistor gate dielectrics. High-K dielectrics can include dielectric materials having a dielectric constant higher than that of silicon oxide. The interfacial gate dielectric layer 151 can be formed by a thermal oxidation process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. The interfacial gate dielectric layer 151 can have a thickness between 0.5 nm and 2 nm. Other materials, deposition processes, and thicknesses can be used for the interfacial gate dielectric layer 151 without departing from the scope of the present invention.

[0043] A high-K dielectric layer 153 is deposited. The high-K dielectric layer 153 is deposited by a conformal deposition process. The conformal deposition process deposits the high-K dielectric layer 153 on the interface gate dielectric layer 151, on the hard mask structure 109, on the substrate 102, on the trench isolation region 116, and on the gate spacer layer 134. The high-K gate dielectric layer 153 surrounds the channel 105. The high-K gate dielectric layer 153 has a thickness between 1 nm and 3 nm. The high-K dielectric layer includes one or more dielectric materials, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, titanium oxide, hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-K dielectric materials, and / or combinations thereof. The high-K dielectric layer 153 can be formed by CVD, ALD, or any suitable method. Other thicknesses, deposition processes, and materials can be used for the high-K dielectric layer 153 without departing from the scope of the present invention.

[0044] A gate metal 155 is deposited. The gate metal 155 is deposited on all exposed surfaces of the high-K dielectric layer 153. The gate metal 155 surrounds the channel 105. Although the gate metal 155 is shown as a single layer in Figure 7 , in practice, the gate metal 155 can include one or more conductive liner layers, work function layers, and gate fill layers, which together constitute the gate metal. The gate metal can include one or more of Ti, TiN, Ta, TaN, Al, Cu, Co, Ru, W, Au, or other suitable conductive materials. The gate metal 155 can be deposited by PVD, ALD, or CVD. Other configurations, materials, and deposition processes can be used for the gate metal 155 without departing from the scope of the present invention. The gate metal 155 serves as a gate electrode surrounding the channel 105.

[0045] At Figure 7 the processing stage shown, except for forming the source / drain contacts and cutting the metal gate structure, the transistor 101 is substantially complete, as described in more detail below. Each transistor 101 includes a stack 122 of channels 105 that extends between the source / drain regions 140 and serves as the stacked channel of the transistor 101.

[0046] Figure 8 is a perspective view of an integrated circuit 100 according to some embodiments. A CMP process is implemented to reduce Figure 7 the height of various surface components shown in

[0047] At Figure 8In it, an isolation structure 163 is formed at some positions to replace the gate metal 155. The isolation structure 163 includes a dielectric layer 165 and a dielectric layer 167. The dielectric layer 165 may include SiO, SiON, SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric layers. The dielectric layer 167 is a dielectric liner layer located on the sidewalls of the gate spacer layer 134. The dielectric layer 167 may include SiO, SiON, SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. The dielectric layers 165 and 167 can be deposited by CVD, ALD, PVD, or other suitable deposition processes. In one example, the dielectric layer 165 includes silicon oxide, and the dielectric layer 167 includes silicon nitride. In some embodiments, the isolation structure 163 can be an on-die cut polycrystalline silicon (CPODE) structure.

[0048] Figure 8 A bottom dielectric structure 147 is also shown below the source / drain region 140. The bottom dielectric structure 147 can be formed before the source / drain region 140 is formed. The bottom dielectric structure 147 may include SiO, SiON, SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. The bottom dielectric structure 147 can be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0049] Figure 8 A dielectric layer 143 formed on the top surface of the shallow trench isolation region 116 at selected positions is also shown. In some embodiments, the dielectric layer 143 is a residue of the dielectric layer forming the gate spacer layer 134. Accordingly, in some embodiments, the dielectric layer 143 is the same material as the gate spacer layer 134. Figure 8 A dielectric layer 145 located on the dielectric layer 143 is also shown. The dielectric layer 145 may include silicon oxide or other suitable dielectric materials. A dielectric layer 144 can be formed on the top surface of the dielectric layer 145 and in contact with a portion of the dielectric layer 143.

[0050] In Figure 9In [description], a hard mask layer 150 is deposited. The hard mask layer 150 is formed by selectively depositing a hard mask material on the gate metal 155, the gate spacer layer 134, the dielectric layer 144, and the polysilicon layer 165. In some embodiments, the hard mask layer 150 does not grow on the interlayer dielectric layer 146 because the hard mask layer 150 selectively grows on the gate metal 155 and the layer including nitrogen, and in some embodiments, the interlayer dielectric layer 146 is silicon oxide. In some embodiments, the hard mask layer 150 includes pure titanium deposited by ALD or other suitable deposition processes. In some cases, a small amount of the hard mask layer 150 may grow on the interlayer dielectric layer 146. In these cases, an etching process including exposing the integrated circuit 100 to dilute hydrofluoric acid (DHF) can remove the small amount of hard mask material from the interlayer dielectric layer 146.

[0051] In some embodiments, a conventional lithography process is used to form the hard mask layer 150. In particular, the hard mask material can be deposited by CVD, ALD, or other suitable deposition processes. Then, lithography can be performed to pattern the hard mask layer 150, as Figure 9 shown.

[0052] Figure 10 is a perspective view of the integrated circuit 100 according to some embodiments. In Figure 10 In [description], an etching process is performed in the presence of the hard mask layer 150. The etching process removes the bottom of the dielectric layer 144 and the interlayer dielectric layer 146, thereby exposing the top surface of the source / drain region 140. After the etching process, the dielectric layer 144 remains on the sidewalls of the gate spacer layer 134 directly under the hard mask layer 150. The vertically thicker portion of the dielectric layer 144 also remains outside the coverage of the hard mask layer 150. For example, although the dielectric layer 144 is removed from the top surfaces of the source / drain region 140 and the dielectric layer 145, the vertically thicker portion of the dielectric layer 144 still remains on the sidewalls of the source / drain region 140 above the dielectric layer 1.45.

[0053] The etching process causes the top surface portion of the source / drain region 140 adjacent to the highest channel 105 of the transistor 101 to be partially recessed. This results in the formation of a U-shaped cavity in the top surface of the source / drain region 140 at certain positions.

[0054] Figure 11 is a perspective view of the integrated circuit 100 according to some embodiments. In Figure 11In this case, a silicide layer 152 is formed. The silicide layer 152 can be formed by depositing a metal layer on the source / drain regions 140 and other exposed surfaces. The metal layer is selected based on the type of silicide to be formed. The metal layer can include Ni, Ti, Al, Sb, Ru, Mo, Zr, Nb, Sc, Y, Rh, Ir, W, or other suitable metal layers. After the deposition of the metal layer, a thermal annealing process is implemented. The thermal annealing process causes the formation of the silicide 152. The silicide corresponds to a combination of silicon from the source / drain regions 140 and the metal of the metal layer. As seen in Figure 11 due to the presence of silicon and the dielectric layers 144 and 145, the silicide 152 is also formed on the dielectric layers 144 and 145. The silicide can have a thickness between 0.2 nm and 10 nm, and other thicknesses can be used without departing from the scope of the present invention.

[0055] In some embodiments, a dopant implantation process is implemented before depositing the metal layer for the silicide. More specifically, for a P-type transistor, a P-type dopant can be deposited on the upper part of the source / drain regions 140 before depositing the metal layer for the silicide. This helps to reduce the interface resistance.

[0056] Figure 12 is a perspective view of an integrated circuit 100 according to some embodiments. In Figure 12 a metal layer 154 is deposited. The metal layer 154 can be deposited by PVD with high directionality such that the metal layer 154 grows mainly on the horizontal surfaces and grows little or not at all on the vertical surfaces. As a result, the metal layer 154 is formed on the hard mask layer 150 and on the portions of the silicide layer 152 that have already been formed on the source / drain regions 140.

[0057] In some embodiments, an etching process is implemented after depositing the metal layer 154. The etching process removes the silicide layer 152 from all positions not covered by the metal layer 154. As a result, the silicide layer 152 is removed from the dielectric layers 144 and 145. The silicide layer 152 remains on the source / drain regions 140. The metal layer 154 can be referred to as a metal capping layer because the metal layer 154 acts as a cap or mask to protect the silicide 152 under the metal layer 154.

[0058] In some embodiments, the metal layer 154 is a very low-resistance metal. In some embodiments, the low-resistance metal includes tungsten, ruthenium, molybdenum, copper, iridium, aluminum, or other suitable metal materials. The metal layer 154 can have a thickness between 0 nm and 2 nm. Based on the deposition characteristics of the PVD process, the metal layer 154 will be thinner at the edges of the silicide 152.

[0059] Figure 13 is a perspective view of an integrated circuit 100 according to some embodiments. InFigure 13 Therein, an interlayer dielectric layer 156 is deposited. In one example, the interlayer dielectric layer 156 includes silicon oxide. However, other dielectric materials can be used without departing from the scope of the present invention. The interlayer dielectric layer 156 is located on the metal layer 154 above the source / drain regions 140. The interlayer dielectric layer 156 is also in direct contact with the dielectric layer 145 and is located on the sidewalls of the dielectric layer 144.

[0060] After forming the interlayer dielectric layer 156, a CMP process is implemented. The CMP process removes the hard mask layer 150 and the metal layer 154 located on the hard mask layer 150.

[0061] In Figure 13 Therein, a gate isolation structure 157 is formed. The gate isolation structure 157 can also be referred to as a "cut metal gate" (CMG) structure. The gate isolation structure 157 electrically isolates the gate electrodes of the transistors 101 adjacent to each other along the Y direction. The gate isolation structure 157 is formed by forming a trench extending along the X direction. The trench extends completely through the gate metal 155, such that the gate metals 155 of the transistors adjacent to each other along the Y direction are electrically isolated from each other. In some embodiments, the trench extends downward through the dielectric layer 143 into the trench isolation region 116 and can even extend into the substrate 102. A dielectric material is deposited in the trench.

[0062] The gate isolation structure 157 includes a dielectric layer 159. The dielectric layer 159 corresponds to a dielectric liner layer and can include SiO, SiON, SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. The dielectric layer 159 can be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0063] The gate isolation structure includes a dielectric layer 161. The dielectric layer 161 fills the gap between adjacent portions of the dielectric liner layer 159. The dielectric layer 161 can include SiO, SiON, SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. The dielectric layer 161 can be deposited by CVD, ALD, PVD, or other suitable deposition processes. In an exemplary embodiment, the dielectric layer 159 includes silicon nitride and the dielectric layer 161 includes silicon oxide.

[0064] Figure 14 is a perspective view of an integrated circuit 100 according to some embodiments. In Figure 14 Therein, a dielectric layer 158 is deposited on the top surface of the integrated circuit 100 such that the dielectric layer 158 initially covers Figure 13The entire top surface shown. The dielectric layer 158 can correspond to an etch stop layer (ESL) and can include SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. The dielectric 158 can be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0065] The interlayer dielectric layer 160 is deposited on the dielectric layer 158. The dielectric layer 160 covers the dielectric layer 158. The dielectric layer 160 can include SiO, SiON, SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. The dielectric layer 160 can be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0066] After depositing the dielectric layers 158 and 160, the trench 162 is formed. The trench 162 corresponds to a source / drain contact trench that extends through the dielectric layers 160, 158, and 156 and exposes the metal layer 154. Accordingly, the etching process stops on the metal layer 154. In some embodiments, portions of the dielectric layer 156 remain on the sidewalls of the dielectric layer 144 above the metal layer 154.

[0067] Figure 15 is a perspective view of an integrated circuit 100 according to some embodiments. In Figure 15 , a metal layer 164 is formed in the trench 162. The metal layer 164 is in direct contact with the top surface of the metal layer 154 and the sidewalls of the dielectric layer 156. The metal layer 164 is a low-resistance metal such as W, Ru, Mo, Cu, Ir, Al, or other suitable metal materials.

[0068] In some embodiments, the metal layer 164 is the same material as the metal layer 154. This results in a uniform interface between the metal layer 154 and the metal layer 164. This reduces the contact resistance of interference. In some embodiments, the metal layer 164 and the metal layer 154 are different metals.

[0069] After forming the metal layer 164, a CMP process is implemented. The CMP process reduces the height of the metal layer 164 and forms the source / drain contact 166. More specifically, the metal layers 154 and 164 together form the source / drain contact 166. Each source / drain contact 166 is electrically connected to a corresponding source / drain region 140, where the silicide 152 is located between the source / drain contact 166 and the source / drain region 140.

[0070] Figure 16 is a cross-sectional view of the integrated circuit 100 taken along the cut line 16 according to some embodiments. Figure 15 Figure 16Shows the interface between metal layers 154 and 164. However, as previously described, in some embodiments, metal layers 154 and 164 are of the same material such that there is no distinct interface or boundary between metal layer 154 and 164.

[0071] In Figure 16 , the source / drain contact 166 includes a lower region 171 and an upper region 173. The lower region 171 corresponds to the portion of the source / drain contact 166 that is below the bottom of the dielectric layer 156 and includes the lower portions of the metal layer 154 and the metal layer 164. The upper region 173 corresponds to the portion of the metal layer 164 that is above the bottom surface of the dielectric layer 156.

[0072] In some embodiments, the lower region 171 has a width dimension D1 along the X direction. The upper region 173 has a width dimension D2 that is less than the width dimension D1. In some embodiments, the dimension D1 is between 5 nm and 30 nm. In some embodiments, the dimension D2 is between 3 nm and 20 nm. Other values of D1 and D2 may be used without departing from the scope of the present invention.

[0073] In some embodiments, the lower region 171 is separated from the gate metal 155 by a dimension D3 along the X direction. The upper region 173 is separated from the gate metal 155 by a dimension D4 along the X direction. The dimension D4 is greater than the dimension D3. Since the upper region 173 is spaced further from the gate metal 155, the total capacitance (also referred to as the gate-to-drain capacitance) between the source / drain contact 166 and the gate metal 155 is greatly reduced. Additionally, this allows the critical dimension of the source / drain contact 166 to be greatly reduced. In some embodiments, the critical dimension is less than that of other possible solutions and is between 2 nm and 4 nm. In some embodiments, the distance between the upper region 173 and the gate metal 155 is greater than that of other possible solutions and is between 1 nm and 2 nm. Additionally, the resistance of the source / drain contact 166 is reduced based on the larger silicide contact area and the self-alignment property of the silicide.

[0074] In some embodiments, the top surface of the metal layer 154 is higher than the top surface of the highest channel 105. Alternatively, in some embodiments, the top layer of the metal layer 154 may be lower than the top surface of the highest channel 105. In some embodiments, the top surface of the metal layer 154 may be between 5 nm below and 20 nm above the top surface of the highest channel 105. In some embodiments, the upper region 173 of the source / drain contact 166 has a height dimension D5 that is between 0 nm and 20 nm, depending on the top surface of the metal layer 154. In some embodiments, the upper region 173 may be completely removed and a CMP process may be performed.

[0075] In some embodiments, the trench 162 may have an overlay offset between 0 nm and 6 nm along the X direction during formation. In other words, due to the wider lower region 171, there is greater flexibility in alignment constraints in the formation of the trench 162 in which the metal layer 164 is deposited. Accordingly, the alignment constraints may be greatly relaxed.

[0076] In some embodiments, although Figure 16 It is not shown, but portions of the silicide layer 152 may remain on the sidewalls of the dielectric layer 144. However, in practice, the sidewall silicide is typically completely removed during an etching process performed in the presence of the metal layer 154.

[0077] Figure 17 According to some embodiments, the cut is taken along the cutting line 17. Figure 15 FIG. 1 is a cross-sectional view of an integrated circuit 100. Figure 17 As can be seen in , the contact area of metal layer 154 on silicide 152 is larger than the contact area between metal layer 154 and metal layer 164. A large silicide contact area results in a smaller contact resistance. This is partly based on the fact that the silicide interface has a greater impact on resistance. If the silicide interface is good, the upper region 173 can have a reduced size without negatively affecting the overall resistance.

[0078] Figure 17 It is also shown that metal layer 164 is intentionally formed smaller along the Y direction to achieve shrinkage. In addition, the right edge of metal layer 164 is laterally offset by dimension D6 relative to the right edge of metal layer 154. This helps to reduce the capacitance between adjacent source / drain contacts 166. Dimension D6 can be between 0 nm and 30 nm, but other values can be used without departing from the scope of the present invention.

[0079] As previously described, the width of the upper region 173 of the gate metal can be reduced to achieve a smaller gate-to-drain capacitance. For the metal layer 154 formed by PVD, current diffusion is not affected. This is because the PVD metal layer 154 has a lower resistance, while the silicide 152 has a high resistance. Relying solely on silicide to guide current from a place without source / drain metal is a high resistance path. After the PVD metal layer 154 is deposited, the entire silicide 152 can easily diffuse current to the PVD metal layer 154 with low resistance. After the current flows from the silicide 152 into the PVD metal layer 154, it can more easily flow into the metal layer 164 deposited on the metal layer 154 due to the low resistance.

[0080] Another advantage of the processes and structures described herein is that dummy source / drain contacts can be omitted. In some solutions, dummy source / drain contacts are used to achieve pattern uniformity. However, with the PVD metal layer 154 and silicide 152 as described herein, the dummy source / drain contacts can be omitted here.

[0081] Figure 18 is a cross-sectional view of integrated circuit 100 taken along cut line 16 according to some embodiments. More specifically, Figure 15 shows an embodiment in which an additional dielectric liner layer 170 is formed in the source / drain contact trenches 162 before depositing the metal layer 164. Accordingly, the dielectric liner layer 170 can be deposited during Figure 18 the processing stage shown. The dielectric liner layer 170 can include SiOCN, SiOC, SiON, SiN, or other suitable dielectric materials. The dielectric liner layer 170 can be deposited by PVD, ALD, CVD, or other suitable dielectric processes. The dielectric liner layer can have a width between 0.2 nm and 2 nm, but other dimensions can be used without departing from the scope of the invention.

[0082] The dielectric liner layer 170 can be used to further reduce the width of the upper region 173. This further reduces the gate-to-drain capacitance. Additionally, this can help enhance the adhesion between the metal layers 154 and 164.

[0083] Figure 19 is a cross-sectional view of integrated circuit 100 taken along cut line 17 according to some embodiments. Figure 15 The dielectric liner layer 170 present on the sidewalls of the metal layer 164 is further shown. Figure 19

[0084] Figure 20 Figure 13 is a perspective view of integrated circuit 100 according to some embodiments. Integrated circuit 100 corresponds to Figure 18 the processing stage shown, except that an additional liner layer 170 is conformally deposited before forming the dielectric layer 156. The dielectric liner layer 170 can correspond to Figure 19 and the dielectric liner layer 170 of. Accordingly, the dielectric liner layer 170 is deposited after forming the metal layer 154 and before depositing the dielectric layer 156.

[0085] Figure 21 Figure 21 is a cross-sectional view of integrated circuit 100 according to some embodiments. Figure 6 The processing stage shown in Figure 21 corresponds to the processing stage shown in ​​A bottom isolation structure 147 is shown.

[0086] Figure 22 According to some embodiments Figure 21 1 is a cross-sectional view of the integrated circuit 100 at a further processing stage. In particular, for embodiments in which the transistor is a PMOS transistor, a P-type dopant implantation process is performed. Then, as previously described, a silicide 152 is formed on the source / drain region 140. Then, as previously described, a metal layer 154 is formed on the silicide layer 152. The silicide 152 and the metal layer 154 are formed before the dielectric layers 144 and 146 are formed.

[0087] Figure 23 is a flow chart of a method 2300 for forming an integrated circuit according to some embodiments. The method 2300 may be combined with Figures 1 - 22 The structure, process, and system described herein. At 2302, the method 2300 includes forming a source / drain region connected to a channel of a plurality of first transistors. An example of a source / drain region is Figure 8 The source / drain region 140. An example of a channel is Figure 8 At 2302, method 2300 includes forming a silicide layer in contact with the source / drain region. An example of a silicide layer is Figure 11 At 2306, method 2300 includes depositing a first metal layer of source / drain contacts of the transistor on the silicide layer using a first deposition process. An example of the first metal layer is Figure 12 The first metal layer 154 is formed by etching the first metal layer 154. At 2308, the method 2300 includes patterning the silicide layer by performing an etching process using the first metal layer as a mask.

[0088] Figure 24 is a flow chart of a method 2400 for forming an integrated circuit according to some embodiments. The method 2400 may be combined with Figures 1 - 22 The structure, process, and system described herein. At 2402, the method 2400 includes forming a gate metal of a transistor above a channel of a stack of multiple transistors. An example of a gate metal is Figure 8 An example of a stacked channel is Figure 8 At 2404, method 2400 includes forming a silicide layer in the trench over the source / drain region of the transistor in contact with a top surface of the source / drain region. An example of a source / drain region is Figure 8 The source / drain region 140. An example of a silicide layer is Figure 11silicide layer 152. At 2406, method 2400 includes forming a first metal layer for the source / drain contacts of the transistor on the silicide layer in the trench. An example of the first metal layer is Figure 12 first metal layer 154. At 2408, method 2400 includes forming a dielectric layer on the first metal layer in the trench. An example of the dielectric layer is Figure 13 dielectric layer 156. At 2410, method 2400 includes patterning the dielectric layer to expose the first metal layer in the trench.

[0089] Embodiments of the present invention provide an integrated circuit including a transistor with source / drain contacts having improved electrical characteristics. A silicide is provided between the semiconductor source / drain region and the source / drain contacts. A first source / drain contact metal is formed on the silicide, and the silicide is patterned in the presence of the first source / drain contact metal. Then a second source / drain contact metal is deposited on the first source / drain contact metal. The silicide has a relatively large area to help reduce the resistance between the source / drain contacts and the source / drain region. Since the resistance is reduced by increasing the silicide area, the critical dimension of the source / drain contacts can be reduced. This further increases the scalability of the source / drain contacts and reduces the capacitance between the source / drain contacts and the gate metal. This enables the transistor to have an increased processing speed, reduced power consumption, and reduced area consumption. This further makes the integrated circuit function better.

[0090] In some embodiments, a method includes: forming source / drain regions connected to the channels of a plurality of first transistors, and forming a silicide layer in contact with the source / drain regions. The method includes: depositing, using a first deposition process, a first metal layer for the source / drain contacts of the transistor on the silicide layer, and patterning the silicide layer by implementing an etching process using the first metal layer as a mask.

[0091] In some embodiments, an integrated circuit includes a transistor. The transistor includes: a plurality of stacked channels; source / drain regions in contact with each stacked channel and including a concave top surface; a silicide layer on the top surface of the source / drain regions; an etch stop layer on the top surface of the source / drain regions. The transistor includes: a first dielectric layer on the sidewalls of the etch stop layer; and a metal source / drain contact including a lower region in contact with the silicide below the first dielectric layer and an upper region laterally adjacent to the sidewalls of the first dielectric layer.

[0092] In some embodiments, a method includes: forming a gate metal of a transistor over a stacked channel of a plurality of transistors; forming a silicide layer in a trench over a source / drain region of the transistor, the silicide layer contacting a top surface of the source / drain region. The method includes: forming a first metal layer of a source / drain contact of the transistor over the silicide layer in the trench; forming a dielectric layer over the first metal layer in the trench; and patterning the dielectric layer to expose the first metal layer in the trench.

[0093] The gate-all-around (GAA) transistor structures discussed herein can be patterned by any suitable method. For example, one or more lithography processes, including double patterning or multiple patterning processes, can be used to pattern the structures. Generally, double patterning or multiple patterning processes can combine lithography and self-alignment processes, allowing the creation of patterns with smaller pitch, for example, compared to the pitch obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a lithography process. A spacer is formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer can then be used to pattern the GAA structure.

[0094] Some embodiments of the present application provide a method of forming an integrated circuit, including: forming source / drain regions connected to channels of a plurality of transistors; forming a silicide layer contacting the source / drain regions; depositing a first metal layer of a source / drain contact of the transistor over the silicide layer using a first deposition process; and patterning the silicide layer by implementing an etching process using the first metal layer as a mask.

[0095] In some embodiments, the method includes: after the etching process, depositing a second metal layer of the source / drain contact on the first metal layer using a second deposition process. In some embodiments, the method includes: forming a gate metal over the plurality of channels adjacent to the gate spacer layer; forming a first dielectric layer on sidewalls of the gate spacer layer and on a top surface of the source / drain region; forming a second dielectric layer on the first dielectric layer; forming a hard mask layer on the gate metal and on the first dielectric layer, the hard mask layer exposing the second dielectric layer; in the presence of the hard mask layer, exposing the top surface of the source / drain region by etching a bottom of the first dielectric layer and the second dielectric layer; and forming the silicide layer on the top surface of the source / drain region after etching the first dielectric layer and the second dielectric layer. In some embodiments, the method includes: forming the hard mask layer by selectively growing the hard mask layer on the gate metal, the gate spacer layer, and the first dielectric layer. In some embodiments, the method includes: depositing the first metal layer over the source / drain region and over the silicide layer over the gate metal by a physical vapor deposition process that does not deposit the gate metal on a vertical surface. In some embodiments, the method includes: removing the hard mask layer after depositing the first metal layer; depositing a third dielectric layer on sidewalls of the first dielectric layer over the first metal layer; and depositing a second metal layer on sidewalls of the third dielectric layer over the first metal layer. In some embodiments, the method includes: exposing the first metal layer by forming a trench in the third dielectric layer; and depositing the second metal layer in the trench over the first metal layer. In some embodiments, the method includes: removing the hard mask layer after depositing the first metal layer; depositing a third dielectric layer on sidewalls of the first dielectric layer over the first metal layer; depositing a fourth dielectric layer on sidewalls of the third dielectric layer over the first metal layer; and depositing the second metal layer on sidewalls of the fourth dielectric layer over the first metal layer. In some embodiments, the first metal layer and the second metal layer are the same metal. In some embodiments, the second metal layer is laterally offset relative to the first metal layer.

[0096] Some other embodiments of the present application provide an integrated circuit, including: a transistor, including: a plurality of stacked channels; source / drain regions in contact with each of the stacked channels and including a concave top surface; a silicide layer on the top surface of the source / drain regions; an etch stop layer on the top surface of the source / drain regions; a first dielectric layer on sidewalls of the etch stop layer; and a metal source / drain contact including a lower region in contact with the silicide layer below the first dielectric layer and an upper region laterally adjacent to sidewalls of the first dielectric layer.

[0097] In some embodiments, the transistor includes a second dielectric layer on a sidewall of the first dielectric layer directly above the lower region, wherein the upper region is in direct contact with a sidewall of the second dielectric layer directly above the lower region. In some embodiments, the lower region is wider than the upper region. In some embodiments, the transistor includes a gate metal above the stacked channels of the transistor, wherein the lower region is laterally closer to the gate metal than the upper region. In some embodiments, the lower region has an arcuate sidewall, wherein the upper region has a straight sidewall. In some embodiments, the upper region is laterally offset with respect to the lower region. In some embodiments, the lower region and the upper region are substantially L-shaped.

[0098] Some other embodiments of the present application provide a method of forming an integrated circuit, including: forming a gate metal of the transistor above stacked channels of a plurality of transistors; forming a silicide layer in a trench above a source / drain region of the transistor, the silicide layer being in contact with a top surface of the source / drain region; forming a first metal layer of a source / drain contact of the transistor on the silicide layer in the trench; forming a dielectric layer on the first metal layer in the trench; and patterning the dielectric layer to expose the first metal layer in the trench.

[0099] In some embodiments, the method includes: after patterning the dielectric layer, forming a second metal layer of the source / drain contact that is in contact with the first metal layer and in contact with a sidewall of the dielectric layer in the trench. In some embodiments, the first metal layer is laterally closer to the gate metal than the second metal layer.

[0100] The features of several embodiments are outlined above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming an integrated circuit, comprising: Forming source / drain regions connected to channels of a plurality of transistors; Forming a silicide layer in contact with the source / drain regions; Depositing a first metal layer of a source / drain contact of the transistor on the silicide layer using a first deposition process; And Patterning the silicide layer by performing an etching process using the first metal layer as a mask.

2. The method according to claim 1, comprising: After the etching process, depositing a second metal layer of the source / drain contact on the first metal layer using a second deposition process.

3. The method according to claim 1, comprising: Forming gate metal above the plurality of channels adjacent to a gate spacer layer; Forming a first dielectric layer on sidewalls of the gate spacer layer and on top surfaces of the source / drain regions; Forming a second dielectric layer on the first dielectric layer; Forming a hard mask layer on the gate metal and on the first dielectric layer, the hard mask layer exposing the second dielectric layer; With the hard mask layer present, exposing the top surfaces of the source / drain regions by etching bottoms of the first dielectric layer and the second dielectric layer; And After etching the first dielectric layer and the second dielectric layer, forming the silicide layer on the top surfaces of the source / drain regions.

4. The method according to claim 3, comprising: The hard mask layer is formed by selectively growing the hard mask layer on the gate metal, the gate spacer layer, and the first dielectric layer.

5. The method according to claim 4, comprising: The first metal layer is deposited on the silicide layer above the source / drain regions and above the gate metal by a physical vapor deposition process that does not deposit the gate metal on vertical surfaces.

6. The method according to claim 3, comprising: Removing the hard mask layer after depositing the first metal layer; Depositing a third dielectric layer on sidewalls of the first dielectric layer above the first metal layer; And Depositing a second metal layer on sidewalls of the third dielectric layer above the first metal layer.

7. The method according to claim 6, comprising: Exposing the first metal layer by forming a trench in the third dielectric layer; And Depositing the second metal layer in the trench on the first metal layer.

8. The method according to claim 3, comprising: Removing the hard mask layer after depositing the first metal layer; Depositing a third dielectric layer on sidewalls of the first dielectric layer above the first metal layer; Depositing a fourth dielectric layer on sidewalls of the third dielectric layer above the first metal layer; And Depositing the second metal layer on sidewalls of the fourth dielectric layer above the first metal layer.

9. An integrated circuit, comprising: A transistor, comprising: A plurality of stacked channels; Source / drain regions in contact with each of the stacked channels and including concave top surfaces; A silicide layer on top surfaces of the source / drain regions; An etch stop layer on the top surfaces of the source / drain regions; A first dielectric layer on sidewalls of the etch stop layer; and A metal source / drain contact, comprising a lower region in contact with the silicide layer under the first dielectric layer, and an upper region laterally adjacent to a sidewall of the first dielectric layer.

10. A method of forming an integrated circuit, comprising: forming a gate metal of the transistor over stacked channels of a plurality of transistors; forming a silicide layer in contact with a top surface of a source / drain region in a trench over the source / drain region of the transistor; forming a first metal layer of the source / drain contact of the transistor over the silicide layer in the trench; forming a dielectric layer over the first metal layer in the trench; and patterning the dielectric layer to expose the first metal layer in the trench.

Images