Semiconductor devices and power equipment

Abstract

The semiconductor device and power equipment disclosed herein include: a substrate; a buffer layer located on one side of the substrate; a channel layer located on the side of the buffer layer away from the substrate; a barrier layer located on the side of the channel layer away from the buffer layer; a trench penetrating the barrier layer and the channel layer and extending into the buffer layer; an ohmic contact layer filling the trench; a source-drain metal layer located on the side of the ohmic contact layer away from the substrate, the source-drain metal layer including a source and a drain; a gate metal layer located on the side of the barrier layer away from the channel layer, the gate metal layer including a gate and an anode; a passivation layer including a first via and a second via, wherein the orthographic projection of the first via on the substrate overlaps with the orthographic projection of the source on the substrate, and the orthographic projection of the second via on the substrate overlaps with the orthographic projection of the anode on the substrate; and a source field plate layer, the source field plate layer connecting the source and the anode through the first via and the second via, and the source field plate layer and the gate are insulated from each other through the passivation layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor device and power equipment. Background Technology

[0002] The breakdown voltage characteristics of semiconductor power devices are closely related to the bandgap of the semiconductor material. Gallium oxide (Ga2O3), as a novel wide-bandgap semiconductor material, possesses an ultra-wide bandgap of 4.8 eV to 4.9 eV, an ultra-high critical breakdown field strength of 8 MV / cm, and a Baliga figure of merit as high as 3444, which is 10 times that of silicon carbide (SiC) and 3444 times that of silicon (Si). In semiconductor manufacturing processes, gallium oxide material has the capability to achieve 10... 14 ~10 20 cm -3 With advantages such as controllable n-type doping and low-cost wafers, it is possible to fabricate high-voltage power devices with ultra-low losses.

[0003] In power conversion circuits such as DC-DC converters and resonant converters, when the power transistor switches to the off state, the induced electromotive force across the coil of the inductive element in the circuit will generate a large peak current and reverse voltage on the transistor, thereby damaging the device. In metal-oxide-semiconductor field-effect transistors (MOSFETs) based on silicon (Si) and silicon carbide (SiC), the presence of a body diode allows the stored charge to be released during the off state, protecting the device.

[0004] High electron mobility transistors (HEMTs) based on gallium oxide offer advantages such as high electron mobility, making them suitable for applications in RF power and other fields. However, the absence of a body diode in HEMTs leads to significant turn-off losses and increased susceptibility to damage and efficiency degradation at high switching speeds. While external anti-parallel freewheeling diodes can discharge reverse current, they increase area and cost, and introduce additional parasitic inductance and capacitance, creating new reliability issues. Summary of the Invention

[0005] This disclosure provides a semiconductor device and power equipment that can reduce reverse conduction losses while having high electron mobility and high breakdown field strength, and solves the problems of high parasitic impedance, high cost, poor reliability and high noise of external anti-parallel diodes.

[0006] The semiconductor devices and power equipment provided in this disclosure are specifically designed as follows:

[0007] In one aspect, embodiments of this disclosure provide a semiconductor device, including:

[0008] Substrate;

[0009] A buffer layer is located on one side of the substrate;

[0010] The channel layer is located on the side of the buffer layer away from the substrate;

[0011] A barrier layer is located on the side of the channel layer away from the buffer layer;

[0012] The trench penetrates the barrier layer and the channel layer and extends into the buffer layer;

[0013] An ohmic contact layer fills the trench;

[0014] A source-drain metal layer is located on the side of the ohmic contact layer away from the substrate, and the source-drain metal layer includes a source and a drain.

[0015] A gate metal layer is located on the side of the barrier layer away from the channel layer, and the gate metal layer includes a gate and an anode;

[0016] The passivation layer includes a first via and a second via, wherein the orthographic projection of the first via on the substrate overlaps with the orthographic projection of the source electrode on the substrate, and the orthographic projection of the second via on the substrate overlaps with the orthographic projection of the anode on the substrate.

[0017] A source field plate layer is provided, wherein the source field plate layer is connected to the source and the anode through the first via and the second via, and the source field plate layer and the gate are insulated from each other through the passivation layer.

[0018] In some embodiments, the semiconductor device provided in this disclosure further includes a delta-doped layer, which is located between the channel layer and the barrier layer.

[0019] In some embodiments, in the semiconductor device provided in this disclosure, the material of the δ-doped layer includes at least one of Si and Sn, and (Al) x Ga 1-x )2O3, 0.01≤x≤0.5.

[0020] In some embodiments, in the semiconductor device provided in this disclosure, the doping concentration of Si and / or Sn in the δ-doped layer is 10. 18 cm -3 ~10 20 cm -3 .

[0021] In some embodiments, the thickness of the channel layer in the semiconductor device provided in this disclosure is 1 nm to 5 nm.

[0022] In some embodiments, in the semiconductor device provided in this disclosure, the material of the buffer layer includes Ga2O3, and the material of the channel layer includes (Al) y Ga 1-y )2O3, 0.1≤y≤0.5.

[0023] In some embodiments, in the semiconductor device provided in this disclosure, the doping concentration of Si and / or Sn in the δ-doped layer is 10. 16 cm -3 ~10 18 cm -3 .

[0024] In some embodiments, in the semiconductor device provided in this disclosure, the thickness of the channel layer is 1 nm to 10 nm, and the material of the channel layer includes (Al). y Ga 1-y )2O3, 0.01≤y≤0.15.

[0025] In some embodiments, the semiconductor device provided in this disclosure further includes a p-type layer disposed between the gate and the barrier layer.

[0026] On the other hand, embodiments of this disclosure provide a power device including the semiconductor device described above. Attached Figure Description

[0027] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure;

[0028] Figure 2 for Figure 1 The equivalent circuit diagram of the semiconductor device shown;

[0029] Figure 3 for Figure 1 A schematic diagram of the semiconductor device in its off-state.

[0030] Figure 4 for Figure 1 A schematic diagram of the semiconductor device in the open state;

[0031] Figure 5 for Figure 1 The diagram shows a semiconductor device switching from the on state to the off state.

[0032] Figure 6 for Figure 1 The diagram shows a semiconductor device switching from the off state to the on state.

[0033] Figure 7 This is another schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure;

[0034] Figure 8 for Figure 1 The diagram shows a structural schematic of a semiconductor device during its fabrication process.

[0035] Figure 9 for Figure 1 The diagram shows another structural schematic of the semiconductor device during its fabrication process.

[0036] Figure 10 for Figure 1 The diagram shows another structural schematic of the semiconductor device during its fabrication process.

[0037] Figure 11 for Figure 1 The diagram shows another structural schematic of the semiconductor device during its fabrication process.

[0038] Figure 12 for Figure 1 The diagram shows another structural schematic of the semiconductor device during its fabrication process.

[0039] Figure 13 for Figure 1 The diagram shows another structural schematic of the semiconductor device during its fabrication process.

[0040] Figure 14 for Figure 1 The diagram shows another structural schematic of the semiconductor device during its fabrication process.

[0041] Figure 15 for Figure 1 The diagram shows another structural schematic of the semiconductor device during its fabrication process.

[0042] Figure 16 for Figure 1 The diagram shows another structural schematic of a semiconductor device during its fabrication process. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that the embodiments described in this disclosure should not be construed as limited to the specific shape of the region shown in this disclosure, but rather include shape deviations caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0044] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0045] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0046] Figure 1 This illustration shows a semiconductor device structure provided in an embodiment of the present disclosure. Figure 2 for Figure 1 The equivalent circuit diagram of the semiconductor device is shown. Figure 1 and Figure 2 As shown, the semiconductor device disclosed herein may include:

[0047] In some embodiments, substrate 101 may be an Fe / Mg-doped semi-insulating homogeneous gallium oxide (Ga2O3) substrate or a heterogeneous material substrate such as Si, sapphire, SiC, or diamond. The resistivity of the Fe / Mg-doped semi-insulating gallium oxide (Ga2O3) may be [not specified in the original text]. ,For example The thickness of the substrate 101 can be 100μm to 650μm, such as 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, 500μm, 550μm, 600μm, etc.

[0048] A buffer layer 102, a channel layer 103, and a barrier layer 104 are sequentially disposed on a substrate 101. A trench V is formed in the buffer layer 102, channel layer 103, and barrier layer 104. This trench V can penetrate the barrier layer 104 and the channel layer 103 and extend into the buffer layer 102. The depth of the trench V can be 40nm~60nm, for example, 45nm, 50nm, 55nm, etc. Within the trench V, heavily doped n-type Ga2O3 can be regrowed as an ohmic contact layer 105. Optionally, to ensure ohmic contact performance, the doping concentration of the n-type impurity in the Ga2O3 can be [specified value]. ,For example .

[0049] The source-drain metal layer 106 is located on the side of the ohmic contact layer 105 away from the substrate 101. The source-drain metal layer 106 may include a source S and a drain D. The source-drain metal layer 106 may be a multilayer structure such as a titanium / gold (Ti / Au) stack or a titanium / aluminum / nickel / gold (Ti / Al / Ni / Au) stack. In some embodiments, the source-drain metal layer 106 may also be a single-layer structure.

[0050] The gate metal layer 107 is located on the side of the barrier layer 104 away from the channel layer 103. The gate metal layer 107 may include a gate G and an anode SG. The material of the gate metal layer 107 includes, but is not limited to, platinum (Pt), nickel (Ni), gold (Au), copper (Cu), etc. The gate metal layer 107 may be a single-layer structure or a multi-layer structure.

[0051] The passivation layer 108 includes a first via H1 and a second via H2, wherein the orthographic projection of the first via H1 on the substrate 101 overlaps with the orthographic projection of the source electrode S on the substrate 101 (for example, the orthographic projection of the first via H1 on the substrate 101 and the orthographic projection of the source electrode S on the substrate 101 only partially overlap, or the orthographic projection of the first via H1 on the substrate 101 is located within the orthographic projection of the source electrode S on the substrate 101, or the orthographic projection of the source electrode S on the substrate 101 is located within the orthographic projection of the first via H1 on the substrate 101), and the orthographic projection of the second via H2 on the substrate 101 overlaps with the orthographic projection of the anode SG on the substrate 101 (for example, the orthographic projection of the second via H1 on the substrate 101 overlaps with the orthographic projection of the anode SG on the substrate 101). 2. The orthogonal projection of the anode SG on the substrate 101 partially coincides with the orthogonal projection of the second via H2 on the substrate 101, or the orthogonal projection of the anode SG on the substrate 101 is located within the orthogonal projection of the second via H2 on the substrate 101; or the orthogonal projection of the anode SG on the substrate 101 is located within the orthogonal projection of the second via H2 on the substrate 101). The material used for the passivation layer 108 can be silicon dioxide, silicon nitride, etc., and the thickness of the passivation layer 108 can be 0.01μm~1μm, such as 0.05μm, 0.1μm, 0.2μm, 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, etc.

[0052] The source field plate 109 connects the source S and the anode SG via a first via H1 and a second via H2, and is insulated from the gate G by a passivation layer 108. The material of the source field plate 109 can be the same as that of the source-drain metal layer 106.

[0053] In the semiconductor device provided in the embodiments of this disclosure, the substrate 101, buffer layer 102, channel layer 103, barrier layer 104, ohmic contact layer 105, passivation layer 108, source S, drain D, and gate G constitute a high electron mobility transistor (HEMT). The anode SG and the barrier layer 104 are connected by a Schottky contact, and the anode SG and the source S are electrically connected through the source field plate layer 109. This achieves the co-integration of the Schottky diode SBD and the high electron mobility transistor HEMT, thus solving the problems of high parasitic impedance, high cost, poor reliability, and high noise of external anti-parallel diodes, and also reducing the packaging difficulty. Furthermore, the presence of the source field plate 109 can alleviate the accumulation of peak electric field and improve the breakdown voltage of the device. The heterojunction formed by the buffer layer 102 and the channel layer 103 can effectively separate the doped region and the channel region, avoid the scattering of ionized impurities, and greatly improve the two-dimensional electron gas (2DEG) at the interface between the two. While ensuring the advantages of high electron mobility, high breakdown voltage and high threshold voltage, it can reduce reverse conduction loss.

[0054] In some embodiments, Figure 3A schematic diagram of the semiconductor device of this disclosure in the off state is provided, by Figure 3 As can be seen, at this time, the gate-source voltage difference Vgs of the high electron mobility transistor (HEMT) is less than the threshold voltage Vth, and the drain-source voltage difference Vds is greater than 0V, so there is no current path. Figure 4 A schematic diagram of the semiconductor device of this disclosure in the on state is provided, by Figure 4 It can be seen that at this time, the gate-source voltage difference Vgs of the high electron mobility transistor (HEMT) is greater than or equal to the threshold voltage Vth, and the drain-source voltage difference Vds is greater than 0V, and the current conducts in the forward direction from the drain D to the source S. Figure 5 A schematic diagram of the semiconductor device of this disclosure switching from the on state to the off state is provided. Figure 5 It can be seen that at this time, the gate-source voltage difference Vgs of the high electron mobility transistor (HEMT) is less than the threshold voltage Vth, and the forward voltage Von of the Schottky diode SBD is greater than the drain-source voltage difference Vds and less than 0V. The semiconductor device conducts in reverse through the integrated Schottky diode SBD. Figure 5 In "-Von,SBD", the "-" indicates that the current direction is opposite to the direction of the signal. Figure 4 The directions of the open-state currents are opposite. Figure 6 A schematic diagram of the semiconductor device of this disclosure switching from the off state to the on state is provided. Figure 6 As can be seen, at this time, the gate-source voltage difference Vgs of the high electron mobility transistor (HEMT) is greater than the threshold voltage Vth, and the conduction voltage Von of the Schottky diode (SBD) is greater than the drain-source voltage difference Vds and less than 0V. The semiconductor device conducts in reverse through the integrated Schottky diode (SBD) and flows from the source (S) to the drain (D).

[0055] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 1 As shown, it may also include a delta-doped layer 110 (also called a delta-doped layer), which is located between the channel layer 103 and the barrier layer 104. In related technologies, high electron mobility transistors (HEMTs) generally require a channel layer 103 thickness of more than 200 nm to achieve high mobility. However, due to the short-channel effect, this is not suitable for fabricating high-frequency devices with small gate lengths. By setting a delta-doped layer 110 between the channel layer 103 and the barrier layer 104, impurity ions are fixed in the crystal lattice, while the provided electrons enter the adjacent channel layer, forming a high-concentration two-dimensional electron gas, thereby improving electron mobility and making it suitable for high-frequency devices.

[0056] In some embodiments, the doping material of the δ-doped layer 110 includes at least one of Si and Sn, and the host material of the δ-doped layer 110 can be (Al). x Ga 1-xThe doping concentration of Si and / or Sn in the δ-doped layer 110 is 0.01 ≤ x ≤ 0.5, where x can be 0.1, 0.2, 0.3, 0.4, etc. The thickness of the δ-doped layer 110 can be 1 nm to 5 nm, such as 2 nm, 3 nm, 4 nm, etc. By decreasing the doping concentration of Si and / or Sn in the δ-doped layer 110 and / or increasing the thickness of the channel layer 103, the threshold voltage of the high electron mobility transistor (HEMT) can gradually change from negative to positive, i.e., the HEMT can change from depletion mode to enhancement mode. Optionally, in the depletion mode HEMT of this disclosure, the thickness of the channel layer 103 can be 1 nm to 5 nm (e.g., 2 nm, 3 nm, 4 nm, etc.), and the doping concentration of Si and / or Sn in the δ-doped layer 110 is 10. 18 cm -3 ~10 20 cm -3 For example, 10 19 cm -3 In the enhancement-mode high electron mobility transistor (HEMT) disclosed herein, the thickness of the channel layer 103 is 1 nm to 10 nm, for example, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, etc., and the doping concentration of Si and / or Sn in the δ-doped layer 110 is 10. 16 cm -3 ~10 18 cm -3 For example, 10 17 cm -3 .

[0057] In some embodiments of the semiconductor device provided in this disclosure, the material of the buffer layer 102 includes Ga2O3, and the material of the channel layer 103 includes (Al) y Ga 1-y The crystal phases of Ga₂O₃ and (Al₂O₃) y Ga 1-y The crystal phases of Ga₂O₃ are the same, 0.1≤y≤0.5, and y can be 0.3, 0.4, etc. Ga₂O₃ can have α, β, γ, δ, ε(κ) crystal phases, and correspondingly, (Al) y Ga 1-y Al₂O₃ uses the same α, β, γ, δ, and ε(κ) crystal phases as Ga₂O₃. The crystal phases of Ga₂O₃ are similar to those of Al₂O₃. y Ga 1-y The same crystal phase as Ga₂O₃ is equivalent to homoepitaxial growth of Al₂O₃ on Ga₂O₃. y Ga 1-y )2O3, thus ensuring better film quality and facilitating the application of Ga2O3 / (Al y Ga 1-yA high-density two-dimensional electron gas is generated at the 2O3 interface; and in the channel layer 103 (Al) y Ga 1-y In 2O3, when the Al component concentration is 0.1≤y≤0.5, the concentration of two-dimensional electron gas can also be increased, thereby increasing the saturation current density of high electron mobility transistors (HEMTs), which is suitable for depletion-type high electron mobility transistors (HEMTs).

[0058] In some embodiments, the doping concentration in the channel layer 103 can be reduced during epitaxial growth using MOCVD or MBE, thereby effectively reducing the two-dimensional electron gas concentration at the interface between the channel layer 103 and the buffer layer 102. This makes the two-dimensional electron gas more easily depleted, achieving an enhancement-mode operation (threshold voltage greater than 0V). Optionally, in the channel layer 103 of the enhancement-mode high electron mobility transistor (HEMT), the doping concentration can be reduced by controlling the doping concentration of the channel layer 103. y Ga 1-y In 2O3, the concentration of Al component is 0.01≤y≤0.15, and the specific values ​​of y can be 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.11, 0.12, 0.13, 0.14, etc.

[0059] In some embodiments, Figure 7 A schematic diagram of yet another structure of the semiconductor device provided in this disclosure is shown. For example... Figure 7 As shown, the semiconductor device of this disclosure may further include a p-type layer 111, which is disposed between the gate G and the barrier layer 104. By introducing a p-type material, such as p-type NiO or Cu2O, under the gate G, it is possible to help deplete the carriers in the channel below the gate G, thereby achieving an enhancement-mode operation. Furthermore, the threshold voltage can be controlled by adjusting the concentration and thickness of the p-type layer 111 under the gate G. The higher the concentration and the thicker the p-type layer 111, the more the device threshold voltage will gradually shift to the right, changing the threshold voltage from less than 0V to greater than 0V, which is equivalent to the high electron mobility transistor (HEMT) changing from depletion mode to enhancement mode.

[0060] On the other hand, this disclosure also provides a method for fabricating a semiconductor device, which will be described below. Figure 1 The fabrication process of the semiconductor device shown is illustrated using an example.

[0061] First step, such as Figure 8As shown, an unintentionally doped buffer layer 102 is epitaxially formed on substrate 101 using methods such as MOCVD, MBE, or pulsed laser deposition (PLD). Optionally, substrate 101 is an Fe-doped Ga2O3 substrate, and buffer layer 102 is β-phase Ga2O3. The thickness of buffer layer 102 is 100nm~600nm, such as 200nm, 300nm, 400nm, 500nm, etc. The Ga2O3 contained in substrate 101 can have the same crystal phase as the Ga2O3 contained in buffer layer 102, such as α phase, β phase, etc.

[0062] The second step, as Figure 9 As shown, a channel layer 103, a δ-doped layer 110, and a barrier layer 104 are epitaxially grown sequentially on the buffer layer 102. The channel layer 103 is made of β-phase (Al₂O₃) material. y Ga 1-y The material of the δ-doped layer 110 includes Al₂O₃. x Ga 1-x The material of the barrier layer 104 includes Al2O3. z Ga 1-z )2O3, of which, (Al x Ga 1-x )2O3 and (Al z Ga 1-z The crystal phase of 2O3 can be related to (Al) y Ga 1-y The crystal phases of 2O3 can be the same or different, with 0.1≤y≤0.5, 0.01≤x≤0.5, and 0.01≤z≤0.5. The thickness of the channel layer 103 is 1nm~5nm, such as 2nm, 3nm, 4nm, etc. The thickness of the δ-doped layer 110 is 1nm~5nm, such as 2nm, 3nm, 4nm, etc. The thickness of the barrier layer 104 is 10nm~30nm, such as 25nm, etc.

[0063] The third step, as Figure 10 As shown, a 500nm thick SiO2 layer is deposited as a hard mask using PECVD or ICP-CVD. The ohmic contact regions of the source (S) and drain (D) are defined by photolithography. The SiO2 layer to be used for the ohmic contact regions is then etched away using ICP-RIE and CF4 gas. Next, trenches V with a depth of 40nm~60nm are etched using ICP with BCl3 and Ar gas. In the ohmic contact region containing trench V, n-type heavily doped Ga2O3 is regrowthed as the ohmic contact layer 105. The Ga2O3 layer outside the ohmic contact region containing trench V is then wet-etched away using BOE solution. The n-type heavily doped Ga2O3 crystal phase can be related to (Al) y Ga 1-y The crystal phases of 2O3 can be the same or different.

[0064] Step four, as Figure 11 As shown, source and drain metal layers 106 are deposited on the ohmic contact layer 105 by electron beam evaporation and then rapidly annealed to enhance the ohmic contact quality; and the source S and drain D are fabricated by mesa isolation based on BCl3 / Ar dry etching using an ICP-RIE device.

[0065] Step 5, as Figure 12 As shown, a gate metal layer 107 is deposited on the barrier layer 104 using electron beam evaporation as a Schottky contact, and a mesa isolation is created using an ICP-RIE device based on BCl3 / Ar dry etching, to fabricate the gate G and anode SG respectively.

[0066] Step 6, as follows Figure 13 As shown, a passivation layer 108, such as silicon oxide or silicon nitride, is deposited by PECVD, and the passivation layer 108 is dry etched to form a first via H1 overlapping with the source electrode S and a second via H2 overlapping with the anode SG.

[0067] In some embodiments, such as Figure 14 As shown, this disclosure can also first deposit a layer of silicon oxide, silicon nitride, etc. as a first passivation layer 1081 by PECVD, and then perform dry etching on the first passivation layer 1081 to form the third via H3 of the gate G to be prepared, and the first sub-via H21 of the anode SG to be prepared. For example... Figure 15 As shown, the gate G is patterned within the third via H3, and the anode SG is patterned within the first sub-via H21. Then, as... Figure 16 As shown, a second passivation layer 1082 is formed covering the gate G and having a second sub-via H21 at the anode SG. At the same time, a first via H1 penetrating the second passivation layer 1082 is also formed at the source S. The second sub-via H21 and the first sub-via H21 together constitute a second via H2. The material of the second passivation layer 1082 can be the same as the material of the first passivation layer 1081.

[0068] Step 7, as Figure 1 As shown, the source field plate 109 is used to connect the anode SG and the source S, thereby realizing the integration of the Schottky diode SBD in the high electron mobility transistor (HEMT).

[0069] Based on the same inventive concept, this disclosure provides a power device including the semiconductor device described above. Since the principle by which this power device solves the problem is similar to that of the semiconductor device described above, the implementation of the power device provided in this disclosure can refer to the implementation of the semiconductor device described above, and repeated details will not be repeated.

[0070] In some embodiments, the power devices provided in this disclosure may include, but are not limited to, radio frequency amplifiers, mixers, radar, satellites, power supplies, automotive electronics, energy-saving lamps, and home appliances. Of course, the power devices provided in this disclosure may include other structures besides semiconductor devices. For example, when the power device is a radar, it may also include structures such as transmitters, antennas, and receivers; when the power device is a mixer, it may also include structures such as input ports and output ports.

[0071] As can be seen from the above, in the semiconductor device disclosed herein, a gallium oxide high electron mobility transistor with a source field plate is provided in anti-parallel with an integrated Schottky diode. When the high electron mobility transistor is reverse-biased and turned off, an additional low-resistance path for reverse current flow is provided at the Schottky diode, achieving low conduction loss and uniform reverse current distribution. This semiconductor device in (Al...) x Ga 1-x The 2O3 / Ga2O3 interface possesses a two-dimensional electron gas (2DEG), which can reduce reverse conduction losses while ensuring advantages such as high electron mobility, high breakdown voltage, and high threshold voltage. Since it is a monolithically integrated anti-parallel diode within a high electron mobility transistor, it solves the problems of high parasitic impedance, high cost, poor reliability, and high noise associated with external anti-parallel diodes.

[0072] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0073] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A buffer layer is located on one side of the substrate; The channel layer is located on the side of the buffer layer away from the substrate; A barrier layer is located on the side of the channel layer away from the buffer layer; The trench penetrates the barrier layer and the channel layer and extends into the buffer layer; An ohmic contact layer fills the trench; A source-drain metal layer is located on the side of the ohmic contact layer away from the substrate, and the source-drain metal layer includes a source and a drain. A gate metal layer is located on the side of the barrier layer away from the channel layer, and the gate metal layer includes a gate and an anode; The passivation layer includes a first via and a second via, wherein the orthographic projection of the first via on the substrate overlaps with the orthographic projection of the source electrode on the substrate, and the orthographic projection of the second via on the substrate overlaps with the orthographic projection of the anode on the substrate. A source field plate layer, wherein the source field plate layer connects the source and the anode through the first via and the second via, and the source field plate layer and the gate are insulated from each other through the passivation layer; It also includes a delta-doped layer located between the channel layer and the barrier layer, the material of the delta-doped layer comprising at least one of Si and Sn, and (Al) x Ga 1-x )2O3, 0.01≤x≤0.5; the doping concentration of Si and / or Sn in the δ-doped layer is 10 18 cm -3 ~10 20 cm -3 The thickness of the channel layer is 1 nm to 5 nm; the material of the buffer layer includes Ga2O3, and the material of the channel layer includes (Al) y Ga 1-y )2O3, 0.1≤y≤0.5, the material of the barrier layer includes (Al) z Ga 1-z )2O3, 0.01≤z≤0.5, (Al x Ga 1-x )2O3 and (Al z Ga 1-z The crystal phase of 2O3 and (Al) y Ga 1-y The crystal phases of 2O3 are different.

2. The semiconductor device as claimed in claim 1, characterized in that, It also includes a p-type layer, which is disposed between the gate and the barrier layer, and the p-type layer includes p-type NiO or Cu2O.

3. A power device, characterized in that, Includes the semiconductor device as described in claim 1 or 2.

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