Semiconductor structure
A dual-layer dielectric isolation structure with a second layer farther from the device area and a gap reduces parasitic capacitance and stress, enhancing semiconductor device performance.
Patent Information
- Application Number
- CN202410495985.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-01-11
- Filing Date
- 2024-04-24
- Publication Date
- 2025-07-15
AI Technical Summary
In semiconductor structures, parasitic capacitance and stress problems between charge in isolation structure and substrate lead to a decrease in electrical performance.
An isolated structure design is adopted including a first dielectric layer and a second dielectric layer, wherein the distance between the portion of the second dielectric layer and the device region is greater than the distance between the first dielectric layer and the device region, and an air gap or a low dielectric constant material fill layer is provided between the second portion and the device region to reduce parasitic capacitance and stress.
It effectively reduces the parasitic capacitance and stress between the charge in the isolation structure and the substrate, and improves the electrical performance of semiconductor devices.
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Figure CN120322019A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure including an isolation structure. Background Art
[0002] In a semiconductor structure, charges accumulate in the isolation structure, and a parasitic capacitance is generated between the charges in the isolation structure and the substrate, thereby reducing the electrical performance of the semiconductor device. In addition, the stress caused by the isolation structure also reduces the electrical performance of the semiconductor device. Therefore, how to effectively reduce the parasitic capacitance between the charges accumulated in the isolation structure and the substrate and the stress caused by the isolation structure is an ongoing goal. Summary of the Invention
[0003] The present invention provides a semiconductor structure that can effectively reduce the parasitic capacitance between the charges accumulated in the isolation structure and the substrate and the stress caused by the isolation structure.
[0004] The present invention provides a semiconductor structure including a substrate and an isolation structure. The substrate includes a device region. The isolation structure is located in the substrate. The isolation structure surrounds the device region. The isolation structure includes a first dielectric layer and a second dielectric layer. The first dielectric layer and the second dielectric layer are located in the substrate. The first dielectric layer is located between the second dielectric layer and the substrate. The second dielectric layer includes a first portion and a second portion. The second portion is located on the first portion. The distance between the second portion and the substrate in the device region is greater than the distance between the first portion and the substrate in the device region.
[0005] The present invention provides another semiconductor structure including a substrate, an isolation structure, and a semiconductor device. The substrate includes a device region. The isolation structure is located in the substrate. The isolation structure surrounds the device region. The isolation structure includes a first dielectric layer and a second dielectric layer. The first dielectric layer and the second dielectric layer are located in the substrate. The first dielectric layer is located between the second dielectric layer and the substrate. The second dielectric layer includes a first portion and a second portion. The second portion is located on the first portion. The distance between the second portion and the substrate in the device region is greater than the distance between the first portion and the substrate in the device region. The semiconductor device is located in the device region. The semiconductor device includes a gate, a gate dielectric layer, a first doped region, and a second doped region. The gate is located on the substrate. The gate dielectric layer is located between the gate and the substrate. The first doped region and the second doped region are located in the substrate on both sides of the gate.
[0006] Based on the above, in the semiconductor structure proposed by the present invention, the second dielectric layer includes a first portion and a second portion. The second portion is located on the first portion. The distance between the second portion and the substrate in the device region is greater than the distance between the first portion and the substrate in the device region. Therefore, the parasitic capacitance between the charge accumulated in the second portion of the isolation structure and the substrate in the device region and the stress caused by the second portion of the isolation structure can be effectively reduced, thereby improving the electrical performance of the semiconductor device located in the device region.
[0007] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are given below and detailed descriptions are made in conjunction with the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1A A cross-sectional view of a semiconductor structure according to some embodiments of the present invention;
[0009] Figure 1B A cross-sectional view of a semiconductor structure according to other embodiments of the present invention;
[0010] Figure 1C A cross-sectional view of a semiconductor structure according to other embodiments of the present invention;
[0011] Figure 2 For Figure 1A the top view of the semiconductor structure;
[0012] Figure 3A A cross-sectional view of a semiconductor structure according to other embodiments of the present invention;
[0013] Figure 3B A cross-sectional view of a semiconductor structure according to other embodiments of the present invention;
[0014] Figure 3C A cross-sectional view of a semiconductor structure according to other embodiments of the present invention;
[0015] Figure 4A A cross-sectional view of a semiconductor structure according to other embodiments of the present invention;
[0016] Figure 4B A cross-sectional view of a semiconductor structure according to other embodiments of the present invention;
[0017] Figure 4C A cross-sectional view of a semiconductor structure according to other embodiments of the present invention;
[0018] Figure 5A A cross-sectional view of a semiconductor structure according to other embodiments of the present invention;
[0019] Figure 5BCross-sectional view of a semiconductor structure according to further embodiments of the present invention;
[0020] Figure 5C Cross-sectional view of a semiconductor structure according to further embodiments of the present invention.
[0021] Reference numeral description:
[0022] 10A to 10L: Semiconductor structure
[0023] 100: Substrate
[0024] 102: Isolation structure
[0025] 104, 106, 110: Dielectric layer
[0026] 106a: First part
[0027] 106b: Second part
[0028] 108: Filling layer
[0029] 200, 300: Semiconductor device
[0030] 202: Gate
[0031] 204: Gate dielectric layer
[0032] 206, 208, 302: Doped region
[0033] 210: Conductive layer
[0034] 212: Hard mask layer
[0035] 214: Spacer
[0036] AG1: Air gap
[0037] D1, D2: Distance
[0038] FS1: Filling structure
[0039] G1: Gap
[0040] R1: Device region
[0041] RC1: Depression
[0042] S1: Upper surface
[0043] S2: Top surface
[0044] SW1: Sidewall Detailed description of the invention
[0045] Examples are listed below and described in detail with reference to the accompanying drawings. However, the provided examples are not intended to limit the scope covered by the present invention. For ease of understanding, the same components will be denoted by the same reference numerals in the following description. In addition, the drawings are for illustrative purposes only and are not drawn to the original scale. In fact, for the sake of clarity of discussion, the sizes of various features can be arbitrarily increased or decreased.
[0046] Please refer to Figure 1A and Figure 2 , the semiconductor structure 10A includes a substrate 100 and an isolation structure 102. The substrate 100 includes a device region R1. The device region R1 can be a semiconductor device region. In some embodiments, the device region R1 can be an active device region or a passive device region. In some embodiments, the device region R1 can be a transistor device region or a resistor device region. In the present embodiment, the device region R1 is taken as an example of a transistor device region, but the present invention is not limited thereto. The semiconductor structure 10A may further include a semiconductor device 200. The semiconductor device 200 is located in the device region R1. In some embodiments, the semiconductor device 200 can be an active device or a passive device. In some embodiments, the semiconductor device 200 can be a transistor device or a resistor device. In the present embodiment, the semiconductor device 200 is taken as an example of a transistor device, but the present invention is not limited thereto.
[0047] The isolation structure 102 is located in the substrate 100. The isolation structure 102 surrounds the device region R1. The isolation structure 102 includes a dielectric layer 104 and a dielectric layer 106. The dielectric layer 104 and the dielectric layer 106 are located in the substrate 100. The dielectric layer 104 is located between the dielectric layer 106 and the substrate 100. The dielectric layer 104 and the dielectric layer 106 can surround the device region R1. In some embodiments, the dielectric constant of the dielectric layer 104 can be lower than the dielectric constant of the dielectric layer 106. In some embodiments, the material of the dielectric layer 104 is, for example, an oxide (such as silicon oxide). In some embodiments, the material of the dielectric layer 106 is, for example, a nitride (such as silicon nitride).
[0048] The dielectric layer 106 includes a first portion 106a and a second portion 106b. The second portion 106b is located on the first portion 106a. The second portion 106b can be located directly above the first portion 106a. The first portion 106a and the second portion 106b can be integrally formed. The distance D2 between the second portion 106b and the substrate 100 in the device region R1 is greater than the distance D1 between the first portion 106a and the substrate 100 in the device region R1. Therefore, the parasitic capacitance between the charge accumulated in the second portion 106b of the isolation structure 102 and the substrate 100 in the device region R1 and the stress caused by the second portion 106b of the isolation structure 102 can be effectively reduced, thereby improving the electrical performance of the semiconductor device 200 located in the device region R1.
[0049] The dielectric layer 106 may have a recess RC1. The recess RC1 may be adjacent to the device region R1. The recess RC1 may be located between the second portion 106b and the substrate 100 in the device region R1. The upper surface S1 of the dielectric layer 104 adjacent to the device region R1 may be lower than the top surface S2 of the dielectric layer 106. The dielectric layer 104 does not directly contact the sidewall SW1 of the second portion 106b adjacent to the device region R1.
[0050] A gap G1 may be provided between the second portion 106b and the substrate 100 in the device region R1. The isolation structure 102 may further include a filling structure FS1. The filling structure FS1 is located between the second portion 106b and the substrate 100 in the device region R1. In this embodiment, the filling structure FS1 may include a filling layer 108 and an air gap AG1. In this embodiment, the filling layer 108 is only located between the top of the second portion 106b and the substrate 100 in the device region R1. The filling layer 108 may seal the top of the gap G1. The filling layer 108 may surround the device region R1. In some embodiments, the material of the filling layer 108 is, for example, an oxide (such as silicon oxide).
[0051] The air gap AG1 is located between the second portion 106b and the substrate 100 in the device region R1, between the filling layer 108 and the dielectric layer 104, and between the filling layer 108 and the first portion 106a. In some embodiments, the air gap AG1 may directly contact the substrate 100, the filling layer 108, the dielectric layer 104, the first portion 106a, and the second portion 106b. The air gap AG1 may surround the device region R1. The dielectric constant of the filling layer 108 and the dielectric constant of the air gap AG1 may be lower than the dielectric constant of the dielectric layer 106, thereby further reducing the parasitic capacitance between the charge accumulated in the second portion 106b of the isolation structure 102 and the substrate 100 in the device region R1, and thus improving the electrical performance of the semiconductor device 200 located in the device region R1. In addition, since the air gap AG1 is located between the second portion 106b and the substrate 100 in the device region R1, the influence of the stress caused by the second portion 106b of the isolation structure 102 on the substrate 100 in the device region R1 can be effectively reduced, and thus the electrical performance of the semiconductor device 200 located in the device region R1 is improved.
[0052] The semiconductor device 200 may include a gate 202, a gate dielectric layer 204, a doped region 206, and a doped region 208. The gate 202 is located on the substrate 100. In some embodiments, the material of the gate 202 is, for example, doped polysilicon. The gate dielectric layer 204 is located between the gate 202 and the substrate 100. In some embodiments, the material of the gate dielectric layer 204 is, for example, an oxide (such as silicon oxide). The doped regions 206 and 208 are located in the substrate 100 on both sides of the gate 202. The doped regions 206 and 208 can be used as one of the source region and the drain region and the other, respectively.
[0053] In some embodiments, the semiconductor device 200 may further include at least one of a conductive layer 210, a hard mask layer 212, and a spacer 214. The conductive layer 210 is located on the gate 202. In some embodiments, the conductive layer 210 includes a metal silicide layer, a metal layer, or a combination thereof. In some embodiments, the material of the conductive layer 210 is, for example, nickel (Ni), nickel silicide (NiSi), cobalt (Co), cobalt silicide (CoSi), tungsten (W), tungsten silicide (WSi), or a combination thereof. The hard mask layer 212 is located on the conductive layer 210. In some embodiments, the material of the hard mask layer 212 is, for example, a nitride (such as silicon nitride). The spacer 214 is located on the sidewalls of the gate 202, the sidewalls of the gate dielectric layer 204, the sidewalls of the conductive layer 210, and the sidewalls of the hard mask layer 212. The spacer 214 can be a single-layer structure or a multi-layer structure. In some embodiments, the material of the spacer 214 is, for example, an oxide (such as silicon oxide), a nitride (such as silicon nitride), or a combination thereof.
[0054] In some other embodiments, when there is a device region R1 on one side of the isolation structure 102 and another device region (not shown) on the other side of the isolation structure 102, the distance between the second part 106b and the substrate 100 in the other device region may be greater than the distance between the first part 106a and the substrate 100 in the other device region.
[0055] Based on the above embodiments, in the semiconductor structure 10A, the dielectric layer 106 includes a first part 106a and a second part 106b. The second part 106b is located on the first part 106a. The distance D2 between the second part 106b and the substrate 100 in the device region R1 is greater than the distance D1 between the first part 106a and the substrate 100 in the device region R1. Therefore, the parasitic capacitance between the charges accumulated in the second part 106b of the isolation structure 102 and the substrate 100 in the device region R1 and the stress caused by the second part 106b of the isolation structure 102 can be effectively reduced, thereby improving the electrical performance of the semiconductor device 200 located in the device region R1.
[0056] Please refer to Figure 1A andFigure 1B , Figure 1B The differences between the semiconductor structure 10B of Figure 1A and the semiconductor structure 10A of Figure 1A and Figure 1B are as follows. In the semiconductor structure 10B, the filling layer 108 can fill the gap G1 and there is no air gap in the filling layer 108. In addition, in
[0057] Please refer to Figure 1A and Figure 1C , Figure 1C The differences between the semiconductor structure 10C of Figure 1A and the semiconductor structure 10A of Figure 1A and Figure 1C are as follows. In the semiconductor structure 10C, the filling layer 108 fills the gap G1, the filling layer 108 can seal the gap G1, an air gap AG1 is located in the filling layer 108, and the air gap AG1 can be surrounded by the filling layer 108. In the semiconductor structure 10C, the air gap AG1 does not directly contact the substrate 100, the dielectric layer 104, and the dielectric layer 106. In addition, in
[0058] Please refer to Figures 1A to 1C and Figures 3A to 3C , compared with Figure 1A the semiconductor structure 10A, Figure 1B the semiconductor structure 10B, and Figure 1C the semiconductor structure 10C, Figure 3A the isolation structure 102 in the semiconductor structure 10D, Figure 3B the semiconductor structure 10E, and Figure 3C the semiconductor structure 10F may further include a dielectric layer 110. The dielectric layer 110 is located in the dielectric layer 106. The dielectric layer 110 can be surrounded by the dielectric layer 106. The dielectric constant of the dielectric layer 110 can be lower than the dielectric constant of the dielectric layer 106. In some embodiments, Figures 3A to 3C the second part 106b in Figures 1A to 1C and Figures 3A to 3C can be a multi-layer structure. In some embodiments, the material of the dielectric layer 110 can be an oxide (such as silicon oxide like spin on glass (SOG), etc.). In addition, in
[0059] Please refer to Figures 1A to 1C and Figures 3A to 5C , Figure 1A the semiconductor structure 10A, Figure 1B the semiconductor structure 10B, Figure 1C the semiconductor structure 10C,Figure 3A in the semiconductor structure 10D, Figure 3B in the semiconductor structure 10E, and Figure 3C in the semiconductor structure 10F, the semiconductor device 200 is replaced with a semiconductor device 300, thereby respectively forming Figure 4A the semiconductor structure 10G, Figure 4B the semiconductor structure 10H, Figure 4C the semiconductor structure 10I, Figure 5A the semiconductor structure 10J, Figure 5B the semiconductor structure 10K, and Figure 5C the semiconductor device 300 in the semiconductor structure 10L. The semiconductor device 300 may be a resistor device. The semiconductor device 300 may include a doped region 302. In addition, Figures 1A to 1C and Figures 3A to 5C in, the same or similar components are denoted by the same reference numerals, and their descriptions are omitted.
[0060] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined by the claims.
Claims
1. A semiconductor structure, comprising: a substrate including a device region; and an isolation structure located in the substrate and surrounding the device region, wherein the isolation structure includes: a first dielectric layer and a second dielectric layer located in the substrate, wherein the first dielectric layer is located between the second dielectric layer and the substrate, and the second dielectric layer includes: a first portion; and a second portion located on the first portion, wherein the distance between the second portion and the substrate in the device region is greater than the distance between the first portion and the substrate in the device region.
2. The semiconductor structure according to claim 1, wherein the dielectric constant of the first dielectric layer is lower than the dielectric constant of the second dielectric layer.
3. The semiconductor structure according to claim 1, wherein the second dielectric layer has a depression adjacent to the device region, and the depression is located between the second portion and the substrate in the device region.
4. The semiconductor structure according to claim 1, wherein the upper surface of the first dielectric layer adjacent to the device region is lower than the top surface of the second dielectric layer.
5. The semiconductor structure according to claim 1, wherein there is a gap between the second portion and the substrate in the device region, and the isolation structure further includes: a filling structure located between the second portion and the substrate in the device region, wherein the filling structure includes: a filling layer only located between the top of the second portion and the substrate in the device region and sealing the top of the gap; and an air gap located between the second portion and the substrate in the device region, between the filling layer and the first dielectric layer, and between the filling layer and the first portion.
6. The semiconductor structure according to claim 5, wherein the air gap directly contacts the substrate, the filling layer, the first dielectric layer, the first portion, and the second portion.
7. The semiconductor structure according to claim 5, wherein the dielectric constant of the filling layer and the dielectric constant of the air gap are lower than the dielectric constant of the second dielectric layer.
8. The semiconductor structure according to claim 1, wherein there is a gap between the second portion and the substrate in the device region, and the isolation structure further includes: a filling structure located between the second portion and the substrate in the device region, wherein the filling structure includes: a filling layer filling the gap.
9. The semiconductor structure according to claim 8, wherein the dielectric constant of the filling layer is lower than the dielectric constant of the second dielectric layer.
10. The semiconductor structure according to claim 1, wherein there is a gap between the second portion and the substrate in the device region, and the isolation structure further includes: a filling structure located between the second portion and the substrate in the device region, wherein the filling structure includes: a filling layer filling and sealing the gap; and an air gap located in the filling layer and surrounded by the filling layer.
11. The semiconductor structure according to claim 10, wherein the dielectric constant of the filling layer and the dielectric constant of the air gap are lower than the dielectric constant of the second dielectric layer.
12. The semiconductor structure according to claim 1, wherein the isolation structure further comprises: a third dielectric layer, located in the second dielectric layer and surrounded by the second dielectric layer, wherein the dielectric constant of the third dielectric layer is lower than the dielectric constant of the second dielectric layer; and a semiconductor device, located in the device region.
13. The semiconductor structure according to claim 12, wherein the semiconductor device comprises an active device or a passive device.
14. A semiconductor structure, comprising: a substrate, comprising a device region; an isolation structure, located in the substrate and surrounding the device region, wherein the isolation structure comprises: a first dielectric layer and a second dielectric layer, located in the substrate, wherein the first dielectric layer is located between the second dielectric layer and the substrate, and the second dielectric layer comprises: a first portion; and a second portion, located on the first portion, wherein the distance between the second portion and the substrate in the device region is greater than the distance between the first portion and the substrate in the device region; and a semiconductor device, located in the device region and comprising: a gate, located on the substrate; a gate dielectric layer, located between the gate and the substrate; and a first doped region and a second doped region, located in the substrate on both sides of the gate.