Display panel and manufacturing method of display panel

Abstract

The invention relates to a display panel and a manufacturing method of the display panel. The display panel includes: a base layer; a transistor on the base layer and including a semiconductor pattern; a first connection electrode connected to the semiconductor pattern; a sensing line at the same layer as the first connection electrode; a first insulating layer on the transistor and the first connection electrode; a second insulating layer on the first insulating layer; a first electrode on the second insulating layer and connected to the connection electrode through a first via; an additional electrode on the second insulating layer, the additional electrode spaced apart from the first electrode in a plan view, and connected to the sensing line through a second via; and a sensing pattern on the first insulating layer, the sensing pattern being electrically connected to the first electrode and the additional electrode, and including silicon.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority and the benefit of Korean Patent Application No. 10-2024-0006150, filed with the Korean Intellectual Property Office on January 15, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure herein relates to a display panel and a method of manufacturing the display panel, and more particularly, to a display panel having improved luminous efficiency and power consumption and a method of manufacturing the display panel. Background Art

[0004] Multimedia devices such as televisions, mobile phones, computers (such as tablet personal computers (PCs)), navigation devices, and game consoles may include a display panel for displaying an image. The display panel may include a plurality of pixels for displaying an image, and each of the plurality of pixels may include a light-emitting element that generates light and a driving element connected to the light-emitting element.

[0005] The light-emitting element and the driving element of the display panel may be formed by stacking thin films and patterning the thin films using a mask. Since the manufacturing process for the display panel using a mask is expensive, it is necessary to simplify the manufacturing process for the display panel to reduce the number of masks required to manufacture the display device. In addition, it is necessary to manufacture a display panel having improved luminous efficiency and power consumption while simplifying the manufacturing process. Summary of the Invention

[0006] The present disclosure provides a display panel having improved luminous efficiency and power consumption.

[0007] The present disclosure provides a method of manufacturing a display panel having improved manufacturing process efficiency.

[0008] One or more embodiments of the present disclosure provide a display panel including: a substrate layer; a transistor on the substrate layer and including a semiconductor pattern; a first connection electrode connected to the semiconductor pattern; a sensing line at the same layer as the first connection electrode; a first insulating layer on the transistor and the first connection electrode; a second insulating layer on the first insulating layer; a first electrode on the second insulating layer and connected to the connection electrode through a first through hole; an additional electrode on the second insulating layer, the additional electrode being spaced apart from the first electrode in a plan view and connected to the sensing line through a second through hole; and a sensing pattern on the first insulating layer, the sensing pattern being electrically connected to the first electrode and the additional electrode and including silicon.

[0009] In one or more embodiments, the light transmittance of the sensing pattern in the visible light wavelength range may be about 10% or greater.

[0010] In one or more embodiments, the display panel may further include a gate insulating pattern layer on the semiconductor pattern. Each of the first connection electrode and the sensing line may be on the gate insulating pattern layer.

[0011] In one or more embodiments, the transistor may further include a gate electrode on the gate insulating pattern layer.

[0012] In one or more embodiments, the first connection electrode, the sensing line, and the gate electrode may include the same material.

[0013] In one or more embodiments, the sensing pattern may further include nitrogen.

[0014] In one or more embodiments, the display panel may further include an intermediate layer and a second electrode on the intermediate layer, the intermediate layer being on the first electrode and including an emission layer.

[0015] In one or more embodiments, the first electrode and the additional electrode may be spaced apart from each other along a first direction. The width of the first electrode in the first direction may be greater than the width of the additional electrode in the first direction.

[0016] In one or more embodiments, the distance between the first electrode and the additional electrode in the first direction may be greater than the width of the additional electrode in the first direction.

[0017] In one or more embodiments, the length of the first electrode in a second direction intersecting the first direction may be substantially the same as the length of the additional electrode in the second direction.

[0018] In one or more embodiments, each of the first through hole and the second through hole may pass through each of the first insulating layer, the second insulating layer, and the sensing pattern.

[0019] In one or more embodiments, each of the first through hole and the second through hole may include a plurality of through holes.

[0020] In one or more embodiments, the first electrode and the additional electrode may be spaced apart from each other along a first direction. Each of the first through hole and the second through hole may include a long side extending in a second direction intersecting the first direction and a short side extending in the first direction.

[0021] In one or more embodiments, the display panel may further include an underlying insulating layer between the substrate layer and the transistor, and a plurality of conductive patterns between the underlying insulating layer and the substrate layer and spaced apart from each other in a plan view. At least a portion of the plurality of conductive patterns may be electrically connected to the first connection electrode.

[0022] In one or more embodiments, the display panel may further include a pixel defining layer on the second insulating layer and having a pixel opening formed therein and exposing at least a portion of the first electrode. The additional electrode may be covered by the pixel defining layer.

[0023] In one or more embodiments, the transmittance of the second insulating layer in a visible light wavelength range may be about 80% or greater.

[0024] In an embodiment of the present disclosure, a display panel includes: a substrate layer; a transistor on the substrate layer and including a semiconductor pattern; a first connection electrode connected to the semiconductor pattern; a sensing line spaced apart from the first connection electrode in a plan view; a first insulating layer on the transistor and the first connection electrode; a second insulating layer on the first insulating layer; a light-emitting element on the second insulating layer and electrically connected to the first connection electrode; an additional electrode on the second insulating layer and connected to the sensing line; and a sensing pattern on the first insulating layer. The light-emitting element includes a first electrode on the second insulating layer, connected to the first connection electrode, and spaced apart from the additional electrode in a plan view, an emission layer on the first electrode, and a second electrode on the emission layer. A portion of each of the first electrode and the additional electrode is in a through hole in the sensing pattern.

[0025] In one or more embodiments, the display panel may further include a pixel defining layer on the second insulating layer and having a pixel opening defined therein and exposing at least a portion of the first electrode. The additional electrode may be covered by the pixel defining layer.

[0026] In one or more embodiments of the present disclosure, a method of manufacturing a display panel includes: forming a semiconductor pattern on a substrate layer; forming a gate insulating pattern layer covering a part of the semiconductor pattern; forming a first connection electrode and a sensing line on the gate insulating pattern layer; forming a first insulating layer covering the first connection electrode and the sensing line; forming a sensing pattern including silicon on the first insulating layer; forming a second insulating layer covering the sensing pattern; forming each of a first through hole and a second through hole passing through the first insulating layer, the sensing pattern, and the second insulating layer; and forming a first electrode connected to the first connection electrode through the first through hole and an additional electrode connected to the sensing line through the second through hole on the second insulating layer.

[0027] In one or more embodiments, in the forming of the sensing pattern, nitrogen (N2) gas and silane (SiH4) gas may be provided. The ratio of nitrogen gas to silane gas may be from about 4.0 to about 10. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure. In the drawings:

[0029] Figure 1 is a perspective view of a display device according to one or more embodiments of the present disclosure;

[0030] Figure 2A is an exploded perspective view of a display device according to one or more embodiments of the present disclosure;

[0031] Figure 2B is a cross-sectional view of a display module according to one or more embodiments of the present disclosure;

[0032] Figure 3 is a plan view of a display panel according to one or more embodiments of the present disclosure;

[0033] Figure 4 is a cross-sectional view of a part of a display module according to one or more embodiments of the present disclosure;

[0034] Figure 5 is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure;

[0035] Figure 6A and Figure 6B are each a plan view of some components of a display panel according to one or more embodiments of the present disclosure;

[0036] Figure 7is a plan view of some components of a display panel according to one or more embodiments of the present disclosure;

[0037] Figures 8A to 8E Each is a plan view of some components of a display panel according to one or more embodiments of the present disclosure;

[0038] Figure 9 is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure;

[0039] Figure 10 is a flowchart of a method of manufacturing a display panel according to one or more embodiments of the present disclosure;

[0040] Figures 11A to 11D is a cross-sectional view of some steps of a method of manufacturing a display panel according to one or more embodiments of the present disclosure;

[0041] Figure 12A is a graph showing values of leakage current compared to the voltage of a sensing pattern according to the amount of light emitted by a light-emitting element in a display panel according to one or more embodiments; and

[0042] Figure 12B is a graph showing values of leakage current compared to the amount of light emitted by a light-emitting element according to the voltage applied to a sensing pattern in a display panel according to one or more embodiments. Detailed Description

[0043] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0044] In this specification, it will be understood that when an element (or region, layer, part, etc.) is referred to as being "on" another element, "connected to" or "coupled to" another element, the element can be directly connected or coupled to the other element, or an intervening element can be provided between the element and the other element.

[0045] The same numbers or symbols always refer to the same elements. Additionally, in the drawings, the thickness, ratio, and dimensions of the elements are exaggerated for effective description of the technical content. The term "and / or" includes all one or more combinations that the related elements can define.

[0046] Although terms such as first, second, etc. may be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the spirit and scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can also be referred to as the first element. Unless the context clearly indicates otherwise, the singular form also includes the plural form.

[0047] Additionally, terms such as "below", "lower side", "above", and "upper side" are used to describe the relationships of the elements shown in the drawings. These terms have relative concepts and are described based on the directions indicated in the drawings.

[0048] It will be understood that when terms such as "comprising" or "having" are used herein, they are intended to specify the presence of the stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0049] As used herein, "directly disposed" may mean that no layer, film, region, plate, etc. is added between a part such as a layer, film, region, or plate and another part. For example, "directly disposed" may mean disposing two layers or two members without using an additional member such as an adhesive member therebetween.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Additionally, unless explicitly defined herein, terms (such as those defined in a general dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized and / or overly formal sense.

[0051] For the purposes of this disclosure, expressions such as "at least one (s / er) of...", "one (s / er) of...", and "selected from..." when preceding or following a list of elements modify the entire list of elements, rather than individual elements of the list. For example, "at least one (s / er) of X, Y, and Z" and "at least one (s / er) selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as XYZ, XY, XZ, and YZ for example) or any variation thereof. Similarly, an expression such as "at least one (s / er) of A and B" can include A, B, or A and B. As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items. For example, an expression such as "A and / or B" can include A, B, or A and B. Additionally, when "may" is used in describing embodiments of the present disclosure, it refers to "one or more embodiments of the present disclosure".

[0052] In addition, any numerical range disclosed and / or recited herein is intended to include all sub-ranges of the same numerical precision contained within the recited range. For example, the range of "1.0 to 10.0" is intended to include all sub-ranges between the recited minimum value of 1.0 and the recited maximum value of 10.0 (and including the endpoint values), e.g., having a minimum value equal to or greater than 1.0 and a maximum value less than or equal to 10.0, such as taking 2.4 to 7.6 as an example. Any maximum numerical limitation recited herein is intended to include all smaller numerical limitations contained within that maximum numerical limitation, and any minimum numerical limitation recited in this specification is intended to include all larger numerical limitations contained within that minimum numerical limitation. Thus, the applicant reserves the right to amend this specification including the claims to expressly recite any sub-ranges contained within the ranges expressly recited herein. All such ranges are intended to be inherently described in this specification such that amending to expressly recite any such sub-ranges.

[0053] Those of ordinary skill in the art will recognize that, given the overall content of the present disclosure, unless otherwise stated or implied, each suitable feature of the various embodiments of the present disclosure can be combined or incorporated in part or in whole with one another and can be interlocked and operated technically in various suitable ways, and each embodiment can be implemented independently of one another or in combination with one another in any suitable way.

[0054] Hereinafter, a display panel and a method of manufacturing the display panel according to one or more embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0055] Figure 1 is a perspective view of a display device according to one or more embodiments of the present disclosure.

[0056] Reference Figure 1 , the display device DD can be activated in response to an electrical signal and display an image. The display device DD can include various embodiments that provide an image IM to a user, and for example, the display device DD can be a large-sized device such as a television and an outdoor billboard, and a small-sized device or a medium-sized device such as a monitor, a mobile phone, a tablet PC, a navigation device, and a game console. However, the embodiments of the display device DD are used as examples, and the display device DD is not limited to any one embodiment and will be applied to any suitable embodiment as long as the display device DD does not deviate from the scope of the present disclosure.

[0057] The display device DD can have a rectangular shape in a plan view, the rectangular shape having a long side extending in a first direction DR1 and a short side extending in a second direction DR2. However, the present disclosure is not limited thereto, and the display device DD can have various shapes such as a circle and / or other polygons.

[0058] The display device DD can display an image IM in a third direction DR3 (e.g., the thickness direction of the display device DD) through a display surface IS parallel to the plane defined by the first direction DR1 and the second direction DR2. The third direction DR3 can be substantially parallel to the normal direction of the display surface IS. The display surface IS on which the image IM is displayed can correspond to the front surface of the display device DD. The image IM can include a still image and a moving image. Figure 1 An icon image is shown as an example of the image IM.

[0059] In this embodiment, the front surface (or upper surface) and the rear surface (or lower surface) of each component constituting the display device DD can be defined based on the third direction DR3. The front surface and the rear surface can be opposite to each other in the third direction DR3 (e.g., contrary), and the normal direction of each of the front surface and the rear surface can be parallel to the third direction DR3. The distance between the front surface and the rear surface defined along the third direction DR3 can correspond to the thickness of the component.

[0060] As used herein, the phrase "in a plan view" can be defined as a state viewed in the third direction DR3. As used herein, the phrase "in a cross-sectional view" can be defined as a state viewed in the first direction DR1 or the second direction DR2. However, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 can have relative concepts and can thus be changed to other directions.

[0061] As an example, Figure 1 A display device DD with a flat display surface IS is shown. However, the form of the display surface IS of the display device DD is not limited thereto, and the display surface IS can be a curved display surface and / or a three-dimensional display surface.

[0062] The display device DD can be flexible. "Flexible" can mean bendable characteristics, and the display device DD can be a device including any one of structures ranging from a fully foldable structure to a structure bendable to the level of several nanometers. For example, the flexible display device DD can include a bending device and / or a foldable device. However, the present disclosure is not limited thereto, and the display device DD can be rigid.

[0063] The display surface IS of the display device DD may include a display portion D-DA and a non-display portion D-NDA disposed along the edge or periphery of the display portion D-DA and surrounding the display portion D-DA. The display portion D-DA may be a portion of the display image IM on the front surface of the display device DD, and the user may view the image IM through the display portion D-DA. In this embodiment, as an example, the display portion D-DA having a quadrilateral shape in a plan view is shown, but the display portion D-DA may have various shapes according to the design of the display device DD.

[0064] The non-display portion D-NDA may be a portion on the front surface of the display device DD that does not display the image IM. The non-display portion D-NDA may be a portion having a suitable color (e.g., a predetermined color) and blocking light. The non-display portion D-NDA may be adjacent to the display portion D-DA. For example, the non-display portion D-NDA may be disposed outside the display portion D-DA and surround the display portion D-DA. However, this is shown as an example, and the non-display portion D-NDA may be adjacent to only one side of the display portion D-DA, or may be disposed on the side surface rather than the front surface of the display device DD. The present disclosure is not limited thereto, and the non-display portion D-NDA may also be omitted.

[0065] In one or more embodiments, the display device DD may sense an external input applied from the outside. The external input may have various forms such as temperature, light, and pressure provided from the outside. The external input may include not only an input that contacts the display device DD (e.g., contact by a user's hand or pen), but also an input applied close to the display device DD (e.g., hovering).

[0066] Figure 2A is an exploded perspective view of a display device according to one or more embodiments of the present disclosure. Figure 2B is a cross-sectional view of a display module according to one or more embodiments of the present disclosure.

[0067] Reference Figure 2A and Figure 2B and

[0068] The window WM and the housing HAU may be coupled to each other to form the exterior of the display device DD and to provide an internal space capable of accommodating components such as the display module DM of the display device DD.

[0069] The window WM can be disposed on the display module DM. The window WM can protect the display module DM from external impacts. The front surface of the window WM can correspond to the display surface IS of the display device DD described above. The front surface of the window WM can include a transmissive region TA and a border region BA.

[0070] The transmissive region TA of the window WM can be an optically transparent region. The window WM can transmit the image provided by the display module DM through the transmissive region TA, and the user can view the image. The transmissive region TA can correspond to the display portion D-DA of the display device DD described above (see Figure 1 ).

[0071] The window WM can include an optically transparent insulating material. For example, the window WM can include glass, sapphire, and / or plastic. The window WM can have a single-layer structure or a multi-layer structure. The window WM can also include functional layers provided on an optically transparent substrate, such as an anti-fingerprint layer, a phase control layer, and / or a hard coating layer.

[0072] The border region BA of the window WM can be provided as a region where a material having a suitable color (e.g., a predetermined color) is deposited, applied, and / or printed on a transparent substrate. The border region BA of the window WM can prevent components of the display module DM that are set to overlap with the border region BA from being seen from the outside. The border region BA can correspond to the non-display portion D-NDA of the display device DD described above (see Figure 1 ).

[0073] The display module DM can be disposed between the window WM and the housing HAU. The display module DM can display an image in response to an electrical signal. The display module DM can include a display region DA and a non-display region NDA adjacent to the display region DA. The non-display region NDA can surround the display region DA along the edge or periphery of the display region DA.

[0074] The display region DA can be a region that is activated in response to an electrical signal and in which an image is output or displayed. The display region DA of the display module DM can overlap with the transmissive region TA of the window WM. As used herein, the phrase "a region / portion and a region / portion overlap with each other" is not limited to the case where the region / portion has the same area size and / or the same shape. The image output from the display region DA can be viewed from the outside through the transmissive region TA.

[0075] The non-display area NDA may be adjacent to the display area DA. For example, the non-display area NDA may surround the display area DA. However, the present disclosure is not limited thereto, and the non-display area NDA may be defined in various shapes. The non-display area NDA may be an area in which driving lines or driving circuits for driving elements provided in the display area DA, various types of signal lines for providing electrical signals, and pads are provided. The non-display area NDA of the display module DM may overlap with the border area BA of the window WM, and components provided in the non-display area NDA may be prevented from being seen from the outside through the border area BA.

[0076] The display panel DP according to one or more embodiments may be an emissive display panel. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, and / or a quantum dot light-emitting display panel. The emission layer of the organic light-emitting display panel may include an organic light-emitting material, and the emission layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. The emission layer of the quantum dot light-emitting display panel may include quantum dots, quantum rods, etc. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0077] The display panel DP may include a substrate layer BS, a circuit element layer DP-CL, a display element layer DP-LED, and a packaging layer TFE.

[0078] The substrate layer BS may provide a substrate surface on which the circuit element layer DP-CL is provided. The substrate layer BS may be a rigid substrate, but is not limited thereto, and may be a flexible substrate.

[0079] The circuit element layer DP-CL may be provided on the substrate layer BS. The circuit element layer DP-CL may include driving elements such as transistors, signal lines, and / or signal pads. The display element layer DP-LED may include light-emitting elements provided to overlap with the display area DA. The light-emitting elements of the display element layer DP-LED may be electrically connected to the driving elements of the circuit element layer DP-CL, and output light through the display area DA in response to signals from the driving elements. The configuration of the circuit element layer DP-CL will be described in detail with reference to Figure 5 and the subsequent drawings.

[0080] The packaging layer TFE may be provided on the display element layer DP-LED and package the light-emitting elements. The packaging layer TFE may include a plurality of thin films. The thin films of the packaging layer TFE may be provided to improve the optical efficiency of the light-emitting elements or protect the light-emitting elements.

[0081] The light control member LCM may be disposed on the display panel DP. The light control member LCM may be provided on the display panel DP and then coupled to the display panel DP through a bonding process using the sealing member SML.

[0082] However, the present disclosure is not limited thereto, and the light control member LCM may be directly disposed on the display panel DP. As used herein, the expression "directly disposed" may indicate formation by a continuous process without disposing a separate adhesive layer or adhesive member. For example, the expression "the light control member LCM is directly disposed on the display panel DP" may indicate that the display panel DP is formed and then the light control member LCM is formed on the substrate surface provided by the display panel DP by a continuous process.

[0083] The light control member LCM may convert the wavelength of the light (i.e., source light) provided by the display panel DP, or selectively transmit the source light. For example, the light control member LCM may include a light control pattern capable of converting the optical characteristics of the source light provided by the display panel DP. The light control member LCM may control the color purity or color gamut of the light emitted from the display device DD and prevent reflection of external light incident from the outside of the display device DD.

[0084] The light control member LCM may include a substrate layer BL, a color filter layer CFL, and a light control layer CCL. The substrate layer BL may be disposed to face the substrate layer BS of the display panel DP, and the color filter layer CFL and the light control layer CCL disposed on the substrate layer BL may be located between the display panel DP and the substrate layer BL.

[0085] The light control layer CCL may include quantum dots that convert the wavelength of the source light provided by the display panel DP, or may further include a transmissive portion that transmits the source light. The source light that has passed through the quantum dots included in the light control layer CCL may be output as light having a color different from the color of the source light.

[0086] The color filter layer CFL may include color filters, and the color filters may transmit and / or absorb the light passing through the light control layer CCL according to the color of the light. The color filter layer CFL may absorb the light not converted by the light control layer CCL, thereby preventing deterioration of the color purity of the display device DD. In addition, the color filter layer CFL may filter the external light to the same color as the color of the pixels, thereby preventing or reducing external light reflection.

[0087] The sealing member SML may be disposed in the non-display area NDA that is the peripheral portion of the display module DM, and prevent foreign substances, oxygen, moisture, etc. from being introduced into the display module DM from the outside of the display module DM. The sealing member SML may be formed of a sealant including a curable resin.

[0088] The display module DM according to one or more embodiments may further include a filling layer FML disposed between the display panel DP and the light control member LCM. The filling layer FML may fill the space between the display panel DP and the light control member LCM. The filling layer FML may serve as a buffer between the display panel DP and the light control member LCM. In one or more embodiments, the filling layer FML may absorb shock and increase the strength of the display module DM.

[0089] The filling layer FML may be formed of a filling resin including a polymer resin. For example, the filling layer FML may include an acrylic resin and / or an epoxy resin, etc. However, since the light control member LCM according to one or more embodiments may be directly disposed on the display panel DP, the filling layer FML and the sealing member SML may be omitted. In one or more embodiments where the light control member LCM is directly disposed on the display panel DP, the base layer BL of the light control member LCM may be omitted.

[0090] The housing HAU may be disposed under the display module DM and accommodate the display module DM. The housing HAU may protect the display module DM by absorbing shock applied to the display module DM from the outside and preventing foreign substances and / or moisture, etc. from being introduced into the display module DM. The housing HAU according to one or more embodiments may be provided in a form in which a plurality of accommodating members are coupled to each other.

[0091] In one or more embodiments, the display device DD may further include an input sensing module. The input sensing module may acquire coordinate information about an external input applied from the outside of the display device DD. The input sensing module may be driven using various methods such as a capacitance method, a resistance method, an infrared method, and / or a pressure method, and is not limited thereto.

[0092] In one or more embodiments, the input sensing module may be disposed on the display module DM. The input sensing module may be directly disposed on the display module DM through a continuous process, but is not limited thereto, and may be separately manufactured from the display module DM and attached to the display module DM through an adhesive layer. However, the present disclosure is not limited thereto, and the input sensing module may be disposed between components of the display module DM. For example, the input sensing module may be arranged between the display panel DP and the light control member LCM.

[0093] Figure 3 is a plan view of a display panel according to one or more embodiments of the present disclosure.

[0094] Reference Figure 3 , the display panel DP may include pixels PX disposed in the display area DA 11 to PX nm and electrically connected to the pixels PX11 to PX nm The signal lines SL1 to SLn and DL1 to DLm, where n and m are positive integers. The display panel DP may include pads PD and a driving circuit GDC provided in the non-display area NDA.

[0095] Pixel PX 11 to PX nm Each of which may include a pixel driving circuit, and the pixel driving circuit includes a light-emitting element, a plurality of transistors (e.g., a switching transistor, a driving transistor, etc.) connected to the light-emitting element, and a capacitor. Pixel PX 11 to PX nm may emit light in response to an electrical signal applied to pixel PX 11 to PX nm . By way of example, Figure 3 shows pixels PX arranged in a matrix form 11 to PX nm , but the arrangement of pixels PX 11 to PX nm is not limited to this.

[0096] The signal lines SL1 to SLn and DL1 to DLm may include scan lines SL1 to SLn and data lines DL1 to DLm. Each of pixels PX 11 to PX nm may be connected to a corresponding scan line from among the scan lines SL1 to SLn and a corresponding data line from among the data lines DL1 to DLm. Depending on the configuration of the pixel driving circuit of pixel PX 11 to PX nm , more various types of signal lines may be included in the display panel DP.

[0097] The driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate a gate signal and sequentially output the gate signal to the scan lines SL1 to SLn. The gate driving circuit may further output another control signal to the pixel driving circuit of pixel PX 11 to PX nm .

[0098] The driving circuit GDC and pixel PX according to one or more embodiments 11 to PX nm may include a plurality of transistors formed by a low-temperature polysilicon (LTPS) process, a low-temperature polycrystalline oxide (LTPO) process, and / or an oxide semiconductor process.

[0099] The pads PD can be arranged in the non-display area NDA along one direction. The pads PD can be parts connected to the circuit board. Each of the pads PD can be connected to a corresponding signal line from among the signal lines SL1 to SLn and DL1 to DLm, and is connected to a corresponding pixel from among the pixels PX 11 to PX nm among them. The pads PD can have a shape integrated with the signal lines SL1 to SLn and DL1 to DLm. However, the present disclosure is not limited thereto, and the pads PD and the signal lines SL1 to SLn and DL1 to DLm can be provided on different layers, and the pads PD can be connected to the signal lines SL1 to SLn and DL1 to DLm through contact holes.

[0100] Figure 4 is a cross-sectional view of a part of a display module according to one or more embodiments of the present disclosure. Figure 4 Shows along Figure 3 a cross-section of the display panel and the light control member provided on the display panel taken along the line I-I' shown in.

[0101] Refer to Figure 4 , the display module DM can include a display panel DP and a light control member LCM provided on the display panel DP. The display panel DP includes a substrate layer BS, a circuit element layer DP-CL provided on the substrate layer BS, and a display element layer DP-LED provided on the circuit element layer DP-CL. The light control member LCM can include a light control layer CCL, a color filter layer CFL, and a substrate layer BL. In the present specification, the display panel DP can be referred to as the lower panel, and the light control member LCM can be referred to as the upper panel.

[0102] The display panel DP can include a substrate layer BS and a circuit element layer DP-CL provided on the substrate layer BS. The circuit element layer DP-CL can be provided on the substrate layer BS. The circuit element layer DP-CL can include an insulating layer, a semiconductor pattern, a conductive pattern, and / or signal lines, etc. The insulating layer, the semiconductor layer, and / or the conductive layer can be formed on the substrate layer BS by coating and / or deposition, etc., and then, the insulating layer, the semiconductor layer, and / or the conductive layer can be selectively patterned by a photolithography process performed multiple times. Thereafter, the semiconductor pattern, the conductive pattern, and / or the signal lines included in the circuit element layer DP-CL can be formed. In one or more embodiments, the circuit element layer DP-CL can include transistors, buffer layers, and / or multiple insulating layers. The configuration of the circuit element layer DP-CL will be described in detail with reference to Figure 5 and the subsequent drawings.

[0103] A light-emitting element LED according to one or more embodiments may include a first electrode AE, a second electrode CE facing the first electrode AE, and an emission layer EML disposed between the first electrode AE and the second electrode CE. The emission layer EML included in the light-emitting element LED may include an organic light-emitting material as a light-emitting material and / or include quantum dots as a light-emitting material. The light-emitting element LED may further include a hole control layer HTR and an electron control layer ETR. In one or more embodiments, the light-emitting element LED may further include a cover layer disposed on the second electrode CE.

[0104] A pixel defining layer PDL may be disposed on the circuit element layer DP-CL and cover a part of the first electrode AE. A light-emitting opening OH is defined in the pixel defining layer PDL. At least a part of the first electrode AE is exposed by the light-emitting opening OH of the pixel defining layer PDL. In this embodiment, light-emitting regions EA1, EA2, and EA3 are defined to correspond to partial regions of the first electrode AE exposed by the light-emitting opening OH.

[0105] A display element layer DP-LED may include a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3. The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be regions separated from each other by the pixel defining layer PDL. The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may correspond to a first pixel region PXA-R, a second pixel region PXA-B, and a third pixel region PXA-G, respectively.

[0106] The light-emitting regions EA1, EA2, and EA3 may overlap with the pixel regions PXA-R, PXA-B, and PXA-G. In a plan view, the area sizes of the pixel regions PXA-R, PXA-B, and PXA-G separated from each other by color filters CF1, CF2, and CF3 may be substantially the same as the area sizes of the light-emitting regions EA1, EA2, and EA3 separated from each other by the pixel defining layer PDL.

[0107] The first electrode AE in the light-emitting element LED is disposed on the circuit element layer DP-CL. The first electrode AE may be an anode or a cathode. Additionally, the first electrode AE may be a pixel electrode. The first electrode AE may be a transmissive electrode, a semi-transmissive reflective electrode, or a reflective electrode.

[0108] The light-emitting element LED includes at least an emission layer EML. In one or more embodiments, the emission layer EML may be provided as a common layer so as to overlap with all light-emitting regions EA1, EA2, and EA3 and the pixel-defining layer PDL that separates the light-emitting regions EA1, EA2, and EA3. In one or more embodiments, the emission layer EML may emit blue light. The emission layer EML may completely overlap with the electron control layer ETR and the hole control layer HTR.

[0109] However, the present disclosure is not limited thereto, and in one or more embodiments, the emission layer EML may be disposed in the light-emitting opening OH. That is, the emission layer EML may be separately formed to correspond to the light-emitting regions EA1, EA2, and EA3 separated from each other by the pixel-defining layer PDL. The emission layer EML separately formed to correspond to the light-emitting regions EA1, EA2, and EA3 may all emit blue light, or may also emit light having different wavelength ranges.

[0110] The emission layer EML may have a single-layer structure formed of a single material, a single-layer structure formed of a plurality of different materials, or a multi-layer structure having a plurality of layers formed of a plurality of different materials. The emission layer EML may include fluorescent and / or phosphorescent materials. The emission layer EML in the light-emitting element according to one or more embodiments may include an organic light-emitting material, a metal-organic complex, and / or a quantum dot, etc. as the light-emitting material. As an example Figure 4 A light-emitting element LED including one emission layer EML is shown, but in one or more embodiments, the light-emitting element LED may further include a plurality of light-emitting stacks each including at least one emission layer.

[0111] The light-emitting element LED may emit light in the direction from the first electrode AE to the second electrode CE. In the light-emitting element LED according to one or more embodiments, the hole control layer HTR may transfer the holes provided from the first electrode AE to the emission layer EML. The electron control layer ETR may transfer the electrons provided from the second electrode CE to the emission layer EML.

[0112] As an example is shown, with respect to the direction of the emitted light, the light-emitting element LED according to one or more embodiments has a structure in which the hole control layer HTR is disposed below the emission layer EML and the electron control layer ETR is disposed above the emission layer EML. That is, the light-emitting element LED according to one or more embodiments may have a forward element structure. However, the present disclosure is not limited thereto, and with respect to the direction of the emitted light, the light-emitting element LED may also have an inverted element structure in which the electron control layer ETR is disposed below the emission layer EML and the hole control layer HTR is disposed above the emission layer EML.

[0113] The hole control layer HTR may include a hole injection layer and a hole transport layer disposed on the hole injection layer. The hole transport layer may be in contact with the lower surface of the emission layer EML. However, the present disclosure is not limited thereto, and the hole control layer HTR may further include a hole-side additional layer disposed on the hole transport layer. The hole-side additional layer may include at least one of a hole buffer layer, an emission assist layer, and an electron blocking layer. The hole buffer layer may be a layer that compensates for the resonance distance according to the wavelength of light emitted from the emission layer EML and increases the light emission efficiency. The electron blocking layer may be a layer for preventing electrons from being injected from the electron control layer ETR into the hole control layer HTR.

[0114] The electron control layer ETR may include an electron transport layer. The electron control layer ETR may further include an electron injection layer disposed on the electron transport layer. The electron control layer ETR may further include an electron-side additional layer disposed between the electron transport layer and the emission layer EML. The electron-side additional layer may include at least one of an electron buffer layer and a hole blocking layer.

[0115] In a light-emitting element LED according to one or more embodiments, the first electrode AE may be a reflective electrode. For example, the first electrode AE may include a highly reflective metal such as Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W, In, Zn, Sn, and / or its compounds and / or mixtures (e.g., a mixture of Ag and Mg), or a material having a multilayer structure such as LiF / Ca or LiF / Al. Optionally, the first electrode AE may have a multilayer structure including a reflective film formed of the material and a transparent conductive film formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc. For example, the first electrode AE may have a bilayer structure of ITO / Ag and a trilayer structure of ITO / Ag / ITO, but is not limited thereto. Additionally, the present disclosure is not limited thereto, and the first electrode AE may include the above metal materials, a combination of two or more metal materials selected from the above metal materials, or oxides of the above metal materials, etc. The thickness of the first electrode AE may be about 70 nm to about 1000 nm. For example, the thickness of the first electrode AE may be about 100 nm to about 300 nm.

[0116] In a light-emitting element LED according to one or more embodiments, the hole control layer HTR may have a single-layer structure formed of a single material, a single-layer structure formed of a plurality of different materials, or a multilayer structure having a plurality of layers formed of a plurality of different materials.

[0117] The hole control layer HTR can be formed by using various methods such as vacuum deposition method, spin coating method, casting method, Langmuir-Blodgett (LB) method, inkjet printing method, laser printing method, and / or laser-induced thermal imaging (LITI) method.

[0118] The hole control layer HTR can include phthalocyanine compounds such as copper phthalocyanine, N 1 ,N 1 '-([1,1'-biphenyl]-4,4'-diyl)bis(N 1 -phenyl-N 4 ,N 4 -di-m-tolylbenzene-1,4-diamine) (DNTPD), 4,4',4"-[tris(3-methylphenyl)phenylamino]triphenylamine (m-MTDATA), 4,4',4"-tris(N,N-diphenylamino)triphenylamine (TDATA), 4,4',4"-tris[N(2-naphthyl)-N-phenylamino]-triphenylamine (2-TNATA), poly(3,4-ethylenedioxythiophene) / poly(4-styrenesulfonate) (PEDOT / PSS), polyaniline / dodecylbenzenesulfonic acid (PANI / DBSA), polyaniline / camphorsulfonic acid (PANI / CSA), polyaniline / poly(4-styrenesulfonate) (PANI / PSS), N,N'-bis(naphthalen-1-yl)-N,N'-diphenyl-benzidine (NPB), triarylamine-containing polyether ketone (TPAPEK), 4-isopropyl-4'-methyldiphenyliodonium [tetrakis(pentafluorophenyl)borate], dipyrazino[2,3-f:2',3'-h]quinoxaline-2,3,6,7,10,11-hexacarbonitrile (HATCN), etc.

[0119] The hole control layer HTR can also include carbazole derivatives such as N-phenylcarbazole and polyvinylcarbazole, fluorene derivatives, N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1'-biphenyl]-4,4'-diamine (TPD), triarylamine derivatives such as 4,4',4"-tris(N-carbazolyl)triphenylamine (TCTA), N,N'-bis(naphthalen-1-yl)-N,N'-diphenyl-benzidine (NPB), 4,4'-cyclohexylidenebis[N,N-bis(4-methylphenyl)aniline] (TAPC), 4,4'-bis[N,N'-(3-tolyl)amino]-3,3'-dimethylbiphenyl (HMTPD), 1,3-bis(N-carbazolyl)benzene (mCP), etc.

[0120] In addition, the hole control layer HTR may include 9-(4-tert-butylphenyl)-3,6-bis(triphenylsilyl)-9H-carbazole (CzSi), 9-phenyl-9H-3,9'-bicarbazole (CCP), 1,3-bis(1,8-dimethyl-9H-carbazol-9-yl)benzene (mDCP), etc.

[0121] The hole control layer HTR may include the above compounds in at least one of the hole injection layer, the hole transport layer, and the hole side additional layer.

[0122] The thickness of the hole control layer HTR may be from about 10 nm to about 1000 nm, for example, from about 10 nm to about 200 nm. The thickness of the hole injection layer may be, for example, from about 5 nm to about 100 nm. The thickness of the hole transport layer may be from about 5 nm to about 100 nm. If the hole control layer HTR includes a hole side additional layer, the thickness of the hole side additional layer may be from about 1 nm to about 100 nm. If the thickness of the hole control layer HTR and the thickness of each layer included therein satisfy the above ranges, satisfactory hole transport characteristics can be obtained without significantly increasing the driving voltage.

[0123] In addition to the above materials, the hole control layer HTR may further include a charge generation material to improve conductivity. The charge generation material may be uniformly or non-uniformly dispersed in the hole control layer HTR. The charge generation material may be, for example, a p-type dopant. The p-type dopant may include at least one of metal halide compounds, quinone derivatives, metal oxides, and cyano-containing compounds, but is not limited thereto. For example, the p-type dopant may include metal halide compounds such as CuI and / or RbI, quinone derivatives such as tetracyanoquinodimethane (TCNQ) and 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4-TCNQ), metal oxides such as tungsten oxide and molybdenum oxide, etc., but the present disclosure is not limited thereto.

[0124] The emission layer EML may include a host material and a dopant material. The emission layer EML may include a material containing a carbazole derivative moiety or an amine derivative moiety as a hole transport host material. The emission layer EML may include a material containing a nitrogen-containing aromatic ring structure such as a pyridine derivative moiety, a pyridazine derivative moiety, a pyrimidine derivative moiety, a pyrazine derivative moiety, and / or a triazine derivative moiety as an electron transport host material.

[0125] The emission layer EML may further include an anthracene derivative, a pyrene derivative, a fluoranthene derivative, Derivatives, dihydrobenzanthracene derivatives, and / or triphenylene derivatives, etc. Additionally, the emission layer EML may further include typical materials known in the art as host materials. For example, the emission layer EML may include at least one of bis[2-(diphenylphosphino)phenyl]ether oxide (DPEPO), 4,4'-bis(carbazol-9-yl)-1,1'-biphenyl (CBP), 1,3-bis(carbazol-9-yl)benzene (mCP), 2,8-bis(diphenylphosphoryl)dibenzofuran (PPF), 4,4',4''-tris(carbazol-9-yl)-triphenylamine (TCTA), and 1,3,5-tris(1-phenyl-1H-benzo[d]imidazol-2-yl)benzene (TPBi) as host materials. However, the present disclosure is not limited thereto, and for example, tris(8-hydroxyquinoline)aluminum (Alq3), poly(N-vinylcarbazole) (PVK), 9,10-di(naphthalen-2-yl)anthracene (ADN), 2-tert-butyl-9,10-di(naphthalen-2-yl)anthracene (TBADN), distyrylarylene (DSA), 4,4'-bis(9-carbazolyl)-2,2'-dimethyl-biphenyl (CDBP), 2-methyl-9,10-di(naphthalen-2-yl)anthracene (MADN), hexaphenylcyclotriphosphazene (CP1), 1,4-bis(triphenylsilyl)benzene (UGH2), hexaphenylcyclotrisiloxane (DPSiO3), octaphenylcyclotetrasiloxane (DPSiO4), etc. may be used as host materials in the emission layer EML.

[0126] In one or more embodiments, the emission layer EML may include styryl derivatives (e.g., 1,4-bis[2-(3-N-ethylcarbazolyl)vinyl]benzene (BCzVB), 4-(di-p-tolylamino)-4'-[(di-p-tolylamino)styryl]stilbene (DPAVB), N-(4-((E)-2-(6-((E)-4-(diphenylamino)styryl)naphthalen-2-yl)vinyl)phenyl)-N-phenylaniline (N-BDAVBi), and 4,4'-bis[2-(4-(N,N-diphenylamino)phenyl)vinyl]biphenyl (DPAVBi)), perylene and its derivatives (e.g., 2,5,8,11-tetra-tert-butylperylene (TBP)), pyrene and its derivatives (e.g., 1,1'-dipyrene, 1,4-dipyrenylbenzene, and 1,4-bis(N,N-diphenylamino)pyrene), etc. as known fluorescent dopant materials.

[0127] In one or more embodiments, a metal complex including iridium (Ir), platinum (Pt), osmium (Os), gold (Au), titanium (Ti), zirconium (Zr), hafnium (Hf), europium (Eu), terbium (Tb), or thulium (Tm) can be used as a known phosphorescent dopant material in the emission layer EML. Specifically, bis(4,6-difluorophenylpyridine-N,C2') iridium(III) picolinate (FIrpic), bis(2,4-difluorophenylpyridine)-tetrakis(1-pyrazolyl) borate iridium(III) (FIr6), and / or platinum octaethylporphyrin (PtOEP) can be used as the phosphorescent dopant.

[0128] The electron control layer ETR can have a single-layer structure formed of a single material, a single-layer structure formed of a plurality of different materials from each other, or a multilayer structure having a plurality of layers formed of a plurality of different materials from each other. For example, at least a part of the electron control layer ETR can include an electron transport layer and an electron injection layer.

[0129] The electron control layer ETR can be formed by using various methods such as a vacuum deposition method, a spin coating method, a casting method, a Langmuir-Blodgett (LB) method, an inkjet printing method, a laser printing method, and / or a laser-induced thermal imaging (LITI) method.

[0130] The electron control layer ETR can include anthracene compounds. However, the present disclosure is not limited thereto, and the electron control layer ETR can include, for example, tris(8-hydroxyquinoline) aluminum (Alq3), 1,3,5-tris[(3-pyridyl)-benzene-3-yl] benzene, 2,4,6-tris(3'-(pyridin-3-yl) biphenyl-3-yl)-1,3,5-triazine (T2T), 2-(4-(N-phenylbenzimidazol-1-yl)phenyl)-9,10-dinaphthylanthracene, 1,3,5-tris(1-phenyl-1H-benz[d]imidazol-2-yl) benzene (TPBi), 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (BCP), 4,7-diphenyl-1,10-phenanthroline (Bphen), 3-(4-biphenyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole (TAZ), 4-(naphthalen-1-yl)-3,5-diphenyl-4H-1,2,4-triazole (NTAZ), 2-(4-biphenyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (tBu-PBD), bis(2-methyl-8-hydroxyquinoline-N1,O8)-(1,1'-biphenyl-4-ol) aluminum (BAlq), bis(benzoquinoline-10-hydroxy) beryllium (Bebq2), 9,10-bis(naphthalen-2-yl) anthracene (ADN), 1,3-bis[3,5-bis(pyridin-3-yl)phenyl] benzene (BmPyPhB), and / or a mixture thereof.

[0131] In addition, the electron control layer ETR may include metal halides such as LiF, NaCl, CsF, RbCl, RbI, CuI, and KI, lanthanide metals such as Yb, and co-deposited materials of metal halides and / or lanthanide metals. For example, the electron control layer ETR may include KI:Yb, RbI:Yb, etc. as co-deposited materials. The electron control layer ETR may include two or more materials selected from Mg, Ag, Yb, and Al. For example, the electron control layer ETR may include Mg and Yb.

[0132] In one or more embodiments, metal oxides (such as Li2O and BaO) or lithium 8-hydroxyquinolate (Liq), etc. may be used in the electron control layer ETR, but the present disclosure is not limited thereto. The electron control layer ETR may also be formed of a mixture of an electron transport material and an organometallic salt having insulating properties. The organometallic salt may be a material having a band gap of about 4 eV or greater. Specifically, for example, the organometallic salt may include metal acetates, metal benzoates, metal acetoacetates, metal acetylacetonates, and / or metal stearates.

[0133] In addition to the above materials, the electron control layer ETR may also include at least one of 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (BCP) and 4,7-diphenyl-1,10-phenanthroline (Bphen), but the present disclosure is not limited thereto.

[0134] The electron control layer ETR may include the compounds described above in the electron injection layer or the electron transport layer. If the electron control layer ETR includes an electron-side additional layer, the above materials may be included in the electron-side additional layer. In one or more embodiments, the electron injection layer may include two or more materials selected from Mg, Ag, Yb, and Al. The electron injection layer may include, for example, a mixture of Mg and Yb.

[0135] The thickness of the electron control layer ETR may be, for example, about 10 nm to about 150 nm. The thickness of the electron transport layer may be about 0.1 nm to about 100 nm, for example, about 0.3 nm to about 50 nm. If the thickness of the electron transport layer satisfies the above range, satisfactory electron transport characteristics can be obtained without significantly increasing the driving voltage.

[0136] The second electrode CE is provided on the electron control layer ETR. The second electrode CE may be a common electrode. The second electrode CE may be a cathode or an anode. For example, if the first electrode AE is an anode, the second electrode CE may be a cathode, and if the first electrode AE is a cathode, the second electrode CE may be an anode.

[0137] The second electrode CE can be a semi-transmissive reflective electrode and / or a transmissive electrode. If the second electrode CE is a transmissive electrode, the second electrode CE can be made of a transparent metal oxide (e.g., indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc.).

[0138] If the second electrode CE is a semi-transmissive reflective electrode or a reflective electrode, the second electrode CE can include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, Yb, W, In, Zn, Sn, and / or their compounds or mixtures (e.g., AgMg, AgYb, or MgYb), or a material having a multilayer structure such as LiF / Ca or LiF / Al. Optionally, the second electrode CE can have a multilayer structure that includes a semi-transmissive reflective film or a reflective film formed of the material and a transparent conductive film formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc. For example, the second electrode CE can include the above metal materials, a combination of two or more metal materials selected from the above metal materials, and / or oxides of the above metal materials.

[0139] In one or more embodiments, the second electrode CE can be connected to an auxiliary electrode. If the second electrode CE is connected to the auxiliary electrode, the resistance of the second electrode CE can be reduced.

[0140] In one or more embodiments, a covering layer can also be provided on the second electrode CE of the light-emitting element LED according to one or more embodiments. The covering layer can include multiple layers or a single layer.

[0141] In one or more embodiments, the covering layer can be an organic layer and / or an inorganic layer. For example, if the covering layer includes an inorganic material, the inorganic material can include an alkali metal compound such as LiF, an alkaline earth metal compound such as MgF2, SiO x N y 、SiN x 、SiO y etc.

[0142] For example, if the covering layer includes an organic material, the organic material can include α-NPD, NPB, TPD, m-MTDATA, Alq3, CuPc, N4,N4,N4',N4'-tetrakis(biphenyl-4-yl)biphenyl-4,4'-diamine (TPD15), 4,4',4"-tris(carbazol-9-yl)triphenylamine (TCTA), etc., and / or include an epoxy resin and / or an acrylate such as a methacrylate.

[0143] In one or more embodiments, the refractive index of the cover layer may be about 1.6 or greater. Specifically, the refractive index of the cover layer for light in the wavelength range of about 550 nm to about 660 nm may be about 1.6 or greater.

[0144] The encapsulation layer TFE may be disposed on the light-emitting element LED. For example, in one or more embodiments, the encapsulation layer TFE may be disposed on the second electrode CE. Additionally, if the light-emitting element LED includes a cover layer, the encapsulation layer TFE may be disposed on the cover layer. The encapsulation layer TFE may include at least one organic film and at least one inorganic film as described above, and the inorganic film and the organic film may be alternately disposed.

[0145] The display module DM of the embodiment may include a light control member LCM disposed on the display element layer DP-LED. The light control member LCM may include a light control layer CCL, a color filter layer CFL, and a substrate layer BL.

[0146] The light control layer CCL may include a light converter. The light converter may be a quantum dot and / or a phosphor, etc. The light converter may convert the wavelength of the provided light and emit light. That is, the light control layer CCL may be a layer at least a part of which includes a quantum dot and / or a phosphor.

[0147] The light control layer CCL may include a plurality of light control patterns CCP-R, CCP-G, and CCP-B. The light control patterns CCP-R, CCP-G, and CCP-B may be spaced apart from each other (e.g., separated). The light control patterns CCP-R, CCP-G, and CCP-B may be arranged to be spaced apart from each other (e.g., separated), and the dam BMP is located therebetween. The light control patterns CCP-R, CCP-G, and CCP-B may be disposed in the dam openings BW-OH defined in the dam BMP. However, the present disclosure is not limited thereto. Figure 4 It is shown that the dam BMP has a rectangular shape in the cross-sectional view and does not overlap with the light control patterns CCP-R, CCP-G, and CCP-B, but in one or more embodiments, the edges of a part of the light control patterns CCP-R, CCP-G, and CCP-B may at least partially overlap with the dam BMP. For example, in one or more embodiments, the edge of the third light control pattern CCP-B may be arranged to overlap with the dam BMP in the plan view. In one or more embodiments, the dam BMP may have a trapezoidal shape in the cross-sectional view. In one or more embodiments, the dam BMP may have a shape in which the cross-sectional width increases toward the display element layer DP-LED.

[0148] The light control patterns CCP-R, CCP-G, and CCP-B may be parts that convert the wavelength of the light provided from the display element layer DP-LED or transmit the provided light.

[0149] The light control layer CCL may include a first light control pattern CCP-R that provides red light as the first light, a second light control pattern CCP-G that provides green light as the second light, and a third light control pattern CCP-B that provides blue light as the third light. The light control layer CCL may include a first light control pattern CCP-R that converts the source light provided from the light emitting element LED into the first light, a second light control pattern CCP-G that converts the source light into the second light, and a third light control pattern CCP-B that transmits the source light. At least a part of the light control patterns CCP-R, CCP-G, and CCP-B may include quantum dots that convert the source light into light having a specific wavelength.

[0150] In this specification, a "quantum dot" refers to a crystal of a semiconductor compound. Quantum dots can emit light having various emission wavelengths according to the size of the crystal. Quantum dots can also emit light having various emission wavelengths according to the adjustment of the element ratio in the quantum compound.

[0151] The diameter of the quantum dot can be, for example, about 1 nm to about 10 nm.

[0152] Quantum dots can be synthesized by wet chemical processes, metal organic chemical vapor deposition processes, molecular beam epitaxy processes, and / or processes similar thereto.

[0153] The wet chemical process is a method of mixing precursor materials with an organic solvent and then growing quantum dot particle crystals. When the crystals grow, the organic solvent can naturally be used as a dispersant coordinated on the surface of the quantum dot crystals and control the growth of the crystals. Therefore, the growth of quantum dot particles can be controlled by the wet chemical process, which is a low-cost process and easier to perform than vapor deposition methods such as metal organic chemical vapor deposition (MOCVD) and / or molecular beam epitaxy (MBE).

[0154] The core of the quantum dot can be selected from II-VI group semiconductor compounds, III-V group semiconductor compounds, III-VI group semiconductor compounds, I-III-VI group semiconductor compounds, IV-VI group semiconductor compounds, II-IV-V group semiconductor compounds, group IV elements, group IV semiconductor compounds, and combinations thereof.

[0155] II-VI group semiconductor compounds can be selected from the group consisting of the following compounds: binary compounds selected from the group consisting of CdSe, CdTe, CdS, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, and mixtures thereof; ternary compounds selected from the group consisting of CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS, and mixtures thereof; and quaternary compounds selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe, and mixtures thereof. Meanwhile, the II-VI group semiconductor compounds may further include Group I metals and / or Group IV elements. I-II-VI group semiconductor compounds may be selected from CuZnS, etc., and / or ZnSnS, etc. may be selected as II-IV-VI group semiconductor compounds. I-II-IV-VI group semiconductor compounds may be selected from: quaternary compounds selected from the group consisting of Cu2ZnSnS2, Cu2ZnSnS4, Cu2ZnSnSe4, Ag2ZnSnS2, and mixtures thereof.

[0156] III-VI group semiconductor compounds may include binary compounds such as In2S3 and In2Se3, ternary compounds such as InGaS3 and InGaSe3, and / or any combination thereof.

[0157] I-III-VI group semiconductor compounds may be selected from: ternary compounds selected from the group consisting of AgInS, AgInS2, CuInS, CuInS2, AgGaS2, CuGaO2, AgGaO2, AgAlO2, and mixtures thereof; and / or quaternary compounds such as AgInGaS2 and / or CuInGaS2.

[0158] III-V semiconductor compounds can be selected from the group consisting of the following compounds: binary compounds selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, and mixtures thereof; ternary compounds selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InAlP, InNP, InNAs, InNSb, InPAs, InPSb, and mixtures thereof; and quaternary compounds selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, and mixtures thereof. In one or more embodiments, the III-V semiconductor compound may further include group II metals. For example, InZnP or the like may be selected as the III-II-V semiconductor compound.

[0159] IV-VI semiconductor compounds can be selected from the group consisting of the following compounds: binary compounds selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe, and mixtures thereof; ternary compounds selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, and mixtures thereof; and quaternary compounds selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe, and mixtures thereof.

[0160] Examples of II-IV-V semiconductor compounds may be ternary compounds selected from the group consisting of ZnSnP, ZnSnP2, ZnSnAs2, ZnGeP2, ZnGeAs2, CdSnP2, and CdGeP2 and / or mixtures thereof.

[0161] Group IV elements can be selected from the group consisting of Si, Ge, and mixtures thereof. Group IV compounds can be binary compounds selected from the group consisting of SiC, SiGe, and mixtures thereof.

[0162] Each element included in a multi-element compound such as a binary compound, a ternary compound, and / or a quaternary compound may be present in the particles in a uniform concentration or a non-uniform concentration. That is, the chemical formula means the type of elements contained in the compound, and the element ratios in the compound may be different. For example, AgInGaS2 may mean AgInx Ga 1-x S2 (where x is a real number between 0 and 1).

[0163] Here, the binary, ternary or quaternary compound may be present in the particles at a uniform concentration, or may be present in the same particle at partially different concentration distributions. Additionally, the quantum dots may have a core-shell structure, where one quantum dot surrounds (e.g., encircles) another quantum dot. The core-shell structure may have a concentration gradient in which the concentration of the elements present in the shell decreases towards the core.

[0164] In one or more embodiments, the quantum dots may have a core-shell structure that includes a core having the above-described nanocrystals and a shell that surrounds (e.g., encircles) the core. The shell of the quantum dots may act as a protective layer for maintaining semiconductor characteristics by preventing chemical modification of the core and / or as a charging layer for imparting electrophoretic characteristics to the quantum dots. The shell may be a single layer or multiple layers. Examples of the shell of the quantum dots may include metal or non-metal oxides, semiconductor compounds, and / or combinations thereof.

[0165] For example, examples of metal or non-metal oxides may be binary compounds such as SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4, and / or NiO, or ternary compounds such as MgAl2O4, CoFe2O4, NiFe2O4, and / or CoMn2O4, but the present disclosure is not limited thereto.

[0166] Additionally, examples of semiconductor compounds may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, etc., but the present disclosure is not limited thereto.

[0167] The full width at half maximum (FWHM) of the emission wavelength spectrum of the quantum dots may be about 45 nm or less, preferably about 40 nm or less, and more preferably about 30 nm or less, and within this range, color purity or color reproducibility can be improved. Additionally, the light emitted by such quantum dots is emitted in all directions, thereby improving the wide viewing angle.

[0168] Furthermore, the shape of the quantum dots is not particularly limited to the shapes commonly used in the art, but more specifically, the quantum dots may be nanoparticles having a spherical, pyramidal, multi-armed or cubic shape, or may be nanotubes, nanowires, nanofibers, nanosheets, etc.

[0169] The band gap of the quantum dots can be controlled by adjusting the size of the quantum dots or the elemental ratio in the quantum compound, and thus light of various wavelengths can be obtained in the quantum dot emission layer. Therefore, by using the quantum dots (having different sizes or having varying elemental ratios in the quantum compound) described above, a light-emitting element that emits light of various wavelengths can be realized. Specifically, the size of the quantum dots and / or the elemental ratio in the quantum compound can be selected to emit red light, green light, and / or blue light. Additionally, the quantum dots can be configured such that beams of various colors are combined to emit white light.

[0170] At least some of the light control patterns CCP-R, CCP-G, and CCP-B can be formed by an inkjet process. In one or more embodiments, the first light control pattern CCP-R and the second light control pattern CCP-G can be formed by an inkjet process. A liquid ink composition can be provided in each of the first bank opening (e.g., bank opening BW-OH) and the second bank opening, and the provided ink composition can be polymerized by a thermal curing process or a photo-curing process, and the first light control pattern CCP-R and the second light control pattern CCP-G can be formed. Some of the light control patterns CCP-R, CCP-G, and CCP-B can be formed by a photoresist process. In one or more embodiments, the third light control pattern CCP-B can be formed by a photoresist process. A photoresist composition can be provided at least in the third bank opening, and then the provided photoresist composition can be cured, and the third light control pattern CCP-B can be formed.

[0171] The light control layer CCL can further include a scatterer. The first light control pattern CCP-R can include a first quantum dot and a scatterer, the second light control pattern CCP-G can include a second quantum dot and a scatterer, and the third light control pattern CCP-B can not include a quantum dot and can include a scatterer. Each of the first light control pattern CCP-R, the second light control pattern CCP-G, and the third light control pattern CCP-B can further include a matrix resin for dispersing the quantum dots and / or the scatterer. Since the third light control pattern CCP-B can be formed by a photoresist process, the third light control pattern CCP-B can include a photosensitive resin.

[0172] The light control layer CCL can include a first barrier layer CAP1 provided on one surface of the light control patterns CCP-R, CCP-G, and CCP-B. The light control layer CCL can include a first barrier layer CAP1 spaced apart (e.g., separated) from the display element layer DP-LED and a second barrier layer CAP2 adjacent to the display element layer DP-LED, while the light control patterns CCP-R, CCP-G, and CCP-B are located between the first barrier layer CAP1 and the display element layer DP-LED.

[0173] A step may be formed between the lower surface of the embankment BMP and the lower surfaces of the light control patterns CCP-R, CCP-G, and CCP-B. That is, the lower surface of the embankment BMP may be defined to be lower than the lower surfaces of the light control patterns CCP-R, CCP-G, and CCP-B. The height difference between the lower surface of the embankment BMP and the lower surfaces of the light control patterns CCP-R, CCP-G, and CCP-B may be, for example, about 2 μm to about 3 μm.

[0174] The second barrier layer CAP2 may be disposed along the step between the embankment BMP and the light control patterns CCP-R, CCP-G, and CCP-B. The second barrier layer CAP2 may be directly disposed on the filling layer FML.

[0175] The light control member LCM in the display module DM includes a color filter layer CFL disposed on the light control layer CCL. The color filter layer CFL may include color filters CF1, CF2, and CF3. The color filter layer CFL may include a first color filter CF1 that transmits a first light, a second color filter CF2 that transmits a second light, and a third color filter CF3 that transmits source light (e.g., a third light). In one or more embodiments, the first color filter CF1 may be a red color filter, the second color filter CF2 may be a green color filter, and the third color filter CF3 may be a blue color filter.

[0176] Each of the color filters CF1, CF2, and CF3 includes a polymer photosensitive resin and / or a colorant. The first color filter CF1 may include a red colorant, the second color filter CF2 may include a green colorant, and the third color filter CF3 may include a blue colorant. The first color filter CF1 may include a red pigment and / or a red dye, the second color filter CF2 may include a green pigment and / or a green dye, and the third color filter CF3 may include a blue pigment and / or a blue dye.

[0177] The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be arranged to correspond to the first pixel region PXA-R, the third pixel region PXA-G, and the second pixel region PXA-B, respectively. Additionally, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be arranged to correspond to the first light control pattern CCP-R, the second light control pattern CCP-G, and the third light control pattern CCP-B, respectively.

[0178] In addition, a plurality of color filters CF1, CF2, and CF3 that transmit different lights can be set to overlap each other corresponding to a peripheral region NPXA provided between pixel regions PXA-R, PXA-B, and PXA-G. The plurality of color filters CF1, CF2, and CF3 can be set to overlap each other in a third direction DR3 that is a thickness direction to define boundaries between adjacent pixel regions PXA-R, PXA-B, and PXA-G. In one or more embodiments, the color filter layer CFL can include a light-blocking portion to define boundaries between adjacent color filters CF1, CF2, and CF3. The light-blocking portion can be formed of a blue color filter or can be formed of an inorganic light-blocking material or an organic light-blocking material containing black pigment and / or black dye.

[0179] A display module DM according to one or more embodiments can include a low refractive index layer LR. The low refractive index layer LR can be provided between the light control layer CCL and the color filter layer CFL. The low refractive index layer LR can be provided above the light control layer CCL (e.g., the first barrier layer CAP1) and prevent the light control patterns CCP-R, CCP-G, and CCP-B from being exposed to moisture and / or oxygen. In addition, the low refractive index layer LR can be provided between the light control patterns CCP-R, CCP-G, and CCP-B and the color filters CF1, CF2, and CF3 and serve as an optical functional layer that increases light extraction efficiency and / or prevents reflected light from entering the light control layer CCL and the like. The low refractive index layer LR can be a layer having a lower refractive index than adjacent layers.

[0180] The low refractive index layer LR can include at least one inorganic layer. For example, the low refractive index layer LR can include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and / or silicon oxynitride, and / or include a metal thin film having light transmissivity, etc. However, the present disclosure is not limited thereto, and the low refractive index layer LR can include an organic film. The low refractive index layer LR can have a structure in which a plurality of hollow particles are dispersed in an organic polymer resin, for example. The low refractive index layer LR can be composed of a single layer or multiple layers.

[0181] The display module DM of the embodiment can further include a filling layer FML provided between the light control member LCM and the display panel DP.

[0182] In one or more embodiments, the filling layer FML can fill a gap between the display element layer DP-LED and the light control layer CCL. The filling layer FML can be directly provided on the encapsulation layer TFE, and the second barrier layer CAP2 can be directly provided on the filling layer FML. The lower surface of the filling layer FML can be in contact with the upper surface of the encapsulation layer TFE, and the upper surface of the filling layer FML can be in contact with the lower surface of the second barrier layer CAP2.

[0183] The filling layer FML can be used as a buffer between the display element layer DP-LED and the light control layer CCL. In one or more embodiments, the filling layer FML can function to absorb impacts and the like, and can increase the strength of the display module DM. The filling layer FML can be formed of a filling resin including a polymer resin. For example, the filling layer FML can be formed of a filling layer resin including an acrylic resin and / or an epoxy resin, etc.

[0184] In one or more embodiments, the filling layer FML can also be disposed between the light control layer CCL and the color filter layer CFL. The filling layer FML can be disposed above the light control layer CCL and prevent the light control patterns CCP-R, CCP-G, and CCP-B from being exposed to moisture and / or oxygen. Additionally, the filling layer FML can be disposed between the light control patterns CCP-R, CCP-G, and CCP-B and the color filters CF1, CF2, and CF3, and function as an optical functional layer for increasing the light extraction efficiency and / or preventing reflected light from incident on the light control layer CCL, etc. The filling layer FML can be a layer having a lower refractive index than other adjacent layers.

[0185] In one or more embodiments, the light control member LCM can further include a substrate layer BL disposed on the color filter layer CFL. The substrate layer BL can be a member providing a substrate surface on which the color filter layer CFL and / or the light control layer CCL, etc. are disposed. The substrate layer BL can be a glass substrate, a metal substrate, a plastic substrate, etc. However, the present disclosure is not limited thereto, and the substrate layer BL can be an inorganic layer, an organic layer, and / or a composite material layer. Additionally, in one or more embodiments, the substrate layer BL can be omitted.

[0186] Figure 5 is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure. Figure 5 shows a main focus on Figure 3 the connection relationship between the light-emitting element LED and the transistor TR included in one pixel of the display panel DP shown in Figure 6A and Figure 6B are each a plan view of some components of a display panel according to one or more embodiments of the present disclosure. Figure 6A shows a plane corresponding to Figure 5 the connection electrodes CNE1 and CNE2, the transistor TR, the first conductive pattern CPT1, and the second conductive pattern CPT2 in Figure 6B shows a plane corresponding to Figure 5 the connection electrodes CNE1 and CNE2, the transistor TR, the first electrode AE, the sensing pattern SSP, and the additional electrode AAE in Figure 5 、 Figure 6A and Figure 6BDescribe a display panel DP according to one or more embodiments of the present disclosure.

[0187] Reference Figure 5 , the display panel DP may include a substrate layer BS, a circuit element layer DP-CL, a display element layer DP-LED, and a packaging layer TFE.

[0188] The circuit element layer DP-CL may include conductive patterns CPT1 and CPT2 disposed on the substrate layer BS, transistors TR, connection electrodes CNE1 and CNE2, a buffer layer BFL, a gate insulating pattern layer GIL, insulating layers INS1 and INS2, a sensing line SGL, a sensing pattern SSP, and a capacitor Cst.

[0189] Each of the first conductive pattern CPT1 and the second conductive pattern CPT2 may have a multi-layer structure. The first conductive pattern CPT1 and the second conductive pattern CPT2 may be formed of the same material and have the same stacking structure. For example, each of the first conductive pattern CPT1 and the second conductive pattern CPT2 may include a first pattern layer PT1 and a second pattern layer PT2 stacked on the substrate layer BS in the thickness direction (e.g., the third direction DR3). However, the present disclosure is not limited thereto, and each of the first conductive pattern CPT1 and the second conductive pattern CPT2 may have a single-layer structure, or may also have a multi-layer structure in which three or more pattern layers are stacked.

[0190] The thickness of the first pattern layer PT1 and the thickness of the second pattern layer PT2 may be different. For example, the thickness of the first pattern layer PT1 may be less than the thickness of the second pattern layer PT2. However, the present disclosure is not limited thereto.

[0191] Each of the first pattern layer PT1 and the second pattern layer PT2 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or their alloys. For example, the first pattern layer PT1 may include titanium (Ti), and the second pattern layer PT2 may include copper (Cu). However, the present disclosure is not limited thereto.

[0192] The buffer layer BFL may be disposed on the substrate layer BS to cover the first conductive pattern CPT1 and the second conductive pattern CPT2. The buffer layer BFL may include at least one inorganic film. In this specification, the buffer layer BFL may be referred to as the "lower insulating layer".

[0193] Refer together Figure 5 and Figure 6A, the transistor TR may include a semiconductor pattern SP and a gate electrode GE. The semiconductor pattern SP may be disposed on the buffer layer BFL. The bonding force between the semiconductor pattern SP and the substrate layer BS may be improved through the buffer layer BFL. The semiconductor pattern SP may include a semiconductor material such as crystalline silicon (e.g., polysilicon) and / or metal oxide.

[0194] The source region S-A, the active region A-A, and the drain region D-A of the transistor TR may be formed of the semiconductor pattern SP. The electrical characteristics of the semiconductor pattern SP may change according to whether the semiconductor pattern is doped or the metal oxide is reduced. The source region S-A and the drain region D-A of the semiconductor pattern SP having relatively high conductivity may be used as electrodes or signal lines. The region of the semiconductor pattern SP that is undoped or doped at a low concentration or in which the metal oxide is not reduced may correspond to the active region A-A having low conductivity.

[0195] In a plan view, the conductive regions CA may be separated from each other (e.g., spaced apart), and the non-conductive region NCA is located therebetween. The conductive regions CA may respectively correspond to the source region S-A and the drain region D-A of the semiconductor pattern SP, and the non-conductive region NCA may correspond to the channel region of the semiconductor pattern SP.

[0196] At least one hole HO may be defined in the semiconductor pattern SP. The hole HO may be formed during an etching process through which the connection electrodes CNE1 and CNE2 and the gate electrode GE are formed. As an example, Figure 5 holes HO formed to be separated from each other (e.g., spaced apart) in the semiconductor pattern SP are shown. One of the holes HO may be surrounded by the source region S-A in a plan view, and the other hole HO may be surrounded by the drain region D-A in a plan view. However, the present disclosure is not limited thereto, and according to the process for the circuit element layer DP-CL, the hole HO may not be formed in the semiconductor pattern SP.

[0197] The gate insulating pattern layer GIL may be disposed on the buffer layer BFL. The gate insulating pattern layer GIL may include at least one inorganic film. The gate insulating pattern layer GIL may include a first insulating pattern GI1, a second insulating pattern GI2, and a third insulating pattern GI3 that are separated from each other (e.g., spaced apart). The first insulating pattern GI1 may cover a part of the drain region D-A and may be disposed on the first conductive pattern CPT1. The second insulating pattern GI2 may be disposed on the active region A-A. The third insulating pattern GI3 may cover a part of the source region S-A and may be disposed on the second conductive pattern CPT2.

[0198] The connection electrodes CNE1 and CNE2 may include a first connection electrode CNE1 and a second connection electrode CNE2. The first connection electrode CNE1 may be disposed on the first insulating pattern GI1. The first connection electrode CNE1 may be connected to the first conductive pattern CPT1 through a first contact hole CH1 that passes through the buffer layer BFL and the first insulating pattern GI1. The first connection electrode CNE1 may contact a part of the drain region D-A and be connected to the drain region D-A. The drain region D-A and the first conductive pattern CPT1 may be electrically connected to each other through the first connection electrode CNE1. Since the first conductive pattern CPT1 having excellent conductivity is connected to the drain region D-A, the current transmission characteristics of the semiconductor pattern SP can be improved.

[0199] The second connection electrode CNE2 may be disposed on the third insulating pattern GI3. The second connection electrode CNE2 may be connected to the second conductive pattern CPT2 through a second contact hole CH2 that passes through the buffer layer BFL and the third insulating pattern GI3. The second connection electrode CNE2 may contact a part of the source region S-A and be connected to the source region S-A. The source region S-A and the second conductive pattern CPT2 may be electrically connected to each other through the second connection electrode CNE2. The second connection electrode CNE2 may be connected to a power line that supplies power to the light-emitting element LED and supply a first voltage to the transistor TR.

[0200] The gate electrode GE may be disposed on the second insulating pattern GI2. The gate electrode GE may overlap the active region A-A in a plan view, and may be spaced apart (e.g., separated) from the semiconductor pattern SP in a thickness direction (e.g., the third direction DR3), and the second insulating pattern GI2 is located between the gate electrode GE and the semiconductor pattern SP.

[0201] The connection electrodes CNE1 and CNE2 and the gate electrode GE may be spaced apart (e.g., separated) from each other in a plan view. Each of the connection electrodes CNE1 and CNE2 and the gate electrode GE may have a multi-layer structure in which conductive layers ML1, ML2, and ML3 including different materials from each other are stacked. The conductive layers ML1, ML2, and ML3 may include a first conductive layer ML1, a second conductive layer ML2, and a third conductive layer ML3. The first conductive layer ML1, the second conductive layer ML2, and the third conductive layer ML3 may be stacked by a sputtering process, but the present disclosure is not limited thereto.

[0202] The first conductive layer ML1, the second conductive layer ML2, and the third conductive layer ML3 may each include a metallic material. For example, the first conductive layer ML1, the second conductive layer ML2, and the third conductive layer ML3 may each include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and / or their alloys and / or indium tin oxide (ITO). The first conductive layer ML1, the second conductive layer ML2, and the third conductive layer ML3 may include different metallic materials from each other. The second conductive layer ML2 may include a metallic material having excellent electrical conductivity, and the first conductive layer ML1 and the third conductive layer ML3 respectively disposed below and on the second conductive layer ML2 may include metallic materials having corrosion resistance. For example, the first conductive layer ML1 may include titanium (Ti), the second conductive layer ML2 may include copper (Cu), and the third conductive layer ML3 may include indium tin oxide (ITO). However, the present disclosure is not limited thereto.

[0203] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, and the third conductive layer ML3 may be different from each other. For example, the thickness of the second conductive layer ML2 including a material with high electrical conductivity may be the largest among the first conductive layer ML1, the second conductive layer ML2, and the third conductive layer ML3. Therefore, the gate electrode GE and the connection electrodes CNE1 and CNE2 formed by the first conductive layer ML1, the second conductive layer ML2, and the third conductive layer ML3 may have the characteristics of low resistance and high electrical conductivity.

[0204] As an example, Figure 5 It is shown that the connection electrodes CNE1 and CNE2 and the gate electrode GE each have a multi-layer structure with three layers, but the present disclosure is not limited thereto. Each of the connection electrodes CNE1 and CNE2 and the gate electrode GE may have a single-layer structure, or may also have a two-layer structure or a multi-layer structure with four or more layers.

[0205] The connection electrodes CNE1 and CNE2 and the gate electrode GE may be formed concurrently (e.g., simultaneously) by the same process. The connection electrodes CNE1 and CNE2 and the gate electrode GE may have the same stacking structure. For example, the connection electrodes CNE1 and CNE2 and the gate electrode GE may have a three-layer structure of Ti / Cu / ITO. Since the connection electrodes CNE1 and CNE2 and the gate electrode GE may be formed concurrently (e.g., simultaneously) by the same process, the display panel DP can be manufactured by a simplified process.

[0206] The first insulating layer INS1 may be disposed on the gate insulating pattern layer GIL and the buffer layer BFL to cover the connection electrodes CNE1 and CNE2 and the gate electrode GE. The second insulating layer (or insulating layer) INS2 may be disposed on the first insulating layer INS1. Each of the first insulating layer INS1 and the second insulating layer INS2 may include at least one inorganic film or organic film. The inorganic film may include aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and / or hafnium oxide, but is not limited to this material. The organic film may include phenolic polymers, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine-based polymers, parylene polymers, polyvinyl alcohol polymers, and / or combinations thereof, but is not limited to this material.

[0207] The display element layer DP-LED may be disposed on the circuit element layer DP-CL. The display element layer DP-LED may include a pixel defining layer PDL and a light emitting element LED. As an example, the light emitting element LED may include an organic light emitting element, an inorganic light emitting element, a quantum dot light emitting element, a micro light emitting diode (LED) light emitting element, and / or a nano LED light emitting element. However, the present disclosure is not limited thereto, and the light emitting element LED may include various embodiments as long as light can be generated or the amount of light can be controlled in response to an electrical signal.

[0208] The pixel defining layer PDL may be disposed on the second insulating layer INS2 of the circuit element layer DP-CL. The pixel defining layer PDL may include a polymer resin. For example, the pixel defining layer PDL may include a polyacrylate resin and / or a polyimide resin. In addition to the polymer resin, the pixel defining layer PDL may further include an inorganic material. Additionally, the pixel defining layer PDL may be formed of an inorganic material. For example, the pixel defining layer PDL may include silicon nitride (SiN x ), silicon oxide (SiO x ), and / or silicon oxynitride (SiO x N y ), etc.

[0209] In one or more embodiments, the pixel defining layer PDL may include a light absorbing material. The pixel defining layer PDL may include a black colorant. The black colorant may include a black dye or a black pigment. The black colorant may include carbon black, a metal such as chromium, and / or its oxide. However, the pixel defining layer PDL is not limited to the examples.

[0210] The light emitting element LED may include a first electrode AE, an emission layer EML, and a second electrode CE stacked in sequence. The description provided above with reference to Figure 4 may be applied to the light emitting element LED. For ease of description, in Figure 5The upper reference among the components of the light-emitting element LED is not shown in the figure. Figure 4 The hole control layer HTR and the electron control layer ETR described above.

[0211] The first electrode AE may be disposed on the second insulating layer INS2 of the circuit element layer DP-CL. The first electrode AE may be electrically connected to the first connection electrode CNE1. The first electrode AE may be connected to the first connection electrode CNE1 through a first through hole TH1 passing through the first insulating layer INS1, the second insulating layer INS2, and the sensing pattern SSP. A part of the first electrode AE may be disposed in the first through hole TH1. Since the first electrode AE can be connected to the first connection electrode CNE1, the drain region D-A can be connected to the light-emitting element LED through the first connection electrode CNE1.

[0212] A light-emitting opening OH exposing at least a part of the first electrode AE may be defined in the pixel defining layer PDL. The part of the first electrode AE exposed by the light-emitting opening OH may correspond to the pixel regions PXA-R, PXA-B, and PXA-G (see Figure 4 ). The region where the pixel defining layer PDL is provided may correspond to the peripheral region NPXA (see Figure 4 ). The peripheral region NPXA may surround (e.g., encircle) the pixel region PXA (see Figure 4 ).

[0213] The encapsulation layer TFE may cover the light-emitting element LED. The encapsulation layer TFE may encapsulate the display element layer DP-LED. The encapsulation layer TFE may include at least one insulating film. According to one or more embodiments, the encapsulation layer TFE may include at least one inorganic film (hereinafter, inorganic encapsulation film). According to one or more embodiments, the encapsulation layer TFE may include an inorganic encapsulation film and at least one organic film (hereinafter, organic encapsulation film) disposed between the inorganic encapsulation films.

[0214] The inorganic encapsulation film may protect the display element layer DP-LED from moisture and / or oxygen, and the organic encapsulation film may protect the display element layer DP-LED from foreign substances such as dust particles. The inorganic encapsulation film may include silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and / or aluminum oxide, etc. However, the present disclosure is not limited thereto. The organic encapsulation film may include acrylic compounds, epoxy compounds, etc. The organic encapsulation film may include a photo-polymerizable organic material and is not particularly limited.

[0215] In one or more embodiments, the display panel DP includes sensing lines SGL. The sensing lines SGL may be lines electrically connected to a sensing pattern SSP described below and transmitting the level of light of light-emitting elements LED measured through the sensing pattern SSP, so that it is possible to determine whether to perform optical compensation according to the level of the light amount.

[0216] Each of the connection electrodes CNE1 and CNE2, the gate electrode GE, and the sensing lines SGL are disposed on the same layer (e.g., at the same layer). The gate insulating pattern layer GIL may further include a fourth insulating pattern GI4, and the sensing lines SGL may be disposed on the fourth insulating pattern GI4. The fourth insulating pattern GI4 may be disposed on an additional pattern SP-a. The additional pattern SP-a may be disposed on the buffer layer BFL and is formed by the same process as the process for the semiconductor pattern SP. In one or more embodiments, the additional pattern SP-a may be omitted, and the fourth insulating pattern GI4 may be directly disposed on the buffer layer BFL.

[0217] The sensing lines SGL may be spaced apart (e.g., separated) from each of the connection electrodes CNE1 and CNE2 and the gate electrode GE in a plan view. The sensing lines SGL may have a multi-layer structure in which the conductive layers ML1, ML2, and ML3 described above are stacked.

[0218] The sensing lines SGL, the connection electrodes CNE1 and CNE2, and the gate electrode GE may be concurrently (e.g., simultaneously) formed by the same process. Each of the connection electrodes CNE1 and CNE2, the gate electrode GE, and the sensing lines SGL may have the same stacked structure. For example, the sensing lines SGL, the connection electrodes CNE1 and CNE2, and the gate electrode GE may have a three-layer structure of Ti / Cu / ITO. Since the sensing lines SGL, the connection electrodes CNE1 and CNE2, and the gate electrode GE may be concurrently (e.g., simultaneously) formed by the same process, the display panel DP may be manufactured by a simplified process.

[0219] Refer together to Figure 5 and Figure 6B , the display panel DP according to one or more embodiments includes a sensing pattern SSP and an additional electrode AAE. The sensing pattern SSP is disposed on the first insulating layer INS1. The additional electrode AAE is disposed on the second insulating layer INS2. The additional electrode AAE and the first electrode AE of the light-emitting element LED are disposed on the same layer (e.g., at the same layer).

[0220] The sensing pattern SSP is disposed on the first insulating layer INS1 and patterned in a partial region. The sensing pattern SSP overlaps at least a part of the first electrode AE and a part of the additional electrode AAE in a plan view. The sensing pattern SSP may overlap a part of the first connection electrode CNE1 and a part of the sensing line SGL in a plan view.

[0221] The sensing pattern SSP includes silicon (Si). The sensing pattern SSP may include silicon and / or nitrogen. In one or more embodiments, the sensing pattern SSP may include amorphous silicon. The sensing pattern SSP may be a deposition pattern formed by providing a source gas including silicon and / or a source gas including nitrogen together.

[0222] In the visible light wavelength range, the light transmittance of the sensing pattern SSP may be about 10% or greater. In the visible light wavelength range, the light transmittance of the sensing pattern SSP may be about 10% to about 20%. As used herein, the light transmittance is a value indicating the degree of light absorption of a material layer. Specifically, the light transmittance represents a value obtained by dividing the intensity of transmitted light incident from the outside by the intensity of incident light. Since the light transmittance of the sensing pattern SSP can be limited to this range, the sensing pattern SSP can provide high sensing sensitivity for measuring the amount of light emitted from the light-emitting element LED by absorbing the light emitted from the light-emitting element LED.

[0223] The sensing pattern SSP is disposed on the first insulating layer INS1 and covered by the second insulating layer INS2. The second insulating layer INS2 covering the sensing pattern SSP may be a layer having a high transmittance in the visible light wavelength range. In one or more embodiments, the light transmittance of the second insulating layer INS2 in the visible light wavelength range may be about 80% or greater. The light transmittance of the second insulating layer INS2 may be about 80% to about 95%. Since the second insulating layer INS2 may have a high light transmittance, the light emitted from the light-emitting element LED may not be blocked by the second insulating layer INS2 and may be introduced into the sensing pattern SSP.

[0224] The additional electrode AAE is disposed on the second insulating layer INS2 and is disposed to be separated (e.g., spaced apart) from the first electrode AE in a plan view. The additional electrode AAE may be separated (e.g., spaced apart) from the first electrode AE along the first direction DR1.

[0225] The additional electrode AAE and the first electrode AE are disposed on the same layer (e.g., at the same layer). The additional electrode AAE and the first electrode AE can be formed concurrently (e.g., simultaneously) by the same process. The additional electrode AAE and the first electrode AE can have the same (e.g., substantially the same) stacked structure. For example, each of the additional electrode AAE and the first electrode AE can have a three-layer structure of ITO / Ag / ITO. Since the additional electrode AAE and the first electrode AE can be formed concurrently (e.g., simultaneously) by the same process, the display panel DP can be manufactured by a simplified process.

[0226] The pixel defining layer PDL can be disposed on the additional electrode AAE. At least a portion of the additional electrode AAE can be covered by the pixel defining layer PDL. The additional electrode AAE can be completely covered by the pixel defining layer PDL. An additional opening for exposing the upper surface of the additional electrode AAE may not be formed in the pixel defining layer PDL. However, the present disclosure is not limited thereto, and in one or more embodiments, a portion of the upper surface of the additional electrode AAE can also be exposed through an opening defined in the pixel defining layer PDL.

[0227] The additional electrode AAE can be electrically connected to the sensing line SGL. The additional electrode AAE can be connected to the sensing line SGL through a second through hole TH2 that passes through the first insulating layer INS1, the second insulating layer INS2, and the sensing pattern SSP. A portion of the additional electrode AAE can be disposed in the second through hole TH2.

[0228] In one or more embodiments, each of the first through hole TH1 and the second through hole TH2 can pass through the sensing pattern SSP disposed on the first insulating layer INS1. Each of the first through hole TH1 and the second through hole TH2 can pass through all of the first insulating layer INS1, the second insulating layer INS2, and the sensing pattern SSP. Each of the first through hole TH1 and the second through hole TH2 can pass through the sensing pattern SSP, a portion of the first electrode AE can be disposed in the first through hole TH1, and a portion of the additional electrode AAE can be disposed in the second through hole TH2. Accordingly, each of the first electrode AE and the additional electrode AAE can be electrically connected to the sensing pattern SSP.

[0229] Figure 7 is a plan view of some components of a display panel according to one or more embodiments of the present disclosure. Figure 7 Schematically shows the planar layout relationship of the sensing pattern SSP, the first electrode AE, and the additional electrode AAE.

[0230] Reference Figure 5 、 Figure 6B and Figure 7, the first electrode AE disposed in the first through hole TH1, the additional electrode AAE disposed in the second through hole TH2, and the sensing pattern SSP may be electrically connected and used as a diode. Each of the first electrode AE and the additional electrode AAE may include a plurality of conductive patterns. The first electrode AE may include a (1-1) conductive pattern CDL1-1 and a (1-2) conductive pattern CDL1-2, and the additional electrode AAE may include a (2-1) conductive pattern CDL2-1 and a (2-2) conductive pattern CDL2-2. Each of the (1-1) conductive pattern CDL1-1 and the (2-1) conductive pattern CDL2-1 may include a transparent conductive oxide such as indium tin oxide (ITO). Each of the (1-2) conductive pattern CDL1-2 and the (2-2) conductive pattern CDL2-2 may include a conductive metal such as silver (Ag).

[0231] The first electrode AE, the additional electrode AAE, and the sensing pattern SSP that are disposed adjacent to each other may form an analog structure of a Schottky diode. In the analog structure of the Schottky diode formed by the first electrode AE, the additional electrode AAE, and the sensing pattern SSP, due to the voltage difference between the first electrode AE and the additional electrode AAE, a current path may be formed in the sensing pattern SSP, and then the sensing pattern SSP may sense the amount of a part of the light generated from the light emitting element LED. Then, the sensing line SGL may transmit the level of the light amount of the light emitting element LED measured by the sensing pattern SSP, and it may be determined whether to perform optical compensation according to the level of the light amount.

[0232] A display panel DP according to one or more embodiments may form an analog structure of a Schottky diode through a structure in which a sensing pattern SSP is disposed on a first insulating layer INS1 and a first electrode AE and an additional electrode AAE are electrically connected to the sensing pattern SSP to measure the amount of light of a light-emitting element LED. Therefore, it is possible to determine whether to perform optical compensation according to the degree of deterioration of the light-emitting element LED, thereby improving the light-emitting efficiency and power consumption of the display panel DP. More specifically, a display panel DP according to one or more embodiments may sense the amount of light traveling in a downward direction, which is a direction opposite to a third direction DR3, of light generated from a light-emitting element LED through a structure in which the sensing pattern SSP is covered by an insulating layer disposed under the first electrode AE and the additional electrode AAE and the first electrode AE and the additional electrode AAE are electrically connected to the sensing pattern SSP, measure the initial light amount of the light-emitting element LED and the light amount of the light-emitting element LED after an appropriate time (e.g., a predetermined time) has elapsed since the initial light emission, and calculate the degree of deterioration of the light from the light-emitting element LED based on the measured light amount. Therefore, through the analog structure of the Schottky diode formed by the sensing pattern SSP, the first electrode AE, and the additional electrode AAE, a display panel DP according to one or more embodiments may check the degree of deterioration of the light from the light-emitting element LED and determine whether to perform optical compensation, and thus may improve the light-emitting efficiency and power consumption of the display panel DP.

[0233] Return reference Figure 5 , a circuit element layer DP-CL of a display panel DP according to one or more embodiments may further include a capacitor Cst. The capacitor Cst may be charged with an amount of charge corresponding to the difference between the voltage corresponding to the data signal and the power voltage received from a power line. The transistor TR described above may control the driving current flowing through the light-emitting element LED according to the amount of charge stored in the capacitor Cst.

[0234] The on-time of the transistor TR may be determined according to the amount of charge charged in the capacitor Cst. The light-emitting element LED may emit light during the on-period of the transistor TR.

[0235] A first capacitor electrode E1 defines one electrode of the capacitor Cst. The first capacitor electrode E1 and the conductive patterns CPT1 and CPT2 may be disposed on the same layer (e.g., at the same layer). The first capacitor electrode E1 may also be a pattern having a shape integrated with the conductive patterns CPT1 and CPT2. Alternatively, the conductive patterns CPT1 and CPT2 and the first capacitor electrode E1 may also be electrically connected to each other through an additional bridge electrode and may also be spaced apart from each other (e.g., spaced) and receive different voltages.

[0236] The second capacitor electrode E2 overlaps with the first capacitor electrode E1 in a plan view. The second capacitor electrode E2 and the first capacitor electrode E1 can form a capacitor Cst, and the buffer layer BFL and the fifth insulating pattern GI5 are located therebetween.

[0237] In this embodiment, the second capacitor electrode E2, the connection electrodes CNE1 and CNE2, the gate electrode GE, and the sense line SGL can be disposed on the same layer (e.g., at the same layer). The second capacitor electrode E2 can be disposed on the gate insulating pattern layer GIL. The gate insulating pattern layer GIL can include the fifth insulating pattern GI5, and the second capacitor electrode E2 can be disposed on the fifth insulating pattern GI5. The second capacitor electrode E2, the connection electrodes CNE1 and CNE2, the gate electrode GE, and the sense line SGL can be formed concurrently (e.g., simultaneously) through one mask. Accordingly, the second capacitor electrode E2, the connection electrodes CNE1 and CNE2, the gate electrode GE, and the sense line SGL can include the same material and have the same stacked structure.

[0238] Figures 8A to 8E Respective plan views of some components of a display panel according to one or more embodiments of the present disclosure. Figures 8A to 8E Respectively schematically illustrate the planar arrangement relationship of the sense pattern SSP, the first electrode AE, and the additional electrode AAE and / or the arrangement relationship of the vias TH1 and TH2, etc.

[0239] Reference Figure 8A , the sense pattern SSP overlaps at least a part of the first electrode AE and a part of the additional electrode AAE in a plan view. The additional electrode AAE is arranged to be spaced apart (e.g., separated) from the first electrode AE in a plan view. The additional electrode AAE can be spaced apart (e.g., separated) from the first electrode AE along the first direction DR1.

[0240] In a plan view, each of the sense pattern SSP, the first electrode AE, and the additional electrode AAE can have a rectangular shape. Each of the sense pattern SSP, the first electrode AE, and the additional electrode AAE can have a rectangular shape having sides extending in the first direction DR1 and the second direction DR2, respectively.

[0241] The additional electrode AAE can have a smaller area size than the first electrode AE in a plan view. The first electrode AE can have a first width W1 in the first direction DR1, the additional electrode AAE can have a second width W2 in the first direction DR1, and the first width W1 can be greater than the second width W2.

[0242] The additional electrode AAE can be separated (e.g., spaced apart) from the first electrode AE by a first distance SS1 in a first direction DR1. In one or more embodiments, the first distance SS1 can be less than the width of each of the additional electrode AAE and the first electrode AE in the first direction DR1. That is, the first distance SS1 can be less than the first width W1 and the second width W2.

[0243] However, the present disclosure is not limited thereto, and as Figure 8B shown, the first distance SS1' can be greater than the width of at least one of the additional electrode AAE and the first electrode AE in the first direction DR1. The first distance SS1' can be greater than the second width W2 of the additional electrode AAE. If the first distance SS1' is designed to be greater than the second width W2, etc., the area size of the sensing pattern SSP that does not overlap with the additional electrode AAE and the first electrode AE can be increased, thereby improving the performance of the sensing pattern SSP for sensing light generated from the light-emitting element LED (see Figure 5 ).

[0244] Returning to reference Figure 8A , the first electrode AE can have a first length L1 in a second direction DR2, the additional electrode AAE can have a second length L2 in the second direction DR2, and the first length L1 and the second length L2 can be substantially the same. As used herein, "substantially the same" for width and / or length, etc. includes not only the case where the width and / or length, etc. have physically identical shapes, but also the case where, although the designs of the width and / or length, etc. are the same, there are differences between them that fall within the error limits of the process.

[0245] However, the present disclosure is not limited thereto, and as Figure 8C shown, the length of the first electrode AE in the second direction DR2 and the length of the additional electrode AAE in the second direction DR2 can be different. In the second direction DR2, the second length L2' of the additional electrode AAE can be less than the first length L1 of the first electrode AE. As Figure 8C shown, both the width W2' of the additional electrode AAE in the first direction DR1 and the length L2' of the additional electrode AAE in the second direction DR2 can be designed to be less than the width W1 and the length L1 of the first electrode AE, and thus the planar area size of the additional electrode AAE can be reduced or minimized.

[0246] A first via TH1 and a second via TH2 can be provided, and they can each have a circular shape in a plan view. However, the present disclosure is not limited thereto, and as Figure 8DAs shown, the first through-hole TH1 and the second through-hole TH2 can each be provided in plural. The first through-hole TH1 can include a (1-1) sub-through-hole TH1-1 and a (1-2) sub-through-hole TH1-2 that are spaced apart from each other (e.g., separated) along the second direction DR2, and the second through-hole TH2 can include a (2-1) sub-through-hole TH2-1 and a (2-2) sub-through-hole TH2-2 that are spaced apart from each other (e.g., separated) along the second direction DR2. In one or more embodiments, the number of each of the first through-hole TH1 and the second through-hole TH2 provided can be 3 or more, and each of the first through-hole TH1 and the second through-hole TH2 can also be arranged along the first direction DR1.

[0247] In addition, in a plan view, the first through-hole TH1' and the second through-hole TH2' can each have a polygonal shape instead of a circular shape. As Figure 8E shown, the first through-hole TH1' and the second through-hole TH2' can each have a rectangular shape. The first through-hole TH1' and the second through-hole TH2' can each have a rectangular shape having a long side in the second direction DR2 and a short side in the first direction DR1. However, the first through-hole TH1' and the second through-hole TH2' can also each have various shapes different from the Figure 8E shapes shown. For example, the first through-hole TH1' and the second through-hole TH2' can each have a rectangular shape with rounded corners.

[0248] Figure 9 is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure. Figure 9 shows a display panel according to one or more embodiments different from the display panel of the embodiment shown in Figure 5 . A description that duplicates the above description of other embodiments may not be provided.

[0249] Referring to Figure 9 , the display panel DP-1 can include a substrate layer BS, a circuit element layer DP-CL, a display element layer DP-LED, and a packaging layer TFE.

[0250] The circuit element layer DP-CL can include a conductive pattern CPT, a transistor TR, connection electrodes CNE1a and CNE2a, a buffer layer BFL, a gate insulating pattern layer GIL, insulating layers INS1a, INS2a, and INS3, a sensing line SGLa, a sensing pattern SSPa, and a capacitor Cst provided on the substrate layer BS.

[0251] The conductive pattern CPT can be disposed on the substrate layer BS. The conductive pattern CPT can receive a bias voltage. The conductive pattern CPT can also receive a first voltage. The conductive pattern CPT can prevent the potential caused by polarization from affecting the transistor TR. The conductive pattern CPT can prevent external light from reaching the transistor TR. In one or more embodiments of the present disclosure, the conductive pattern CPT can also be a floating electrode isolated from another electrode or wiring. The conductive pattern CPT can be disposed to correspond to the transistor TR. The conductive pattern CPT can include a metal such as molybdenum.

[0252] The first connection electrode CNE1a can be disposed on the first insulating layer INS1a. The first connection electrode CNE1a can contact a part of the drain region D-A through a first contact hole CH1a that passes through the first insulating layer INS1a and is connected to the drain region D-A. Additionally, the first connection electrode CNE1a can be connected to the conductive pattern CPT through a contact hole that passes through the buffer layer BFL and the first insulating layer INS1a. The drain region D-A and the conductive pattern CPT can be electrically connected to each other through the first connection electrode CNE1a. Since the conductive pattern CPT having excellent conductivity is connected to the drain region D-A, the current transmission characteristics can be improved.

[0253] The second connection electrode CNE2a can be disposed on the first insulating layer INS1a. The second connection electrode CNE2a can be connected to the source region S-A through a second contact hole CH2a that passes through the first insulating layer INS1a. The second connection electrode CNE2a can be connected to a power line that supplies power to the light-emitting element LED and provides a first voltage to the transistor TR.

[0254] The sensing line SGLa can be disposed on the first insulating layer INS1a. The sensing line SGLa can be a line that is electrically connected to the sensing pattern SSPa and transmits the level of the amount of light of the light-emitting element LED measured through the sensing pattern SSPa, so that it can be determined whether to perform optical compensation according to the level of the amount of light.

[0255] The sensing line SGLa and the connection electrodes CNE1a and CNE2a are disposed on the same layer (e.g., at the same layer). The sensing line SGLa and the connection electrodes CNE1a and CNE2a can be directly disposed on the first insulating layer INS1a.

[0256] The sensing line SGLa can be spaced apart (e.g., separated) from the connection electrodes CNE1a and CNE2a in a plan view. The sensing line SGLa can have a multi-layer structure in which conductive layers ML1a, ML2a, and ML3a similar to the conductive layers ML1, ML2, and ML3 described above are stacked. Figure 5 of the conductive layers ML1, ML2, and ML3 are stacked.

[0257] The sensing line SGLa and the connection electrodes CNE1a and CNE2a can be formed concurrently (e.g., simultaneously) by the same process. Each of the connection electrodes CNE1a and CNE2a and the sensing line SGLa can have the same (e.g., substantially the same) stacked structure. Each of the connection electrodes CNE1a and CNE2a and the sensing line SGLa can have a multilayer structure in which conductive layers ML1a, ML2a, and ML3a including different materials are stacked. The conductive layers ML1a, ML2a, and ML3a can include a first conductive layer ML1a, a second conductive layer ML2a, and a third conductive layer ML3a. The first conductive layer ML1a, the second conductive layer ML2a, and the third conductive layer ML3a can be stacked by a sputtering process, but the present disclosure is not limited thereto.

[0258] Each of the first conductive layer ML1a, the second conductive layer ML2a, and the third conductive layer ML3a can include a metallic material. For example, each of the first conductive layer ML1a, the second conductive layer ML2a, and the third conductive layer ML3a can include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and / or their alloys and / or indium tin oxide (ITO). The first conductive layer ML1a, the second conductive layer ML2a, and the third conductive layer ML3a can include different metallic materials. The second conductive layer ML2a can include a metallic material having excellent electrical conductivity, and the first conductive layer ML1a and the third conductive layer ML3a respectively disposed below and above the second conductive layer ML2a can include metallic materials having corrosion resistance. For example, the first conductive layer ML1a can include titanium (Ti), the second conductive layer ML2a can include copper (Cu), and the third conductive layer ML3a can include indium tin oxide (ITO). However, the present disclosure is not limited thereto.

[0259] The gate electrode GE can be disposed on the gate insulating pattern layer GIL. The gate electrode GE can overlap with the active region A-A in a plan view, and can be separated (e.g., spaced apart) from the active region A-A in the thickness direction (e.g., the third direction DR3), and the gate insulating pattern layer GIL is located between the gate electrode GE and the active region A-A.

[0260] The connection electrodes CNE1a and CNE2a and the gate electrode GE can be separated (e.g., spaced apart) from each other in a plan view. The connection electrodes CNE1a and CNE2a and the gate electrode GE can include different materials. That is, different from the connection electrodes CNE1 and CNE2 and the gate electrode GE shown in Figure 5 , the connection electrodes CNE1a and CNE2a and the gate electrode GE can be formed by separate processes.

[0261] The first electrode AE can be disposed on the third insulating layer INS3 of the circuit element layer DP-CL. The first electrode AE can be connected to the first connection electrode CNE1a through a first through hole TH1 that passes through the second insulating layer INS2a, the sensing pattern SSPa, and the third insulating layer INS3. A part of the first electrode AE can be disposed in the first through hole TH1. Since the first electrode AE can be connected to the first connection electrode CNE1a, the drain region D-A can be connected to the light-emitting element LED through the first connection electrode CNE1a.

[0262] The sensing pattern SSPa can be disposed on the second insulating layer INS2a and covered by the third insulating layer INS3. An additional electrode AAE is disposed on the third insulating layer INS3. The additional electrode AAE and the first electrode AE are disposed on the same layer (e.g., at the same layer).

[0263] The sensing pattern SSPa is disposed on the second insulating layer INS2a and patterned in a partial region. The sensing pattern SSPa overlaps at least a part of the first electrode AE and a part of the additional electrode AAE in a plan view. The sensing pattern SSPa can overlap a part of the first connection electrode CNE1a and a part of the sensing line SGLa in a plan view.

[0264] The third insulating layer INS3 covering the sensing pattern SSPa and the second insulating layer INS2a can be a layer having a high transmittance in the visible light wavelength range. In one or more embodiments, the light transmittance of the third insulating layer INS3 in the visible light wavelength range can be about 80% or greater. The light transmittance of the third insulating layer INS3 can be about 80% to about 95%. Since the third insulating layer INS3 can have a high light transmittance, the light emitted from the light-emitting element LED can not be blocked by the third insulating layer INS3 and can be introduced into the sensing pattern SSPa.

[0265] The additional electrode AAE is disposed on the third insulating layer INS3 and is disposed to be separated (e.g., spaced apart) from the first electrode AE in a plan view. The additional electrode AAE can be separated (e.g., spaced apart) from the first electrode AE along the first direction DR1.

[0266] The additional electrode AAE and the first electrode AE can be disposed on the same layer (e.g., at the same layer). The additional electrode AAE and the first electrode AE can be formed concurrently (e.g., simultaneously) by the same process.

[0267] The pixel defining layer PDL can be disposed on the additional electrode AAE. At least a part of the additional electrode AAE can be covered by the pixel defining layer PDL. The additional electrode AAE can be completely covered by the pixel defining layer PDL.

[0268] The additional electrode AAE may be electrically connected to the sensing line SGLa. The additional electrode AAE may be connected to the sensing line SGLa through a second through hole TH2 that passes through the second insulating layer INS2a, the sensing pattern SSPa, and the third insulating layer INS3. A portion of the additional electrode AAE may be disposed in the second through hole TH2.

[0269] Each of the first through hole TH1 and the second through hole TH2 may pass through the sensing pattern SSPa disposed on the second insulating layer INS2a. Each of the first through hole TH1 and the second through hole TH2 may pass through all of the second insulating layer INS2a, the third insulating layer INS3, and the sensing pattern SSPa. Each of the first through hole TH1 and the second through hole TH2 may pass through the sensing pattern SSPa, a portion of the first electrode AE may be disposed in the first through hole TH1, and a portion of the additional electrode AAE may be disposed in the second through hole TH2. Accordingly, each of the first electrode AE and the additional electrode AAE may be electrically connected to the sensing pattern SSPa. In one or more embodiments, as Figure 9 shown, the sensing pattern SSPa may have a shape in which a central portion of the sensing pattern SSPa may be bent or curved and may be inserted into the second insulating layer INS2a. However, the present disclosure is not limited thereto.

[0270] Hereinafter, a method of manufacturing a display panel according to one or more embodiments of the present disclosure will be described.

[0271] Figure 10 is a flowchart of a method of manufacturing a display panel according to one or more embodiments of the present disclosure. Figures 11A to 11D is a cross-sectional view of some steps of a method of manufacturing a display panel according to one or more embodiments of the present disclosure. Figures 11A to 11D Each shows a state of some steps of the method of manufacturing a display panel in a cross-section corresponding to the cross-section shown in Figure 5 Hereinafter.

[0272] Refer to Figure 10, a method of manufacturing a display panel according to one or more embodiments includes: forming a semiconductor pattern on a substrate layer (S100); forming a gate insulating pattern layer covering a part of the semiconductor pattern (S200); forming a first connection electrode and a sensing line on the gate insulating pattern layer (S300); forming a first insulating layer covering the first connection electrode and the sensing line (S400); forming a sensing pattern including silicon on the first insulating layer (S500); forming a second insulating layer covering the sensing pattern (S600); forming each of a first through hole and a second through hole passing through the first insulating layer, the sensing pattern, and the second insulating layer (S700); and forming a first electrode connected to the first connection electrode through the first through hole and an additional electrode connected to the sensing line through the second through hole on the second insulating layer (S800).

[0273] Figures 11A to 11D A cross-section corresponding to forming a sensing pattern including silicon on a first insulating layer (S500), forming a second insulating layer covering the sensing pattern (S600), forming each of a first through hole and a second through hole passing through the first insulating layer, the sensing pattern, and the second insulating layer (S700), and forming a first electrode connected to the first connection electrode through the first through hole and an additional electrode connected to the sensing line through the second through hole on the second insulating layer (S800) in the method of manufacturing a display panel is shown.

[0274] Refer together to Figure 10 , Figure 11A and Figure 11B , in a method of manufacturing a display panel according to one or more embodiments, a sensing pattern SSP is formed on a first insulating layer INS1. The sensing pattern SSP can be formed by providing a source gas DG to form a sensing pattern layer and then patterning the sensing pattern layer. The sensing pattern SSP can be patterned to overlap at least a part of each of the first connection electrode CNE1 and the sensing line SGL.

[0275] The source gas DG can include nitrogen (N2) gas and / or silane (SiH4) gas. The source gas DG can include nitrogen (N2) gas, ammonia (NH3) gas, silane (SiH4) gas, and hydrogen (H2) gas. The sensing pattern SSP can be formed by the following steps: providing each of nitrogen (N2) gas, ammonia (NH3) gas, silane (SiH4) gas, and / or hydrogen (H2) gas by chemical vapor deposition (CVD) to form a deposition film; and then patterning the deposition film by a dry etching process or the like. In the source gas DG, the ratio of nitrogen gas to silane gas can be about 4.0 to about 10. Since the ratio of nitrogen gas to silane gas in the source gas DG can be limited within this range, the sensing pattern SSP formed by the source gas DG can absorb light from a light-emitting element LED (see Figure 5)The emitted light provides high sensing sensitivity for measuring the light amount of the light-emitting element LED.

[0276] Reference Figure 10 、 Figure 11B and Figure 11C In the method of manufacturing a display panel according to one or more embodiments, a second insulating layer INS2 is formed on the first insulating layer INS1 and the sensing pattern SSP. The second insulating layer INS2 may include an organic material. The second insulating layer INS2 covering the sensing pattern SSP may be formed of a material having a high transmittance in the visible light wavelength range. In one or more embodiments, the transmittance of the second insulating layer INS2 in the visible light wavelength range may be about 80% or greater. The transmittance of the second insulating layer INS2 may be about 80% to about 95%.

[0277] Reference Figure 10 、 Figure 11C and Figure 11D In the method of manufacturing a display panel according to one or more embodiments, each of a first through hole TH1 and a second through hole TH2 is formed. Each of the first through hole TH1 and the second through hole TH2 may be formed to pass through all of the first insulating layer INS1, the second insulating layer INS2, and the sensing pattern SSP. The first through hole TH1 and the second through hole TH2 may be formed by the same process.

[0278] After forming the through holes TH1 and TH2, a first electrode AE and an additional electrode AAE are formed. The first electrode AE may be formed to be connected to a first connection electrode CNE1 through the first through hole TH1. The additional electrode AAE may be formed to be connected to a sensing line SGL through the second through hole TH2. The first electrode AE and the additional electrode AAE may be formed by the same process. The first electrode AE and the additional electrode AAE may include the same material. Each of the first electrode AE and the additional electrode AAE may be formed by forming a deposited layer having an integrated shape and a part of which is disposed in the through holes TH1 and TH2 and then patterning the deposited layer. The first through hole TH1 and the second through hole TH2 may each pass through the sensing pattern SSP, a part of the first electrode AE may be disposed in the first through hole TH1, and a part of the additional electrode AAE may be disposed in the second through hole TH2. Accordingly, each of the first electrode AE and the additional electrode AAE may be electrically connected to the sensing pattern SSP.

[0279] Figure 12A is a graph showing the value of the leakage current compared to the voltage of the sensing pattern according to the amount of light emitted from the light-emitting element in a display panel according to one or more embodiments. Figure 12BIt is a graph showing the value of the leakage current compared to the amount of light emitted by a light-emitting element according to the voltage applied to a sensing pattern in a display panel according to one or more embodiments. Figure 12B Each of the amount of light emitted and the leakage current is displayed on a logarithmic scale.

[0280] Reference Figure 12A and Figure 12B In the graphs in, it can be seen that as the amount of light emitted by the light-emitting element increases, the value of the leakage current generated in the sensing pattern increases proportionally to the amount of light emitted. Through Figure 12A and Figure 12B In the graphs in, it can be seen that a display panel according to one or more embodiments of the present disclosure can measure the amount of light of a light-emitting element through an analog structure of a Schottky diode formed by a structure in which a sensing pattern is provided under the light-emitting element and a first electrode and an additional electrode are electrically connected to the sensing pattern as described above. Therefore, a display panel according to one or more embodiments can have improved luminous efficiency and power consumption.

[0281] According to one or more embodiments of the present disclosure, the degree of deterioration of a light-emitting element can be measured by providing an analog structure of a diode in a circuit element layer of a display panel, and it can be determined whether to perform optical compensation according to the degree of deterioration of the light-emitting element, thereby improving the luminous efficiency and power consumption of the display panel. In addition, an analog structure of a diode can be formed in the circuit element layer through a simple process without an additional doping process or the like, thereby improving the efficiency of the display panel manufacturing process.

[0282] Although the present disclosure has been described with reference to embodiments of the present disclosure, it should be understood that the present disclosure should not be limited to these embodiments, but various changes and modifications can be made by those of ordinary skill in the art within the spirit and scope of the present disclosure as claimed. Therefore, the technical scope of the present disclosure is not limited to the content described in the detailed description of the specification, but should be determined by the appended claims and their equivalents.

Claims

1. A display panel, wherein, The display panel includes: a substrate layer; a transistor on the substrate layer and including a semiconductor pattern; a first connection electrode connected to the semiconductor pattern; a sensing line at the same layer as the first connection electrode; a first insulating layer on the transistor and the first connection electrode; a second insulating layer on the first insulating layer; a first electrode on the second insulating layer and connected to the first connection electrode through a first via hole; an additional electrode on the second insulating layer, the additional electrode being spaced apart from the first electrode in a plan view and connected to the sensing line through a second via hole; and a sensing pattern on the first insulating layer, the sensing pattern being electrically connected to the first electrode and the additional electrode and including silicon.

2. The display panel according to claim 1, wherein, The light transmittance of the sensing pattern in the visible light wavelength range is 10% or more.

3. The display panel according to claim 1, wherein, The display panel further includes a gate insulating pattern layer on the semiconductor pattern, wherein each of the first connection electrode and the sensing line is on the gate insulating pattern layer.

4. The display panel according to claim 3, wherein, The transistor further includes a gate electrode on the gate insulating pattern layer.

5. The display panel according to claim 4, wherein, The first connection electrode, the sensing line, and the gate electrode include the same material.

6. The display panel according to claim 1, wherein, The sensing pattern further includes nitrogen.

7. The display panel according to claim 1, wherein, The first electrode and the additional electrode are spaced apart from each other along a first direction, and the width of the first electrode in the first direction is greater than the width of the additional electrode in the first direction.

8. The display panel according to claim 1, wherein, Each of the first via hole and the second via hole passes through each of the first insulating layer, the second insulating layer, and the sensing pattern.

9. A display panel, wherein, The display panel includes: a substrate layer; a transistor on the substrate layer and including a semiconductor pattern; a first connection electrode connected to the semiconductor pattern; a sensing line spaced apart from the first connection electrode in a plan view; a first insulating layer on the transistor and the first connection electrode; a second insulating layer on the first insulating layer; a light-emitting element on the second insulating layer and electrically connected to the first connection electrode; an additional electrode on the second insulating layer and connected to the sensing line; and a sensing pattern on the first insulating layer, wherein the light-emitting element includes: a first electrode on the second insulating layer, the first electrode being connected to the first connection electrode and spaced apart from the additional electrode in a plan view; an emission layer on the first electrode; and a second electrode on the emission layer, and wherein a part of each of the first electrode and the additional electrode is in a via hole in the sensing pattern.

10. A manufacturing method of a display panel, wherein, The manufacturing method includes: forming a semiconductor pattern on a substrate layer; forming a gate insulating pattern layer covering a part of the semiconductor pattern; forming a first connection electrode and a sensing line on the gate insulating pattern layer; forming a first insulating layer covering the first connection electrode and the sensing line; forming a sensing pattern including silicon on the first insulating layer; forming a second insulating layer covering the sensing pattern; Form each of a first via hole and a second via hole that penetrate through the first insulating layer, the sensing pattern, and the second insulating layer; and Form a first electrode connected to the first connection electrode through the first via hole and an additional electrode connected to the sensing line through the second via hole on the second insulating layer.

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