Processor and computer

Abstract

The invention provides a processor and a computer, the processor comprises a plurality of quantum integrated chips and a photoelectric co-packaging chip, and each quantum integrated chip comprises a quantum adapter plate, an adjustable bus core particle, a quantum bit core particle, a superconducting memory core particle, an electronic integrated core particle and a complementary metal oxide semiconductor core particle. The plurality of quantum integrated chips are arranged on the photoelectric co-packaging adapter plate to form the photoelectric co-packaging chip, and a first photon integrated core particle is integrated in the photoelectric co-packaging adapter plate. The photoelectric co-packaging chip is arranged on a photoelectric co-packaging substrate to form the processor, and a second photon integrated core particle is integrated in the photoelectric co-packaging substrate. And the processor is arranged in a dilution refrigerator to form the computer. According to the quantum integrated chip, the photoelectric co-packaging chip, the processor and the computer provided by the embodiment of the invention, the expandability of superconducting quantum calculation is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a processor and a computer. Background Art

[0002] Superconducting quantum processors use the quantum properties of quantum bits at low temperatures, such as entanglement and superposition, to achieve quantum computing, which can significantly increase the computing speed compared to classical computers. Superconducting quantum processors are expected to play an important role in scientific research, finance, artificial intelligence, cryptography and other fields.

[0003] In the post-Moore era, as semiconductor process technology is gradually approaching the dual limits of technology and economy, core particle technology and three-dimensional integration technology have received extensive attention in recent years, aiming to achieve vertical expansion of integrated circuits through modular design, inter-layer and intra-layer interconnection structures, thereby improving integration density and overall system performance. In the field of superconducting quantum computing, this development trend has gradually become one of the important routes to achieve large-scale expansion of quantum bits.

[0004] To achieve a highly fault-tolerant, general-purpose superconducting quantum processor, millions of superconducting quantum bits are needed as a hardware foundation. The large-scale expansion of superconducting quantum bits requires solving problems such as crosstalk, high-precision measurement and control, and signal integrity under high integration. The three-dimensional integration of superconducting quantum processors may also face thermal management issues for non-superconducting or non-superconducting structures. In addition, signal delays caused by long-distance electrical interconnects in large-scale superconducting quantum processors may also become one of the limiting factors of system performance. Therefore, how to propose a superconducting quantum processor architecture that is easy to expand and integrate and has excellent comprehensive performance has become an important issue that needs to be urgently addressed in this field. Summary of the invention

[0005] In view of the problems in the prior art, embodiments of the present invention provide a processor and a computer, which can at least partially solve the problems in the prior art.

[0006] In a first aspect, the present invention provides a processor, comprising a plurality of quantum integrated chips and an optoelectronic co-sealed adapter board, wherein:

[0007] The multiple quantum integrated chips are arranged on the optoelectronic co-sealed adapter board, the optoelectronic co-sealed adapter board is integrated with a first photon integrated core particle, and the multiple quantum integrated chips communicate with each other through the first photon integrated core particle integrated on the optoelectronic co-sealed adapter board.

[0008] Furthermore, the quantum integrated chip includes a quantum switch board, an adjustable bus core particle, a quantum bit core particle, an electronic integration core particle and a superconducting memory core particle, wherein:

[0009] There are multiple qubit dies, and the qubit dies and corresponding electronic integrated dies are disposed on the quantum adapter board, and the superconducting memory dies corresponding to the qubit dies are disposed on the qubit dies;

[0010] The adjustable bus die is integrated in the quantum adapter board, and each qubit die is electrically connected through the adjustable bus die, and the qubit die is electrically connected to the corresponding superconducting memory die and electronic integrated die.

[0011] Furthermore, the quantum integrated chip further includes a first complementary metal oxide semiconductor die, and the first complementary metal oxide semiconductor die is disposed on and electrically connected to the electronic integrated die.

[0012] Furthermore, the processor provided by the embodiment of the present invention further includes a second complementary metal oxide semiconductor die, and the second complementary metal oxide semiconductor die is disposed on the electronic integrated die of an adjacent quantum integrated chip and is electrically connected to the electronic integrated die of the adjacent quantum integrated chip respectively.

[0013] Furthermore, the multiple quantum integrated chips and the first photon integrated dies integrated in the optical-electrical co-packaged adapter board are arranged alternately;

[0014] If the multiple quantum integrated chips and the first photon integrated dies integrated in the optical-electrical co-packaged adapter board are linearly arranged, then in the arrangement direction, the quantum integrated chip is adjacent to at least one of the first photon integrated dies, and each first photon integrated die is adjacent to at least two quantum integrated chips;

[0015] If the multiple quantum integrated chips and the first photon integrated dies integrated in the optical-electrical co-packaged adapter board are arranged in a two-dimensional array, then the quantum integrated chip is adjacent to at least 2 of the first photon integrated dies, and each first photon integrated die is adjacent to at least 2 quantum integrated chips.

[0016] Furthermore, the processor provided by the embodiment of the present invention further includes an optical-electrical co-packaged substrate, and a second photon integrated die is integrated in the optical-electrical co-packaged substrate, and the second photon integrated dies are connected to each other through optical waveguides; multiple optical-electrical co-packaged chips are disposed on the optical-electrical co-packaged substrate, and the multiple optical-electrical co-packaged chips communicate through the second photon integrated die integrated in the optical-electrical co-packaged substrate, and each optical-electrical co-packaged chip includes multiple quantum integrated chips.

[0017] Furthermore, a first thermal interface material is disposed at the bottom of the optical-electrical co-packaged substrate.

[0018] Furthermore, a second thermal interface material is disposed on the top of the quantum integrated chip.

[0019] In a second aspect, the present invention provides a computer, comprising the processor and the dilution refrigerator according to any of the above embodiments. The dilution refrigerator includes a first cold plate and a second cold plate. The processor is disposed between the first cold plate and the second cold plate and is in contact with the first cold plate and the second cold plate respectively.

[0020] Further, a first heat dissipation layer is disposed between the processor and the first cold plate, and / or a second heat dissipation layer is disposed between the processor and the second cold plate.

[0021] The processor and the computer provided by the embodiments of the present invention include a plurality of quantum integrated chips and an optical-electrical co-packaged adapter board. The plurality of quantum integrated chips are disposed on the optical-electrical co-packaged adapter board. The optical-electrical co-packaged adapter board integrates a first photonic integrated die. The plurality of quantum integrated chips communicate with each other through the first photonic integrated die integrated in the optical-electrical co-packaged adapter board, improving the scalability of the processor. Description of the Drawings

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings. In the drawings:

[0023] Figure 1A is a top view structural schematic diagram of the processor provided by the first embodiment of the present invention.

[0024] Figure 1B is a cross-sectional structural schematic diagram of the processor provided by the first embodiment of the present invention.

[0025] Figure 2 is a cross-sectional structural schematic diagram of the quantum integrated chip provided by the second embodiment of the present invention.

[0026] Figure 3 is a cross-sectional structural schematic diagram of the quantum integrated chip provided by the third embodiment of the present invention.

[0027] Figure 4 is a cross-sectional structural schematic diagram of the optical-electrical co-packaged chip provided by the fourth embodiment of the present invention.

[0028] Figure 5 is a top view structural schematic diagram of the processor provided by the fifth embodiment of the present invention.

[0029] Figure 6 is a top view structural schematic diagram of the processor provided by the sixth embodiment of the present invention.

[0030] Figure 7It is a schematic cross-sectional structure diagram of the processor provided by the seventh embodiment of the present invention.

[0031] Figure 8 It is a schematic structure diagram of the computer provided by the eighth embodiment of the present invention.

[0032] Figure 9 It is a schematic cross-sectional structure diagram of the computer provided by the ninth embodiment of the present invention. Detailed implementation manners

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer and more understandable, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but not to limit the present invention. It should be noted that, without conflict, the embodiments and features in the embodiments in this application can be combined with each other arbitrarily. The acquisition, storage, use, processing, etc. of data in the technical solutions in this application all comply with the relevant regulations of laws and regulations.

[0034] To facilitate the understanding of the technical solutions provided in this application, the relevant content of the technical solutions in this application will be described first below.

[0035] The silicon interposer in the 2.5D packaging structure can provide narrow pitch and high-density wiring capabilities, thus helping to improve the integration density and system performance. However, the large-area silicon interposer has a high cost and a low yield. Therefore, this application introduces a bridging structure in the key areas and adopts targeted high-density wiring to avoid performance degradation. Other areas can use materials with lower costs such as organic or molded materials, which helps to achieve a good balance between cost and performance. In addition, instantiating some general functions as buried bridging structures helps to save on-chip space and improve the functional density of active devices; when the application requirements change, the top chiplet can also be replaced to realize the reuse of the bridging structure, significantly improving the flexibility of system design. At the same time, the bridging structure can achieve high-bandwidth and low-latency inter-chip communication by providing short-distance high-density interconnections under the chip, thereby improving the overall performance of the system.

[0036] On the other hand, at the current stage, superconducting quantum processors usually adopt the technical route of System on Chip (SoC). However, in future large-scale general-purpose quantum computing, the SoC solution will encounter some significant technical bottlenecks: First, as the number of qubits increases, the area of the SoC chip will continue to grow, which will lead to a rapid decline in the process yield of the entire SoC, thereby increasing the manufacturing cost. Second, different functional units in the entire superconducting quantum processor have different requirements for the process limit, which provides a basis for more efficient modular design, that is, the functional units can be "chipletized" to fully achieve the balance between the overall system performance and cost. The chipletization scheme proposed in this application requires that different functional units in the superconducting quantum processor be decoupled in design and space, and be provided in the form of separate small-sized, high-yield chiplets, and then three-dimensionally integrated through mature bump (interlayer interconnection) and via (intralayer interconnection) structures to achieve the complete function of the superconducting quantum processor. This method can effectively reduce the construction cost, tape-out cycle and system yield of the superconducting quantum processor, and also supports hardware reuse. Replacement can be achieved by simply debonding and rebonding the failed chiplets, significantly improving the design flexibility.

[0037] Since the tunable bus chiplet and the Photonic Integrated Circuit (PIC) have dual-ended interfaces, allowing flexible bidirectional signal conversion or transmission, this application proposes to embed the tunable bus chiplet in the quantum interposer, and embed the photonic integrated chiplets in the co-packaged optics (CPO) interposer and the co-packaged optics (CPO) substrate respectively to achieve the bridging function. Among them, the tunable bus chiplet is embedded in the quantum interposer to bridge the stack of adjacent qubit chiplets and superconducting memory chiplets; on the one hand, the photonic integrated chiplet can be used as a local bridging structure and embedded in the co-packaged optics (CPO) interposer to bridge adjacent quantum integrated chips; on the other hand, it can be used as a global bridging structure and embedded in the co-packaged optics (CPO) substrate to bridge adjacent co-packaged optics (CPO) chips. Through the above method, a network architecture of a processor with high scalability can be achieved. This application exemplifies the photonic integrated chiplet and the tunable bus chiplet as bridging structures, and proposes a two-level interconnection architecture of the global bridging structure and the local bridging structure, effectively alleviating the pursuit of the limit of the area of a single interposer, and adopting a globally symmetric design, significantly improving the design flexibility and scalability.

[0038] The dilution refrigerator has great difficulty in cooling down and the speed is slow. For a superconducting quantum processor, it often takes several days to cool down to the mK level using a dilution refrigerator. Due to reasons such as different superconducting transition temperatures required for different materials to enter the superconducting state, uneven temperature distribution in different parts of the superconducting quantum processor, and the possible existence of some non-superconducting components inside the superconducting quantum computer, the Joule heat continuously generated by some electrical structures that have not entered the superconducting state or have no superconducting characteristics will further extend the cooling time and affect the stability of the electrical structures that have entered the superconducting state. The uniform and rapid heat dissipation of the superconducting quantum processor helps to improve the cooling speed and the stability of the quantum state. Therefore, it is urgent to explore an effective conduction heat dissipation mechanism to optimize the heat dissipation path of the superconducting quantum processor during the cooling process. In this application, an effective continuous conduction heat dissipation path is achieved by introducing a thermal interface layer and a heat dissipation layer to closely fit the upper and lower surfaces of the superconducting quantum processor to the cold plate, which helps to solve the complex heat dissipation problem of the superconducting quantum processor adopting a three-dimensional integrated architecture.

[0039] The purpose of the present invention is to provide a processor with a bridging structure and an optical-electrical co-packaging architecture. The key points of the present invention include die design methodologies (such as qubit dies, tunable bus dies), adapted intra-layer (vias), inter-layer (bumps) interconnect technologies, and on-chip optical-electrical co-packaging technologies, in order to optimize aspects such as the integration density, electrical performance, and manufacturing cost of the processor, and lay a technical foundation for future large-scale general quantum computing.

[0040] This application decouples the quantum integration chip into qubit dies, tunable bus dies, superconducting memory dies, electronic integration dies, and the first photon integration die; adjacent quantum integration chips, the second complementary metal-oxide-semiconductor die, and the optical-electrical co-packaging adapter board can form an optical-electrical co-packaged chip; the optical-electrical co-packaged chip and the optical-electrical co-packaging substrate can form a processor; the processor and the dilution refrigerator can form a computer.

[0041] Figure 1A is a top view structural schematic diagram of the processor provided by the first embodiment of the present invention, Figure 1B is a cross-sectional structural schematic diagram of the processor provided by the first embodiment of the present invention, Figure 1B is Figure 1A the cross-sectional view taken along A-A in Figure 1A and Figure 1B As shown, the processor provided by the embodiment of the present invention includes a plurality of quantum integration chips 1 and an optical-electrical co-packaging adapter board 2, wherein:

[0042] A plurality of quantum integration chips 1 are arranged on the optical-electrical co-packaging adapter board 2, and the first photon integration die 3 is integrated in the optical-electrical co-packaging adapter board 2. The plurality of quantum integration chips 1 communicate with each other through the first photon integration die 3 integrated in the optical-electrical co-packaging adapter board 2.

[0043] Specifically, a first photonic integrated die 3 is embedded in the optical-electronic co-pack interposer 2 to bridge adjacent quantum integrated chips 1, that is, the quantum integrated chips 1 can communicate with each other through the connected first photonic integrated die 3. The optical-electronic co-pack interposer 2 can be made of materials such as silicon. Multiple quantum integrated chips 1 are arranged on the optical-electronic co-pack interposer 2, and the arrangement of the multiple quantum integrated chips 1 on the optical-electronic co-pack interposer 2 is set according to actual needs, which is not limited in the embodiments of the present invention.

[0044] The quantum integrated chip 1 may include a quantum interposer, a tunable bus die, a qubit die, a superconducting memory die, and an electronic integrated die. The tunable bus die can be embedded in the quantum interposer to bridge adjacent qubit dies. The superconducting memory die can be stacked on the qubit die to reduce the distance required for information access and storage in the superconducting memory die, reducing latency and signal distortion. The electronic integrated die (Electronic Integrated Circuit, abbreviated as EIC) in the quantum integrated chip 1 and the first photonic integrated die 3 in the optical-electronic co-pack interposer 2 can form a local optical engine (Optical Engine, abbreviated as OE).

[0045] For example, if the first photonic integrated dies integrated with multiple quantum integrated chips and the optical-electronic co-pack interposer are linearly arranged, then in the arrangement direction, the quantum integrated chip is adjacent to at least one first photonic integrated die, and each first photonic integrated die is adjacent to at least two quantum integrated chips;

[0046] For example, if the first photonic integrated dies integrated with multiple quantum integrated chips and the optical-electronic co-pack interposer are arranged in a two-dimensional array, then the quantum integrated chip is adjacent to at least 2 first photonic integrated dies, and each first photonic integrated die is adjacent to at least 2 quantum integrated chips.

[0047] The processor provided by the embodiments of the present invention includes multiple quantum integrated chips and an optical-electronic co-pack interposer. The multiple quantum integrated chips are arranged on the optical-electronic co-pack interposer. The optical-electronic co-pack interposer integrates a first photonic integrated die. The multiple quantum integrated chips communicate with each other through the first photonic integrated die integrated in the optical-electronic co-pack interposer, improving the scalability of the processor.

[0048] Figure 2 is a schematic cross-sectional structure diagram of the quantum integrated chip provided by the second embodiment of the present invention. As Figure 2 shown, on the basis of the above embodiments, further, the quantum integrated chip 1 includes a quantum interposer 1-1, a tunable bus die 1-2, a qubit die 1-3, a superconducting memory die 1-4, and an electronic integrated die 1-5, where:

[0049] There are multiple qubit dies 1-3. The qubit dies 1-3 and the corresponding electronic integrated dies 1-5 are disposed on the quantum adapter board 1-1, and the superconducting memory dies 1-4 corresponding to the qubit dies 1-3 are disposed on the qubit dies 1-3;

[0050] The quantum adapter board 1-1 integrates the tunable bus die 1-2. Each qubit die 1-3 is electrically connected through the tunable bus die 1-2, and the qubit die 1-3 is electrically connected to the corresponding superconducting memory die 1-4 and the electronic integrated die 1-5. The quantum adapter board 1-1 can be a silicon-based adapter board, a glass-based adapter board, etc., and is selected according to actual needs. The embodiments of the present invention do not make limitations.

[0051] In order to fully utilize the advantages brought by die integration such as short cycle, high yield, and high flexibility, the quantum integrated chip of this application is decoupled into qubit dies 1-3, tunable bus dies 1-2, superconducting memory dies 1-4, electronic integrated dies 1-5, and first photon integrated dies 3 according to functions. The tunable bus die 1-2 is embedded in the quantum adapter board 1-1, which plays a role in connecting and coupling adjacent qubit dies on both sides, realizing signal transmission between each qubit die 1-3. The superconducting memory die 1-4 is stacked on the corresponding qubit die 1-3, which helps to achieve in-memory computing, reduces the distance required for information access and storage in the superconducting memory die, and reduces latency and signal distortion. The electronic integrated die 1-5 corresponding to the qubit die 1-3 and the first photon integrated die 3 can form a local OE.

[0052] The types of qubits in the qubit die 1-3 can include various mainstream qubit types such as flux, charge, phase, Transmon, etc., preferably Transmon qubits. The types of qubits in the tunable bus die 102 can be selected from various frequency-tunable qubits, preferably Transmon qubits. The superconducting memory die 1-4 can be any physical structure that can maintain quantum information for a long time.

[0053] For example, as Figure 2As shown, an adjustable bus die 1-2 is embedded in the quantum interposer 1-1. The quantum bit die 1-3 is bonded to the quantum interposer 1-1 through the bump bonding pair 1-13 and the bump bonding pair 1-23. The electronic integration die 1-5 is bonded to the quantum interposer 1-1 through the bump bonding pair 1-15. The superconducting memory die 1-4 is bonded to the quantum bit die 1-3 through the bump bonding pair 1-34. The quantum bit die 1-3 is electrically connected to the superconducting memory die 1-4 through the bump bonding pair 1-34. Each adjacent quantum bit die 1-3 is electrically connected to the adjustable bus die 1-2 through its corresponding bump bonding pair 1-23. An electrical interconnection line 1-1-3 is provided on the quantum interposer 1-1. The quantum bit die 1-3 is electrically connected to the electronic integration die 1-5 through the bump bonding pair 1-13, the electrical interconnection line 1-1-3, and the bump bonding pair 1-15 connected to the electrical interconnection line 1-1-3. A conductive via 1-1-1 is provided in the quantum interposer 1-1. Through the conductive via 1-1-1, the quantum integration chip 1 can receive external signals and transmit the signals of the quantum integration chip 1 outward. Among them, the bump bonding pair 1-13 includes an upper bump 1-3-0 and a lower bump 1-1-2. After the upper bump 1-3-0 and the lower bump 1-1-2 are bonded, the bump bonding pair 1-13 is formed. The upper bump 1-3-0 is fabricated on the lower surface of the quantum bit die 1-3, and the lower bump 1-1-2 is fabricated on the upper surface of the quantum interposer 1-1. The bump bonding pair 1-23 includes an upper bump 1-3-0 and a lower bump 1-2-0. After the upper bump 1-3-0 and the lower bump 1-2-0 are bonded, the bump bonding pair 1-23 is formed. The upper bump 1-3-0 is fabricated on the lower surface of the quantum bit die 1-3, and the lower bump 1-2-0 is fabricated on the upper surface of the adjustable bus die 1-2. The bump bonding pair 1-15 includes an upper bump 1-5-0 and a lower bump 1-1-0. After the upper bump 1-5-0 and the lower bump 1-1-0 are bonded, the bump bonding pair 1-15 is formed. The upper bump 1-5-0 is fabricated on the lower surface of the electronic integration die 1-5, and the lower bump 1-1-0 is fabricated on the upper surface of the quantum interposer 1-1. The bump bonding pair 1-34 includes an upper bump 1-4-0 and a lower bump 1-3-1. After the upper bump 1-4-0 and the lower bump 1-3-1 are bonded, the bump bonding pair 1-34 is formed. The upper bump 1-4-0 is fabricated on the lower surface of the superconducting memory die 1-4, and the lower bump 1-3-1 is fabricated on the upper surface of the quantum bit die 1-3.

[0054] Figure 3 is a schematic cross-sectional structure diagram of the quantum integration chip provided by the third embodiment of the present invention, as Figure 3As shown, based on the above embodiments, further, the quantum integration chip 1 further includes a first complementary metal oxide semiconductor (CMOS) die 1-6. The first CMOS die 1-6 is disposed on the electronic integration die 1-5 and electrically connected to the electronic integration die 1-5. The first CMOS die 1-6 may include a memory module for data caching function, capable of caching the data processed by the connected electronic integration die 1-5. The memory module may adopt a static random access memory (SRAM), a dynamic random access memory (DRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), etc., which is selected according to actual needs and is not limited in the embodiments of the present invention.

[0055] For example, as Figure 3 shown, an adjustable bus die 1-2 is embedded in the quantum adapter board 1-1. The qubit die 1-3 is bonded to the quantum adapter board 1-1 through the bump bond pair 1-13 and the bump bond pair 1-23. The electronic integration die 1-5 is bonded to the quantum adapter board 1-1 through the bump bond pair 1-15. The superconducting memory die 1-4 is bonded to the qubit die 1-3 through the bump bond pair 1-34. The first CMOS die 1-6 is bonded to the electronic integration die 1-5 through the bump bond pair 1-56. The qubit die 1-3 is electrically connected to the superconducting memory die 1-4 through the bump bond pair 1-34. The electronic integration die 1-5 is electrically connected to the first CMOS die 1-6 through the bump bond pair 1-56. Two adjacent qubit dies 1-3 are electrically connected through their respective corresponding bump bond pairs 1-23 and the adjustable bus die 1-2. An electrical interconnection line 1-1-3 is disposed on the quantum adapter board 1-1. The qubit die 1-3 is electrically connected to the electronic integration die 1-5 through the bump bond pair 1-13, the electrical interconnection line 1-1-3, and the bump bond pair 1-15. A conductive via 1-1-1 is disposed in the quantum adapter board 1-1. Through the conductive via 1-1-1, the quantum integration chip 1 can receive external signals and transmit the signals of the quantum integration chip 1 outward. Among them, the bump bond pair 1-56 includes an upper bump 1-6-0 and a lower bump 1-5-1. After the upper bump 1-6-0 and the lower bump 1-5-1 are bonded, the bump bond pair 1-56 is formed. The upper bump 1-6-0 is fabricated on the lower surface of the first CMOS die 1-6, and the lower bump 1-5-1 is fabricated on the upper surface of the electronic integration die 1-5.

[0056] It can be understood that the second embodiment of the present invention is applicable to application scenarios with relatively low computing loads, that is, the built-in logic circuits and storage circuits of the electronic integrated die 1-5 are sufficient to meet the computing and scheduling requirements of the quantum integrated chip 1; the third embodiment of the present invention is applicable to application scenarios with relatively high computing loads. For example, the number of qubit die 1-3 on the quantum adapter board 1-1 is relatively large, and the electronic integrated die 1-5, as a simple interface module, cannot fully handle all computing and scheduling requirements. Therefore, a first CMOS die 1-6 needs to be added to assist in load balancing scheduling, data caching, and other functions.

[0057] Figure 4 FIG. is a schematic cross-sectional structure diagram of the optoelectronic co-packaged chip provided by the fourth embodiment of the present invention. As Figure 4 shown, on the basis of the above embodiments, further, the superconducting quantum chip provided by the embodiment of the present invention further includes a second CMOS die 4. The second CMOS die 4 is disposed on the electronic integrated die 1-5 of the adjacent quantum integrated chip 1 and is electrically connected to the electronic integrated die 1-5 of the adjacent quantum integrated chip 1 respectively. The second CMOS die 4 may include an SRAM module and an Application Specific Integrated Circuit (ASIC) module. The SRAM module has a data caching function and can provide data caching functions for two adjacent electronic integrated die. The ASIC module is used for data communication between adjacent quantum integrated chips 1 and can perform load balancing scheduling on adjacent quantum integrated chips 1.

[0058] Two adjacent quantum integrated chips 1, the second CMOS die 4, and the optoelectronic co-packaged adapter board 2 can form an optoelectronic co-packaged chip.

[0059] For example, as Figure 4As shown in the figure, the photoelectric co-packaged chip may include a second CMOS die 4, a photoelectric co-packaged interposer 2, and two quantum integrated chips 1. The first photonic integrated die 3 is embedded in the photoelectric co-packaged interposer 2. The quantum integrated chip 1 is bonded to the photoelectric co-packaged interposer 2 through the bump bond pair 0-12. The second CMOS die 4 is bonded to the adjacent quantum integrated chips 1 through the bump bond pairs 0-14-0 and 0-14-1 respectively, that is, bonded to the electronic integrated die 1-5 of the adjacent quantum integrated chips 1 respectively. The adjacent quantum integrated chips 1 are electrically connected to the first photonic integrated die 3 through their respective bump bond pairs 0-13. Among them, the bump bond pair 0-12 includes an upper bump 1-0 and a lower bump 2-0. After the upper bump 1-0 and the lower bump 2-0 are bonded, the bump bond pair 0-12 is formed. The upper bump 1-0 is fabricated on the lower surface of the quantum integrated chip 1, and the lower bump 2-0 is fabricated on the upper surface of the photoelectric co-packaged interposer 2. The bump bond pair 0-14-0 includes an upper bump 4-0 and a lower bump 1-5-1. After the upper bump 4-0 and the lower bump 1-5-1 are bonded, the bump bond pair 0-14-0 is formed. The upper bump 4-0 is fabricated on the lower surface of the second CMOS die 4, and the lower bump 1-5-1 is fabricated on the upper surface of the electronic integrated die 1-5 included in the quantum integrated chip 1. The bump bond pair 0-14-1 includes an upper bump 4-1 and a lower bump 1-5-1. After the upper bump 4-1 and the lower bump 1-5-1 are bonded, the bump bond pair 0-14-1 is formed. The upper bump 4-1 is fabricated on the lower surface of the second CMOS die 4, and the lower bump 1-5-1 is fabricated on the upper surface of the electronic integrated die 1-5 included in another quantum integrated chip 1. The bump bond pair 0-13 includes an upper bump 1-7 and a lower bump 3-0. After the upper bump 1-7 and the lower bump 3-0 are bonded, the bump bond pair 0-13 is formed. The upper bump 1-7 is fabricated on the lower surface of the quantum integrated chip 1 and is connected to the conductive via 1-1-1, and the lower bump 3-0 is fabricated on the upper surface of the first photonic integrated die 3.

[0060] Each quantum integrated chip 1 includes a quantum interposer 1-1, an adjustable bus die 1-2, a qubit die 1-3, a superconducting memory die 1-4, an electronic integrated die 1-5, and a first CMOS die 1-6. The adjustable bus die 1-2 is embedded in the quantum interposer 1-1. The quantum interposer 1-1 is bonded to the photoelectric co-packaged interposer 2 through the bump bond pair 0-12. The qubit die 1-3 is bonded to the quantum interposer 1-1 through the bump bond pair 1-23. The electronic integrated die 1-5 is bonded to the quantum interposer 1-1 through the bump bond pair 1-15. The superconducting memory die 1-4 is bonded to the qubit die 1-3 through the bump bond pair 1-34. The first CMOS die 1-6 is bonded to the electronic integrated die 1-5 through the bump bond pair 1-56.

[0061] The quantum bit dies 1-3 are electrically connected to the superconducting memory die 1-4 through the bump bonding pairs 1-34. The electronic integration die 1-5 is electrically connected to the first CMOS die 1-6 through the bump bonding pair 1-56. Two adjacent quantum bit dies 1-3 are electrically connected through their respective corresponding bump bonding pairs 1-23 and the adjustable bus die 1-2. An electrical interconnection line 1-1-3 is provided on the quantum interposer 1-1. The quantum bit die 1-3 is electrically connected to the electronic integration die 1-5 through the bump bonding pair 1-13, the electrical interconnection line 1-1-3, and the bump bonding pair 1-15.

[0062] A conductive via 1-1-1 is provided in the quantum interposer 1-1. A coupler 2-2 and a photoelectric conversion module 2-3 are provided on the co-packaged optical-electrical interposer 2. A via structure 2-4 is provided in the first photon integration die 3, and the via structure 2-4 allows an external optical fiber to penetrate. The coupler 2-2 is used to change the propagation direction of the optical signal so that the optical signal is introduced into the photoelectric conversion module 2-3 from the external optical fiber. The photoelectric conversion module 2-3 is used to convert the received optical signal into an electrical signal. The optical signal of the external optical fiber is introduced into the electronic integration die 1-5 through the coupler 2-2, the photoelectric conversion module 2-3, the bump bonding pair 0-13, the conductive via 1-1-1, and the bump bonding pair 1-15.

[0063] A conductive via 1-1-1 is provided in the quantum interposer 1-1. An electrical interconnection line 1-1-4 is provided on the surface of the quantum interposer 1-1 facing the co-packaged optical-electrical interposer 2. A conductive via 2-1 is provided in the co-packaged optical-electrical interposer 2. The electronic integration die 1-5 can transmit electrical signals to the outside or receive external electrical signals through the bump bonding pair 1-15, the conductive via 1-1-1, the electrical interconnection line 1-1-4, the bump bonding pair 0-12, and the conductive via 2-1.

[0064] After processing the signals from the first photon integration die 3, the electronic integration die 1-5 transmits them to the quantum bit die 1-3 and the superconducting memory die 1-4 for calculation and storage. The calculation results can be interacted with the adjacent quantum bit die 1-3 and the superconducting memory die 1-4 through the bridging structure formed by the adjustable bus die 1-2. The adjacent quantum bit die 1-3 and the superconducting memory die 1-4 are also connected to the corresponding electronic integration die 1-5, forming a symmetric structure that can be extended bidirectionally.

[0065] Figure 5 It is a top view structural schematic diagram of the processor provided by the fifth embodiment of the present invention. Figure 6 It is a top view structural schematic diagram of the processor provided by the sixth embodiment of the present invention. As Figure 5 and Figure 6 shown, on the basis of the above embodiments, further, the first photon integration dies 3 integrated with multiple quantum integration chips 1 and the co-packaged optical-electrical interposer 2 are alternately arranged;

[0066] For example, as Figure 5 shown, if the first photonic integrated die 3 integrated by multiple quantum integrated chips 1 and the optoelectronic co-packaged adapter board 2 is linearly arranged, then in the arrangement direction, the quantum integrated chip 1 is adjacent to at least one first photonic integrated die 3, and each first photonic integrated die 3 is adjacent to at least two quantum integrated chips 1;

[0067] If the first photonic integrated die 3 integrated by multiple quantum integrated chips 1 and the optoelectronic co-packaged adapter board 2 is arranged in a two-dimensional array, then the quantum integrated chip 1 is adjacent to at least 2 first photonic integrated dies 3, and each first photonic integrated die 3 is adjacent to at least 2 quantum integrated chips 1.

[0068] For example, as Figure 6 shown, multiple quantum integrated chips 1 and multiple first photonic integrated dies 3 are arranged in a two-dimensional array on the optoelectronic co-packaged adapter board 2. The quantum integrated chip 1 is adjacent to at least 2 first photonic integrated dies 3, and each first photonic integrated die 3 is adjacent to at least 3 quantum integrated chips 1.

[0069] Figure 7 is a schematic cross-sectional structure diagram of the processor provided by the seventh embodiment of the present invention. As Figure 7 shown, on the basis of the above embodiments, further, the processor provided by the embodiment of the present invention further includes an optoelectronic co-packaged substrate 5. The optoelectronic co-packaged substrate 5 integrates second photonic integrated dies 6, and the second photonic integrated dies 6 are connected by optical waveguides 7; multiple optoelectronic co-packaged chips 100 are arranged on the optoelectronic co-packaged substrate 5, and the multiple optoelectronic co-packaged chips 100 communicate through the second photonic integrated dies 6 integrated in the optoelectronic co-packaged substrate 5. Each optoelectronic co-packaged chip 100 includes multiple quantum integrated chips 1 and an optoelectronic co-packaged adapter board 2, and the multiple quantum integrated chips 1 included in the optoelectronic co-packaged chip 100 are arranged on the optoelectronic co-packaged adapter board 2. Among them, the number of the second photonic integrated dies 6 integrated in the optoelectronic co-packaged substrate 5 is set according to actual needs, and the embodiment of the present invention does not make a limitation.

[0070] Each optoelectronic co-packaged chip 100 can be bonded to the optoelectronic co-packaged substrate 5 through solder balls 2-0-1, solder balls 2-0-2, solder balls 2-0-3, and solder balls 2-0-4. The solder balls can be elemental solder balls or alloy solder balls with superconducting characteristics, and are selected according to actual needs. The embodiment of the present invention does not make a limitation. The second photonic integrated die 6 is embedded in the optoelectronic co-packaged substrate 5 to realize the communication connection of each optoelectronic co-packaged chip 100. Since the second photonic integrated dies 6 are connected by optical waveguides 7, an optical communication link is introduced in the communication of each optoelectronic co-packaged chip 100, reducing the communication delay and interference, and improving the communication bandwidth, thereby improving the communication efficiency and reliability between each optoelectronic co-packaged chip 100.

[0071] For example, as Figure 7 shown, two photoelectric co-packaged chips 100 are bonded to the photoelectric co-packaged substrate 5 through their respective corresponding solder balls 2-0-1, solder balls 2-0-2, solder balls 2-0-3, and solder balls 2-0-4. Two second photon integrated dies 6 are embedded in the photoelectric co-packaged substrate 5. Each photoelectric co-packaged chip 100 is electrically connected to one second photon integrated die 6, and optical communication is carried out between the two second photon integrated dies 6 through an optical waveguide. Each photoelectric co-packaged chip 100 can be electrically connected to the corresponding second photon integrated die 6 through the solder ball 2-0-4 and the electrical interconnection line 5-4. Each photoelectric co-packaged chip 100 can also be electrically connected to the corresponding second photon integrated die 6 through the solder ball 2-0-3 and the electrical interconnection line 5-3. The second photon integrated die 6 can convert the received electrical signal into an optical signal for transmission through the optical waveguide 7, and can also convert the optical signal received from the optical waveguide 7 into an electrical signal for transmission to the electrical interconnection line 5-4 or 5-3. Among them, the solder ball can be a single-element solder ball or an alloy solder ball with superconducting characteristics, which is selected according to actual needs, and is not limited in the embodiments of the present invention.

[0072] Each photoelectric co-packaged chip 100 can transmit electrical signals to the outside or receive electrical signals from the outside through the solder ball 2-0-1 and the electrical interconnection line 5-1. Each photoelectric co-packaged chip 100 can transmit electrical signals to the outside or receive electrical signals from the outside through the solder ball 2-0-2 and the electrical interconnection line 5-2. The electrical interconnection line 5-1 and the electrical interconnection line 5-2 can be connected to the welding head patch cord. Figure 7 In, the cross-sections of the solder ball 2-0-2 and the solder ball 2-0-1 are coplanar. It can be understood that the solder ball 2-0-2 and the solder ball 2-0-1 can also be non-coplanar and misaligned. The electrical interconnection line 5-1 and the electrical interconnection line 5-2 are non-coplanar.

[0073] The co-packaged optoelectronic chip 100 includes a co-packaged optoelectronic adapter board 2 provided with conductive vias 2-1, and each of the solder balls 2-0-1, solder balls 2-0-2, solder balls 2-0-3, and solder balls 2-0-4 corresponds to a conductive via 2-1. The bump bonding pair 0-12 corresponding to the quantum integration chip 1 included in the co-packaged optoelectronic chip 100 is electrically connected to the conductive via 2-1. A first photonic integration die 3 is embedded in the co-packaged optoelectronic adapter board 2, and a via structure 2-4 is provided in the first photonic integration die 3. The via structure 2-4 allows an external optical fiber 8 to penetrate. The optical signal of the external optical fiber 8 is introduced into the quantum integration chip 1 through a coupler 2-2, an optoelectronic conversion module 2-3, and a bump bonding pair 0-13. The quantum integration chip 1 includes structures such as a quantum adapter board 1-1, a tunable bus die 1-2, a qubit die 1-3, a superconducting memory die 1-4, an electronic integration die 1-5, and a first CMOS die 1-6. The positional relationship, connection relationship, and respective functions of the various components of the quantum integration chip 1, the co-packaged optoelectronic adapter board 2, and the second CMOS die 4 included in the co-packaged optoelectronic chip 100 are as described above, and will not be elaborated here. It should be noted that the signals processed by the quantum integration chip 1 can come from the second photonic integration die 6 in the co-packaged optoelectronic adapter board 2, or from the external optical fiber, or from the external coaxial cable, thus improving the design flexibility and hardware reusability. The specific structure of the co-packaged optoelectronic chip 100 can adopt, for example, Figure 4 the structure shown.

[0074] Based on the above embodiments, further, a first thermal interface material is provided at the bottom of the co-packaged optoelectronic substrate. The first thermal interface material is used to reduce the contact thermal resistance and improve the device heat dissipation performance. The first thermal interface material can adopt various thermal interface materials (Thermal Interface Material, TIM) compatible with low-temperature scenarios, etc., and is set according to actual needs, which is not limited in the embodiments of the present invention.

[0075] The thermal interface material can effectively fill the gaps between different solid contact surfaces, exclude air, and provide a good heat conduction path.

[0076] For example, as Figure 9 shown, a first thermal interface material 801-8 is provided at the bottom of the co-packaged optoelectronic substrate 801-5.

[0077] Based on the above embodiments, further, a second thermal interface material is provided on the top of the quantum integration chip 1. Among them, the second thermal interface material can adopt various thermal interface materials compatible with low-temperature scenarios. The thermal interface material is used to fill the micro-gaps and uneven holes on the surface generated when the top of the quantum integration chip contacts the cold plate of the dilution refrigerator, reduce the contact thermal resistance, and improve the device heat dissipation performance. The thermal interface material is selected according to actual needs, which is not limited in the embodiments of the present invention.

[0078] For example, as Figure 9 shown, a second thermal interface material 801-9 is provided on the top of the quantum integration chip 801-1.

[0079] Figure 8 is a schematic structural diagram of a computer provided by the eighth embodiment of the present invention. As Figure 8 shown, the dilution refrigerator includes a first cold plate 802 and a second cold plate 803. The processor 801 is disposed between the first cold plate 802 and the second cold plate 803 and is in contact with the first cold plate 802 and the second cold plate 803 respectively. The processor 801 is cooled by heat conduction with the first cold plate 802 and the second cold plate 803.

[0080] Figure 9 is a schematic cross-sectional structural diagram of a computer provided by the ninth embodiment of the present invention. As Figure 9 shown, on the basis of the above embodiments, further, a first heat dissipation layer 804 is provided between the processor 801 and the first cold plate 802, and / or a second heat dissipation layer 805 is provided between the processor 801 and the second cold plate 803. The first heat dissipation layer 804 and the second heat dissipation layer 805 can adopt heat dissipation materials with relatively high thermal conductivity such as diamond heat sinks.

[0081] Diamond has excellent insulation and ultra-high thermal conductivity. The diamond heat sink is an ideal heat dissipation material. After the processor 801 contacts the diamond heat sink through the thermal interface material, relying on the high thermal conductivity of diamond, the heat generated by the processor 801 will quickly spread laterally in the first heat dissipation layer 804 and / or the second heat dissipation layer 805 and is dissipated through the first cold plate 802 and the second cold plate 803, thereby significantly improving the heat dissipation capacity of the processor. It can be understood that according to the different materials selected for the first heat dissipation layer 804 and the second heat dissipation layer 805, a thermal interface material can be added between the first heat dissipation layer 804 and the first cold plate 802, and between the second heat dissipation layer 805 and the second cold plate 803 as required. Its functions, positional relationships, connection relationships, etc. are similar to those of the first thermal interface material 801-8 and the second thermal interface material 801-9, and will not be elaborated here.

[0082] As Figure 9 shown, the computer provided by the embodiment of the present invention includes a processor 801, a first cold plate 802, a second cold plate 803, a first heat dissipation layer 804, and a second heat dissipation layer 805, wherein:

[0083] The first heat dissipation layer 804 is disposed between the lower surface of the processor 801 and the first cold plate 802, and the second heat dissipation layer 805 is disposed between the upper surface of the processor 801 and the second cold plate 803, that is, between the top of the multiple quantum integration chips 801-1 and the second cold plate 803. The first heat dissipation layer 804 and the second heat dissipation layer 805 can adopt diamond heat sinks to improve the heat dissipation efficiency of the processor 801. The processor 801 performs electrical communication with the outside through the solder joint patch cord 806, and the processor 801 performs optical communication with the outside through the optical fiber 807.

[0084] The processor 801 includes multiple quantum integration chips 801-1, an optical and electrical co-packaged adapter board 801-2, a first photon integration die 801-3, a second CMOS die 801-4, an optical and electrical co-packaged substrate 801-5, a second photon integration die 801-6, an optical waveguide 801-7, a first thermal interface material 801-8, a second thermal interface material 801-9 and other component structures. The positional relationship, connection relationship and functions of the various component structures included in the processor 801 are as described above, and will not be elaborated here.

[0085] It should be noted that in this application, corresponding conductive vias or multi-layer via structures need to be provided at all places where chips are stacked to ensure information interaction between the bottom chip and the top chip; all inter-chip interconnections are allowed to use solder bumps, stud bumps, etc. The bump material has superconducting characteristics, and the formed bumps are superconducting bumps; the conductive vias can be made by through-silicon via technology (TSV), through-glass via technology (TGV), through-molding via technology (TMV), etc. The inside of the via contains a conductive layer with superconducting characteristics. All planar optical waveguides can adopt buried waveguides, slab waveguides, ridge waveguides, circular waveguides, etc., and are selected according to actual needs. The coupler can adopt a grating coupler, an end-face coupler, etc., and is selected according to actual needs.

[0086] The processor provided by the embodiment of the present invention has the following advantages:

[0087] (1) By replacing part of the long-distance electrical link with an optical link, it avoids the adverse effects of hardware bottlenecks such as electrical interconnection transmission delay, parasitic effects, and bandwidth capabilities on the development of large-scale and scalable quantum processors, and gives full play to the technical advantages of optical interconnection such as high speed, high bandwidth, low energy consumption, and wavelength division multiplexing.

[0088] (2) In this application, by converting the photon integration die and the tunable bus die into a bridging structure, a two-level interconnection architecture of global PIC bridging and local PIC bridging is proposed, which effectively alleviates the extreme pursuit of the area of a single adapter board, and adopts a globally symmetric grid design, significantly improving the design flexibility and scalability.

[0089] (3) The stacking method of the qubit die and the superconducting memory die helps to achieve in-memory computing, reducing the distance required for information access and storage in the superconducting memory die, and reducing latency and signal distortion.

[0090] (4) The designed multi-die integrated packaging architecture takes into account the comprehensive requirements of the quantum processor in terms of cost control, decoherence suppression, electrical conductivity, heat dissipation efficiency, etc.

[0091] (5) By screening known-good-chiplets (KGCs), the high yield of the die used in the system integration stage can be guaranteed, thus solving the problem that the overall yield of the quantum processor rapidly decreases as the integration scale increases.

[0092] (6) The optical-electrical co-packaged substrate allows multiple optical-electrical co-packaged interposer boards to be mounted; different types and functions of qubit dies can be mounted between different quantum interposer boards, greatly improving the large-scale scalability of the system while ensuring the yield, and at the same time helping to provide a convenient test platform for the horizontal comparison of the performance of different types of qubits.

[0093] In the description of this specification, the description with reference to terms such as "one embodiment", "a specific embodiment", "some embodiments", "for example", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0094] The specific embodiments described above further elaborate on the purpose, technical solutions, and beneficial effects of the present invention. It should be understood that the above description is only specific embodiments of the present invention and is not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

Claims

1. A processor, characterized in that, Comprising a plurality of quantum integrated chips and an optical-electrical co-packaged adapter board, wherein: The plurality of quantum integrated chips are disposed on the optical-electrical co-packaged adapter board, and a first photonic integrated die is integrated in the optical-electrical co-packaged adapter board. The plurality of quantum integrated chips communicate with each other through the first photonic integrated die integrated on the optical-electrical co-packaged adapter board.

2. The processor according to claim 1, wherein The quantum integrated chip includes a quantum adapter board, a tunable bus die, a qubit die, and a superconducting memory die, wherein: There are a plurality of qubit dies. The qubit dies and corresponding electronic integrated dies are disposed on the quantum adapter board, and the superconducting memory die corresponding to the qubit die is disposed on the qubit die. The tunable bus die is integrated in the quantum adapter board. Each qubit die is electrically connected through the tunable bus die, and the qubit die is electrically connected to the corresponding superconducting memory die and electronic integrated die.

3. The processor according to claim 2, wherein, The quantum integrated chip further includes a first complementary metal-oxide-semiconductor die, which is disposed on the electronic integrated die and electrically connected to the electronic integrated die.

4. The processor according to claim 2, wherein A second complementary metal-oxide-semiconductor die is further included. The second complementary metal-oxide-semiconductor die is disposed on the electronic integrated dies of adjacent quantum integrated chips and is electrically connected to the electronic integrated dies of adjacent quantum integrated chips respectively.

5. The processor according to claim 1, wherein The plurality of quantum integrated chips and the first photonic integrated die integrated in the optical-electrical co-packaged adapter board are arranged alternately. If the plurality of quantum integrated chips and the first photonic integrated die integrated in the optical-electrical co-packaged adapter board are linearly arranged, then in the arrangement direction, the quantum integrated chip is adjacent to at least one of the first photonic integrated dies, and each first photonic integrated die is adjacent to at least two quantum integrated chips. If the plurality of quantum integrated chips and the first photonic integrated die integrated in the optical-electrical co-packaged adapter board are arranged in a two-dimensional array, then the quantum integrated chip is adjacent to at least 2 of the first photonic integrated dies, and each first photonic integrated die is adjacent to at least 2 quantum integrated chips.

6. The processor according to claim 1, wherein An optical-electrical co-packaged substrate is further included. A second photonic integrated die is integrated in the optical-electrical co-packaged substrate, and the second photonic integrated dies are connected to each other through optical waveguides. A plurality of optical-electrical co-packaged chips are disposed on the optical-electrical co-packaged substrate. The plurality of optical-electrical co-packaged chips communicate with each other through the second photonic integrated die integrated in the optical-electrical co-packaged substrate, and each optical-electrical co-packaged chip includes a plurality of quantum integrated chips.

7. The processor according to claim 6, characterized in that, A first thermal interface material is disposed at the bottom of the optical-electrical co-packaged substrate.

8. The processor according to any one of claims 1 to 7, characterized in that, A second thermal interface material is disposed on the top of the quantum integrated chip.

9. A computer, characterized in that, Comprising the processor according to any one of claims 1 to 8 and a dilution refrigerator. The dilution refrigerator includes a first cold plate and a second cold plate. The processor is disposed between the first cold plate and the second cold plate and is in contact with the first cold plate and the second cold plate respectively.

10. The computer according to claim 9, characterized in that, A first heat dissipation layer is disposed between the processor and the first cold plate, and / or a second heat dissipation layer is disposed between the processor and the second cold plate.

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