Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes: an insulating layer; the first bonding pad is arranged on the insulating layer; the protection layer is arranged on the insulation layer and comprises a first opening area vertically overlapped with the first bonding pad, the width of the first opening area in the horizontal direction is smaller than that of the first bonding pad in the horizontal direction, and the protection layer is arranged on the insulation layer and comprises a second opening area vertically overlapped with the first bonding pad in the horizontal direction. The inner wall of the first opening area forming the protective layer is provided with a first inner wall and a second inner wall, and the first inner wall and the second inner wall are provided with steps in the horizontal direction.

Description

Technical Field

[0001] The embodiments relate to a circuit board and a semiconductor package including the circuit board. Background Art

[0002] Generally, a printed circuit board (PCB) is a laminated structure in which insulating layers and conductor layers are alternately laminated, and the conductor layers can be patterned to form circuit patterns.

[0003] The printed circuit board as described above is provided with a solder resist (SR), which protects the circuits formed on the outermost side of the laminated structure, prevents oxidation of the conductor layers, and also serves as an insulator when electrically connected to chips mounted on the printed circuit board or other substrates.

[0004] Typical solder resists form opening areas (SRO, Solder Resist Opening), which become electrical connection paths by bonding connectors such as solder or bumps, and the opening areas of the solder resist require a larger number of opening areas because as the printed circuit board becomes high-performance and densified, the I / O (Input / Output) performance improves, thus requiring a small bump pitch for the opening areas. At this time, the bump pitch of the opening areas of the solder resist means the center distance between adjacent opening areas.

[0005] Meanwhile, the opening areas (SRO) of the solder resist include SMD (Solder Mask Defined type) and NSMD (Non-Solder Mask Defined type).

[0006] The SMD type is characterized in that the width of the opening area (SRO) is smaller than the width of the pad exposed through the opening area (SRO). Therefore, at least a part of the upper surface of the pad in the SMD type is covered by the solder resist.

[0007] In addition, the NSMD type is characterized in that the width of the opening area (SRO) is larger than the width of the pad exposed through the opening area (SRO). Therefore, in the NSMD type, the solder resist is arranged to be spaced apart from the pad by a predetermined distance, and thus has a structure in which both the upper surface and the side surface of the pad are exposed.

[0008] However, in the case of the SMD type, after the semiconductor package is combined with the main board, during the solder ball joint reliability test for the bonding strength of the solder balls, there is a problem that the solder balls are separated from the pads exposed through the opening areas (SRO).

[0009] In addition, the column bumps can be disposed in the opening regions of the solder mask of the SMD type. However, in a conventional semiconductor package, when an impact occurs from the outside, the impact may be transmitted to the column bumps as a whole, and thus there is a problem that cracks occur in the column bumps. SUMMARY OF THE INVENTION

[0010] TECHNICAL PROBLEM

[0011] Embodiments provide a circuit board having a novel structure and a semiconductor package including the circuit board.

[0012] In addition, embodiments provide a circuit board having improved mechanical reliability and physical reliability and a semiconductor package including the circuit board.

[0013] In addition, embodiments provide a circuit board including a protective layer having an opening region with a novel design and a semiconductor package including the circuit board.

[0014] The technical problems to be solved by the proposed embodiments are not limited to the above technical problems, and other technical problems not mentioned can be clearly understood by those skilled in the art to which the proposed embodiments belong from the following description.

[0015] TECHNICAL SOLUTION

[0016] A circuit board according to an embodiment includes: an insulating layer; a first pad disposed on the insulating layer; and a protective layer disposed on the insulating layer and including a first opening region vertically overlapping the first pad, wherein a width of the first opening region in a horizontal direction is smaller than a width of the first pad in the horizontal direction, inner walls of the first opening region forming the protective layer have a first inner wall and a second inner wall, and the first inner wall and the second inner wall have a step in a horizontal direction.

[0017] In addition, the first opening region of the protective layer includes a first portion and a second portion, the first portion forms the first inner wall, and the second portion protrudes from the first portion toward a side surface of the first pad and forms the second inner wall.

[0018] In addition, the second portion of the first opening region includes a plurality of sub-portions protruding in a direction away from the first portion at positions spaced apart from each other.

[0019] In addition, a planar shape of the second portion has a circular or elliptical shape.

[0020] In addition, a planar shape of the first portion has at least one of a circular, elliptical, square, triangular, and polygonal shape.

[0021] In addition, the planar shape of the first part is different from the planar shape of the second part.

[0022] In addition, the first inner wall and the second inner wall do not vertically overlap the edge of the upper surface of the first pad.

[0023] In addition, the circuit board further includes a first bump, the first bump is disposed on the first pad that vertically overlaps with the first opening region, and the lower surface of the first bump has a planar shape corresponding to the planar shape of the first opening region.

[0024] In addition, the width of the region having the maximum width in the first opening region in the horizontal direction satisfies the range of 70% to 90% of the width of the first pad in the horizontal direction.

[0025] In addition, the width of the first part of the first opening region in the horizontal direction satisfies the range of 30% to 70% of the width of the first pad in the horizontal direction, and the width of the second part of the first opening region in the horizontal direction satisfies the range of 5% to 30% of the width of the first pad in the horizontal direction.

[0026] In addition, the circuit board further includes a second pad spaced apart from the first pad in the horizontal direction, the protective layer further includes a second opening region vertically overlapping with the second pad, and the planar shape of the second opening region is different from the planar shape of the first opening region.

[0027] In addition, the width of the second pad in the horizontal direction is smaller than the width of the first pad in the horizontal direction, and the width of the second opening region in the horizontal direction is smaller than the width of the second pad in the horizontal direction.

[0028] In addition, the inner wall of the first opening region has a step in the horizontal direction, and the inner wall of the second opening region does not have a step in the horizontal direction.

[0029] Meanwhile, the circuit board according to the embodiment includes: an insulating layer; a first pad disposed on the insulating layer; a second pad disposed on the insulating layer and spaced apart from the first pad in the horizontal direction; and a protective layer disposed on the insulating layer and including a first opening region vertically overlapping with the first pad and a second opening region vertically overlapping with the second pad, and the planar shape of the second opening region is different from the planar shape of the first opening region.

[0030] In addition, the width of the second pad in the horizontal direction is smaller than the width of the first pad in the horizontal direction, and the width of the second opening region in the horizontal direction is smaller than the width of the second pad in the horizontal direction.

[0031] In addition, the inner wall of the first opening region has a step in the horizontal direction, and the inner wall of the second opening region does not have a step in the horizontal direction.

[0032] Meanwhile, the semiconductor package according to the embodiment includes: an insulating layer; a first circuit layer disposed on the insulating layer and including a first pad; a protective layer disposed on the first insulating layer and including a first opening region vertically overlapping the first pad; a first bump disposed on the first pad vertically overlapping the first opening region; a first connection portion disposed on the first bump; and a first semiconductor device or a first external substrate coupled to the first connection portion, wherein the width of the first opening region in the horizontal direction is smaller than the width of the first pad in the horizontal direction, the first opening region of the protective layer includes a first inner wall and a second inner wall, and the first inner wall and the second inner wall have a step along the horizontal direction, wherein the second inner wall protrudes further from the first inner wall toward the side surface of the first pad.

[0033] Beneficial effects

[0034] The circuit board according to the embodiment includes: a first insulating layer; a first circuit layer disposed on the first insulating layer and including a first pad; a first protective layer disposed on the first insulating layer and including a first opening region vertically overlapping the first pad, wherein the width of the first opening region in the horizontal direction is smaller than the width of the first pad in the horizontal direction, the first opening region of the first protective layer includes a first portion vertically overlapping the upper surface of the first pad, and a second portion connected to the first portion and protruding from the first portion in the direction toward the side surface of the first pad.

[0035] In addition, the second portion of the first opening region includes a plurality of sub-portions protruding in a direction away from the first portion at positions spaced apart from each other.

[0036] In addition, the first opening region of the first protective layer includes a first inner wall corresponding to the first portion and a second inner wall corresponding to the second portion, and the first inner wall and the second inner wall have a step in the horizontal direction.

[0037] In addition, the planar shape of the second portion has a circular or elliptical shape.

[0038] In addition, the planar shape of the first portion has at least one of a circular, elliptical, square, triangular, and polygonal shape.

[0039] In addition, the first inner wall and the second inner wall do not vertically overlap the edge of the upper surface of the first pad.

[0040] In addition, the circuit board further includes a first bump disposed on the first pad that vertically overlaps the first opening region, and the lower surface of the first bump has a planar shape corresponding to the planar shape of the first opening region.

[0041] In addition, the width of the region with the maximum width in the first opening region in the horizontal direction satisfies the range of 70% to 90% of the width of the first pad in the horizontal direction.

[0042] In addition, the width of the first part of the first opening region in the horizontal direction satisfies the range of 30% to 70% of the width of the first pad in the horizontal direction, and the width of the second part of the first opening region in the horizontal direction satisfies the range of 5% to 30% of the width of the first pad in the horizontal direction.

[0043] In addition, the circuit board further includes a second pad spaced apart from the first pad in the horizontal direction, and the protective layer further includes a second opening region that vertically overlaps the second pad, and the planar shape of the second opening region is different from the planar shape of the first opening region.

[0044] In addition, the width of the second pad in the horizontal direction is less than the width of the first pad in the horizontal direction, and the width of the second opening region in the horizontal direction is less than the width of the second pad in the horizontal direction.

[0045] In addition, the inner wall of the first opening region has a step in the horizontal direction, and the inner wall of the second opening region does not have a step in the horizontal direction.

[0046] Meanwhile, the circuit board according to the embodiment includes: an insulating layer; a first pad disposed on the insulating layer; a second pad disposed on the insulating layer and spaced apart from the first pad in the horizontal direction; and a protective layer, the protective layer is disposed on the insulating layer and includes a first opening region that vertically overlaps the first pad and a second opening region that vertically overlaps the second pad, and the planar shape of the second opening region is different from the planar shape of the first opening region.

[0047] In addition, the width of the second pad in the horizontal direction is less than the width of the first pad in the horizontal direction, and the width of the second opening region in the horizontal direction is less than the width of the second pad in the horizontal direction.

[0048] In addition, the inner wall of the first opening region has a step in the horizontal direction, and the inner wall of the second opening region does not have a step in the horizontal direction.

[0049] Meanwhile, the semiconductor package according to the embodiment includes: an insulating layer; a first circuit layer disposed on the insulating layer and including a first pad; a protective layer disposed on the first insulating layer and including a first opening region vertically overlapping the first pad; a first bump disposed on the first pad vertically overlapping the first opening region; a first connection portion disposed on the first bump; and a first semiconductor device or a first external substrate coupled to the first connection portion, wherein a width of the first opening region in a horizontal direction is smaller than a width of the first pad in the horizontal direction, the first opening region of the first protective layer includes a first portion vertically overlapping an upper surface of the first pad, and a second portion connected to the first portion and protruding from the first portion in a direction of a side surface facing the first pad, and inner walls of the first portion and the second portion of the first opening region have a step in the horizontal direction.

[0050] In addition, the semiconductor package further includes a second insulating layer disposed under the first insulating layer; a third pad disposed under the second insulating layer; and a second protective layer, the second protective layer including a third opening region disposed under the second insulating layer and vertically overlapping the third pad, wherein a planar shape of the third opening region corresponds to a planar shape of the first opening region.

[0051] In addition, the semiconductor package further includes a second connection portion disposed under the third pad; and a second semiconductor device or a second external substrate disposed under the second connection portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 is a cross-sectional view showing a circuit board according to a first embodiment.

[0053] Figure 2 is a cross-sectional view showing a circuit board according to a second embodiment.

[0054] Figure 3 is a plan view showing a state in which the first bump is removed from the Figure 2 circuit board.

[0055] Figure 4 is a plan view showing a state in which the first bump is disposed in the Figure 2 circuit board.

[0056] Figure 5a and Figure 5b are diagrams for explaining the first opening region of the first protective layer according to the embodiment.

[0057] Figure 6 are diagrams for explaining the second opening region of the first protective layer according to the embodiment.

[0058] Figure 7It is an enlarged view of the first opening area provided on the 1-1 pad according to the embodiment.

[0059] Figure 8 It is an enlarged view of the first opening area provided on the 1-2 pad according to the embodiment.

[0060] Figure 9 It is a modified example of the first opening area according to the embodiment.

[0061] Figure 9 It is a modified example of the first opening area according to the embodiment.

[0062] Figure 10 It is a diagram showing a semiconductor package according to the first embodiment.

[0063] Figure 11 It is a diagram showing a semiconductor package according to the second embodiment.

[0064] Figure 12 It is a diagram showing a semiconductor package according to the third embodiment.

[0065] Figure 13 It is a diagram showing a semiconductor package according to the fourth embodiment. Detailed Description of the Invention

[0066] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0067] However, the spirit and scope of the present invention are not limited to a part of the described embodiments, can be implemented in various other forms, and within the spirit and scope of the present invention, one or more elements of the embodiments can be selectively combined and rearranged.

[0068] In addition, unless otherwise clearly defined and described, the terms (including technical terms and scientific terms) used in the embodiments of the present invention can be interpreted as having the same meaning as that generally understood by those of ordinary skill in the art to which the present invention pertains, and terms such as those defined in a common dictionary can be interpreted as having a meaning consistent with their meaning in the context of the relevant field. Further, the terms used in the embodiments of the present invention are used to describe the embodiments and are not intended to limit the present invention.

[0069] In this specification, the singular form may also include the plural form, unless specifically stated in a phrase, and when described in "at least one (or more) of A (and), B, and C" may include at least one of all combinations combined in A, B, and C. In addition, when describing elements of the embodiments of the present invention, terms such as first, second, A, B, (a), and (b) may be used.

[0070] These terms are only used to distinguish an element from other elements, and these terms do not limit the nature, order or sequence of the element. Additionally, when an element is described as "connected", "coupled" or "coupled to" another element, it may include not only that the element is directly "connected", "coupled" or "coupled to" the other element, but also that the element is "connected", "coupled" or "coupled to" the other element through another element between the element and the other element.

[0071] Additionally, when described as being "on (above)" or "under (below)" each element, "on (above)" or "under (below)" may include not only when two elements are directly connected to each other, but also that one or more other elements are formed or disposed between the two elements. Additionally, when expressed as "on (above)..." or "under (below)...", it may include not only the upper direction based on one element, but also the lower direction.

[0072] Electronic device

[0073] Before describing the embodiments, an electronic device to which the embodiments of the semiconductor package are applied will be briefly described. The electronic device includes a main board (not shown). The main board can be physically and / or electrically connected to various components. For example, the main board can be connected to the semiconductor package of the embodiment. Various semiconductor devices can be mounted on the semiconductor package.

[0074] The semiconductor device can include active devices and / or passive devices. The active device can be a semiconductor chip in the form of an integrated circuit (IC), in which hundreds to millions of devices are integrated into one semiconductor device. The semiconductor device can be a logic chip, a memory chip, etc. The logic chip can be a central processing unit (CPU), a graphics processing unit (GPU), etc. For example, the logic chip can be an application processor (AP) chip including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an ASIC (application-specific IC), etc., or a chipset including a specific combination of those listed so far.

[0075] The memory chip can be a stacked memory such as HBM. The memory chip can also include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), or flash memory.

[0076] On the other hand, the product group of the semiconductor package of the application embodiment can be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package on Package), and SIP (System In Package), but is not limited thereto.

[0077] In addition, the electronic device can be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an Automotive, etc. However, the embodiment is not limited thereto and can be any other electronic device that processes data other than these.

[0078] Figure 1 is a cross-sectional view of a circuit board according to the first embodiment, Figure 2 is a cross-sectional view of a circuit board according to the second embodiment.

[0079] Compare Figure 1 and Figure 2 , the circuit board may include bumps for bonding to semiconductor devices and / or external substrates. At this time, in Figure 1 , the bumps may be provided only on one side of the circuit board.

[0080] According to Figure 1 's first embodiment, the semiconductor devices and / or external substrates on one side of the circuit board can be electrically bonded through bumps, and the semiconductor devices and / or external substrates on the other side of the circuit board can be electrically bonded through a connecting member such as solder without bumps.

[0081] According to Figure 2 's second embodiment, the semiconductor devices and / or external substrates on each of one side and the other side of the circuit board can be electrically bonded through bumps.

[0082] Hereinafter, reference will be made to Figure 2Describe the overall structure of the circuit board according to an embodiment.

[0083] Reference Figure 2 , the circuit board 100 can be coupled to at least one semiconductor device. In addition, the circuit board 100 of the embodiment can be coupled to an external substrate.

[0084] In one embodiment, the external substrate can represent a substrate provided in an electronic device. For example, the external substrate can represent the main board of an electronic device. For example, the main board can represent the motherboard of an electronic device.

[0085] In another embodiment, the external substrate can represent a separate package. For example, when the circuit board is applied to a POP (Package on Package) structure, the external substrate can be a package substrate coupled to a separate semiconductor device. For example, the separate semiconductor device can represent a memory device, and the package substrate can be a memory substrate including the memory device, or an interposer connecting the memory substrate and the circuit board.

[0086] In addition, the semiconductor device mounted on the circuit board 100 can be one, or can be two or more. For example, one processor chip can be mounted on the circuit board 100. For example, at least two processor chips with different functions can be mounted on the circuit board 100. For example, one processor chip and one memory chip can be mounted on the circuit board 100. For example, at least two processor chips with different functions and at least one memory chip can be mounted on the circuit board 100.

[0087] The circuit board 100 can include an insulating layer 110.

[0088] The insulating layer 110 can have a multi-layer stacked structure. For example, as shown in the figure, the insulating layer 110 can have a three-layer structure, but is not limited thereto.

[0089] At this time, the circuit board 100 of the embodiment can be a core board. For example, the circuit board 100 can include a core layer. For example, the insulating layer 110 of the circuit board 100 of the embodiment can include a third insulating layer 113 corresponding to the core layer.

[0090] For example, in the structure of the circuit board 100, a plurality of insulating layers with a symmetrical structure can be stacked on the upper and lower parts of the third insulating layer 113 based on the third insulating layer 113. However, the embodiment is not limited thereto. For example, a plurality of insulating layers with an asymmetrical structure can be provided on the upper and lower parts of the third insulating layer 113 based on the third insulating layer 113.

[0091] In the following, the circuit board 100 of the embodiment is described as a core board. Therefore, the third insulating layer 113 is the core layer. However, the embodiment is not limited thereto. For example, the circuit board 100 of the embodiment may be a coreless board that does not include a core layer. The structural feature of the circuit board 100 of the embodiment lies in the outermost circuit layer of the circuit board 100 and the bumps provided on the circuit layer. In the following, the structure of the outermost circuit layer and the bumps of the circuit board 100 of the embodiment will be described.

[0092] Therefore, the structures of the outermost circuit layers 120 and 130 and the bumps 180 and 190 of the circuit board 100 described below can be applied to a core board, and differently, can be applied to a coreless board.

[0093] In addition, one of the outermost circuit layers 120 and 130 may have a structure embedded in the insulating layer 110. For example, the circuit board of the embodiment may have an ETS (Embedded Trace Substrate) structure. In addition, the bumps 180 and 190 of the embodiment may be provided on the outermost circuit layers 120 and 130 having an ETS structure.

[0094] The insulating layer 110 may include a first insulating layer 111 as the first outermost insulating layer. For example, the first insulating layer 111 may refer to the insulating layer provided on the uppermost side among a plurality of insulating layers. In addition, the insulating layer 110 may include a second insulating layer 112 as the second outermost insulating layer. For example, the second insulating layer 112 may refer to the insulating layer provided on the lowermost side among a plurality of insulating layers.

[0095] In addition, the insulating layer 110 may include a third insulating layer 113 provided between the first insulating layer 111 and the second insulating layer 112. The third insulating layer 113 may be an inner insulating layer.

[0096] The third insulating layer 113 may refer to the inner insulating layer provided in the inner layer among a plurality of insulating layers of the circuit board 100.

[0097] At this time, the third insulating layer 113 is shown in the figure as having a single-layer structure, but is not limited thereto. For example, the third insulating layer 113 may have a multi-layer structure. For example, the circuit board 100 may have a layer structure of four or more layers. At this time, the third insulating layer 113 corresponding to the inner insulating layer of the circuit board 100 may have a multi-layer structure based on the total number of layers of the circuit board 100. When the third insulating layer 113 has a multi-layer structure, the multi-layers of the third insulating layer 113 may include different insulating materials, but are not limited thereto.

[0098] The first insulating layer 111 may be provided on the third insulating layer 113. For example, the first insulating layer 111 may be provided on the upper surface of the third insulating layer 113.

[0099] The first insulating layer 111 may provide a mounting area for mounting a chip or a bonding area for bonding to an external substrate.

[0100] The second insulating layer 112 may be disposed on the lower surface of the third insulating layer 113. The second insulating layer 112 may refer to the second outermost insulating layer in the insulating layer 110 of the circuit board 100. For example, the second insulating layer 112 may refer to the insulating layer disposed on the lowermost side in the insulating layer 110 of the circuit board 100.

[0101] The first insulating layer 111 and the second insulating layer 112 may be rigid or flexible. For example, the first insulating layer 111 and the second insulating layer 112 may include glass or plastic. Specifically, the first insulating layer 111 and the second insulating layer 112 may include chemically strengthened / semi-strengthened glass, such as soda lime glass or aluminosilicate glass. Alternatively, the first insulating layer 111 and the second insulating layer 112 may include strengthened or flexible plastic, such as Polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). Alternatively, the first insulating layer 111 and the second insulating layer 112 may include sapphire.

[0102] In addition, the first insulating layer 111 and the second insulating layer 112 may include an optically isotropic film. For example, the first insulating layer 111 and the second insulating layer 112 may include Cyclic Olefin Copolymer (COC), Cyclic Olefin Polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA).

[0103] In addition, the first insulating layer 111 and the second insulating layer 112 may be formed of an insulating material including an inorganic filler and an insulating resin. For example, the first insulating layer 111 and the second insulating layer 112 may include a structure in which an inorganic filler such as silica or alumina is dispersed in a thermosetting resin such as epoxy resin or a thermoplastic resin such as polyimide. For example, the first insulating layer 111 and the second insulating layer 112 may include Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), Photo Imageable Dielectric resin (PID), BT, etc.

[0104] In addition, the first insulating layer 111 and the second insulating layer 112 can be bent while having a partially curved surface. That is, the first insulating layer 111 and the second insulating layer 112 can be bent while having a partially flat surface and a partially curved surface. Specifically, the first insulating layer 111 and the second insulating layer 112 can be bent while having a curved surface at the end, or can be bent or folded while having a surface including a random curvature.

[0105] Each of the first insulating layer 111 and the second insulating layer 112 can have a thickness in the range of 10 μm to 60 μm. Preferably, each of the first insulating layer 111 and the second insulating layer 112 can have a thickness in the range of 12 μm to 50 μm. More preferably, each of the first insulating layer 111 and the second insulating layer 112 can have a thickness in the range of 15 μm to 40 μm.

[0106] If the thickness of the first insulating layer 111 or the second insulating layer 112 is less than 10 μm, it may not be possible to stably protect the circuit layer included in the circuit board 100.

[0107] In addition, if the thickness of the first insulating layer 111 or the second insulating layer 112 exceeds 60 μm, the thickness of the circuit board 100 may increase, and thus the thickness of the semiconductor package may increase. In addition, if the thickness of the first insulating layer 111 or the second insulating layer 112 exceeds 60 μm, the thickness of the circuit layer and the thickness of the through electrode may increase accordingly. In addition, if the thickness of the circuit layer and the thickness of the through electrode increase, it may be difficult to achieve miniaturization, which may reduce the circuit integration degree, and the signal transmission distance may increase, which may increase the signal transmission loss.

[0108] The circuit board 100 of the embodiment includes a circuit layer provided on the insulating layer 110.

[0109] For example, the circuit board 100 can include a first circuit layer 120 provided on the upper surface of the first insulating layer 111.

[0110] For example, the circuit board 100 can include a second circuit layer 130 provided on the lower surface of the second insulating layer 112.

[0111] In addition, the circuit board 100 can include a third circuit layer 140 provided between the lower surface of the first insulating layer 111 and the upper surface of the third insulating layer 113.

[0112] For example, the circuit board 100 can include a fourth circuit layer 150 provided between the upper surface of the second insulating layer 112 and the lower surface of the third insulating layer 113.

[0113] The first circuit layer 120, the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 can be manufactured using conventional manufacturing processes for printed circuit boards, such as the Additive Process, the Subtractive Process, the MSAP (Modified Semi Additive process), and the SAP (Semi Additive Process). The detailed description thereof will be omitted herein.

[0114] The first circuit layer 120 can refer to the circuit layer provided on the first outermost layer of the circuit board 100. In addition, the second circuit layer 130 can represent the circuit layer provided on the second outermost layer of the circuit board 100.

[0115] The first circuit layer 120 can have a structure protruding above the upper surface of the first insulating layer 111. Additionally, the second circuit layer 130 can have a structure protruding below the lower surface of the second insulating layer 112. However, the embodiments are not limited thereto. For example, when the circuit board 100 of the embodiment has an ETS structure, either the first circuit layer 120 or the second circuit layer 130 can have a structure embedded within the surface of the insulating layer.

[0116] The first circuit layer 120 can be divided into multiple circuit patterns according to functions.

[0117] For example, the first circuit layer 120 can include multiple pads.

[0118] For example, the first circuit layer 120 can include a first pad 121 and a second pad 122. Additionally, the first circuit layer 120 can include a trace 121-3. The trace 121-3 may not be an essential component.

[0119] For example, in one embodiment, the circuit layer provided on the uppermost side of the circuit board can include a trace 121-3, and one of the first pad 121 and the second pad 122 can be electrically connected to the other of the first pad 121 and the second pad 122 through the trace 121-3.

[0120] In another embodiment, the circuit layer provided on the uppermost side of the circuit board may not have a trace 121-3. In this case, the first pad 121 and the second pad 122 may not be directly connected to each other on the first insulating layer 111. For example, the first pad 121 and the second pad 122 can be connected to a first via electrode 161 and can be electrically connected to each other through the via electrode.

[0121] The first pad 121 can be provided in a plurality of numbers. Preferably, the first pad 121 can be provided in a plurality of numbers at physically spaced-apart positions.

[0122] The second pad 122 may be provided in a plurality of numbers. Preferably, the second pads 122 may be provided in a plurality of numbers at positions physically spaced apart from each other.

[0123] In one embodiment, the first pad 121 may be used as a pad electrically coupled to an external substrate (e.g., an interposer or other packaging substrate) on the circuit board 100. In another embodiment, the first pad 121 may be used as a pad electrically coupled to a semiconductor device.

[0124] The second pad 122 may be used as a pad electrically coupled to a semiconductor device.

[0125] In addition, the first circuit layer 120 may include traces connected to at least one of the first pad 121 and the second pad 122.

[0126] The first pad 121 and the second pad 122 may have different widths. For example, the planar areas of the first pad 121 and the second pad 122 may be different from each other. Here, the planar area may represent the area of the upper surface of each pad.

[0127] In one embodiment, each of the first pad 121 and the second pad 122 may be a pad electrically coupled to a semiconductor device. At this time, the width of the terminals provided in the semiconductor device coupled to the first pad 121 and / or the interval between a plurality of terminals may be different from the width of the terminals provided in the semiconductor device coupled to the second pad 122 and / or the interval between a plurality of terminals. Preferably, in this case, the width of the terminals provided in the semiconductor device coupled to the first pad 121 and / or the interval between a plurality of terminals may be greater than the width of the terminals provided in the semiconductor device coupled to the second pad 122 and / or the interval between a plurality of terminals.

[0128] In another embodiment, the first pad 121 may be a pad electrically coupled to an external substrate, and the second pad 122 may be a pad electrically coupled to a semiconductor device. At this time, the width of the external pads provided in the external substrate coupled to the first pad 121 and / or the interval between a plurality of external pads may be different from the width of the terminals provided in the semiconductor device coupled to the second pad 122 and / or the interval between a plurality of terminals. Preferably, the width of the external pads provided in the external substrate coupled to the first pad 121 and / or the interval between a plurality of external pads may be greater than the width of the terminals provided in the semiconductor device coupled to the second pad 122 and / or the interval between a plurality of terminals.

[0129] Accordingly, the planar area of the first pad 121 may be larger than the planar area of the second pad 122. For example, the planar area of the first pad 121 may be 1.2 times or more the planar area of the second pad 122. For example, the planar area of the first pad 121 may be 1.5 times or more the planar area of the second pad 122. For example, the planar area of the first pad 121 may be 2 times or more the planar area of the second pad 122.

[0130] Specifically, the planar area of the first pad 121 may range from 1.2 to 5 times the planar area of the second pad 122. Preferably, the planar area of the first pad 121 may range from 1.5 to 4 times the planar area of the second pad 122. More preferably, the planar area of the first pad 121 may range from 2 to 3.5 times the planar area of the second pad 122.

[0131] If the planar area of the first pad 121 is less than 1.2 times the planar area of the second pad 122, the semiconductor device or the external substrate may not be stably bonded to the first pad 121. Additionally, if the planar area of the first pad 121 is less than 1.2 times the planar area of the second pad 122, the heat dissipation performance of the circuit board and the semiconductor package improved in proportion to the planar area of the first pad 121 may deteriorate. For example, if the planar area of the first pad 121 is less than 1.2 times the planar area of the second pad 122, the heat dissipation characteristics of the semiconductor device or the external substrate mounted on the circuit board 100 may deteriorate, and thus the operating speed or the operating reliability of the semiconductor device may deteriorate.

[0132] On the other hand, if the planar area of the first pad 121 exceeds five times the planar area of the second pad 122, the time required to form the first pad 121 may increase, and thus the product yield of the circuit board may decrease. Additionally, if the planar area of the first pad 121 exceeds five times the planar area of the second pad 122, the flatness of the first pad 121 may deteriorate. For example, if the planar area of the first pad 121 exceeds five times the planar area of the second pad 122, the height difference between regions on the upper surface of the first pad 121 may increase. Further, the flatness of the first bump 180 disposed on the first pad 121 may deteriorate. Additionally, if the flatness of the first pad 121 or the first bump 180 deteriorates or the height difference between regions increases, a process for adjusting the flatness of the first pad 121 is required, and the manufacturing process may become correspondingly complex. Additionally, if the planar area of the first pad 121 exceeds five times the planar area of the second pad 122, a grinding process for adjusting the flatness of the first bump 180 disposed on the first pad 121 must be performed, or the time required to perform the grinding process may increase. Additionally, if the planar area of the first pad 121 exceeds five times the planar area of the second pad 122, the first pad 121 may reduce the circuit integration density, and thus the volumes of the circuit board and the semiconductor package may increase.

[0133] Meanwhile, the planar area can also be expressed as the width in the horizontal direction. For example, the width of the first pad 121 in the horizontal direction can be greater than the width of the second pad 122 in the horizontal direction. At this time, the first pad 121 and the second pad 122 can have a circular shape, and the width in the horizontal direction can represent the diameter of each of the circular-shaped first pad 121 and second pad 122. At this time, the first pad 121 and the second pad 122 can have an oval shape, and the width in the horizontal direction can represent the diameter of each of the oval-shaped first pad 121 and second pad 122 in the major axis direction or the minor axis direction. Additionally, the first pad 122 and the second pad 122 can have a square shape, and the width in the horizontal direction can represent any one of the horizontal distance in the width direction, the horizontal distance in the length direction, and the horizontal distance in the diagonal direction of each of the square-shaped first pad 121 and second pad 122.

[0134] For example, the second circuit layer 130 can include a third pad 131 and a fourth pad 132. At this time, the drawings show that the second circuit layer 130 includes only the third pad 131 and the fourth pad 132, but it is not limited thereto.

[0135] The third pad 131 can be provided in a plurality of numbers. Preferably, the third pad 131 can be provided in a plurality of numbers at physically spaced-apart positions.

[0136] The fourth pad 132 may be provided in a plurality of numbers. Preferably, the fourth pads 132 may be provided in a plurality of numbers at positions physically spaced apart from each other.

[0137] Meanwhile, the third pad 131 of the second circuit layer 130 may be a pad electrically coupled to an external substrate or a pad electrically coupled to a semiconductor device. Additionally, the fourth pad 132 may be a pad electrically coupled to a semiconductor device.

[0138] At this time, the third pad 131 may have a structure corresponding to that of the first pad 121, and the fourth pad 132 may have a structure corresponding to that of the second pad 122. Accordingly, a detailed description of the third pad 131 and the fourth pad 132 will be omitted.

[0139] The first circuit layer 120, the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Additionally, the first circuit layer 120, the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 may be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength. Preferably, the first circuit layer 120, the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 may be formed of relatively inexpensive copper (Cu).

[0140] Meanwhile, the first circuit layer 120 and the second circuit layer 130 may have a thickness in the range of 5 μm to 20 μm. For example, the first circuit layer 120 and the second circuit layer 130 may have a thickness in the range of 6 μm to 17 μm. The first circuit layer 120 and the second circuit layer 130 may have a thickness in the range of 7 μm to 13 μm. If the thickness of the first circuit layer 120 and the second circuit layer 130 is less than 5 μm, the resistance may increase. If the thickness of the first circuit layer 120 and the second circuit layer 130 exceeds 20 μm, it may be difficult to miniaturize the circuit, and thus the circuit integration degree may decrease.

[0141] Meanwhile, the circuit board may include a via electrode penetrating at least a part of the region of the insulating layer 110.

[0142] For example, the first via electrode 161 may be provided in the first insulating layer 111. For example, the second via electrode 162 may be provided in the second insulating layer 112. For example, the third via electrode 163 may be provided in the third insulating layer 113.

[0143] The first via electrode 161 can electrically connect the first circuit layer 120 and the third circuit layer 140 in the vertical direction.

[0144] The second via electrode 162 can electrically connect the second circuit layer 130 and the fourth circuit layer 150 in the vertical direction.

[0145] The third via electrode 163 can electrically connect the third circuit layer 140 and the fourth circuit layer 150 in the vertical direction.

[0146] The first via electrodes 161 can be provided in a plurality of numbers and spaced apart from each other in the horizontal direction. At least one of the first via electrodes 161 can vertically overlap with the first pad 121. Additionally, at least another one of the first via electrodes 161 can vertically overlap with the second pad 122.

[0147] At this time, the first via electrode 161 vertically overlapping with the first pad 121 and the first via electrode 161 vertically overlapping with the second pad 122 can have different widths in the horizontal direction. For example, the width of the first via electrode 161 vertically overlapping with the first pad 121 in the horizontal direction can be greater than the width of the first via electrode 161 vertically overlapping with the second pad 122 in the horizontal direction.

[0148] Additionally, the second via electrodes 162 can be provided in a plurality of numbers and spaced apart from each other in the horizontal direction. At least one of the second via electrodes 162 can vertically overlap with the third pad 131. Additionally, at least another one of the second via electrodes 162 can vertically overlap with the fourth pad 132.

[0149] At this time, the second via electrode 162 vertically overlapping with the third pad 131 and the second via electrode 162 vertically overlapping with the fourth pad 132 can have different widths in the horizontal direction. For example, the width of the second via electrode 162 vertically overlapping with the third pad 131 in the horizontal direction can be greater than the width of the second via electrode 162 vertically overlapping with the fourth pad 132 in the horizontal direction.

[0150] Therefore, the embodiment can adjust the width of each via electrode based on the width of each pad in the horizontal direction. Thereby, the embodiment can minimize the difference between the width of the via electrode and the width of the pad, and can minimize the signal transmission loss that may occur as the width difference increases. Thereby, the embodiment can further improve the electrical characteristics of the circuit board and the semiconductor package including the circuit board.

[0151] The first through electrode 161, the second through electrode 162, and the third through electrode 163 can be formed by filling the interior of vias penetrating each insulating layer with a conductive material. The vias can be formed by any one of mechanical, laser, and chemical processing methods. The vias can be formed by mechanical processing methods such as milling, drill, and routing. Additionally, the vias can be formed using a UV or CO2 laser method. Additionally, the first via can be formed using a chemical processing method that uses chemical reagents including aminosilane, ketone, etc.

[0152] When forming the vias, the interior of the vias can be filled with any one of metal materials selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), thereby forming the first through electrode 161, the second through electrode 162, and the third through electrode 163. At this time, the filling of the conductive material can utilize any one or a combination of electroless plating, electroplating, screen printing, sputtering, evaporation, inkjet, and dispensing.

[0153] The circuit board 100 of the embodiment includes a bump portion provided on a pad.

[0154] Specifically, the circuit board 100 of the embodiment can include a first bump 180 provided on the first circuit layer 120. The first bump 180 can be provided on the first pad 121 of the first circuit layer 120. The first bump 180 can be a column bump. The first bump 180 can be provided to improve the electrical coupling with a semiconductor device and / or an external substrate.

[0155] That is, as the width and pitch of the terminals of the semiconductor device to be bonded to the circuit board are miniaturized, when the semiconductor device is mounted using a conductive adhesive such as solder, the conductive adhesive may spread, and thus there may be a problem that multiple conductive adhesives are connected to each other. Accordingly, the embodiment can perform thermal compression bonding to reduce the volume of the conductive adhesive. At this time, if the first bump 180 is not provided in the circuit board, it may be difficult to reduce the volume of the conductive adhesive. This may be because the height of the electrode on which the conductive adhesive is provided is lower than the upper surface of the first protective layer 170, and thus the volume of the conductive adhesive increases by the difference between the electrode height and the insulating layer height.

[0156] Therefore, embodiments may have a first bump 180 protruding above the first protective layer 170 to ensure alignment with the terminals of the semiconductor device and to ensure diffusion prevention ability to prevent the intermetallic compound (IMC) formed between the conductive adhesive and the electrode from diffusing into the circuit board.

[0157] Meanwhile, a second bump 190 may be disposed on the lower surface of the second circuit layer 130. For example, the second bump 190 may be disposed on the lower surface of the third pad 131 of the second circuit layer 130. The second bump 190 may have a structure corresponding to that of the first bump 180, and thus, its detailed description will be omitted.

[0158] The first bump 180 and the second bump 190 may each have a certain thickness in the vertical direction. The thickness of each of the first bump 180 and the second bump 190 in the vertical direction may be in the range of 75 μm to 210 μm. For example, the thickness of each of the first bump 180 and the second bump 190 in the vertical direction may be in the range of 80 μm to 200 μm. For example, the thickness of each of the first bump 180 and the second bump 190 in the vertical direction may be in the range of 90 μm to 180 μm.

[0159] If the thicknesses of the first bump 180 and the second bump 190 in the vertical direction are less than 75 μm, the external substrate and / or the semiconductor device may not be stably bonded to the first bump 180 and the second bump 190. Thus, the operating characteristics of the external substrate and / or the semiconductor device may deteriorate. If the vertical thicknesses of the first bump 180 and the second bump 190 are less than 75 μm, the volume of the conductive adhesive such as solder may not be reduced, and thus, physical reliability and / or electrical reliability problems may occur due to the diffusion of the intermetallic compound. Additionally, if the vertical thicknesses of the first bump 180 and the second bump 190 exceed 210 μm, the rigidity of the bumps may deteriorate, and thus, reliability problems such as collapse of the semiconductor device and / or the external substrate may occur when bonding is performed. If the vertical thicknesses of the first bump 180 and the second bump 190 exceed 210 μm, the thickness of the circuit board 100 and the thickness of the semiconductor package may increase.

[0160] The circuit board 100 of the embodiments may include a protective layer.

[0161] Specifically, the first protective layer 170 may be disposed on the first insulating layer 111. The first protective layer 170 may include at least one opening area. Preferably, the first protective layer 170 may include a plurality of opening areas.

[0162] The first protective layer 170 may include a first opening region 171 that vertically overlaps the first pad 121. The first opening region 171 of the first protective layer 170 may expose a part of the upper surface of the first pad 121. For example, the first protective layer 170 may cover at least a part of the upper surface of the first pad 121 and may include the first opening region 171 that partially exposes the upper surface of the first pad 121. The first opening region 171 of the first protective layer 170 may expose the part of the upper surface of the first pad 121 where the first bump 180 is to be provided. Thus, the first opening region 171 of the first protective layer 170 may be filled with the first bump 180.

[0163] The first protective layer 170 may include a second opening region 172 that vertically overlaps the second pad 122. The second opening region 172 of the first protective layer 170 may expose a part of the upper surface of the second pad 122. For example, the second opening region 172 of the first protective layer 170 may cover at least a part of the upper surface of the second pad 122 and may include the second opening region 172 that partially exposes the upper surface of the second pad 122.

[0164] Specifically, each of the first opening region 171 and the second opening region 172 of the first protective layer 170 may be set as SMD (Solder Mask Defined type).

[0165] The planar area of the first opening region 171 of the first protective layer 170 may be different from the planar area of the second opening region 172. Preferably, the planar shape of the first opening region 171 of the first protective layer 170 may be different from the planar shape of the second opening region 172.

[0166] For example, the planar shape of the first opening region 171 of the first protective layer 170 may have a snowflake shape including a plurality of protruding portions spaced apart from each other. Thus, the horizontal distance between the inner wall of the first opening region 171 of the first protective layer 170 and the side surface of the first pad 121 may have different horizontal distances along the edge of the upper surface of the first pad 121. For example, the horizontal distance of the protruding portion of the first opening region 171 of the first protective layer 170 may be less than the horizontal distance of the other portions of the first opening region 171 of the first protective layer 170 except for the protruding portion.

[0167] The planar shape of the second opening region 172 of the first protective layer 170 may be different from the planar shape of the first opening region 171 of the first protective layer 170. For example, the planar shape of the second opening region 172 of the first protective layer 170 may not have the protruding portion in the planar shape of the first opening region 171. For example, the planar shape of the second opening region 172 may be any one of a square shape, a circular shape, an oval shape, and a polygonal shape.

[0168] Meanwhile, the second protective layer 175 may be disposed under the second insulating layer 112. The second protective layer 175 may include a third opening region 176 and a fourth opening region 177. The third opening region 176 of the second protective layer 175 may have a planar shape corresponding to the first opening region 171 of the first protective layer 170. Additionally, the fourth opening region 177 of the second protective layer 175 may have a planar shape corresponding to the second opening region 172 of the first protective layer 170.

[0169] Meanwhile, although the second protective layer 175 is described as including the third opening region 176 and the fourth opening region 177, the embodiments are not limited thereto. For example, according to an embodiment, the second protective layer 175 may include only the third opening region 176, may include only the fourth opening region 177, or may include both the third opening region 176 and the fourth opening region 177.

[0170] The first protective layer 170 and the second protective layer 175 may include an insulating material. The first protective layer 170 and the second protective layer 175 may include various materials that can be applied and then cured by heating to protect the surfaces of the insulating layer and the circuit layer.

[0171] The first protective layer 170 and the second protective layer 175 may be solder mask layers containing organic polymer materials. For example, the first protective layer 170 and the second protective layer 175 may contain epoxy acrylate-based resins. Specifically, the first protective layer 170 and the second protective layer 175 may contain resins, curing agents, photoinitiators, pigments, solvents, fillers, additives, acrylic monomers, etc. However, the embodiments are not limited thereto, and the first protective layer 170 and the second protective layer 175 may be any one of a photosensitive solder mask layer, a cover-lay, and a polymer material.

[0172] The thickness of the first protective layer 170 and the thickness of the second protective layer 175 may be 1 μm to 20 μm. The thickness of the first protective layer 170 and the second protective layer 175 may be 1 μm to 15 μm. For example, the thickness of the first protective layer 170 and the second protective layer 175 may be 5 μm to 20 μm. If the thickness of the first protective layer 170 and the second protective layer 175 exceeds 20 μm, the total thickness of the circuit board and the semiconductor package may increase.

[0173] Hereinafter, the opening regions provided in the first protective layer 170 and the second protective layer 175 according to the embodiment will be described.

[0174] However, the third opening region 176 and the fourth opening region 177 provided in the second protective layer 175 may correspond to the first opening region 171 and the second opening region 172 provided in the first protective layer 170. Therefore, the first opening region 171 and the second opening region 172 provided in the first protective layer 170, and the first pad 121 and the second pad 122 of the first circuit layer 120 will be described below.

[0175] Figure 3 is a plan view showing a state in which the first bump is removed from the Figure 2 circuit board, Figure 4 is a plan view showing a state in which the first bump is provided in the Figure 2 circuit board, Figure 5a and Figure 5b is a view for explaining the first opening region of the first protective layer according to the embodiment, Figure 6 is a view for explaining the second opening region of the first protective layer according to the embodiment, Figure 7 is an enlarged view of the first opening region provided on the 1-1 pad according to the embodiment, Figure 8 is an enlarged view of the first opening region provided on the 1-2 pad according to the embodiment, Figure 9 is a modified example of the first opening region according to the embodiment.

[0176] Hereinafter, with reference to Figures 3 to 9 the first opening region 171 and the second opening region 172 provided in the first protective layer 170 of the embodiment will be described in detail.

[0177] With reference to Figure 3 and Figure 4 , the first circuit layer 120 may be provided on the first insulating layer 111.

[0178] The first circuit layer 120 may include a first pad 121 and a second pad 122. At this time, although not shown in the figure, the first circuit layer 120 may include traces connected to at least one of the first pad 121 and the second pad 122.

[0179] In addition, the first protective layer 170 may be provided on the first insulating layer 111. At this time, the first protective layer 170 may include a first opening region 171 and a second opening region 172.

[0180] At this time, the first protective layer 170 may include a first region R1 and a second region R2. The first region R1 may represent the edge region of the first protective layer 170, but is not limited thereto. The first region R1 may represent the region of the first protective layer 170 that vertically overlaps with the first pad 121 of the first circuit layer 120. The second region R2 may represent the central region of the first protective layer 170, but is not limited thereto. The second region R2 may represent the region of the first protective layer 170 that vertically overlaps with the second pad 122 of the first circuit layer 120.

[0181] In addition, a first opening region 171 may be provided in the first region R1 of the first protective layer 170. In addition, a second opening region 172 may be provided in the second region R2 of the first protective layer 170.

[0182] Meanwhile, each of the first pad 121 and the second pad 122 of the first circuit layer 120 may vertically overlap with the first opening region 171 and the second opening region 172 of the first protective layer 170.

[0183] For example, the first pad 121 may vertically overlap with the first opening region 171 of the first protective layer 170. At this time, the upper surface of the first pad 121 may partially vertically overlap with the first opening region 171 of the first protective layer 170. For example, the upper surface of the first pad 121 may include a portion covered by the first protective layer 170 and a portion exposed by vertically overlapping with the first opening region 171.

[0184] At this time, the edge of the upper surface of the first pad 121 may not vertically overlap with the first opening region 171 of the first protective layer 170. Preferably, the edge of the upper surface of the first pad 121 may be covered by the first protective layer 170. Therefore, the first opening region 171 of the first protective layer 170 may partially expose the region of the upper surface of the first pad 121 that is spaced apart from the edge of the upper surface of the first pad 121.

[0185] For example, the second pad 122 may vertically overlap with the second opening region 172 of the first protective layer 170. At this time, the upper surface of the second pad 122 may partially vertically overlap with the second opening region 172 of the first protective layer 170. For example, the upper surface of the second pad 122 may include a portion covered by the first protective layer 170 and a portion exposed by vertically overlapping with the second opening region 172.

[0186] In addition, the edge of the upper surface of the second pad 122 may not perpendicularly overlap with the second opening region 172 of the first protective layer 170. Preferably, the edge of the upper surface of the second pad 122 may be covered by the first protective layer 170. Therefore, the second opening region 172 of the first protective layer 170 may partially expose the region of the upper surface of the second pad 122 that is separated from the edge of the upper surface of the second pad 122.

[0187] The width of the first pad 121 in the horizontal direction may be in the range of 70 μm to 110 μm. Preferably, the width of the first pad 121 in the horizontal direction may be in the range of 75 μm to 105 μm. More preferably, the width of the first pad 121 in the horizontal direction may be in the range of 80 μm to 100 μm. If the width of the first pad 121 in the horizontal direction is less than 70 μm, the contact area between the first pad 121 and the first bump 180 may decrease, and thus the physical bonding reliability between them may deteriorate. If the width of the first pad 121 in the horizontal direction is less than 70 μm, the first bump 180 may not be stably disposed on the first pad 121, and further, the semiconductor device and / or the external substrate may not be stably disposed on the first bump 180.

[0188] If the width of the first pad 121 in the horizontal direction is greater than 110 μm, the space occupied by the first pad 121 may increase, and thus the area of the circuit board and the semiconductor package may increase. For example, if the width of the first pad 121 in the horizontal direction is greater than 110 μm, the first pad 121 may not be entirely disposed within the limited space, and thus the circuit integration degree may decrease.

[0189] The width of the second pad 122 in the horizontal direction can be smaller than the width of the first pad 121 in the horizontal direction. For example, the width of the second pad 122 in the horizontal direction can be in the range of 20 μm to 70 μm. Preferably, the width of the second pad 122 in the horizontal direction can be in the range of 25 μm to 65 μm. More preferably, the width of the second pad 122 in the horizontal direction can be in the range of 30 μm to 60 μm. If the width of the second pad 122 in the horizontal direction is less than 20 μm, the semiconductor device may not be stably set on the second pad 122. For example, if the width of the second pad 122 in the horizontal direction is less than 20 μm, the reliability of the electrical connection with the semiconductor device may deteriorate. If the width of the second pad 122 in the horizontal direction is greater than 70 μm, the second pad 122 may not be entirely set within the limited space. If the width of the second pad 122 in the horizontal direction is greater than 70 μm, the spacing between the multiple second pads connected to the terminals of the semiconductor device may increase, and thus the signal transmission distance may increase. When the signal transmission distance increases, the signal transmission loss may increase proportionally to the signal transmission distance, and thus the electrical reliability may deteriorate. For example, if the width of the second pad 122 in the horizontal direction is greater than 70 μm, the operating characteristics of the semiconductor device may deteriorate.

[0190] Meanwhile, the planar shapes of the first pad 121 and the second pad 122 can be the same as each other or can be different from each other.

[0191] For example, the first pad 121 can include a 1-1 pad 121-1 having a first planar shape. For example, the 1-1 pad 121-1 can have a planar shape of a circular or elliptical shape.

[0192] In addition, the first pad 121 can include a 1-2 pad 121-2 having a second planar shape. For example, the 1-2 pad 121-2 can have a planar shape of a square shape.

[0193] In addition, the second pad 122 can include a 2-1 pad 122-1 having a first planar shape. For example, the 2-1 pad 122-1 can have a planar shape of a circular or elliptical shape.

[0194] In addition, the second pad 122 can include a 2-2 pad 122-2 having a second planar shape. For example, the 2-2 pad 122-2 can have a planar shape of a square shape.

[0195] In addition, the 1-1 pad 121-1 can be selectively connected to the trace 121-3. In addition, the 1-2 pad 121-2 can be selectively connected to the trace 121-3. In addition, the second pad 122 can be selectively connected to the trace 121-3.

[0196] Meanwhile, the first opening region 171 of the first protective layer 170 may have a planar shape different from that of the first pad 121. Additionally, the first opening region 171 of the first protective layer 170 may have a planar shape different from that of the second pad 122. Additionally, the first opening region 171 of the first protective layer 170 may have a planar shape different from that of the second opening region 172 of the first protective layer 170.

[0197] Each of the 1-1 pad 121-1 and the 1-2 pad 121-2 of the first pad 121 may vertically overlap with the first opening region 171 of the first protective layer 170. For example, each of the 1-1 pad 121-1 and the 1-2 pad 121-2 of the first pad 121 may partially vertically overlap with the first opening region 171 of the first protective layer 170.

[0198] Each of the 1-1 pad 121-1 and the 1-2 pad 121-2 of the first pad 121 may include a non-overlapping region that does not vertically overlap with the first opening region 171 of the first protective layer 170 and an overlapping region that vertically overlaps with the first opening region 171.

[0199] For example, the 1-1 pad 121-1 of the first pad 121 may include a first portion 121a1 covered by the first protective layer 170. The first portion 121a1 of the 1-1 pad 121-1 of the first pad 121 may not vertically overlap with the first opening region 171 of the first protective layer 170. The first portion 121a1 of the 1-1 pad 121-1 of the first pad 121 may be provided along the edge of the upper surface of the 1-1 pad 121-1. That is, the edge portion of the upper surface of the 1-1 pad 121-1 corresponding to the first portion 121a1 of the 1-1 pad 121-1 may be completely covered by the first protective layer 170 and may not vertically overlap with the first opening region 171.

[0200] Additionally, the 1-1 pad 121-1 of the first pad 121 may include a second portion 121b1 that vertically overlaps with the first opening region 171 of the first protective layer 170.

[0201] In addition, the first part 121a2 of the 1-2 pad 121-2 of the first pad 121 may be covered by the first protective layer 170. The first part 121a2 of the 1-2 pad 121-2 of the first pad 121 may not vertically overlap with the first opening region 171 of the first protective layer 170. The first part 121a2 of the 1-2 pad 121-2 of the first pad 121 may be disposed along the edge of the upper surface of the 1-2 pad 121-2. That is, the edge portion of the upper surface of the 1-2 pad 121-2 corresponding to the first part 121a2 of the 1-2 pad 121-2 may be completely covered by the first protective layer 170 and may not vertically overlap with the first opening region 171.

[0202] In addition, the 1-2 pad 121-2 of the first pad 121 may include a second part 121b2 that vertically overlaps with the first opening region 171 of the first protective layer 170.

[0203] In addition, the second pad 122 may include a first part 122a covered by the first protective layer 170. The first part 122a of the second pad 122 may not vertically overlap with the second opening region 172 of the first protective layer 170. The first part 122a of the second pad 122 may be disposed along the edge of the upper surface of the second pad 122. That is, the edge portion of the upper surface of the second pad 122 corresponding to the first part 122a of the second pad 122 may be completely covered by the first protective layer 170 and may not vertically overlap with the second opening region 172.

[0204] In addition, the second pad 122 may include a second part 122b that vertically overlaps with the second opening region 172 of the first protective layer 170.

[0205] Meanwhile, the first bump 180 may be disposed on the first pad 121. For example, the first bump 180 may be disposed on the first parts 121a1 and 121a2 of each of the 1-1 pad 121-1 and the 1-2 pad 121-2 of the first pad 121. For example, the first bump 180 may be disposed in the first opening region 171 of the first protective layer 170. Preferably, the first bump 180 may include a part disposed in the first opening region 171 of the first protective layer 170. The planar shape of the first bump 180 may correspond to the planar shape of the first opening region 171 of the first protective layer 170. For example, the planar shape of the lower surface of the first bump 180 may correspond to the planar shape of the first opening region 171 of the first protective layer 170. For example, the lower surface of the first bump 180 may have a planar shape including a plurality of protruding parts spaced apart from each other. For example, the lower surface of the first bump 180 may have a snowflake shape.

[0206] The planar shapes of the first opening region 171 and the second opening region 172 will be described in more detail below.

[0207] Referring Figure 5a , the first pad 121-1 and the first pad 121-2 of the first pad 121 may each have a different planar shape. At this time, the first pad 121-1 and the first pad 121-2 may not be directly connected to the trace 121-3. For example, Figure 5a the first pad 121-1 and the first pad 121-2 of may represent pads not connected to the trace 121-3.

[0208] Referring Figure 5a to (A) of, the planar shape of the first pad 121-1 of the first pad 121 may be a circular shape. Additionally, referring Figure 5a to (B) of, the planar shape of the first pad 121-2 of the first pad 121 may be a square shape.

[0209] At this time, the first protective layer 170 may include a first opening region 171 that vertically overlaps the first pad 121-1 and the first pad 121-2 respectively. The planar shape of the first opening region vertically overlapping the first pad 121-1 may be the same as the planar shape of the first opening region vertically overlapping the first pad 121-2.

[0210] However, the embodiment is not limited thereto, and the planar shape of the first opening region vertically overlapping the first pad 121-1 may be different from the planar shape of the first opening region vertically overlapping the first pad 121-2. For example, the planar shape of the first opening region vertically overlapping the first pad 121-2 may be as shown in Figure 5a (B) of. The planar shape of the first opening region vertically overlapping the first pad 121-1 may be as shown in Figure 9 . For example, the first opening region 171 may include a first portion 171-1 and a second portion 171-2 described below. For example, the inner surface forming the first opening region 171 may have a first inner surface and a second inner surface with steps in the horizontal direction. Additionally, the first inner surface may represent the inner surface of the first portion 171-1, and the second inner surface may represent the inner surface of the second portion 171-2.

[0211] In addition, the first part 171-1 of the first opening area 171 may follow the shape of the pad that vertically overlaps it. For example, the first part 171-1 of the first opening area that vertically overlaps the 1-1 pad 121-1 may have a circular shape corresponding to the planar shape of the 1-1 pad 121-1. In addition, the first part 171-1 of the first opening area that vertically overlaps the 1-2 pad 121-2 may have a square shape corresponding to the planar shape of the 1-2 pad 121-2.

[0212] Meanwhile, the first part 171-1 and the second part 171-2 of the first opening area 171 may be connected to each other. That is, the second part 171-2 of the first opening area 171 may be a part that protrudes from the first part 171-1 in the outward direction. For example, the second part 171-2 of the first opening area 171 may be a part that protrudes or extends from the first part 171-1 toward the edge of the upper surface of the first pad 121. The second part 171-2 of the first opening area 171 may be provided in a plurality of numbers. For example, the first opening area 171 may include the first part 171-1 and a plurality of second parts 171-2 that protrude from the first part 171-1 in the outward direction and are spaced apart from each other.

[0213] Therefore, referring to Figure 5a in (A) and (B), the horizontal distance between the inner wall of the first opening area 171 of the first protective layer 170 and the side surface of the first pad 121 may have different horizontal distances along the edge of the upper surface of the first pad 121. For example, the horizontal distance D1 of the second part 171-2 of the first opening area 171 of the first protective layer 170 may be less than the horizontal distance D2 of the first part 171-1 of the first opening area 171 of the first protective layer 170. For example, the first inner wall of the first part 171-1 of the first opening area 171 and the second inner wall of the second part 171-2 may have a step in the horizontal direction. For example, the first inner wall of the first part 171-1 of the first opening area 171 may be positioned more inward than the second inner wall of the second part 171-2. On the contrary, the second inner wall of the second part 171-2 of the first opening area 171 may be positioned more outward than the first inner wall of the first part 171-1. Here, the fact that the first inner wall and the second inner wall have a step may indicate that the entire inner wall of the first opening area 171 includes an outer part that is relatively outwardly positioned and a protruding surface inner part that protrudes inward from the outer part.

[0214] Meanwhile, referring to Figure 5b , the 1-1 pad 121-1 and the 1-2 pad 121-2 may be connected to the trace 121-3.

[0215] Trace 121-3 may not perpendicularly overlap with the first opening region 171 of the first protective layer 170. Specifically, trace 121-3 is connected to the side portions of the 1-1 pad 121-1 and / or the 1-2 pad 121-2. At this time, the edge regions of the upper surfaces of the 1-1 pad 121-1 and the 1-2 pad 121-2 adjacent to the side portions of the 1-1 pad 121-1 and the 1-2 pad 121-2 may not perpendicularly overlap with the first opening region 171 of the first protective layer 170. Accordingly, trace 121-3 may not perpendicularly overlap with the first opening region 171 of the first protective layer 170.

[0216] The horizontal distance D3 between one side surface and the other side surface of trace 121-3 may be determined by the widths of the 1-1 pad 121-1 and the 1-2 pad 121-2 and the width of the opening region 171 of the first protective layer 170. The horizontal distance D3 between one side surface and the other side surface of trace 121-3 may represent the width D3 of trace 121-3 in the horizontal direction. This will be described in more detail below.

[0217] Meanwhile, referring to Figure 6 , the inner wall of the second opening region 172 of the first protective layer 170 may not have a step in the horizontal direction. For example, the second opening region 172 of the first protective layer 170 may not include the protruding portion in the first opening region 171.

[0218] For example, referring to Figure 6 of (A), the second opening region 172 of the first protective layer 170 may include a 2-1 opening region 172-1 that perpendicularly overlaps with the 2-1 pad 122-1 of the second pad 122. The planar shape of the 2-1 pad 122-1 of the second pad 122 may have a circular shape. Accordingly, the planar shape of the 2-1 opening region 172-1 may have a circular shape corresponding to the planar shape of the 2-1 pad 122-1 of the second pad 122.

[0219] For example, referring to Figure 6 of (B), the second opening region 172 of the first protective layer 170 may include a 2-2 opening region 172-2 that perpendicularly overlaps with the 2-2 pad 122-2 of the second pad 122. The planar shape of the 2-2 pad 122-2 of the second pad 122 may have a square shape. Accordingly, the planar shape of the 2-2 opening region 172-2 may have a square shape corresponding to the planar shape of the 2-2 pad 122-2 of the second pad 122.

[0220] At this time, the inner walls of the 2-1 opening area 172-1 and the 2-2 opening area 172-2 of the first protective layer 170 may not have steps in the horizontal direction. For example, the 2-1 opening area 172-1 and the 2-2 opening area 172-2 of the first protective layer 170 may not include the second part 171-2 of the first opening area 171. For example, the 2-1 opening area 172-1 and the 2-2 opening area 172-2 of the first protective layer 170 may only include the first part 171-1 of the first opening area 171.

[0221] That is, the bump may not be provided on the second pad 122. Additionally, the second pad 122 may have a smaller width than the first pad 121. Therefore, even if the inner wall of the second opening area 172 that vertically overlaps the second pad 122 does not have steps in the horizontal direction, it may not affect the bonding with the semiconductor device or the bonding with the bump.

[0222] However, the first bump 180 may be provided on the first pad 121. Therefore, the first opening area 171 that vertically overlaps the first pad 121 may affect the bonding reliability with the first bump 180 and the bonding reliability with the external substrate and / or the semiconductor device.

[0223] For example, if the inner wall of the first opening area 171 does not have steps in the horizontal direction, the bonding reliability between the first bump 180 and the first pad 121 may be reduced. For example, when an impact occurs from the outside, since the inner wall of the first opening area 171 does not have steps, the impact can be transmitted to the entire area of the first bump 180 simultaneously, which may cause cracks to appear in the first bump 180.

[0224] In contrast, the inner wall of the first opening area 171 of the embodiment may have steps in the horizontal direction. Therefore, when an impact occurs from the outside, since the inner wall of the first opening area 171 has steps, the impact can be transmitted only to the relatively outer area of the entire area of the first bump 180, and the impact may not be transmitted to the relatively inner area. For example, the embodiment may make the inner wall of the first opening area 171 have steps, and may disperse the impact generated on the first bump 180 based on the steps. Thus, the embodiment can improve the mechanical reliability and / or electrical reliability of the first bump 180, and can improve the mechanical reliability and / or electrical reliability between the circuit board and the semiconductor device and / or the external substrate.

[0225] In summary, the first opening region 171 may include a first portion 171-1 and a second portion 171-2 that protrudes outward from the first portion 171-1. Additionally, the inner wall of the first opening region 171 may have a step in the horizontal direction according to the first portion 171-1 and the second portion 171-2. Accordingly, the embodiment may disperse the physical impact applied to the first bump 180 based on the step of the inner wall of the first opening region 171. That is, the embodiment may increase the resistance of the first bump 180 to mechanical stress by having the inner wall of the first opening region 171 have a step in the horizontal direction, thereby improving the mechanical and / or physical reliability of the circuit board and the semiconductor package including the circuit board.

[0226] Meanwhile, referring to Figure 7 and Figure 8 , the first opening region 171 may include a first portion 171-1 and a second portion 171-2. The second portion 171-2 may be disposed at a plurality of positions spaced apart from each other.

[0227] The first portion 171-1 of the first opening region 171 may have a square shape. The second portion 171-2 may protrude outward from each of the four corner portions of the first portion 171-1.

[0228] For example, the second portion 171-2 may include first to fourth sub-portions 171-2a, 171-2b, 171-2c, and 171-2d that protrude outward from different positions of the first portion 171-1.

[0229] At this time, the total width of the first opening region 171, the width of the first portion 171-1, and the width of the second portion 171-2 may be determined based on the width of the first pad 121.

[0230] Since the width W1 of the first pad 121 has been described above, a detailed description thereof will be omitted. For example, if the first pad 121 has a circular shape corresponding to the 1-1 pad 121-1 of Figure 7 , the width W1 may represent the diameter of the 1-1 pad 121-1. For example, if the first pad 121 has a square shape corresponding to the 1-2 pad 121-2 of Figure 8 , the width W1 may represent the width of the 1-2 pad 121-2 in the horizontal direction.

[0231] The first opening region 171 may have a second width W2. The second width W2 may represent the width of the region having the maximum width in the entire region of the first opening region 171. For example, the second width W2 may represent the width between the ends of two sub-portions of the second portion 171-2 facing each other.

[0232] Therefore, the second width W2 of the first opening region 171 may represent the maximum width of the first opening region 171.

[0233] The maximum width W2 of the first opening region 171 may be in the range of 70% to 95% of the width W1 of the first pad 121. For example, the maximum width W2 of the first opening region 171 may be in the range of 72% to 92% of the width W1 of the first pad 121. For example, the maximum width W2 of the first opening region 171 may be in the range of 75% to 90% of the width W1 of the first pad 121.

[0234] If the maximum width W2 of the first opening region 171 is less than 70% of the width W1 of the first pad 121, the area of the upper surface of the first pad 121 exposed through the first opening region 171 may be reduced. Additionally, if the area of the exposed upper surface of the first pad 121 is reduced, the contact area between the first pad 121 and the first bump 180 may be reduced, and thus, the first bump 180 may be peeled off from the first pad 121. Additionally, if the maximum width W2 of the first opening region 171 is less than 70% of the width W1 of the first pad 121, the width difference between the first bump 180 and the first pad 121 may increase, and thus, the signal transmission loss may increase. Additionally, if the maximum width W2 of the first opening region 171 exceeds 95% of the width W1 of the first pad 121, at least a part of the edge of the upper surface of the first pad 121 may be exposed through the first opening region 171. For example, if the maximum width W2 of the first opening region 171 exceeds 95% of the width W1 of the first pad 121, due to process errors during the formation of the first opening region 171, at least a part of the side surface of the first pad 121 may not be covered by the first protective layer 170, and thus, mechanical reliability and / or electrical reliability problems may occur.

[0235] Meanwhile, the width W3 of the first portion 171-1 of the first opening region 171 may be in the range of 30% to 70% of the width W1 of the first pad 121. For example, the width W3 of the first portion 171-1 of the first opening region 171 may be in the range of 32% to 68% of the width W1 of the first pad 121. For example, the width W3 of the first portion 171-1 of the first opening region 171 may be in the range of 35% to 65% of the width W1 of the first pad 121.

[0236] If the width W3 of the first part 171-1 of the first opening region 171 is less than 30% of the width W1 of the first pad 121, the contact area between the first bump 180 and the first pad 121 is reduced, and thus mechanical reliability and / or physical reliability problems may occur. For example, if the width W3 of the first part 171-1 of the first opening region 171 is less than 30% of the width W1 of the first pad 121, a region with a rapidly decreasing width may be provided in the first bump 180, and thus cracks may occur in the first bump 180.

[0237] If the width W3 of the first part 171-1 of the first opening region 171 exceeds 70% of the width W1 of the first pad 121, the horizontal length of the step of the first opening region 171 may be reduced, and the effect of dispersing mechanical stress by the step structure of the embodiment may be insufficient.

[0238] Meanwhile, the width W4 of each second part 171-2 of the first opening region 171 may be in the range of 5% to 30% of the width W1 of the first pad 121. For example, the width W4 of each second part 171-2 of the first opening region 171 may be in the range of 8% to 27% of the width W1 of the first pad 121. For example, the width W4 of each second part 171-2 of the first opening region 171 may be in the range of 10% to 20% of the width W1 of the first pad 121.

[0239] If the width W4 of each second part 171-2 of the first opening region 171 is less than 5% of the width W1 of the first pad 121, the horizontal length of the step of the first opening region 171 formed by the second part 171-2 may be reduced, and thus the effect of dispersing mechanical stress by the step structure of the embodiment may be insufficient. If the width W4 of each second part 171-2 of the first opening region 171 exceeds 30% of the width W1 of the first pad 121, the second part 171-2 may vertically overlap the edge of the upper surface of the first pad 121 due to process errors. Additionally, if the width W4 of each second part 171-2 of the first opening region 171 exceeds 30% of the width W1 of the first pad 121, the width W3 of the first part 171-1 may be correspondingly reduced, thereby deteriorating the mechanical reliability and / or physical reliability between the first pad 121 and the first bump 180.

[0240] Meanwhile, it has been described that the first part 171-1 may have a square shape and the second part 171-2 may have a circular shape, but the embodiment is not limited thereto. For example, referring to Figure 9, the first part 171-1 and the second part 171-2 can each have a circular shape, and by controlling the width between the first part 171-1 and the second part 171-2, the inner wall of the first opening region 171 can have a step in the horizontal direction.

[0241] However, the inner wall of the second part 171-2 is located outside the first part 171-1 and can be the part where external mechanical stress is first transmitted. At this time, if the second part 171-2 has a square planar shape with a non-circular edge, the stress may concentrate on the edge part, and thus the effect of dispersing mechanical stress through the step may be reduced. Therefore, preferably, the planar shape of the second part 171-2 has a circular shape, and the first part 171-1 can be deformed into various shapes, such as circular, oval, square, triangular, and polygonal shapes.

[0242] Meanwhile, when the first circuit layer 120 is provided with a trace 121-3 and the first pad 121 is connected to the trace 121-3, the width D3 of the trace 121-3 can be determined by the width of the first opening region 171 of the first protective layer 170. Conversely, when the trace 121-3 is provided, the width of the first opening region 171 of the first protective layer 170 can be determined based on the width D3 of the trace 121-3.

[0243] The width D3 of the trace 121-3 can be smaller than the width W3 of the first part 171-1 of the first opening region 171. If the width D3 of the trace 121-3 is greater than the width W3 of the first part 171-1 of the first opening region 171, the ratio of the width of the trace 121-3 to the width of the first pad 121 can increase significantly, and thus the transmission loss of the signal transmitted through the first pad 121 and the trace 121-3 can increase. In addition, if the width of the trace 121-3 is greater than the width W3 of the first part 171-1 of the first opening region 171, the area occupied by the trace 121-3 on the first insulating layer 111 may increase, and thus it may be difficult to make the circuit board thinner.

[0244] The width D3 of the trace 121-3 may be less than or greater than the width W4 of the second part 171-2 of the first opening region 171. For example, the width D3 of the trace 121-3 may be 50% or more of the width W4 of the second part 171-2 of the first opening region 171. For example, the width D3 of the trace 121-3 may be 55% or more of the width W4 of the second part 171-2 of the first opening region 171. For example, the width D3 of the trace 121-3 may be 60% or more of the width W4 of the second part 171-2 of the first opening region 171. If the width D3 of the trace 121-3 is less than 50% of the width W4 of the second part 171-2 of the first opening region 171, the width of the trace 121-3 may be significantly less than the width of the first pad 121, and the signal transmission loss due to the width difference between the first pad 121 and the trace 121-3 may increase. If the width D3 of the trace 121-3 is less than 50% of the width W4 of the second part 171-2 of the first opening region 171, the area occupied by the second part 171-2 in the first opening region 171 of the first protective layer 170 may increase. Therefore, there may be a problem that at least a part of the edge region of the upper surface of the first pad 121 vertically overlaps with the first opening region 171 of the first protective layer 170. If the width D3 of the trace 121-3 is less than 50% of the width W4 of the second part 171-2 of the first opening region 171, the width W4 of the second part 171-2 may become greater than the width W3 of the first part 171-1 of the first opening region 171. Therefore, the exposed area of the upper surface of the first pad 121 may decrease. In addition, when the exposed area decreases, the semiconductor device may not be stably bonded to the first pad 121. Therefore, the semiconductor device may not operate stably or the operating characteristics of the semiconductor device may deteriorate. For example, when the width W4 of the second part 171-2 of the first opening region 171 of the first protective layer 170 is 5 μm to 10 μm, the width D3 of the trace 121-3 may be greater than 2.5 μm to 5 μm.

[0245] Meanwhile, the width D3 of the trace 121-3 can be greater than one-third of half of the difference between the width W3 of the first part 171-1 of the first opening region 171 and the width W1 of the first pad 121. For example, the width D3 of the trace 121-3 can be greater than one-third of the horizontal distance D2 from the side surface of the first pad 121 to the inner wall of the first part 171-1 of the first opening region 171 of the first protective layer 170. If the width D3 of the trace 121-3 is less than one-third of the horizontal distance D2 from the side surface of the first pad 121 to the inner wall of the first part 171-1 of the first opening region 171 of the first protective layer 170, the planar area of the first pad 121 that vertically overlaps with the first opening region 171 may be outside the reference range. For example, if the planar area of the first pad 121 exceeds the reference range, electrical reliability and / or physical reliability problems may occur due to the edge region of the upper surface of the first pad 121 being exposed from the first opening region 171. Additionally, if the planar area of the first pad 121 is less than the reference range, the contact area between the first pad 121 and the solder, which is a conductive adhesive, may decrease, and thus the bonding strength between the first pad 121 and the semiconductor device may deteriorate.

[0246] The circuit board of the embodiment can include a first protective layer, and the first protective layer includes a first pad and a first opening region that vertically overlaps with the first pad. The inner wall of the first opening region of the first protective layer can have a step in the horizontal direction. For example, the first opening region of the first protective layer can include a first part and a second part that protrudes from the first part in the outward direction. The second parts can be provided in a plurality of numbers and can each protrude from different positions of the first part. The first opening region of the first protective layer can include the inner wall of the first part and the inner wall of the second part, and the inner wall of the first part and the inner wall of the second part can have a step in the horizontal direction.

[0247] Therefore, the embodiment can improve the bonding reliability between the first pad and the first bump, and further improve the bonding reliability with the external substrate and / or the semiconductor device.

[0248] For example, if the inner wall of the first opening region does not have a step in the horizontal direction, the bonding reliability between the first bump and the first pad may deteriorate. For example, when an impact occurs from the outside, since the inner wall of the first opening region does not have a step, the impact can be transmitted to the entire region of the first bump at the same time, which may cause cracks to appear in the first bump.

[0249] In contrast, the inner wall of the first opening region of the embodiment may have a step in the horizontal direction. Thus, when an impact occurs from the outside, since the inner wall of the first opening region has a step, the impact can be transmitted only to the relatively outer region of the entire region of the first bump, and the impact can not be transmitted to the relatively inner region. For example, the embodiment may allow a step to be provided on the inner wall of the first opening region, and the impact occurring in the first bump may be dispersed based on the step. Thereby, the embodiment can improve the mechanical reliability and / or electrical reliability of the first bump, and thus improve the mechanical reliability and / or electrical reliability between the circuit board and the semiconductor device and / or the external substrate.

[0250] Semiconductor package

[0251] Hereinafter, a semiconductor package according to an embodiment will be described.

[0252] Figure 10 is a diagram showing a semiconductor package according to a first embodiment, Figure 11 is a diagram showing a semiconductor package according to a second embodiment, Figure 12 is a diagram showing a semiconductor package according to a third embodiment, Figure 13 is a diagram showing a semiconductor package according to a fourth embodiment.

[0253] Reference Figure 10 , the semiconductor package includes a circuit board.

[0254] In addition, the semiconductor package may include a first connection portion 210 provided on the second pad 122 of the first circuit layer 120 of the circuit board.

[0255] The first connection portion 210 may include a spherical shape. For example, the cross section of the first connection portion 210 may include a circular shape or a semi-circular shape. For example, the cross section of the first connection portion 210 may include a partially or completely circular shape. For example, the cross-sectional shape of the first connection portion 210 may be flat on one side and curved on the other side.

[0256] A semiconductor package may include a first semiconductor device 220 disposed on a first connection portion 210. The first semiconductor device 220 includes terminals 225. The terminals 225 of the first semiconductor device 220 may be electrically coupled to a second pad 122 through the first connection portion 210. The first semiconductor device 220 may include a logic chip. For example, the first semiconductor device 220 may include an application processor chip. For example, the first semiconductor device 220 may include an analog-to-digital converter or an ASIC (application-specific IC). For example, the first semiconductor device 220 may include a memory chip. The memory chip may be a stacked memory such as HBM. For example, the memory chip may include a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, etc. Additionally, the first semiconductor device 220 may include at least one of a drive IC chip, a diode chip, a power IC chip, a touch sensor IC chip, an MLCC (Multi-Layer Ceramic Condenser) chip, a BGA (Ball Grid Array) chip, and a chip capacitor.

[0257] Additionally, the semiconductor package may include a second connection portion 230 disposed on a first bump 180. At least one second semiconductor device 240 may be disposed on the second connection portion 230. For example, the terminals 245 of at least one second semiconductor device 240 may be electrically coupled to the first bump 180 through the second connection portion 230.

[0258] Additionally, the semiconductor package may further include a first molding member 250. The first molding member 250 may mold the first semiconductor device 220 and the second semiconductor device 240. Additionally, the first molding member 250 may mold the first bump 180.

[0259] The first molding member 250 may have a low dielectric constant to enhance heat dissipation characteristics. For example, the dielectric constant (Dk) of the first molding member 250 may be from 0.2 to 10. For example, the dielectric constant (Dk) of the first molding member 250 may be from 0.5 to 8. For example, the dielectric constant (Dk) of the first molding member 250 may be from 0.8 to 5. Thus, in an embodiment, the first molding member 250 has a low dielectric constant to enhance the heat dissipation characteristics of the first and second semiconductor devices.

[0260] Meanwhile, the semiconductor package may include a third connection portion 260. At this time, the second bump 190 may not be disposed on the lower surface of the second circuit layer 130 of the semiconductor package. Additionally, the third connection portion 260 may also perform the function of the second bump 190.

[0261] The first external substrate 300 may be coupled below the third connection portion 260. The first external substrate 300 may include at least one external pad 310 and an external protective layer 320 including an opening region vertically overlapping the external pad 310. The first external substrate 300 may be a main board of an electronic device. In another embodiment, the first external substrate 300 may be a separate package. For example, the first external substrate 300 may be a memory package. For example, the first external substrate 300 may be an interposer that connects to a memory substrate on which a memory device is disposed. Alternatively, the first external substrate 300 may be a memory substrate.

[0262] In addition, the semiconductor package may include a second molding member 250 disposed between the circuit board and the first external substrate 300. The second molding member 250 may mold the third connection portion 260.

[0263] Meanwhile, referring to Figure 11 , compared with the semiconductor package of the first embodiment, the semiconductor package of the second embodiment may have a second external substrate 330 coupled to the second connection portion 230 instead of at least one second semiconductor device. The second external substrate 330 may include at least one external pad 335, and the external pad 335 may be electrically coupled to the first bump 180 through the second connection portion 230.

[0264] Meanwhile, referring to Figure 12 , compared with the semiconductor package of the first embodiment, the semiconductor package of the third embodiment may include a second bump 190 disposed below the second circuit layer 130. In addition, the third connection portion 260 may be disposed below the second bump 190. At this time, at least one third semiconductor device 280 may be coupled to the third connection portion 260. For example, the terminals 285 of at least one third semiconductor device 280 may be electrically coupled to the second bump 190 through the third connection portion 260. Meanwhile, instead of the third semiconductor device 280, the first external substrate 300 may be coupled to the third connection portion 260.

[0265] Meanwhile, referring to Figure 13 , compared with the semiconductor package of the third embodiment, the semiconductor package of the fourth embodiment may have a structure in which at least one third semiconductor device and the first external substrate are all coupled.

[0266] For example, the semiconductor package may have a third connection portion 260 disposed below the second bump 190, and the external pad 310 of the first external substrate 300 is coupled to the third connection portion 260. In addition, the semiconductor package may include a fourth connection portion 290 disposed below the fourth pad 132 of the second circuit layer 130. The terminals 285 of at least one third semiconductor device 280 may be coupled to the fourth connection portion 290.

[0267] On the other hand, when the circuit board having the above-described features of the present invention is used in IT devices or household appliances (such as smart phones, server computers, TVs, etc.), functions such as signal transmission or power supply can be stably performed. For example, when the circuit board having the features of the present invention performs a semiconductor packaging function, the circuit board can be used to safely protect a semiconductor chip from external moisture or contaminants, or problems such as leakage current, electrical short circuit, and electrical open circuit between terminals provided to the semiconductor chip can be solved. In addition, when the signal transmission function is dominant, the noise problem can be solved. Thus, the circuit board having the above-described features of the present invention can maintain the stable functions of IT devices or household appliances, such that the entire product and the circuit board applying the present invention can achieve functional unity or technical interlock with each other.

[0268] When the circuit board having the above-described features of the present invention is used in a transportation device such as a vehicle, the problem of signal distortion transmitted to the transportation device can be solved, or the safety of the transportation device can be further improved by safely protecting a semiconductor chip that controls the transportation device from the outside and solving problems such as leakage current, electrical short circuit, or electrical open circuit between terminals provided to the semiconductor chip. Therefore, the transportation device and the circuit board applying the present invention can achieve functional integrity or technical interlock with each other.

[0269] The characteristics, structures, and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. In addition, those of ordinary skill in the art to which the embodiments pertain can even combine or modify the characteristics, structures, effects, etc. shown in each embodiment with respect to other embodiments. Therefore, it should be understood that the content related to such combinations and such modifications is included within the scope of the embodiments.

[0270] The above description focuses on the embodiments, but it is merely illustrative and does not limit the embodiments. Those skilled in the art to which the embodiments pertain can understand that various modifications and applications not shown above are possible without departing from the basic features of the embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, it should be understood that the differences related to these changes and applications are included within the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board, comprising: An insulating layer; A first pad, the first pad being disposed on the insulating layer; And A protective layer, the protective layer being disposed on the insulating layer and including a first opening area that vertically overlaps the first pad, Wherein, the width of the first opening area in the horizontal direction is smaller than the width of the first pad in the horizontal direction, Wherein, the inner walls of the first opening area forming the protective layer have a first inner wall and a second inner wall, and the first inner wall and the second inner wall have a step along the horizontal direction.

2. The circuit board according to claim 1, wherein, The first opening area of the protective layer includes a first part and a second part, the first part forms the first inner wall, and the second part protrudes from the first part toward the side surface of the first pad and forms the second inner wall.

3. The circuit board according to claim 2, wherein, The second part of the first opening area includes a plurality of sub-parts that protrude in a direction away from the first part at positions spaced apart from each other.

4. The circuit board according to claim 2, wherein, The planar shape of the second part has a circular or elliptical shape.

5. The circuit board according to claim 4, wherein, The planar shape of the first part has at least one of the shapes of a circle, an ellipse, a square, a triangle, and a polygon.

6. The circuit board according to claim 4, wherein, The planar shape of the first part is different from the planar shape of the second part.

7. The circuit board according to claim 1, wherein, The first inner wall and the second inner wall do not vertically overlap the edge of the upper surface of the first pad.

8. The circuit board according to claim 1, further comprising: A first bump, the first bump being disposed on the first pad that vertically overlaps the first opening area, Wherein, the lower surface of the first bump has a planar shape corresponding to the planar shape of the first opening area.

9. The circuit board according to claim 1, wherein, The width of the area with the maximum width in the first opening area satisfies the range of 70% to 90% of the width of the first pad in the horizontal direction.

10. The circuit board according to claim 9, wherein, The width of the first part of the first opening area satisfies the range of 30% to 70% of the width of the first pad in the horizontal direction, Wherein, the width of the second part of the first opening area satisfies the range of 5% to 30% of the width of the first pad in the horizontal direction.

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