Three-dimensional memory devices including self-aligned channel cap structures and methods of forming same

Abstract

A semiconductor structure includes: an alternating stack of insulating layers and conductive layers; a memory opening, the memory opening extending vertically through the alternating stack; a memory opening fill structure in the memory opening and including a memory film, a vertical semiconductor channel, and a semiconductor cap structure including a semiconductor core structure contacting a bottom end of the vertical semiconductor channel and laterally surrounding the semiconductor core structure, a ring-shaped semiconductor structure having a smaller vertical range than the semiconductor core structure; and a source layer contacting a bottom surface of the semiconductor core structure.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of U.S. Non - Provisional Application No. 18 / 450,095, filed on August 15, 2023, entitled "THREE - DIMENSIONAL MEMORY DEVICES INCLUDING SELF - ALIGNED CHANNEL CAP STRUCTURES AND METHODS FOR FORMING THE SAME", which is hereby incorporated by reference in its entirety for all purposes, and which claims the priority of U.S. Provisional Application No. 63 / 504,915, filed on May 30, 2023. Technical field

[0003] The present disclosure generally relates to the field of semiconductor devices, and more particularly to three - dimensional memory devices including self - aligned channel cap structures and methods for forming the same. Background art

[0004] A three - dimensional vertical NAND string having one bit per cell is disclosed in the article by T. Endoh et al., entitled "Novel Ultra High Density Memory With A Stacked - Surrounding Gate Transistor (S - SGT) Structured Cell" (Proceedings of the IEDM Conference, 2001, pp. 33 - 36). Summary of the invention

[0005] According to one aspect of the present disclosure, a semiconductor structure is provided, which includes: an alternating stack of insulating layers and conductive layers; a memory opening extending vertically through the alternating stack; a memory opening filling structure located in the memory opening and including a memory film, a vertical semiconductor channel, and a semiconductor cap structure, the semiconductor cap structure including a semiconductor core structure contacting the bottom end of the vertical semiconductor channel and an annular semiconductor structure laterally surrounding the semiconductor core structure and having a vertical extent smaller than that of the semiconductor core structure; and a source layer contacting the bottom surface of the semiconductor core structure.

[0006] According to another aspect of the present disclosure, a method of forming a semiconductor structure is provided. The method includes: forming a material layer over a carrier substrate; forming an alternating stack of an insulating layer and a spacer material layer over the material layer, wherein the spacer material layer is formed as a conductive layer or is subsequently replaced by a conductive layer; forming a memory opening through the alternating stack and into the material layer; forming an annular cavity around a bottom portion of the memory opening at the level of the material layer; forming a memory film on exposed surfaces of the memory opening and the annular cavity; forming an annular semiconductor structure within a remaining volume of the annular cavity; forming a semiconductor core structure on an inner sidewall of the annular semiconductor structure; and forming a vertical semiconductor channel on a top surface of the semiconductor core structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic vertical cross-sectional view of a first exemplary structure after forming a first alternating stack of an insulating material layer, a semiconductor material layer, and a first insulating layer and a first sacrificial material layer over a carrier substrate according to a first embodiment of the present disclosure.

[0008] Figure 2 is a schematic vertical cross-sectional view of a first exemplary structure after forming a first stepped surface and a first stepped dielectric material portion according to a first embodiment of the present disclosure.

[0009] Figure 3 is a schematic vertical cross-sectional view of a first exemplary structure after forming a first layer opening according to a first embodiment of the present disclosure.

[0010] Figure 4 is a vertical cross-sectional view of a first exemplary structure after forming a sacrificial opening filling structure according to a first embodiment of the present disclosure.

[0011] Figure 5 is a vertical cross-sectional view of a first exemplary structure after forming a second alternating stack of a second insulating layer and a second sacrificial material layer, a second stepped surface, and a second reverse stepped dielectric material portion according to a first embodiment of the present disclosure.

[0012] Figure 6 is a vertical cross-sectional view of a first exemplary structure after forming a second layer opening according to a first embodiment of the present disclosure.

[0013] Figure 7A is a schematic vertical cross-sectional view of a first exemplary structure after forming an interlayer memory opening and an interlayer support opening according to a first embodiment of the present disclosure.

[0014] Figure 7B is Figure 7A a top view of a first exemplary structure. Vertical plane A-A isFigure 7A The cross-section of the vertical sectional view.

[0015] Figures 8A to 8G Is a sequential vertical sectional view of the memory opening during the formation of the memory opening filling structure in the first exemplary structure according to the first embodiment of the present disclosure.

[0016] Figure 9A Is a schematic vertical sectional view of the first exemplary structure after the formation of the memory opening filling structure according to the first embodiment of the present disclosure.

[0017] Figure 9B Is Figure 9A The top view of the first exemplary structure. The vertical plane A-A is Figure 9A The cross-section of the vertical sectional view.

[0018] Figure 10A Is a vertical sectional view of the first exemplary structure after the formation of the lateral isolation trench according to the first embodiment of the present disclosure.

[0019] Figure 10B Is Figure 10A The top view of the first exemplary structure. The vertical plane A-A is Figure 10A The cross-section of the vertical sectional view.

[0020] Figure 11 Is a vertical sectional view of the first exemplary structure after the formation of the laterally extending cavity according to the first embodiment of the present disclosure.

[0021] Figure 12 Is a schematic vertical sectional view of the first exemplary structure after the formation of the conductive layer according to the first embodiment of the present disclosure.

[0022] Figure 13A Is a vertical sectional view of the first exemplary structure after the formation of the lateral isolation trench filling structure, the layer contact via structure, and the drain contact via structure according to the first embodiment of the present disclosure.

[0023] Figure 13B Is Figure 13A The top view of the first exemplary structure. The vertical plane A-A is Figure 13A The cross-section of the vertical sectional view.

[0024] Figure 14 Is a vertical sectional view of the first exemplary structure after the formation of the memory die according to the first embodiment of the present disclosure.

[0025] Figure 15 Is a vertical sectional view of the logic die according to the first embodiment of the present disclosure.

[0026] Figure 16 A vertical cross-sectional view of a first exemplary structure after attaching a logic die to a memory die according to a first embodiment of the present disclosure.

[0027] Figure 17 A vertical cross-sectional view of a first exemplary structure after thinning a carrier substrate according to a first embodiment of the present disclosure.

[0028] Figure 18A A vertical cross-sectional view of a first exemplary structure after removing a carrier substrate and an insulating material layer according to a first embodiment of the present disclosure.

[0029] Figure 18B and Figure 18C is Figure 18A An enlarged view of a region of an alternative configuration of a first exemplary structure of

[0030] Figure 19 A vertical cross-sectional view of a first exemplary structure after forming a source layer according to a first embodiment of the present disclosure.

[0031] Figure 20A A vertical cross-sectional view of a first exemplary structure after forming a backside insulating layer and a source contact structure according to a first embodiment of the present disclosure.

[0032] Figure 20B and Figure 20C is Figure 20A An enlarged view of a region of an alternative configuration of a first exemplary structure of

[0033] Figure 21 A schematic vertical cross-sectional view of a second exemplary structure after forming a first layer opening according to a second embodiment of the present disclosure.

[0034] Figure 22 A schematic vertical cross-sectional view of a second exemplary structure after forming an interlayer memory opening and an interlayer support opening according to a second embodiment of the present disclosure.

[0035] Figures 23A to 23G A sequential vertical cross-sectional view of a memory opening during the formation of a memory opening filling structure in a second exemplary structure according to a second embodiment of the present disclosure.

[0036] Figures 24A to 24C A sequential vertical cross-sectional view of a region of a second exemplary structure during the removal of a carrier substrate, an insulating material layer, and a bottom portion of a semiconductor material layer and a memory opening and during the formation of a source layer according to a second embodiment of the present disclosure.

[0037] Figure 25AA vertical cross-sectional view of a third exemplary structure after forming a sacrificial plate structure according to a third embodiment of the present disclosure.

[0038] Figure 25B Is Figure 25A A top view of a third exemplary structure.

[0039] Figure 26 A schematic vertical cross-sectional view of a third exemplary structure after forming a first layer opening according to a third embodiment of the present disclosure.

[0040] Figure 27 A schematic vertical cross-sectional view of a third exemplary structure after forming an interlayer memory opening and an interlayer support opening according to a third embodiment of the present disclosure.

[0041] Figures 28A to 28G A sequential vertical cross-sectional view of a memory opening during the formation of a memory opening filling structure in a third exemplary structure according to a third embodiment of the present disclosure.

[0042] Figures 29A to 29C A sequential vertical cross-sectional view of a region of a third exemplary structure during the removal of a carrier substrate and a bottom portion of an embedded insulating layer and a memory opening and the formation of a source layer according to a third embodiment of the present disclosure.

[0043] Figure 30 A schematic vertical cross-sectional view of a third exemplary structure after forming a source contact structure according to a third embodiment of the present disclosure. Detailed Description

[0044] As discussed above, embodiments of the present disclosure are directed to three-dimensional memory devices containing a self-aligned channel capping structure and methods of forming the same, and various aspects of these embodiments are described below. Embodiments of the present disclosure can be used to form various structures including multi-level memory structures, non-limiting examples of which include three-dimensional memory devices containing multiple memory strings.

[0045] The drawings are not drawn to scale. In cases where a single example of an element is shown, multiple instances of the element may be replicated unless otherwise explicitly described or clearly indicated that no replication of the element exists. Ordinal numbers such as "first," "second," and "third" are only used to identify similar elements, and different ordinal numbers may be employed in the specification and claims of the present disclosure. The term "at least one" element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0046] Like reference numerals refer to like or similar elements. Unless otherwise specified, elements with like reference numerals are considered to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. If two or more elements do not contact each other directly, the two elements are "separated" from each other or "separated" from one another. As used herein, an element located "on" a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, an element "is directly located on" a second element if there is physical contact between the surface of the element and the surface of the second element. As used herein, an element "is electrically connected to" a second element if there is an electrical conduction path composed of at least one conductive material between the element and the second element. As used herein, a "prototype" structure or "in-process" structure refers to an instantaneous structure in which the shape or composition of at least one component is subsequently modified.

[0047] As used herein, a "layer" refers to a portion of a material including a region having a thickness. The layer may extend over the entire underlying or overlying structure, or the extent may be less than the extent of the underlying or overlying structure. Further, the layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes thereat. The layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below it.

[0048] Generally, a semiconductor die or semiconductor package may include memory chips. Each semiconductor package contains one or more dies (e.g., one, two, or four). A die is the smallest unit capable of independently executing commands or reporting status. Each die contains one or more planes (usually one or two). The same concurrent operations may occur on each plane, although there are some limitations. Each plane contains a plurality of blocks, which are the smallest units that can be erased in a single erase operation. Each block contains a number of pages, which is the smallest unit that can be programmed, i.e., the smallest unit on which a read operation can be performed.

[0049] As used herein, a "semiconductor material" refers to a material having a conductivity in the range of 1×10 -5 S / m to 1×10 5 S / m. As used herein, a "semiconductor material" refers to a material having a conductivity in the range of 1×10 -5 S / m to 1 S / m in the absence of electrical dopants, and capable of producing a conductivity in the range of 1 S / m to 1×10 7Doping materials within the range of S / m. As used herein, an "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, a "conductive material" refers to a material with a conductivity greater than 1×10 5 S / m. As used herein, an "insulating material" or "dielectric material" refers to a material with a conductivity less than 1×10 -5 S / m. As used herein, a "heavily doped semiconductor material" refers to a semiconductor material doped with an electrical dopant at a high enough atomic concentration to become a conductive material, which is formed as a crystalline material or if transformed into a crystalline material through an annealing process (e.g., from an initial amorphous state), i.e., providing a conductivity greater than 1×10 5 S / m. A "doped semiconductor material" can be a heavily doped semiconductor material or can be a semiconductor material including an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) providing a concentration within the range of 1×10 -5 S / m to 1×10 7 S / m. An "intrinsic semiconductor material" refers to a semiconductor material not doped with an electrical dopant. Thus, a semiconductor material can be semi-conductive or conductive and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semi-conductive or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, a "metallic material" refers to a conductive material including at least one metallic element. All conductivity measurements are performed under standard conditions.

[0050] Reference Figure 1 , shows a first exemplary structure according to a first embodiment of the present disclosure. The first exemplary structure includes a carrier substrate 9, which can be a semiconductor substrate or a conductive substrate. For example, the carrier substrate 9 can include a commercially available silicon wafer. Alternatively, the carrier substrate 9 can include any material that can selectively remove the insulating layer 32 and the dielectric material portion to be formed subsequently. In the case where the carrier substrate 9 includes silicon (e.g., a single-crystalline silicon wafer), at least the top surface portion of the carrier substrate 9 can be doped with boron to act as an etch stop and prevent collateral etching during subsequent etching steps. The boron atom concentration in at least the boron-doped portion of the carrier substrate 9 (or throughout the carrier substrate) can be at least 1×10 19 / cm 3 , such as within the range from 5×10 19 / cm 3 to 2×10 21 / cm 3 , such as from 1×10 20 / cm 3 to 1×10 21 / cm 3, but smaller or larger thicknesses can also be employed.

[0051] An embedded insulating layer 12 can be formed on the top surface of the carrier substrate 9. The embedded insulating layer 12 includes an insulating material such as silicon oxide, and the thickness can range from 10 nm to 200 nm, such as from 20 nm to 100 nm, but smaller and larger thicknesses can also be employed. The embedded insulating layer 12 can be deposited on the carrier substrate 9 by chemical vapor deposition, atomic layer deposition, or sputtering deposition. Alternatively, if the carrier substrate 9 includes a silicon substrate, the embedded insulating layer 12 can be formed by oxidizing the upper surface of the carrier substrate 9.

[0052] A semiconductor material layer 14 can be formed above the embedded insulating layer 12. The semiconductor material layer 14 includes a semiconductor material and / or consists essentially of a semiconductor material, which can be an elemental semiconductor material such as silicon or germanium, or a compound semiconductor material such as a silicon-germanium or III-V compound semiconductor material. If the carrier substrate 9 includes a semiconductor material, the semiconductor material layer 14 can include a semiconductor material that provides a higher etching rate than the semiconductor material of the carrier substrate 9 during an isotropic etching process.

[0053] For example, if the carrier substrate 9 includes boron-doped silicon, the semiconductor material layer 14 can include undoped (i.e., intrinsic) silicon. In one embodiment, the atomic concentration of the electrical dopant (such residual p-type or n-type dopant) in the semiconductor material layer 14 can be less than 5×10 15 / cm 3 , such as in the range from 1×10 11 / cm 3 to 1×10 15 / cm 3 , such as from 1×10 12 / cm 3 to 1×10 14 / cm 3 . Alternatively, if the carrier substrate 9 includes undoped silicon, the semiconductor material layer 14 can include a silicon-germanium compound semiconductor material (including germanium with an atomic concentration greater than 10%) that can be etched at a higher etching rate than silicon in buffered hydrofluoric acid or in a mixture of nitric acid and hydrofluoric acid.

[0054] The thickness of the semiconductor material layer 14 is less than the lateral dimension (such as the diameter) of the memory opening to be formed subsequently, and greater than twice the thickness of the memory film to be formed therein. In one embodiment, the thickness of the semiconductor material layer 14 can range from 20 nm to 60 nm, such as from 35 nm to 50 nm, but smaller or larger thicknesses can also be employed.

[0055] An insulating layer 32 and a first alternating stack of spacer material layers may be formed over a carrier substrate 9. The spacer material layer may be formed as a sacrificial material layer 42. In a case where a second alternating stack of additional insulating layers and additional spacer material layers is subsequently formed over the first alternating stack to form a multi-layer structure, the first alternating stack is referred to as the first layer alternating stack, and the second alternating stack is referred to as the second layer alternating stack. Figure 1 The first layer alternating stack is shown, and the second layer alternating stack is not shown. In this case, the insulating layer 32 within the first layer alternating stack is referred to herein as the first insulating layer 132, and the spacer material layer (such as the sacrificial material layer 42) within the first layer alternating stack is referred to herein as the first spacer material layer (such as the first sacrificial material layer 142). In one embodiment, the first spacer material layer may include the first sacrificial material layer 142. In this case, a first layer alternating stack (132, 142) of the first insulating layer 132 and the first sacrificial material layer 142 may be formed over the semiconductor material layer 14.

[0056] The first insulating layer 132 includes an insulating material such as undoped silicate glass or doped silicate glass, and the first sacrificial material layer 142 includes a sacrificial material such as silicon nitride or a silicon-germanium alloy. In one embodiment, the first insulating layer 132 may include a silicon oxide layer, and the first sacrificial material layer 142 may include a silicon nitride layer. The first layer alternating stack (132, 142) may include a plurality of repetitions of a unit layer stack including the first insulating layer 132 and the first sacrificial material layer 142. The total number of repetitions of the unit layer stack within the first layer alternating stack (132, 142) may be, for example, in the range from 8 to 1,024, such as from 32 to 256, but fewer and more repetitions may also be employed.

[0057] The thickness of each first insulating layer in the first insulating layer 132 may be in the range from 20 nm to 100 nm (such as from 30 nm to 60 nm), but smaller and larger thicknesses may also be employed. The thickness of each first sacrificial material layer in the first sacrificial material layer 142 may be in the range from 20 nm to 100 nm (such as from 30 nm to 60 nm), but smaller and larger thicknesses may also be employed. The first exemplary structure includes a memory array region 100 and a contact region 300, in which a three-dimensional array of memory elements will be subsequently formed in the memory array region, and a layer contact via structure for contacting word lines will be subsequently formed in the contact region.

[0058] Although embodiments are described in which the first spacer material layer is formed as the first sacrificial material layer 142, in alternative embodiments, the first spacer material layer may be formed as the first conductive layer. In such a case, the processing steps performed to replace the first sacrificial material layer 142 with the first conductive layer may be omitted. Generally, the spacer material layer of the present disclosure may be formed as a conductive layer or may subsequently be replaced with a conductive layer.

[0059] Reference Figure 2 , an optional stepped surface is formed in the contact region 300. As used herein, a "stepped surface" refers to a set of surfaces including at least two horizontal surfaces and at least two vertical surfaces such that each horizontal surface is adjacent to a first vertical surface extending upward from a first edge of the horizontal surface and adjacent to a second vertical surface extending downward from a second edge of the horizontal surface. A first stepped cavity is formed within the volume, removing portions of the first layer alternating stack (132, 142) from the volume by the formation of the stepped surface. A "stepped cavity" refers to a cavity having a stepped surface.

[0060] The first stepped cavity may have various stepped surfaces such that the horizontal cross-sectional shape of the first stepped cavity changes stepwise according to the vertical distance from the top surface of the carrier substrate 9. In one embodiment, the first stepped cavity may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etching process and a second type of etching process, the first type of etching process vertically increasing the depth of the cavity by one or more levels, and the second type of etching process laterally expanding the region vertically etched in the subsequent first type of etching process. As used herein, a "level" of a structure including multiple alternating layers is defined as the relative position of a pair of a first material layer and a second material layer within the structure.

[0061] The stepped surface of the first layer alternating stack (132, 142) extends continuously from the bottommost layer within the first layer alternating stack (132, 142) to the topmost layer within the first layer alternating stack (132, 142).

[0062] A first stepped dielectric material portion 165 (i.e., an insulating fill material portion) can be formed in the first stepped cavity by depositing a dielectric material therein. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. An excess portion of the deposited dielectric material can be removed, for example, by chemical mechanical planarization (CMP) above the top surface of the topmost layer of the first layer alternating stack (132, 142). The remaining portion of the deposited dielectric material that fills the first stepped cavity constitutes the first stepped dielectric material portion 165. As used herein, a "stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that gradually increases or decreases with the vertical distance from the top surface of the substrate on which the element is present. If silicon oxide is used for the first stepped dielectric material portion 165, the silicon oxide of the first stepped dielectric material portion 165 can be doped or can be undoped with dopants such as B, P, and / or F.

[0063] Reference Figure 3 , a first etch mask layer (such as a photoresist layer) can be formed above the first layer alternating stack (132, 142), and it can be lithographically patterned to form openings therein. A first anisotropic etch process can be performed to transfer the pattern of the openings in the first etch mask layer through the first stepped dielectric material portion 165, the first layer alternating stack (132, 142), the semiconductor material layer 14, and the buried insulating layer 12, and optionally into the upper portion of the carrier substrate 9. In the memory array region 100, a first layer memory opening 149 can be formed through the first layer alternating stack (132, 142) and the semiconductor material layer 14, and in the contact region 300, a first layer support opening 119 can be formed through the first stepped dielectric material portion 165, the first layer alternating stack (132, 142), and the semiconductor material layer 14. Each of the first layer memory opening 149 and the first layer support opening 119 can extend vertically into the carrier substrate 9. In one embodiment, the bottom surfaces of the first layer memory opening 149 and the first layer support opening 119 can be formed at or below the top surface of the carrier substrate 9. The diameters of the first layer memory opening 149 and the first layer support opening 119 can be in the range from 40 nm to 400 nm (such as from 80 nm to 200 nm), but smaller and larger thicknesses can be employed. For example, the first etch mask layer can be removed by ashing after the first anisotropic etch process.

[0064] Reference Figure 4, a sacrificial fill material (such as a carbon-based material (e.g., amorphous carbon, diamond-like carbon, or doped carbon material), a high etch rate dielectric material (e.g., borosilicate glass or organosilicate glass), or a polymer material) can be deposited in the first layer memory openings 149 and the first layer support openings 119 by a conformal deposition process. An excess portion of the sacrificial fill material can be removed, for example, by a recess etch process from above the top surface of the first layer alternating stack (132, 142). Each remaining portion of the sacrificial fill material filling the corresponding first layer memory opening 149 constitutes a sacrificial memory opening fill structure 148. Each remaining portion of the sacrificial fill material filling the corresponding first layer support opening 119 constitutes a sacrificial support opening fill structure 118.

[0065] Reference Figure 5 , a second layer alternating stack (232, 242) of a second insulating layer 232 and a second spacer material layer can be formed over the first layer alternating stack (132, 142) and the first stepped dielectric material portion 165. The second insulating layer 232 can be an additional insulating layer 32 having the same material composition and the same thickness range as the first insulating layer 132. The second spacer material layer can be an additional spacer material layer having the same material composition and the same thickness range as the first spacer material layer in the first layer alternating stack (132, 142). In one embodiment, the second spacer material layer can include a second sacrificial material layer 242. In such a case, the second sacrificial material layer 242 can be an additional sacrificial material layer 42 having the same material composition and the same thickness range as the first sacrificial material layer 142.

[0066] The second layer alternating stack (232, 242) can include a plurality of repetitions of a unit layer stack that includes the second insulating layer 232 and the second sacrificial material layer 242. The total number of repetitions of the unit layer stack within the second layer alternating stack (232, 242) can be, for example, in the range from 8 to 1,024, such as from 32 to 256, but fewer and greater numbers of repetitions can also be employed. The thickness of each second insulating layer in the second insulating layer 232 can be in the range from 20 nm to 100 nm (such as from 30 nm to 60 nm), but smaller and greater thicknesses can also be employed. The thickness of each second sacrificial material layer in the second sacrificial material layer 242 can be in the range from 20 nm to 100 nm (such as from 30 nm to 60 nm), but smaller and greater thicknesses can also be employed.

[0067] Although embodiments are described in which the second spacer material layer is formed as the second sacrificial material layer 242, in an alternative embodiment, the second spacer material layer may be formed as the second conductive layer. In such a case, the processing steps performed to replace the second sacrificial material layer 242 with the second conductive layer may be omitted. Generally, the spacer material layer of the present disclosure may be formed as a conductive layer or may subsequently be replaced with a conductive layer.

[0068] An optional stepped surface is formed in the contact region 300 by patterning the second layer alternating stack (232, 242). In a plan view, the stepped surface of the second layer alternating stack (232, 242) may be laterally offset with respect to the stepped surface of the first layer alternating stack (132, 142) towards the memory array region 100. A second stepped cavity is formed within the volume by removing portions of the second layer alternating stack (232, 242) from the volume through the formation of the stepped surface. A "stepped cavity" refers to a cavity having a stepped surface. The second stepped cavity may have various stepped surfaces such that the horizontal cross-sectional shape of the second stepped cavity changes step by step according to the vertical distance from the top surface of the carrier substrate 9. In one embodiment, the second stepped cavity may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etching process and a second type of etching process, the first type of etching process vertically increasing the depth of the cavity by one or more levels, and the second type of etching process laterally expanding the region vertically etched in the subsequent first type of etching process.

[0069] The stepped surface of the second layer alternating stack (232, 242) continuously extends from the bottommost layer within the second layer alternating stack (232, 242) to the topmost layer within the second layer alternating stack (232, 242).

[0070] A second stepped dielectric material portion 265 (i.e., an insulating fill material portion) may be formed in the second stepped cavity by depositing a dielectric material therein. For example, a dielectric material such as silicon oxide may be deposited in the stepped cavity. The excess portion of the deposited dielectric material may be removed, for example, by chemical mechanical planarization (CMP) above the top surface of the topmost layer of the second layer alternating stack (232, 242). The remaining portion of the deposited dielectric material filling the second stepped cavity constitutes the second stepped dielectric material portion 265. If silicon dioxide is used for the second stepped dielectric material portion 265, the silicon dioxide of the second stepped dielectric material portion 265 may or may not be doped with dopants such as B, P, and / or F. The combination of the first stepped dielectric material portion 165 and the second stepped dielectric material portion 265 may be collectively referred to as the reverse stepped dielectric material portion 65.

[0071] Reference Figure 6, a second etch mask layer (such as a photoresist layer) can be formed over the second alternating stack (232, 242), and the second etch mask layer can be lithographically patterned to form openings therein. A second anisotropic etch process can be performed to transfer the pattern of the openings in the second etch mask layer through the second stepped dielectric material portion 265 and the second alternating stack (232, 242). In the memory array region 100, the second layer memory openings 249 can be formed directly on the top surface of the corresponding sacrificial memory opening fill structures 148 through the second alternating stack (232, 242). In the contact region 300, the second layer support openings 219 can be formed directly on the top surface of the corresponding sacrificial support opening fill structures 118 through the second stepped dielectric material portion 265 and the second alternating stack (232, 242). The diameter of each of the second layer memory openings 249 and the second layer support openings 219 can be approximately the same as the diameter of the corresponding underlying sacrificial opening fill structures (148, 118). For example, the second etch mask layer can be removed by ashing after the second anisotropic etch process.

[0072] Reference Figure 7A and Figure 7B , the sacrificial memory opening fill structures 148 and the sacrificial support opening fill structures 118 can be selectively removed for the materials of the second alternating stack (232, 242), the first alternating stack (132, 142), the stepped dielectric material portion 65, the semiconductor material layer 14, the buried insulating layer 12, and the carrier substrate 9. In an illustrative example, if the sacrificial memory opening fill structures 148 and the sacrificial support opening fill structures 118 include a carbon-based material, an ashing process can be performed to remove the sacrificial memory opening fill structures 148 and the sacrificial support opening fill structures 118. The interlayer memory openings 49 (which are also referred to as memory openings 49) can be formed through the second alternating stack (232, 242), the first alternating stack (132, 142), the semiconductor material layer 14, and the buried insulating layer 12, and optionally into the upper portion of the carrier substrate 9. The interlayer support openings 19 (which are also referred to as support openings 19) can be formed through the stepped dielectric material portion 65, at least through the first alternating stack (132, 142) and optionally through the second alternating stack (232, 242), and through the semiconductor material layer 14 and the buried insulating layer 12, and optionally into the upper portion of the carrier substrate 9.

[0073] In summary, in the first exemplary structure, a semiconductor material layer 14 may be formed over a carrier substrate 9, and at least one alternating stack of an insulating layer 32 and a spacer material layer (such as a sacrificial material layer 42) may be formed over the semiconductor material layer 14. The spacer material layer is formed as a conductive layer or is subsequently replaced by a conductive layer (in the case of being formed as a sacrificial material layer 42). Memory openings 49 may be formed through the alternating stack (32, 42) in the memory array region 100. The alternating stack (32, 42) may include a single-layer structure that includes a single stepped dielectric material portion, or may include a multi-layer structure that includes a first alternating stack (132, 142) and a first stepped dielectric material portion 165 as a first-layer structure, and a second alternating stack (232, 242) and a second stepped dielectric material portion 265 as a second-layer structure, and optionally includes an additional layer structure (not shown) formed over the second-layer structure.

[0074] Each of the memory openings 49 in the memory openings 49 may extend at least vertically to the top surface of the carrier substrate 9. In one embodiment, the bottom surface of the memory opening 49 may be formed at or below the top surface of the carrier substrate 9. Each cluster of memory openings 49 may include multiple rows of memory openings 49. Each row of memory openings 49 may include a plurality of memory openings 49 arranged at a uniform pitch along a first horizontal direction hd1. The rows of memory openings 49 may be laterally spaced from each other along a second horizontal direction hd2 that may be perpendicular to the first horizontal direction hd2. In one embodiment, each cluster of memory openings 49 may be formed as a two-dimensional periodic array of memory openings 49. The diameter of the memory openings 49 may be in the range from 60 nm to 400 nm (e.g., from 120 nm to 300 nm), but smaller and larger thicknesses may be employed. In an alternative embodiment, support openings 19 are formed simultaneously with the memory openings 49 using the same patterned photoresist layer.

[0075] Figures 8A to 8G is a sequential vertical cross-sectional view of the memory openings 49 during the formation of the memory opening fill structure 58 in the first exemplary structure according to the first embodiment of the present disclosure. During Figures 8A to 8G the processing steps of, similar structural changes may occur in every other memory opening 49 and in each of the support openings 19.

[0076] Reference Figure 8A, an isotropic etching process (such as a selective wet etching process) can be performed that selectively etches the material of the semiconductor material layer 14 for the physically exposed portions of the carrier substrate 9 underlying the memory openings 49 and the support openings 19. As used herein, if the etching rate of the etching process for a first material is at least three times the etching rate for a second material, the etching process selectively etches the first material with respect to the second material. In some embodiments, the etching rate of the isotropic etching process for the material of the semiconductor material layer 14 can be at least 5 times and / or at least 10 times the etching rate for the material of the carrier substrate 9.

[0077] For example, if the semiconductor material layer 14 comprises an undoped semiconductor material (such as undoped polysilicon or undoped amorphous silicon), and if at least an upper portion of the carrier substrate 9 comprises boron-doped silicon, the isotropic etching process can comprise an NC2 wet etching process, which is a wet etching process using a mixture of nitric acid and hydrofluoric acid and selectively etches undoped silicon with respect to heavily boron-doped silicon. In another embodiment, if the carrier substrate 9 comprises doped or undoped silicon, and if the semiconductor material layer 14 comprises a silicon-germanium alloy comprising germanium with an atomic concentration greater than 10%, a wet etching process using buffered hydrofluoric acid or a mixture of nitric acid and hydrofluoric acid can be used for the isotropic etching process. Alternatively, an alkaline solution such as KOH can be used to perform the isotropic etching process.

[0078] The isotropic etching process causes the physically exposed cylindrical sidewalls of the semiconductor material layer 14 to be isotropically recessed to form an annular cavity 13 around each memory opening 49 and around each support opening 19. The lateral recess distance of the semiconductor material layer 14 of the isotropic etching process can be less than half of the lateral spacing between adjacent pairs of memory openings 49 and less than half of the lateral spacing between adjacent pairs of support openings 19.

[0079] In summary, an annular cavity 13 can be formed around the bottom portion of each memory opening 49 at the level of the semiconductor material layer 14. In one embodiment, each annular cavity 13 can be formed by laterally recessing an annular portion of the semiconductor material layer 14 around the corresponding memory opening 49.

[0080] Reference Figure 8B, a memory film 50 including a memory material layer 54 can be deposited conformally. In an illustrative example, the memory film 50 can include an optional barrier dielectric layer 52, a memory material layer 54, and an optional dielectric liner 56. The memory material layer 54 includes a memory material, that is, a material in which data bits can be stored. The memory material layer 54 can include a charge storage material (such as silicon nitride), a ferroelectric material, a phase change memory material, or any other memory material that can store data bits by inducing a change in resistivity, ferroelectric polarization, or any other measurable physical property. In the case where the memory material layer 54 includes a charge storage material, the optional dielectric liner 56 can include a tunneling dielectric layer. The memory film 50 is formed on the exposed surfaces of the memory openings 49 and the annular cavity 13.

[0081] Reference Figure 8C , a conformal semiconductor deposition process can be performed to deposit a semiconductor fill material in the annular cavity 13 and in the peripheral portions of each of the memory openings 49. The deposited semiconductor fill material forms a semiconductor fill material layer 160L. The semiconductor fill material layer 160L can include an undoped semiconductor material (i.e., a semiconductor material that does not include any intentionally introduced electrical dopants, such as silicon), or a doped semiconductor material having a conductivity type opposite to that of the subsequently formed vertical semiconductor channel, such as phosphorus-doped silicon. For example, if the subsequently formed vertical semiconductor channel is doped with a first conductivity type, the semiconductor fill material layer 160L can be undoped or doped with a second conductivity type opposite to the first conductivity type. If the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. If the semiconductor fill material layer 160L is doped with a second conductivity type, the atomic concentration of the dopant of the second conductivity type in the semiconductor fill material layer 160L can be in the range from 1×10 14 / cm 3 to 1×10 21 / cm 3 , such as from 1×10 16 / cm 3 to 1×10 20 / cm 3 , but smaller or larger atomic concentrations can also be employed. The thickness of the semiconductor fill material layer 160L can be less than half the diameter of each memory opening 49 and can be less than half the diameter of each support opening 19. In this case, cavities can exist within each memory opening 49 and within each support opening 19.

[0082] Reference Figure 8D, at least one etching process can be performed to remove portions of the semiconductor fill material layer 160L that are located outside the annular cavity 13. The at least one etching process can include an anisotropic etching process (such as a reactive ion etching process or a chemical dry etching process). Each remaining portion of the semiconductor fill material layer 160L that fills the volume of the corresponding annular cavity 13 constitutes an annular semiconductor structure 160, such as an annular silicon structure. In one embodiment, the anisotropic etching process removes portions of the semiconductor fill material layer 160L that are close to the vertical sidewalls of the memory film 50. In this case, each annular semiconductor structure 160 can include a corresponding inner cylindrical sidewall that is vertically coincident with the inner sidewall of the memory film 50. As used herein, if a second surface overlies or underlies a first surface and if there is a vertical plane that includes the first surface and the second surface, then the first surface and the second surface are vertically coincident with each other.

[0083] Reference Figure 8E , a selective semiconductor deposition process can be performed to grow a doped semiconductor material from the physically exposed cylindrical surfaces of the annular semiconductor structures 160 while suppressing the growth of the doped semiconductor material from physically exposed dielectric surfaces (such as the physically exposed surface of the memory film 50) (e.g., from the physically exposed surface of the dielectric liner 56, which can be a tunneling dielectric layer). A selective deposition process is a deposition process that grows material from a first type of surface while suppressing the deposition of material from a second type of surface. A selective semiconductor deposition process is a deposition process in which a semiconductor material (e.g., silicon) grows from a first type of surface (such as a physically exposed semiconductor (e.g., silicon) surface), while the deposition of the semiconductor material from a second type of surface (such as an insulating surface) is suppressed.

[0084] The selective semiconductor deposition process forms a semiconductor core structure 161, such as an n-type (e.g., phosphorus) doped silicon core structure, on the inner sidewalls of each annular semiconductor structure 160. The duration of the selective semiconductor deposition process can be selected such that the growth surfaces of the semiconductor material of the semiconductor core structure 161 merge in the central portion to form a central seam CS.

[0085] According to one aspect of the present disclosure, the selective semiconductor deposition process can be performed with in-situ doping of a dopant (e.g., phosphorus) of a second conductivity type (e.g., n-type). The atomic concentration of the dopant of the second conductivity type in the semiconductor core structure 161 can be at least 1×10 19 / cm 3 , such as in the range from 5×10 19 / cm 3 to 2×10 21 / cm 3 , such as from 1×10 20 / cm 3from 1×10 21 / cm 3 , but smaller or larger atomic concentrations may also be employed. In an illustrative example, if the subsequently formed vertical semiconductor channel comprises silicon doped with a p-type dopant such as boron, the semiconductor core structure 161 comprises silicon doped with an n-type dopant such as phosphorus or arsenic. The semiconductor core structure 161 forms a p-n junction with the subsequently formed vertical semiconductor channel and thus serves as a component of the subsequently formed source structure. Controlling the duration of the selective semiconductor deposition process allows controlling the position of the top surface of the semiconductor core structure 161 and thus allows controlling the height of the subsequently formed p-n junction.

[0086] In one embodiment, each semiconductor core structure 161 may include a central seam CS extending vertically from the center of its top surface to the center of its bottom surface. In one embodiment, each semiconductor core structure 161 includes a wavy top surface having a periphery that bulges above the center point of the wavy top surface (located above the central seam). In one embodiment, the wavy top surface of each semiconductor core structure 161 includes two convex surfaces that meet at the center. In one embodiment, each semiconductor core structure 161 projects downward below the horizontal plane of the bottom surface of the annular semiconductor structure 160. In one embodiment, the semiconductor core structure 161 includes a wavy bottom surface having a periphery located below the center point of the wavy bottom surface.

[0087] In one embodiment, each semiconductor core structure 161 includes a wavy top surface having a lowest point at its center. In one embodiment, each semiconductor core structure 161 includes a wavy bottom surface having a highest point at its center. In one embodiment, the memory membrane 50 includes a vertically extending portion and a laterally protruding portion, the vertically extending portion extending vertically through the alternating stacks (32, 42), the laterally protruding portion adjoining the bottom end of the vertically extending portion and protruding laterally outward from the bottom end of the vertically extending portion and laterally surrounding the annular semiconductor structure 160. In one embodiment, the semiconductor material layer 14 does not contact the annular semiconductor structure 160 and is laterally spaced from the annular semiconductor structure by the laterally protruding portion of the memory membrane 50. The semiconductor material layer 14 may laterally surround each of the annular semiconductor structures in the annular semiconductor structure 160. Depending on the height of the semiconductor core structure 161, an optional cavity (e.g., an air gap) 69 may be located between the bottom surface of the semiconductor core structure 161 and the bottom surface of the memory membrane 50 at the bottom of the memory opening 49.

[0088] Reference Figure 8F, by performing a conformal deposition process, a semiconductor channel material layer 60L can be deposited on each semiconductor core structure in the memory film 50 and the semiconductor core structure 161. In one embodiment, the semiconductor channel material layer 60L can include silicon (e.g., polysilicon or amorphous silicon), which is intrinsic or intentionally doped with a dopant of a first conductivity type (e.g., p-type) opposite to the second conductivity type. The atomic concentration of the dopant of the first conductivity type in the semiconductor channel material layer 60L can be in the range from 1×10 12 / cm 3 to 3.0×10 17 / cm 3 , such as from 1×10 14 / cm 3 to 3.0×10 16 / cm 3 , but smaller and larger atomic concentrations can also be employed. The thickness of the semiconductor channel material layer 60L can be in the range from 3 nm to 60 nm, such as from 6 nm to 30 nm, but smaller and larger thicknesses can also be employed. In one embodiment, each portion of the semiconductor channel material layer 60L located within the respective memory opening 49 can include a wavy bottom surface that includes two concave surfaces contacting two corresponding convex surfaces of the semiconductor core structure 161. The wavy bottom surface of the semiconductor channel material layer 60L protrudes downward into the recess at the center seam between two corresponding convex surfaces of the semiconductor core structure 161. A p-n junction can be formed at each interface between the semiconductor channel material layer 60L and each semiconductor core structure in the semiconductor core structure 161.

[0089] A dielectric core layer including a dielectric fill material (such as silicon oxide) can be deposited in the remaining volume of the memory opening 49. The dielectric core layer can be vertically recessed such that each remaining portion of the dielectric core layer has a top surface at or near the horizontal plane of the bottom surface of the topmost insulating layer 32. Each remaining portion of the dielectric core layer constitutes the dielectric core 62.

[0090] Referring Figure 8G , a doped semiconductor material having a second conductivity type (e.g., n-type) can be deposited in each recessed region above the dielectric core 62. The dopant concentration in the deposited semiconductor material can be in the range from 5×10 18 / cm 3 to 2×10 21 / cm 3within a range, but smaller or larger dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon. Excess portions of the doped deposited semiconductor material having a second conductivity type, horizontal extension portions of the semiconductor channel layer 60L, and horizontal extension portions of the memory film 50 can be removed, for example, by chemical mechanical planarization (CMP) or recess etching processes above the horizontal plane of the top surface of the topmost layer including the alternating stack (32, 42). Each remaining portion of the doped semiconductor material having a second conductivity type constitutes a drain region 63. Each remaining portion of the semiconductor channel layer 60L (which has doping of a first conductivity type) constitutes a vertical semiconductor channel 60.

[0091] Each adjacent combination of the memory film 50 and the vertical semiconductor channel 60 constitutes a memory stack structure 55. All groups of material portions that continuously combine to fill the memory opening 49 and the annular cavity 13 constitute a memory opening filling structure 58. All groups of material portions that continuously combine to fill the support opening 19 and the annular cavity 13 constitute a support pillar structure. Each memory opening filling structure 58 can be located in the memory opening 49 and can include the memory film 50, the vertical semiconductor channel 60, and a semiconductor capping structure (160, 161) that includes a semiconductor core structure 161 contacting the bottom end of the vertical semiconductor channel 60 and further includes an annular semiconductor structure 160 that laterally surrounds the semiconductor core structure 161. In one embodiment, the annular semiconductor structure 160 has a smaller vertical extent than the semiconductor core structure 161.

[0092] Reference Figure 9A and Figure 9B illustrates a first exemplary structure after forming the memory opening filling structure 58 within the memory opening 49 and forming the support pillar structure 20 within the support opening 19. Each support pillar structure within the support pillar structure 20 can have the same set of materials as the memory opening filling structure 58.

[0093] In an alternative embodiment, the second layer memory opening 249 shown can be filled with additional sacrificial material, a cavity can be formed within the support opening 19, and a dielectric filling material (such as silicon oxide) can be deposited within the support opening 19 to form a dielectric support pillar structure within the support opening 19 while filling the memory opening 49 with a sacrificial filling material. In this case, a dielectric support pillar structure can be formed to replace Figure 6 the support pillar structure shown in Figure 9A and Figure 9B and the sacrificial filling material within the memory opening 49 can then be removed and reference Figures 8A to 8GThe described processing steps form a memory opening fill structure 58 in a corresponding memory opening 49. Thus, in an alternative embodiment, the support pillar structure 20 can consist essentially of at least one dielectric material such as silicon oxide.

[0094] Reference Figure 10A and Figure 10B , a dielectric material such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass can be deposited over the alternating stack (32, 42) to form a contact-level dielectric layer 80. The thickness of the contact-level dielectric layer 80 can be in the range from 100 nm to 600 nm, such as from 200 nm to 400 nm, but smaller and larger thicknesses can also be employed.

[0095] A photoresist layer (not shown) can be applied over the contact-level dielectric layer 80 and can be lithographically patterned to form elongated openings that laterally extend between adjacent clusters of the memory opening fill structure 58 along a first horizontal direction hd1. An anisotropic etching process can be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer 80, the alternating stack (32, 42), and the stepped dielectric material portion 65, and at least transfer to the top surface of the carrier substrate 9. Lateral isolation trenches 79 that laterally extend along the first horizontal direction hd1 can be formed through the alternating stack (32, 42), the stepped dielectric material portion 65, and the contact-level dielectric layer 80. Each of the lateral isolation trenches 79 in the lateral isolation trenches can include a corresponding pair of longitudinal sidewalls that are parallel to the first horizontal direction hd1 and vertically extend from the carrier substrate 9 to the top surface of the contact-level dielectric layer 80. The surface of the carrier substrate 9 can be physically exposed under each lateral isolation trench 79. Subsequently, the photoresist layer can be removed, for example, by ashing.

[0096] Reference Figure 11 , an etchant that selectively etches the material of the sacrificial material layer 42 with respect to the materials of the insulating layer 32, the semiconductor material layer 14, and the carrier substrate 9 can be introduced into the trenches 79, for example, using an isotropic etching process. Lateral recesses 43 are formed in the volume where the sacrificial material layer 42 is removed. The sacrificial material layer 42 can be selectively removed with respect to the material of the insulating layer 32, the material of the stepped dielectric material portion 65, and the outermost layer of the memory film 50. In one embodiment, the sacrificial material layer 42 can include silicon nitride, and the materials of the insulating layer 32 and the stepped dielectric material portion 65 can include silicon oxide.

[0097] The etching process for selectively removing the second material from the first material and the outermost layer of the memory film 50 can be a wet etching process using a wet etching solution, or it can be a vapor (dry) etching process, where the etchant is introduced into the trench 79 in a vapor phase. For example, if the sacrificial material layer 42 includes silicon nitride, the etching process can be a wet etching process, where the first exemplary structure is immersed in a wet etching bath including phosphoric acid, and the wet etching bath selectively etches silicon nitride with respect to silicon oxide, silicon, and various other materials used in the art. The support pillar structure 20, the stepped dielectric material portion 65, and the memory stack structure 55 provide structural support, while the lateral recess 43 exists within the volume previously occupied by the sacrificial material layer 42.

[0098] Each lateral recess 43 can be a laterally extending cavity, and its lateral dimension is greater than the vertical extent of the cavity. In other words, the lateral dimension of each lateral recess 43 can be greater than the height of the lateral recess 43. A plurality of lateral recesses 43 can be formed in the volume of the second material from which the sacrificial material layer 42 is removed. Compared with the lateral recess 43, the memory opening in which the memory stack structure 55 is formed is referred to herein as a front-side opening or a front-side cavity.

[0099] Each lateral recess 43 among the plurality of lateral recesses 43 can extend substantially parallel to the top surface of the carrier substrate 9. The lateral recess 43 can be vertically defined by the top surface of the underlying insulating layer 32 and the bottom surface of the overlying insulating layer 32. In one embodiment, each lateral recess 43 can always have a consistent height.

[0100] Reference Figure 12 , an external blocking dielectric layer ( Figure 12 not explicitly shown in ) can be optionally formed. The external blocking dielectric layer (if present) includes a dielectric material that serves as a control gate dielectric for the control gate that will be formed in the lateral recess 43 subsequently.

[0101] When the blocking dielectric layer 52 is present in each memory opening, the external blocking dielectric layer is optional. In the case where the blocking dielectric layer 52 is omitted, there is an external blocking dielectric layer.

[0102] At least one conductive material can be deposited in the lateral recess 43 by providing at least one reactive gas into the lateral recess 43 via the access trench 79. A metal barrier layer can be deposited in the lateral recess 43. The metal barrier layer includes a conductive metal material, which can be used as a diffusion barrier layer and / or an adhesion promoting layer for a subsequently deposited metal fill material. The metal barrier layer can include a conductive metal nitride material, such as TiN, TaN, WN, or a stack thereof, or can include a conductive metal carbide material, such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metal barrier layer can be deposited by a conformal deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier layer can be in the range of 2 nm to 8 nm, such as from 3 nm to 6 nm, but smaller and larger thicknesses can also be employed. In one embodiment, the metal barrier layer can consist essentially of a conductive metal nitride such as TiN.

[0103] A metal fill material is deposited in the plurality of lateral recesses 43, on the sidewalls of at least one access trench 79, and above the top surface of the contact-level dielectric layer 80 to form a metal fill material layer. The metal fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metal fill material layer can consist essentially of at least one elemental metal. The at least one elemental metal of the metal fill material layer can be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metal fill material layer can consist essentially of a single elemental metal. In one embodiment, a fluorine-containing precursor gas, such as WF6, can be employed to deposit the metal fill material layer. In one embodiment, the metal fill material layer can be a tungsten layer including residual levels of fluorine atoms as impurities. The metal fill material layer is separated from the insulating layer 32 and the memory stack structure 55 by the metal barrier layer, which is a metal barrier layer that blocks the diffusion of fluorine atoms therethrough.

[0104] A plurality of conductive layers 46 can be formed in the plurality of lateral recesses 43, and a continuous metal material layer can be formed on the sidewalls of each access trench 79 and above the contact-level dielectric layer 80. Each conductive layer 46 includes a portion of the metal barrier layer and a portion of the metal fill material layer, which are located between a vertically adjacent pair of dielectric material layers, such as a pair of insulating layers 32. The continuous metal material layer includes a continuous portion of the metal barrier layer and a continuous portion of the metal fill material layer, and the continuous portion of the metal barrier layer and the continuous portion of the metal fill material layer are located in the access trench 79 or above the contact-level dielectric layer 80.

[0105] By performing an isotropic etching process for etching at least one conductive material of the continuous conductive material layer, the deposited metal material of the continuous conductive material layer is etched back from the sidewalls of each of the access trenches 79 and from above the contact-level dielectric layer 80. Each remaining portion of the metal material deposited in the lateral recesses 43 constitutes a conductive layer 46. Each conductive layer 46 can be a wire structure. Thus, the sacrificial material layer 42 is replaced by the conductive layer 46. Generally, the conductive layer 46 can be formed by supplying a metal precursor gas into the lateral isolation trenches 79 and the lateral recesses 43.

[0106] At least one uppermost conductive layer 46 can include a drain-side select gate electrode. At least one lowermost conductive layer 46 can include a source-side select gate electrode. The remaining conductive layers 46 can include word lines. Each word line serves as a common control gate electrode for a plurality of vertical NAND strings (e.g., memory opening fill structures 58).

[0107] Reference Figure 13A and Figure 13B As shown in and, a dielectric fill material (such as silicon oxide) can be deposited in the lateral isolation trenches 79. The excess portion of the dielectric fill material can be removed from above the contact-level dielectric layer 80. Each remaining portion of the dielectric fill material filling a corresponding one of the lateral isolation trenches 79 constitutes a lateral isolation trench fill structure 76, which can be a dielectric wall structure. In an alternative embodiment, an insulating spacer having a tubular configuration can be formed in the peripheral portion of each of the lateral isolation trenches 79, and a through-stack conductive via structure can be formed within a corresponding one of the insulating spacers. In this case, each lateral isolation trench fill structure 76 can include a combination of a through-stack conductive via structure and an insulating spacer laterally surrounding the through-stack conductive via structure.

[0108] Contact via structures (88, 86) can be formed through the contact-level dielectric layer 80 and optionally through the stepped dielectric material portion 65. For example, a drain contact via structure 88 can be formed through the contact-level dielectric layer 80 over each drain region 63. A layer contact via structure 86 can be formed through the contact-level dielectric layer 80 and through the stepped dielectric material portion 65 over the conductive layer 46.

[0109] Reference Figure 14, an additional dielectric material layer and an additional metal interconnect structure can be formed over the contact-level dielectric layer 80. The additional dielectric material layer can include at least one via-level dielectric layer, at least one additional line-level dielectric layer, and / or at least one additional line and via-level dielectric layer. The additional metal interconnect structure can include a metal via structure, a metal line structure, and / or an integrated metal line and via structure. The additional dielectric material layer formed over the contact-level dielectric layer 80 is referred to herein as the memory-side dielectric material layer 960. The additional metal interconnect structures are collectively referred to as the memory-side dielectric material layer 960. The memory-side dielectric material layer 960 includes a bit-line-level dielectric material layer embedding bit lines, which are a subgroup of the memory-side metal interconnect structures 980.

[0110] A metal bonding pad (referred to herein as the upper bonding pad 988) can be formed at the topmost level of the memory-side dielectric material layer 960. The upper bonding pad 988 can be electrically connected to the memory-side metal interconnect structure 980 and various nodes of the three-dimensional memory array, including the conductive layer 46 and the memory opening fill structure 58. Thus, the memory die 900 can be provided.

[0111] The memory-side dielectric material layer 960 is formed over the alternating stack (32, 46). The memory-side metal interconnect structure 980 is embedded in the memory-side dielectric material layer 960. The memory-side bonding pad 988 can be embedded within the memory-side dielectric material layer 960, and specifically, within the topmost layer among the memory-side dielectric material layers 960. The memory-side bonding pad 988 can be electrically connected to the memory-side metal interconnect structure 980.

[0112] In one embodiment, the memory die 900 can include: a three-dimensional memory array underlying a first dielectric material layer 110 and including an alternating stack (32, 46) of an insulating layer 32 and a conductive layer 46; a two-dimensional array of memory openings 49 extending vertically through the alternating stack (32, 46); and a two-dimensional array of memory opening fill structures 58 located in the two-dimensional array of memory openings 49 and including corresponding vertical memory element stacks and corresponding vertical semiconductor channels 60; and a two-dimensional array of contact via structures (such as drain contact via structures 88) overlying the three-dimensional memory array and electrically connected to a corresponding one of the vertical semiconductor channels in the vertical semiconductor channels 60.

[0113] Reference Figure 15, a logic die 700 can be provided. The logic die 700 includes a logic-side substrate 709, a peripheral circuit 720 located on the logic-side substrate 709 and including logic-side semiconductor devices (such as field effect transistors), a logic-side metal interconnect structure 780 embedded in a logic-side dielectric material layer 760, and a logic-side bonding pad 778. The peripheral circuit 720 can be configured to control the operation of a memory array within the memory die 900. Specifically, the peripheral circuit 720 can be configured to drive various electrical components within the memory array, including (but not limited to) the conductive layer 46, the drain region 63, and the subsequently formed source contact structure. The peripheral circuit 720 can be configured to control the operation of the vertical memory element stacks within the memory array in the memory die 900.

[0114] Reference Figure 16 , the logic die 700 can be attached to the memory die 900, for example, by bonding the logic-side bonding pad 788 to the memory-side bonding pad 988 at the bonding interface. The bonding between the memory die 900 and the logic die 700 can be performed using a wafer-to-wafer bonding process, in which a two-dimensional array of the memory die 900 is bonded to a two-dimensional array of the logic die 700 through a die-to-bonding process or through a die-to-die bonding process. The logic-side bonding pad 788 within each logic die 700 can be bonded to the memory-side bonding pad 988 within the corresponding memory die 900.

[0115] Reference Figure 17 , at least a backside portion of the carrier substrate 9 can be removed, for example, by grinding, polishing, cutting, an isotropic etching process, and / or an anisotropic etching process. In one embodiment, after removing the backside of the carrier substrate 9, a thinned carrier substrate 9' can be retained. The thickness of the thinned carrier substrate 9' can range from 0.1 micrometer to 10 micrometers, but smaller and larger thicknesses can also be employed. Alternatively, the entire carrier substrate 9 can be removed during the Figure 17 steps shown.

[0116] Reference Figure 18A and Figure 18B , if the thinned carrier substrate 9' still exists, the thinned carrier substrate can be removed, for example, by performing an etching process that selectively removes the material of the thinned carrier substrate 9' for the material of the buried insulating layer 12. For example, if the thinned carrier substrate 9' includes silicon, a wet etching process using KOH can be performed to selectively remove the thinned carrier substrate 9' for the buried insulating layer 12.

[0117] Subsequently, the buried insulating layer 12 and the bottom portions of each memory film 50 can be selectively removed with respect to the semiconductor material of the semiconductor material layer 14 and the semiconductor top cover structures (160, 161). In an illustrative example, the buried insulating layer 12 and the bottom portions of the memory films 50 can be removed by performing an isotropic etching process (such as a wet etching process using dilute hydrofluoric acid or a chemical dry etching process). The bottom surface of the semiconductor material layer 14 and the bottom surfaces of the semiconductor top cover structures (160, 161) can act as etch stoppers and are exposed after the isotropic etching process.

[0118] As Figure 18B shown, the backside surface 162 of each semiconductor top cover structure (160, 161) can include the planar annular horizontal backside surface 160H of the annular semiconductor structure 160, the cylindrical vertical surface section 161V of the semiconductor core section 161, and the wavy bottom surface 161B of the semiconductor core section 161 having two opposing convex surfaces 161C1 and 161C2 that meet at a recess 161R above the central seam CS of the semiconductor core section 161. In one embodiment, the cylindrical vertical surface section 14V of the semiconductor material layer 14 can be physically exposed around each opening 15 of the semiconductor material layer 14 through the corresponding memory opening filling structure 58. The cylindrical vertical surface section 14V abuts the edge of the horizontal backside surface 14H of the semiconductor material layer 14. The external barrier dielectric layer 44 embedding the conductive layer 46 is clearly shown.

[0119] In Figure 18C an alternative configuration of the first exemplary structure shown, the horizontal portion 50H of the memory film 50 covering the horizontal bottom surface 160H of the annular semiconductor structure 160 is not removed. In this alternative configuration, the annular semiconductor structure 160 is not exposed after the buried insulating layer 12 is removed.

[0120] Referring Figure 19 to, at least one conductive material can be deposited on the physically exposed backside surface of the semiconductor material layer 14 and on the physically exposed backside surface 162 of the semiconductor top cover structures (160, 161) to form the source layer 16. In one embodiment, the source layer 16 can include at least one conductive material. In one embodiment, the at least one metal material can include a metal barrier material (such as TiN, TaN, WN, MoN, TiC, TaC, or WC) and a highly conductive metal material (such as Cu, Mo, Co, Ru, W, etc.).

[0121] Referring Figure 20A and Figure 20B, the source layer 16 can be patterned, for example, by a combination of a photolithography method and at least one etching process. A backside insulating layer 34 can be formed over the patterned source layer 16. At least one source contact structure (36, 38) can be optionally formed through the backside insulating layer 34 on the backside surface of the source layer 16. Each source contact structure (36, 38) can include a metal via structure 36 and a metal pad structure 38. The metal pad structure 38 can be used as a bonding pad for C4 bonding or wire bonding. Alternatively or additionally, the patterned source layer 16 can be controlled by a corresponding source control circuit in the logic die 700 using interconnects (not shown) that extend through the memory die 900.

[0122] In a configuration derived from Figure 18B the configuration of Figure 20B , the source layer 16 is formed on the exposed surfaces 161V and 161B of the semiconductor core structure 161 and on the horizontal backside surface 160H of the annular semiconductor structure 160. In this configuration, the source layer 16 contacts the bottom surfaces 162 of the semiconductor core structure 161 and the annular semiconductor structure 160. In one embodiment, the source layer 16 contacts the horizontal backside surface 14H of the semiconductor material layer 14 and the vertical surface segments 14V of the sidewalls of the openings 15 in the semiconductor material layer 14.

[0123] In an alternative configuration derived from Figure 18C the configuration of Figure 20C , the source layer 16 is formed on the exposed surfaces 161V and 161B of the semiconductor core structure 161, but not on the horizontal backside surface 160H of the annular semiconductor structure 160. Instead, the source layer 16 is formed on the horizontal portion 50H of the memory film 50 that covers the horizontal backside surface 160H of the annular semiconductor structure 160. Thus, in this alternative configuration, the source layer 16 contacts the semiconductor core structure 161 but does not contact the annular semiconductor structure 160. In one embodiment, the source layer 16 contacts the horizontal backside surface 14H of the semiconductor material layer 14, but does not contact the vertical surface segments of the semiconductor material layer 14.

[0124] Referring to Figure 21 , it can be derived from Figure 3The first exemplary structure leads to a second exemplary structure according to a second embodiment of the present disclosure. The thickness of the semiconductor material layer 14 can be at least 100 nm, such as in the range of 100 nm to 500 nm. The chemical reaction of the anisotropic etching process for etching the materials of the first layer alternating stack (132, 142) can be selected such that the bottom surfaces of the first layer memory opening 149 and the first layer support opening 119 are formed at or below the horizontal plane including the top surface of the semiconductor material layer 14. In other words, in the second embodiment, the first layer memory opening 149 and the first layer support opening 119 extend into or into the semiconductor material layer 14, but do not extend all the way through the semiconductor material layer 14.

[0125] Reference Figure 22 , the processing steps described in reference Figures 4 to 7B can be performed to form the sacrificial opening fill structures (148, 118), form the second level alternating stack of the second insulating layer 232 and the second sacrificial material layer 242 and the stepped surface thereon, the second stepped dielectric material portion 265, and the second level openings (249, 219), and form the memory opening 49 and the support opening 19 by removing the sacrificial opening fill structures (148, 118).

[0126] Figures 23A to 23G is a sequential vertical cross-sectional view of the memory opening 49 during the formation of the memory opening fill structure 58 in the second exemplary structure according to the second embodiment of the present disclosure.

[0127] Reference Figure 23A , an isotropic etching process for selectively etching the semiconductor material of the semiconductor material layer 14 with respect to the materials of the alternating stack (32, 42) can be performed. For example, a wet etching process using trimethyl-2-hydroxyethyl ammonium hydroxide (TMY), tetramethyl ammonium hydroxide (TMAH), or dilute potassium hydroxide can be performed to isotropically etch the semiconductor material of the semiconductor material layer 14 from below the memory opening 49 and the support opening 19.

[0128] The duration of the isotropic etching process can be selected such that the semiconductor material layer 14 is not etched all the way through after the isotropic etching process. Since the wet etching process does not reach the carrier substrate 9, the carrier substrate 9 can include any material, such as doped or undoped silicon, or another material. An annular cavity 13 is formed in each volume, and the semiconductor material of the semiconductor material layer 14 is removed from this volume. Generally, the bottom surface of each memory opening 49 can be formed at the top surface of the semiconductor material layer 14 or within the semiconductor material layer 14. Each annular cavity 13 can be formed by isotropically recessing a portion of the semiconductor material layer 14 adjacent to the corresponding memory opening 49.

[0129] Reference Figure 23B , the processing steps described in the reference can be executed Figure 8B to form the memory film 50. The memory film 50 can be formed conformally and thus can always have a uniform thickness.

[0130] Reference Figure 23C , the processing steps described in the reference can be executed Figure 8C to form the semiconductor fill material layer 160L.

[0131] Reference Figure 23D , the processing steps described in the reference can be executed Figure 8D to form an annular semiconductor structure 160 within each annular cavity 13. In one embodiment, each annular semiconductor structure 160 can have a corresponding cylindrical sidewall that is vertically coincident with the inner cylindrical sidewall of the corresponding overlying portion of the memory film 50.

[0132] Reference Figure 23E , the processing steps described in the reference can be executed Figure 8E to form a semiconductor core structure 161 on the cylindrical sidewall of each annular semiconductor structure 160. In a second exemplary structure, the memory opening 49 does not extend below the bottom surface of the semiconductor material layer 14. Thus, the bottom surface of each semiconductor core structure 161 can contact the horizontal top surface of the corresponding horizontally extending portion of the memory film 50 in the underlying cavity of the corresponding memory opening 49.

[0133] In one embodiment, the semiconductor core structure 161 includes a central seam CS that extends vertically from the center of its top surface to the center of its bottom surface. In one embodiment, the semiconductor core structure 161 includes a wavy top surface that has a periphery that bulges above the center point of the wavy top surface. In one embodiment, the wavy top surface of the semiconductor core structure 161 includes two opposing convex surfaces.

[0134] In one embodiment, each semiconductor core structure 161 includes a horizontal bottom surface that lies in the same horizontal plane as the horizontally extending portion of the bottom surface of the corresponding annular semiconductor structure 160. In one embodiment, the bottom surface of each annular semiconductor structure 160 can include a tapered convex annular surface that has a bottom periphery that abuts the periphery of the horizontally extending portion of the bottom surface of the corresponding annular semiconductor structure 160.

[0135] The semiconductor material layer 14 can laterally surround and can be embedded in each annular semiconductor structure 160. In one embodiment, the memory membrane 50 includes a vertically extending portion and a laterally protruding portion, the vertically extending portion vertically extends through the alternating stack (32, 42), the laterally protruding portion is adjacent to the bottom end of the vertically extending portion and laterally protrudes outward from the bottom end of the vertically extending portion and laterally surrounds the annular semiconductor structure 160. In one embodiment, the semiconductor material layer 14 does not contact the annular semiconductor structure 160 and is laterally separated from each annular semiconductor structure in the annular semiconductor structure by the laterally protruding portion of the memory membrane 50.

[0136] Reference Figure 23F , the described processing steps can be performed to form the semiconductor channel material layer 60L and the dielectric core 62. Figure 8F

[0137] Reference Figure 23G , the described processing steps can be performed to form the drain region 63 and the vertical semiconductor channel 60. In one embodiment, each vertical semiconductor channel 60 includes a wavy bottom surface, the wavy bottom surface includes a relatively concave surface that contacts the corresponding relatively convex surface of the semiconductor core structure 161. A p-n junction can be formed at each interface between the semiconductor core structure 161 and the vertical semiconductor channel 60. Figure 8G

[0138] Subsequently, the described processing steps can be performed to replace the sacrificial material layer 42 with the conductive layer 46, form the memory side metal interconnect structure 960, bond the logic die 700 to the memory die 900, and remove the carrier substrate 9 or thin the back side portion of the carrier substrate 9 to form the thinned carrier substrate 9'. Figures 10A to 17

[0139] Figures 24A to 24C is a sequential vertical cross-sectional view of a region of a second exemplary structure during removal of the carrier substrate 9, the buried insulating layer 12, and the bottom portions of the semiconductor material layer 14 and the memory membrane 50 and formation of the source layer 16 according to a second embodiment of the present disclosure.

[0140] Reference Figure 24A , if the thinned carrier substrate 9' is retained, a first etching process can be performed to selectively remove the thinned carrier substrate 9' for the material of the buried insulating layer 12. The back side surface (i.e., the distal surface) of the semiconductor material layer 14 can be physically exposed.

[0141] Reference Figure 24B ​​​, an etching process can be performed to remove a back surface portion of the semiconductor material layer 14 and physically expose the bottom surface of each memory film 50. The etching process can include an isotropic etching process or an anisotropic etching process. A series of etching processes can be performed to sequentially etch the respective layers of the memory film 50. For example, the physically exposed portions of the barrier dielectric layer 52, the memory material layer 54, and the optional dielectric liner 56 of each memory film 50 can be sequentially etched. The terminal etching step of the etching process sequence can be selective for the material of the semiconductor capping structure (160, 161). The bottom surface (i.e., the back surface) 162 of the semiconductor capping structure (160, 161) can be physically exposed after the etching process sequence.

[0142] Reference Figure 24C , a reference Figure 19 、 Figure 20A and Figure 20B The processing steps described to form and pattern the source layer 16, the backside insulating layer 34, and at least one optional source contact structure (36, 38).

[0143] In summary, the source layer 16 contacts the bottom surface 162 of the semiconductor core structure 161 and the annular semiconductor structure 160. In one embodiment, the source layer 16 includes a conductive metal or metal material. In one embodiment, the source layer 16 contacts the horizontal back surface 14H of the semiconductor material layer 14 and the surface segments of the inwardly curved sidewalls 14S of each opening 15 in the semiconductor material layer 14.

[0144] Reference Figure 25A and Figure 25B , shows a third exemplary structure according to a third embodiment of the present disclosure. The third exemplary structure includes a carrier substrate 9 (which can be the same as the carrier substrate 9 in the first or second exemplary structure), and a buried insulating layer 12 located above the carrier substrate 9. The buried insulating layer 12 includes an insulating material, such as silicon oxide, and has a thickness in the range from 80 nm to 400 nm, such as from 120 nm to 300 nm, but smaller and larger thicknesses can also be employed.

[0145] A photoresist layer (not shown) can be applied over the top surface of the buried insulating layer 12, and it can be lithographically patterned with the same pattern as that of the first layer memory openings 149 and the first layer support openings 119 in the case where each opening in the photoresist layer is modified. Specifically, the area of each opening in the photoresist layer can be larger than the area of the corresponding first layer memory opening 149 or the corresponding first layer support opening 119 that will subsequently be formed in the same area. In one embodiment, each opening in the photoresist layer can have a periphery that is laterally offset outward from the periphery of the corresponding first layer memory opening 149 or the corresponding first layer support opening 119 that will be formed in the overlapping region. According to one aspect of the present disclosure, the size of each opening in the photoresist layer can be selected such that adjacent opening pairs do not merge with each other.

[0146] An anisotropic etching process can be performed to etch the upper portion of the buried insulating layer 12 that is not masked by the photoresist layer. A recessed cavity is formed in the volume of the material from which the buried insulating layer 12 is etched. The depth of the recessed cavity can be approximately the thickness of the semiconductor material layer 14 described above, and can be in the range from 30 nm to 300 nm, such as from 50 nm to 200 nm, but smaller and larger thicknesses can also be employed. Subsequently, the patterned photoresist layer can be removed, for example, by ashing.

[0147] A sacrificial fill material, such as amorphous silicon, polycrystalline silicon, a carbon-based material (such as amorphous carbon or diamond-like carbon (DLC)), a high-etch-rate silicate glass (such as borosilicate glass or organosilicate glass), or a polymer material, is deposited in the recessed cavity. The excess portion of the sacrificial fill material can be removed from above the horizontal plane including the top surface of the buried insulating layer 12. The remaining portion of the sacrificial fill material in the recessed cavity constitutes the sacrificial plate structure 114. The sacrificial plate structure 114 is embedded in the buried insulating layer 12.

[0148] Reference Figure 26 , the first layer alternating stack (132, 142) can be formed in the manner described in reference Figure 1 as described. An execution reference Figure 2 and Figure 3The described processing steps are to form the first stepped dielectric material portion 165, the first layer memory opening 149, and the first layer support opening 119. In the third exemplary structure, the chemistry of the anisotropic etching process for forming the first layer memory opening 149 and the first layer support opening 119 can be modified to be selective for the material of the sacrificial plate structure 114. In this case, the sacrificial plate structure 114 can serve as an etch stop structure for the anisotropic etching process for forming the first layer memory opening 149 and the first layer support opening 119. The bottom surfaces of the first layer memory opening 149 and the first layer support opening 119 can include the recessed top surface of the sacrificial plate structure 114.

[0149] Figures 28A to 28G is a sequential vertical cross-sectional view of the memory opening 49 during the formation of the memory opening filling structure 58 in the third exemplary structure of the third embodiment according to the present disclosure.

[0150] Reference Figure 28A , a selective isotropic etching process or an ashing process can be performed to selectively remove the sacrificial plate structure 114 for the materials of the first layer alternating stack (132, 142) and the buried insulation layer 12. For example, if the sacrificial plate structure 114 includes amorphous silicon, a selective silicon etching process can be used. If the sacrificial plate structure 114 includes a carbon material, an ashing process can be used. The memory opening 49 can vertically extend downward to the recessed horizontal surface of the recessed cavity in the buried insulation layer 12. In addition, an annular cavity 13 can be formed between the bottom surface of the recessed cavity in the buried insulation layer 12 and the bottom of the first layer alternating stack (132, 142) around each bottom portion of the memory opening 49.

[0151] Reference Figure 28B , the processing steps described with reference Figure 8B can be performed to form the memory film 50. The memory film 50 can be conformally formed and thus can always have a uniform thickness.

[0152] Reference Figure 28C , the processing steps described with reference Figure 8C can be performed to form the semiconductor fill material layer 160L.

[0153] Reference Figure 28D , the processing steps described with reference Figure 8D can be performed to form an annular semiconductor structure 160 within each annular cavity 13. In one embodiment, each annular semiconductor structure 160 can have a corresponding internal cylindrical sidewall that is vertically coincident with the internal cylindrical sidewall of the corresponding overlying portion of the memory film 50.

[0154] Reference Figure 28E , the processing steps described with referenceFigure 8E The described processing steps are to form a semiconductor core structure 161 on the inner cylindrical sidewall of each annular semiconductor structure 160. In the third exemplary structure, the memory opening 49 does not extend below the bottom surface of the buried insulating layer 12. Thus, the bottom surface of each semiconductor core structure 161 can contact the horizontal top surface of the corresponding horizontally extending portion of the memory film 50 in the cavity underlying the corresponding memory opening 49.

[0155] In one embodiment, the semiconductor core structure 161 includes a central seam CS that extends vertically from the center of its top surface to the center of its bottom surface. In one embodiment, the semiconductor core structure 161 includes a wavy top surface that has a periphery that bulges above the center point of the wavy top surface. In one embodiment, the wavy top surface of the semiconductor core structure 161 includes opposing convex surfaces. In one embodiment, each semiconductor core structure 161 includes a horizontal bottom surface that lies in the same horizontal plane as the horizontally extending portion of the bottom surface of the corresponding annular semiconductor structure 160.

[0156] The buried insulating layer 12 can laterally surround and can be embedded in each annular semiconductor structure 160. In one embodiment, the memory film 50 includes a vertically extending portion and a laterally protruding portion that vertically extends through the alternating stack (32, 42), and the laterally protruding portion abuts the bottom end of the vertically extending portion and laterally protrudes outwardly from the bottom end of the vertically extending portion and laterally surrounds the annular semiconductor structure 160. In one embodiment, the buried insulating layer 12 does not contact the annular semiconductor structure 160 and is laterally separated from each of the annular semiconductor structures in the annular semiconductor structure by the laterally protruding portion of the memory film 50.

[0157] Reference Figure 28F , the processing steps described in reference Figure 8F can be performed to form a semiconductor channel material layer 60L and a dielectric core 62.

[0158] Reference Figure 28G , the processing steps described in reference Figure 8G can be performed to form a drain region 63 and a vertical semiconductor channel 60. In one embodiment, each vertical semiconductor channel 60 includes a wavy bottom surface that includes opposing concave surfaces that contact the corresponding opposing convex surfaces of the semiconductor core structure 161. A p-n junction can be formed at each interface between the semiconductor core structure 161 and the vertical semiconductor channel 60.

[0159] Subsequently, the reference Figures 10A to 17The described processing steps include replacing the sacrificial material layer 42 with a conductive layer 46, forming the memory side metal interconnect structure 960, bonding the logic die 700 to the memory die 900, and removing the carrier substrate 9 or thinning the backside portion of the carrier substrate 9 to form a thinned carrier substrate 9'.

[0160] Figures 29A to 29C is a sequential vertical cross-sectional view of a region of a third exemplary structure during removal of the carrier substrate 9 and the bottom of the buried insulating layer 12 and the memory openings 49 and formation of the source layer 16 according to a third embodiment of the present disclosure.

[0161] Reference Figure 29A , if there is a thinned carrier substrate 9', a first etching process can be performed to selectively etch the material of the thinned carrier substrate 9' for the material of the buried insulating layer 12.

[0162] Reference Figure 29B , a second etching process can be performed to remove the backside surface portion of the buried insulating layer 12 and physically expose the bottom surface of each memory film 50. The etching process can include an isotropic etching process or an anisotropic etching process. For example, a wet etching process using diluted hydrofluoric acid can be employed to remove the backside surface portion of the buried insulating layer 12. A series of etching processes can be performed to sequentially etch the respective layers of the memory film 50. For example, the physically exposed portions of the barrier dielectric layer 52, the memory material layer 54, and the optional dielectric liner 56 of each memory film 50 can be etched sequentially. The final etching step of the etching process sequence can be selective for the material of the semiconductor capping structure (160, 161). The flat bottom surface (i.e., the backside surface) 162 of the semiconductor capping structure (160, 161) can be physically exposed after the etching process sequence.

[0163] Reference Figure 29C , the processing steps described with reference Figure 19 can be performed to form the source layer 16 and pattern the source layer. Generally, the source layer 16 contacts the flat bottom surface 162 of the semiconductor core structure 161 and the annular semiconductor structure 160. In one embodiment, the source layer 16 includes a metal material. In the third embodiment, the semiconductor material layer 14 can be omitted.

[0164] Reference Figure 30 , the processing steps described with reference Figure 20A and Figure 20B can be performed to form the backside insulating layer 34 and optionally form at least one source contact structure (36, 38).

[0165] Reference Figures 1 to 30And according to various embodiments of the present disclosure, a semiconductor structure includes: an alternating stack of an insulating layer 32 and a conductive layer 46; a memory opening 49 that extends vertically through the alternating stack (32, 46); a memory opening fill structure 58 that is located in the memory opening 49 and includes a memory film 50, a vertical semiconductor channel 60, and a semiconductor capping structure that includes a semiconductor core structure 161 contacting a bottom end of the vertical semiconductor channel 60 and an annular semiconductor structure 160 that laterally surrounds the semiconductor core structure 161 and has a vertical extent smaller than that of the semiconductor core structure 161; and a source layer 16 that contacts a bottom surface of the semiconductor core structure 161.

[0166] In Figure 20B , Figure 24C and Figure 29C embodiments, the source layer 16 also contacts a bottom of the annular semiconductor structure 160. However, in Figure 20C alternative embodiments, the source layer 16 does not contact the annular semiconductor structure 160.

[0167] In one embodiment, the semiconductor core structure 161 includes a central seam CS that extends vertically from a center of its top surface to a center of its bottom surface. In one embodiment, the semiconductor core structure 161 includes a wavy top surface that has a periphery that bulges above a center point of the wavy top surface. In one embodiment, the wavy top surface of the semiconductor core structure 161 includes opposing (e.g., facing each other) convex surfaces; and the vertical semiconductor channel 60 includes a wavy bottom surface that includes opposing (e.g., facing each other) concave surfaces that contact respective opposing convex surfaces of the semiconductor core structure 161.

[0168] In one embodiment, the semiconductor structure includes a semiconductor material layer 14 that is interposed between the alternating stack (32, 46) and the source layer 16 and laterally surrounds the annular semiconductor structure 160. In one embodiment, the memory film 50 includes: a vertically extending portion that extends vertically through the alternating stack (32, 46); and a laterally protruding portion that is adjacent to a bottom end of the vertically extending portion and laterally protrudes outward from the bottom end of the vertically extending portion and laterally surrounds the annular semiconductor structure 160. In one embodiment, the semiconductor material layer 14 does not contact the annular semiconductor structure 160 and is laterally spaced from the annular semiconductor structure by the laterally protruding portion of the memory film 50. In one embodiment, the source layer 16 contacts a horizontal back surface 14H of the semiconductor material layer 14 and optionally contacts a vertical or curved surface section (14V, 14S) of a sidewall of an opening 15 in the semiconductor material layer 14.

[0169] In one embodiment, the semiconductor structure includes a buried insulating layer 12 that is located between the alternating stacks (32, 46) and the source layer 16 and laterally surrounds the annular semiconductor structure 160.

[0170] In one embodiment, the semiconductor core structure 161 projects downward below the horizontal plane including the bottom surface of the annular semiconductor structure 160. In one embodiment, the semiconductor core structure 161 includes a wavy bottom surface that has a periphery located below the center point of the wavy bottom surface.

[0171] In one embodiment, the semiconductor core structure 161 includes a horizontal bottom surface that is in the same horizontal plane as the horizontal extension of the bottom surface of the annular semiconductor structure 160. In one embodiment, the bottom surface of the annular semiconductor structure 160 includes a tapered convex annular surface that abuts the horizontal extension of the bottom surface of the annular semiconductor structure 160. In one embodiment, the source layer 16 includes a metal material.

[0172] Various embodiments of the present disclosure can be employed to provide enhanced control over the position of the p-n junction between the vertical semiconductor channel 60 and the source structure (160, 161, 16). The source structure (160, 161, 16) includes a semiconductor top cover structure (160, 161) and a source layer 16, which can be a metal source layer that forms a low-resistance ohmic contact with the semiconductor top cover structure. The embodiment method has a reduced number of steps, does not require an additional step of removing the bottom of the semiconductor channel material layer 60L through the memory opening 49, and does not require laser annealing to activate dopants in the semiconductor source structure, which may adversely affect the copper interconnects and bond pads at the interface between the logic die 700 and the memory die 900. The position of the p-n junction can be precisely adjusted by controlling the duration of the selective semiconductor deposition process that forms the semiconductor core structure 161 and by controlling the thermal budget after p-n junction formation.

[0173] Although the foregoing relates to particularly preferred embodiments, it is to be understood that the disclosure is not limited thereto. Those of ordinary skill in the art will recognize that various modifications can be made to the disclosed embodiments, and such modifications are intended to be within the scope of the disclosure. Compatibility is assumed between all embodiments that are not alternatives to one another. The words "comprising" or "including" cover all embodiments in which the words "consisting essentially of" or the words "consisting of" replace the words "comprising" or "including", unless expressly stated otherwise. Whenever two or more elements are listed as alternatives in the same or different paragraphs, a Markush group including the list of two or more elements is also implicitly disclosed. Whenever the auxiliary verb "can" is used in this disclosure to describe the formation of an element or the performance of a processing step, embodiments in which such an element or such a processing step is not performed are also clearly contemplated, provided that the resulting device or apparatus can provide equivalent results. Accordingly, the auxiliary verb "can" as applied to the formation of an element or the performance of a processing step should also be interpreted as "can" or "can, or can not", whenever the omission of the formation of such an element or such a processing step can provide the same result or an equivalent result, equivalent results including slightly superior results and slightly inferior results. Where embodiments employing a particular structure and / or configuration are shown in this disclosure, it is to be understood that the disclosure can be practiced with any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or otherwise known to be impossible to those of ordinary skill in the art. If publications, patent applications, and / or patents are cited herein, each of these documents is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor structure, the semiconductor structure comprising: An alternating stack of an insulating layer and a conductive layer; A memory opening that extends vertically through the alternating stack; A memory opening filling structure that is located in the memory opening and includes a memory film, a vertical semiconductor channel, and a semiconductor top cover structure, the semiconductor top cover structure including a semiconductor core structure that contacts a bottom end of the vertical semiconductor channel and laterally surrounds the semiconductor core structure and having an annular semiconductor structure with a vertical extent smaller than that of the semiconductor core structure; And A source layer that contacts a bottom surface of the semiconductor core structure.

2. The semiconductor structure according to claim 1, wherein the source layer further contacts a bottom surface of the annular semiconductor structure.

3. The semiconductor structure according to claim 1, wherein: The semiconductor core structure includes a central seam that extends vertically from a center of a top surface thereof to a center of a bottom surface thereof; and The semiconductor core structure includes a wavy top surface that has a periphery that bulges above a center point of the wavy top surface.

4. The semiconductor structure according to claim 3, wherein: The wavy top surface of the semiconductor core structure includes opposing convex surfaces; and The vertical semiconductor channel includes a wavy bottom surface that includes opposing concave surfaces that contact corresponding opposing convex surfaces of the semiconductor core structure.

5. The semiconductor structure according to claim 1, the semiconductor structure further including a semiconductor material layer that is located between the alternating stack and the source layer and laterally surrounds the annular semiconductor structure.

6. The semiconductor structure according to claim 5, wherein the memory film includes: A vertically extending portion that extends vertically through the alternating stack; And A laterally protruding portion that is adjacent to a bottom end of the vertically extending portion and laterally protrudes outward from the bottom end of the vertically extending portion and laterally surrounds the annular semiconductor structure.

7. The semiconductor structure according to claim 6, wherein the semiconductor material layer does not contact the annular semiconductor structure and is laterally spaced apart from the annular semiconductor structure by the laterally protruding portion of the memory film.

8. The semiconductor structure according to claim 5, wherein the source layer contacts a horizontal back surface of the semiconductor material layer.

9. The semiconductor structure according to claim 1, the semiconductor structure further including an insulating material layer that is located between the alternating stack and the source layer and laterally surrounds the annular semiconductor structure.

10. The semiconductor structure according to claim 1, wherein the semiconductor core structure protrudes downward below a horizontal plane including a bottom surface of the annular semiconductor structure.

11. The semiconductor structure according to claim 10, wherein the semiconductor core structure includes a wavy bottom surface that has a periphery that is below a center point of the wavy bottom surface.

12. The semiconductor structure according to claim 1, wherein the semiconductor core structure includes a horizontal bottom surface, and the horizontal bottom surface is located in the same horizontal plane as the horizontal extension of the bottom surface of the annular semiconductor structure.

13. The semiconductor structure according to claim 12, wherein the bottom surface of the annular semiconductor structure includes a tapered convex annular surface, and the tapered convex annular surface is adjacent to the horizontal extension of the bottom surface of the annular semiconductor structure.

14. The semiconductor structure according to claim 1, wherein the source layer comprises a metallic material.

15. A method of forming a semiconductor structure, the method comprising: forming a material layer above a carrier substrate; forming an alternating stack of an insulating layer and a spacer material layer above the material layer, wherein the spacer material layer is formed as a conductive layer or is subsequently replaced by a conductive layer; forming a memory opening through the alternating stack and into the material layer; forming an annular cavity around a bottom portion of the memory opening at the level of the material layer; forming a memory film on the exposed surfaces of the memory opening and the annular cavity; forming an annular semiconductor structure within the remaining volume of the annular cavity; forming a semiconductor core structure on an inner sidewall of the annular semiconductor structure; and forming a vertical semiconductor channel on a top surface of the semiconductor core structure.

16. The method according to claim 15, the method further comprising: removing the carrier substrate; exposing a surface of the semiconductor core structure after removing the carrier substrate; and forming a source layer on the exposed surface of the semiconductor core structure.

17. The method according to claim 15, wherein the step of forming the annular semiconductor structure comprises: conformally depositing a semiconductor fill material in the annular cavity and in a peripheral portion of the memory opening; and removing a portion of the semiconductor fill material from inside the memory opening, wherein the remaining portion of the deposited semiconductor fill material is the annular cavity that constitutes the annular semiconductor structure.

18. The method according to claim 15, wherein: the material layer comprises a semiconductor material layer; the memory opening is formed through the semiconductor material layer; and the annular cavity is formed by laterally recessing an annular portion of the semiconductor material layer around the memory opening.

19. The method according to claim 15, wherein: the material layer comprises a semiconductor material layer; a bottom surface of the memory opening is formed on a top surface of the semiconductor material layer or within the semiconductor material layer; and the annular cavity is formed by isotropically recessing a portion of the semiconductor material layer adjacent to the memory opening.

20. The method according to claim 15, the method further comprising: forming a sacrificial plate structure within the material layer, wherein the material layer comprises an insulating material layer; and Removing the sacrificial plate structure through the memory opening, wherein a portion of the volume of the sacrificial plate structure that is removed and has no area overlap with the memory opening in a plan view includes the annular cavity.

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