Three-dimensional memory devices including horizontal semiconductor channels and methods of forming same

Abstract

A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and semiconductor material layers on a substrate; and forming a laterally alternating sequence of laterally insulated electrode structures and dielectric isolation pillar structures through the alternating stack. At least a portion of the lateral insulated electrode structures each includes a memory film and a word line electrode.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of the entire contents of U.S. Non - provisional Application No. 18 / 349,488, filed on July 10, 2023, with the U.S. Patent and Trademark Office, entitled "THREE - DIMENSIONAL MEMORY DEVICE INCLUDING HORIZONTAL SEMICONDUCTOR CHANNELS AND METHODS OF FORMING THE SAME", and hereby incorporates it by reference in its entirety for all purposes. Technical field

[0003] The present disclosure generally relates to the field of semiconductor devices, and more particularly to three - dimensional memory devices including horizontal semiconductor channels and methods of manufacturing the same. Background art

[0004] A three - dimensional vertical NAND string having one bit per cell is disclosed in the article "Novel Ultra High Density Memory With A Stacked - Surrounding Gate Transistor (S - SGT) Structured Cell" by T. Endoh et al., in the Proceedings of the IEDM Conference (2001), pages 33 - 36. Summary of the invention

[0005] According to one aspect of the present disclosure, a semiconductor device includes: a vertical alternating sequence of vertical via insulating layers and vertical via composite layers, wherein a plurality of elongated openings vertically extend through each of the vertical via insulating layers and the vertical via composite layers in the vertical alternating sequence; each vertical via composite layer in the vertical via composite layers includes a corresponding plurality of horizontal semiconductor channel strips; and each horizontal semiconductor channel strip in the corresponding plurality of horizontal semiconductor channel strips is located between each adjacent pair of the plurality of elongated openings; and a horizontal alternating sequence of a horizontal insulating electrode structure and a dielectric isolation column structure, wherein each horizontal alternating sequence in the horizontal alternating sequence is located within a corresponding one of the plurality of elongated openings, and a corresponding subset of the horizontal insulating electrode structure and a corresponding subset of the dielectric isolation column structure are horizontally alternating along a first horizontal direction within each horizontal alternating sequence in the horizontal alternating sequence.

[0006] According to another aspect of the present disclosure, a method of forming a three-dimensional memory device includes: forming an alternating stack of an insulating layer and a semiconductor material layer on a substrate; and forming a lateral alternating sequence of a lateral insulating electrode structure and a dielectric isolation column structure through the alternating stack. At least a portion of the lateral insulating electrode structure each includes a memory film and a word line electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1A to 1D are various views of an exemplary structure after forming various trenches in a substrate and a dielectric etch stop layer according to an embodiment of the present disclosure. Figure 1A 、 Figure 1B and Figure 1C are vertical cross-sectional views, and Figure 1D is a top view. Figure 1D The vertical planes A-A', B-B', and C-C' in Figure 1A 、 Figure 1B and Figure 1C are the cutting planes of

[0008] Figures 2A to 2C are various views of an exemplary structure after forming various sacrificial fill structures, an alternating stack of an insulating layer and a semiconductor material layer, and an insulating capping layer according to an embodiment of the present disclosure. Figure 2A 、 Figure 2B and Figure 2C The positions of the cutting planes of Figure 1D correspond to the positions of the vertical planes A-A', B-B', and C-C' in

[0009] Figures 3A to 3C are various views of an exemplary structure after forming a dielectric isolation column structure according to an embodiment of the present disclosure. Figure 3A 、 Figure 3B and Figure 3C The positions of the cutting planes of Figure 1D correspond to the positions of the vertical planes A-A', B-B', and C-C' in

[0010] Figures 4A to 4D are various views of an exemplary structure after forming source side trenches according to an embodiment of the present disclosure. Figure 4A 、 Figure 4B and Figure 4C are vertical cross-sectional views, and Figure 4D is a top view. Figure 4D The vertical planes A-A', B-B', and C-C' in Figure 4A 、 Figure 4B and Figure 4C are the cutting planes of

[0011] Figures 5A to 5CVarious views of an exemplary structure after forming a source line according to an embodiment of the present disclosure. Figure 5A , Figure 5B and Figure 5C The positions of the cutting planes respectively correspond to Figure 4D the positions of the vertical planes A-A′, B-B′, and C-C′ in

[0012] Figures 6A to 6E Various views of an exemplary structure after forming a lateral insulating electrode structure according to an embodiment of the present disclosure. Figure 6A , Figure 6B and Figure 6C are vertical cross-sectional views, and Figure 6D is a top view. Figure 6D The vertical planes A-A′, B-B′, and C-C′ in Figure 6A , Figure 6B and Figure 6C are the cutting planes of Figure 6E is a horizontal cross-sectional view of a region of an exemplary structure along the Figure 6B horizontal plane E-E′.

[0013] Figures 7A to 7C Various views of an exemplary structure after forming a drain-side trench according to an embodiment of the present disclosure. Figure 7A , Figure 7B and Figure 7C The positions of the cutting planes respectively correspond to Figure 6D the positions of the vertical planes A-A′, B-B′, and C-C′ in

[0014] Figures 8A to 8D Various views of an exemplary structure after forming a lateral groove and a drain region according to an embodiment of the present disclosure. Figure 8A , Figure 8B and Figure 8C The positions of the cutting planes respectively correspond to Figure 8D the positions of the vertical planes A-A′, B-B′, and C-C′ in

[0015] Figures 9A to 9C Various views of an exemplary structure after forming a conductive layer according to an embodiment of the present disclosure. Figure 9A , Figure 9B and Figure 9C The positions of the cutting planes respectively correspond to Figure 8D the positions of the vertical planes A-A′, B-B′, and C-C′ in

[0016] Figures 10A to 10D Various views of an exemplary structure after forming a trench filling structure according to an embodiment of the present disclosure. Figure 10A , Figure 10Band Figure 10C is a vertical cross-sectional view, and Figure 10D is a horizontal cross-sectional view along the Figures 10A to 10C horizontal plane D-D′ in Figure 10D The vertical planes A-A′, B-B′, and C-C′ in Figure 10A are Figure 10B and Figure 10C the cutting planes of

[0017] Figures 11A to 11G are various views of an exemplary structure after forming an electrode contact via structure, a word line metal line, a connection via structure, and an upper metal line according to an embodiment of the present disclosure. Figure 10D The vertical planes A-A′, B-B′, and C-C′ in Figure 11A are Figure 11B and Figure 11C the cutting planes of Figure 11D is a partial perspective top view of an exemplary structure observed from the level of the electrode contact via structure. Figure 11E is a partial perspective top view of an exemplary structure observed from the level of the first metal line. Figure 11F is a partial perspective top view of an exemplary structure observed from the level of the connection via structure. Figure 11G is a partial perspective top view of an exemplary structure observed from the level of the second metal line.

[0018] Figure 12A is a schematic top view of a part of a memory plane according to an embodiment of the present disclosure.

[0019] Figure 12B is Figure 12A an enlarged view of region B of

[0020] Figure 12C is Figure 12B a perspective top view of a part of one memory block of

[0021] Figure 12D is Figure 12C an enlarged view of a region of the perspective top view of

[0022] Figure 13A is a schematic vertical cross-sectional view of an exemplary structure during a programming operation, while Figure 13B is a programming table for the exemplary structure of Figure 13A

[0023] Figure 14A is a schematic diagram of the drain select electrode of Figure 12D during a programming operation.

[0024] Figure 14B illustrates for Figure 14A ​Exemplary biasing schemes for programming a memory device.

[0025] Figure 15A is a schematic vertical cross-sectional view of an exemplary structure during a read operation, while Figure 15B is for Figure 15A a read table of the exemplary structure.

[0026] Figure 16 is a vertical cross-sectional view illustrating the formation of an inversion region in a horizontal semiconductor channel according to an embodiment of the present disclosure. Detailed Description

[0027] As discussed above, the present disclosure relates to three-dimensional memory devices including horizontal semiconductor channels and methods of manufacturing the same, aspects of which are described below. Embodiments of the present disclosure can be used to form various structures including multi-level memory structures, non-limiting examples of which include semiconductor devices such as three-dimensional memory array devices including multiple memory strings.

[0028] The drawings are not drawn to scale. Multiple instances of an element can be replicated in the case of illustrating a single instance of the element, unless otherwise explicitly described or clearly indicated that there is no replication of the element. Ordinal numbers such as "first", "second", and "third" are only used to identify similar elements and different ordinal numbers can be used in the specification and claims of the present disclosure. The term "at least one" element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0029] Like reference numerals denote like or similar elements. Unless otherwise specified, elements having the same reference numerals are considered to have the same composition and the same function. Unless otherwise specified, "contact" between elements means direct contact providing an edge or surface shared by the elements. If two or more elements do not directly contact each other or do not directly contact each other, the two elements are "separated" from each other or are "separated" from each other. As used herein, an element located "on" a second element can be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, an element is "directly" located "on" a second element if there is physical contact between the surface of the element and the surface of the second element. As used herein, an element is "electrically connected to" a second element if there is an electrical conduction path composed of at least one conductive material between the element and the second element. As used herein, a "prototype" structure or a "work-in-progress" structure refers to a transient structure whose shape or composition of at least one of its components is subsequently modified.

[0030] As used herein, a "layer" refers to a portion of a material that includes a region having a thickness. The layer can extend across an entire underlying or overlying structure, or its extent can be less than that of the underlying or overlying structure. Additionally, a layer can be a region of a uniform or non-uniform continuous structure having a thickness less than that of the continuous structure. For example, a layer can be between any pair of horizontal planes between the top surface and the bottom surface of the continuous structure or at the top surface and the bottom surface. The layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, or can have one or more layers on, above, and / or below it.

[0031] Generally speaking, a semiconductor die or a semiconductor package can include memory chips. Each semiconductor package contains one or more dies (e.g., one, two, or four). A die is the smallest unit capable of independently executing commands or reporting status. Each die contains one or more planes (usually one or two). Despite some limitations, the same, concurrent operations can be performed on each plane. Each plane contains a plurality of blocks, which are the smallest units that can be erased in a single erase operation. Each block contains a plurality of pages, which are the smallest programmable units, i.e., the smallest units on which a read operation can be performed.

[0032] As used herein, a "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -5 S / m to 1.0×10 5 S / m. As used herein, a "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -5 S / m to 1.0 S / m in the absence of an electrical dopant, and capable of producing a doped material having a conductivity in the range of 1.0 S / m to 1.0×10 7 S / m when appropriately doped with an electrical dopant. As used herein, an "electrical dopant" is a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, a "conductive material" refers to a material having a conductivity greater than 1.0×10 5 S / m. As used herein, an "insulating material" or "dielectric material" refers to a material having a conductivity less than 1.0×10 -5 S / m. As used herein, a "heavily doped semiconductor material" refers to a semiconductor material doped with an electrical dopant at a high enough atomic concentration to become a conductive material, which is formed as a crystalline material or transformed into a crystalline material through an annealing process (e.g., from an initial amorphous state), i.e., providing a conductivity greater than 1.0×10 5The conductivity of S / m. The "doped semiconductor material" can be a heavily doped semiconductor material or can be a semiconductor material including an electrical dopant (i.e., p-type dopant and / or n-type dopant), and the concentration of these electrical dopants provides a conductivity in the range of 1.0×10 -5 S / m to 1.0×10 7 S / m. The "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, the semiconductor material can be semiconducting or conducting and can be an intrinsic semiconductor material or a doped semiconductor material. The doped semiconductor material can be semiconducting or conducting, depending on the atomic concentration of the electrical dopant therein. As used herein, the "metallic material" refers to a conducting material that contains at least one metallic element. All conductivity measurements are performed under standard conditions.

[0033] Reference Figures 1A to 1D , illustrates an exemplary structure according to an embodiment of the present disclosure, the exemplary structure including a substrate 9 and a dielectric etch stop layer 12. The substrate 9 can include any substrate that can provide sufficient mechanical strength to the device structures to be performed subsequently. Generally speaking, the substrate 9 can include a semiconductor substrate, an insulating substrate, or a conducting substrate. In one embodiment, the substrate 9 can include a semiconductor substrate, such as a commercially available single-crystalline silicon wafer.

[0034] The dielectric etch stop layer 12 contains a material that can be used as an etch stop material. The dielectric etch stop layer 12 can include silicon oxide, silicon nitride, a dielectric metal oxide, or a combination thereof. If the substrate 9 includes a semiconductor substrate (such as a silicon substrate), the dielectric etch stop layer 12 can include a dielectric semiconductor oxide material (such as silicon oxide), which can be formed by oxidizing a surface portion of the semiconductor substrate.

[0035] In one embodiment, a photoresist layer (not shown) can be applied on the substrate 9 and can be lithographically patterned to form various vertical grooves in the upper portion of the substrate 9 before forming the dielectric etch stop layer 12. The various vertical grooves can include a source-side groove 81, a drain-side groove 71, and an electrode region groove 41. The source-side groove 81 and the drain-side groove 71 can be laterally spaced apart along a first horizontal direction hd1, and the electrode region groove 41 can be formed between the source-side groove 81 and the drain-side groove 71. The electrode region groove 41 can extend laterally along the first horizontal direction hd1 and can be laterally spaced apart from each other along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0036] Reference Figures 2A to 2C, a sacrificial filler material can be deposited in various vertical grooves (81, 71, 41), and the excess of the sacrificial filler material can be removed above the horizontal plane including the topmost surface of the dielectric etch stop layer 12. The sacrificial filler material can include a carbon-based material (such as amorphous carbon or diamond-like carbon (DLC)) or a semiconductor material (such as amorphous silicon or organosilicate glass or a polymer material). The remaining portion of the sacrificial filler material filling the source-side groove 81 constitutes the source-side sacrificial filler material portion 83. The remaining portion of the sacrificial filler material filling the drain-side groove 71 constitutes the drain-side sacrificial filler material portion 73. Each remaining portion of the sacrificial filler material filling the electrode region groove 41 constitutes the electrode region sacrificial filler material portion 43. The sacrificial material portions (41, 73, 83) can include a stop region (e.g., an etch stop region) for a subsequent etching step.

[0037] An alternating stack (32, 44L) of the insulating layer 32 and the semiconductor material layer 44L can be formed over the dielectric etch stop layer 12 and the various sacrificial filler material portions (83, 73, 43). The insulating layer 32 contains an insulating material such as silicon oxide (i.e., undoped silicate glass), doped silicate glass, silicon nitride, and / or a dielectric metal oxide. In one embodiment, the insulating layer 32 contains silicon oxide and / or consists essentially of silicon oxide.

[0038] The semiconductor material layer 44L contains a semiconductor material that is intrinsic or doped with a first conductivity type. The first conductivity type can be p-type or n-type. In one embodiment, the semiconductor material layer 44L can include silicon, silicon germanium, a compound semiconductor material (such as a III-V compound semiconductor material or a II-VI compound semiconductor material), a semiconductor metal oxide material (such as indium gallium zinc oxide), or a semiconductor metal chalcogenide material. For example, the semiconductor material layer 44L can include intrinsic or p-type polysilicon. The dopant concentration of the dopant of the first conductivity type in the semiconductor material layer 44L can be in the range of 1.0×10 13 / cm 3 to 1.0×10 18 / cm 3 (such as 1.0×10 14 / cm 3 to 1.0×10 17 / cm 3 ), but smaller and larger dopant concentrations can also be employed.

[0039] The total number of repetitions of a pair of the insulating layer 32 and the semiconductor material layer 44L in the alternating stack (32, 44L) can be between 2 and 2 10within a range, but larger quantities can also be employed. The thickness of each insulating layer 32 can be within a range of 10 nm to 60 nm, but smaller and larger thicknesses can also be employed. The thickness of each semiconductor material layer 44L can be within a range of 10 nm to 60 nm (such as 15 nm to 25 nm), but smaller and larger thicknesses can also be employed. The insulating capping layer 70 can be formed over the alternating stack (32, 44L). The thickness of the insulating capping layer 70 can be within a range of 20 nm to 200 nm, but smaller and larger thicknesses can also be employed.

[0040] Figures 3A to 3C are various views of an exemplary structure after forming the dielectric isolation pillar structure 20 according to an embodiment of the present disclosure. Referring to Figures 3A to 3C , a photoresist layer (not shown) can be applied over the insulating capping layer 70 and can be lithographically patterned to form an array of discrete openings within the region of the sacrificial fill material portion 43 in the electrode area. A one-dimensional array of discrete openings can be formed over each electrode area sacrificial fill material portion 43. An anisotropic etching process can be performed to transfer the pattern of the openings in the photoresist layer through the insulating capping layer 70 and the alternating stack (32, 44L) to form isolation openings. In one embodiment, the isolation openings can have a cylindrical shape. The anisotropic etching process can be extended by varying the etching chemistry to remove the portion of the electrode area sacrificial fill material portion 43 located beneath the isolation openings. Thus, the isolation openings can extend vertically through the insulating capping layer 70 and the alternating stack (32, 44L) to the top surface of the dielectric etch stop layer 12. The photoresist layer can be removed, for example, by ashing.

[0041] A dielectric fill material (such as silicon oxide) can be deposited in the isolation openings. The excess portion of the dielectric fill material can be removed from above the top surface of the insulating capping layer 70 by performing a recess etching process. Each remaining portion of the dielectric fill material filling the corresponding isolation opening constitutes the dielectric isolation pillar structure 20. A two-dimensional array of the dielectric isolation pillar structures 20 can be formed.

[0042] Referring to Figures 4A to 4D , a photoresist layer (not shown) can be applied over the insulating capping layer 70 and can be lithographically patterned to form a linear opening within the region of the source-side sacrificial fill material portion 83. An anisotropic etching process can be performed to etch the portions of the insulating capping layer 70 and the alternating stack (32, 44L) located beneath the linear opening in the photoresist layer. Subsequently, the source-side sacrificial fill material portion 83 can be selectively removed relative to the dielectric etch stop layer 12. The source-side trench 89 can be formed in the volume of the material from which the insulating capping layer 70, the alternating stack (32, 44L), and the source-side sacrificial fill material portion 83 are removed.

[0043] Reference Figures 5A to 5C , a doped semiconductor material having a second conductivity type can be conformally deposited to form a conformal doped semiconductor layer. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The atomic concentration of the dopant of the second conductivity type in the conformal doped semiconductor layer can be in the range of 5.0×10 18 / cm 3 to 2.0×10 21 / cm 3 (such as 1.0×10 19 / cm 3 to 1.0×10 21 / cm 3 ), but smaller and larger atomic concentrations can also be employed. The thickness of the conformal doped semiconductor layer can be less than half of the width of the source-side trench 89 along the first horizontal direction hd1.

[0044] For example, the top portion of the conformal doped semiconductor layer can be removed in the following manner: depositing a sacrificial filling material (such as a photoresist material, a polymer material, or a carbon-based material) in the retention volume of the source-side trench 89; vertically recessing the sacrificial filling material such that the sacrificial filling material is removed from above the horizontal plane including the top surface of the insulating capping layer 70; and isotropically etching the conformal doped semiconductor layer. The remaining portion of the conformal doped semiconductor layer after the isotropic etching process constitutes the doped semiconductor spacer 82. The doped semiconductor spacer 82 includes a vertically extending portion (which is referred to herein as the vertically extending wall portion) and may include a horizontal bottom portion adjacent to the bottom of each vertically extending portion. Subsequently, the sacrificial filling material can be removed, for example, by ashing or by a selective isotropic etching process.

[0045] At least one conductive material (such as a combination of a metal nitride barrier material and a highly conductive metal) can be deposited in the voids within the volume of the source-side trench 89. The excess portion of the at least one conductive material can be removed above the horizontal plane of the top surface including the insulating capping layer 70 by a planarization process (such as a chemical mechanical polishing (CMP) process). The remaining portion of the at least one conductive material constitutes the conductive core 87. In one embodiment, the conductive core 87 can include a conductive barrier liner that contains a metal nitride material (such as TiN, TaN, WN, and / or MoN) and a conductive fill material (such as W, Co, Ru, Mo, Ti, Ta, Cu, etc.). The combination of the doped semiconductor spacer 82 and the conductive core 87 constitutes the source line 88. The source line 88 extends vertically through each layer within the alternating stack (32, 44L), and can include a doped semiconductor spacer 82 that includes a vertically extending wall portion and contacts each layer within the alternating stack (32, 44L); and a conductive core 87 that contacts the inner sidewall of the doped semiconductor spacer 82.

[0046] Reference Figures 6A to 6E , an annealing process can be performed to cause dopants of the second conductivity type (e.g., phosphorus or arsenic) to diffuse from the doped semiconductor spacer 82 into the adjacent portion of the semiconductor material layer 44L. The first region of each semiconductor material layer in the semiconductor material layer 44L can be converted into a doped source region 42 having the second conductivity type (e.g., n-type). A vertical stack of the source regions 42 can be formed. Each source region 42 contacts the remaining portion of a corresponding one of the semiconductor material layers in the semiconductor material layer 44L and forms a corresponding first p-n junction with these remaining portions. The average atomic concentration of the dopants of the second conductivity type in the source regions 42 can be in the range of 1.0×10 18 / cm 3 to 5.0×10 20 / cm 3 (such as 1.0×10 19 / cm 3 to 2.0×10 20 / cm 3 ), but smaller and larger average atomic concentrations can also be employed. The lateral distance between the doped semiconductor spacer 82 and the corresponding nearest p-n junction can be in the range of 20 nm to 200 nm, but smaller and larger lateral distances can also be employed.

[0047] The first contact-level dielectric layer 80 can be deposited on the insulating capping layer 70. The first contact-level dielectric layer 80 contains a dielectric material (such as silicon oxide) and can have a thickness in the range of 30 nm to 200 nm, but smaller and larger thicknesses can also be employed.

[0048] A photoresist layer (not shown) may be applied over the first contact level dielectric layer 80 and may be lithographically patterned to form an opening row within the region of the electrode region sacrificial fill material portion 43. The opening row in the photoresist layer may be selected such that the region of the openings is interwoven with the region of the dielectric isolation column structure 20 along the first horizontal direction hd1. The combination of the region of the openings in the photoresist layer and the region of the dielectric isolation column structure 20 may together cover the entire region or a major portion of the entire region of the electrode region recess 41 formed at the processing step as described in reference Figures 1A to 1D and cover the entire region or a major portion of the entire region of the electrode region recess 41 formed at the processing step as described in reference

[0049] An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the first contact level dielectric layer 80, the insulating capping layer 70, the alternating stack (32, 44L), and the portions of the dielectric isolation column structure 20 that are within the region of the openings in the photoresist layer. Additionally, the remaining portion of the electrode region sacrificial fill material portion 43 may be removed during or after the anisotropic etching process. The openings formed below the openings in the photoresist layer are referred to herein as electrode openings.

[0050] Generally, the electrode openings may be formed through the alternating stack (32, 44L) such that the electrode openings cut through the peripheral portion of the dielectric isolation column structure 20. In one embodiment, each electrode opening may have a circular or elliptical horizontal cross-sectional shape. In such a case, the electrode opening may have a cylindrical shape or an elliptical cylindrical shape. All sidewalls of the electrode opening may have a convex horizontal cross-sectional shape and may be vertical or substantially vertical.

[0051] In one embodiment, each dielectric isolation column structure 20 between an adjacent pair of electrode openings that are laterally spaced apart along the first horizontal direction hd1 may be etched at two peripheral portions such that two vertically straight and horizontally recessed sidewalls are formed on the dielectric isolation column structure 20. As used herein, a vertically straight sidewall refers to a sidewall having a straight vertical cross-sectional profile. As used herein, a horizontally recessed sidewall refers to a sidewall having a recessed horizontal cross-sectional profile. As used herein, a horizontally convex sidewall refers to a sidewall having a convex horizontal cross-sectional profile.

[0052] At least one dielectric layer and at least one electrode material including a conductive material can be formed in each of the electrode openings. For example, a layer stack including a gate dielectric layer 56, a memory material layer 54, and a blocking dielectric layer 52 can be conformally deposited in the peripheral portion of each electrode opening. The gate dielectric layer 56 includes a gate dielectric material such as silicon oxide, silicon oxynitride, and / or dielectric metal oxide. In one embodiment, the gate dielectric layer 56 includes a tunneling dielectric material through which charge tunneling can occur under appropriate electrical bias conditions. The memory material layer 54 can include any suitable memory material such as a charge storage material, a ferroelectric memory material, a phase change memory material, etc. For example, the memory material layer 54 can include a silicon nitride charge storage layer, or a hafnium oxide-based ferroelectric layer or a chalcogenide phase change layer. The blocking dielectric layer 52 includes a blocking dielectric material that can block charge tunneling. For example, the blocking dielectric layer can include a silicon oxide layer and / or a dielectric metal oxide layer such as aluminum oxide.

[0053] At least one electrode material (such as a combination of a conductive barrier liner material and a conductive fill material) can be deposited in the remaining voids in the electrode openings. The excess portions of the at least one electrode material and the layer stack can be removed from above a horizontal plane including the top surface of the first contact level dielectric layer 80 by a planarization process, which can include a trench etching process and / or a chemical mechanical planarization process. Each remaining portion of the at least one electrode material constitutes an electrode 57.

[0054] The electrode 57 includes: a word line electrode (e.g., a control gate electrode) 57W that serves as part of the word line of a three-dimensional memory array; a source select electrode 57S that is used to selectively activate a horizontal semiconductor channel of the three-dimensional memory array from the source side; a drain select electrode 57D that is used to selectively activate the horizontal semiconductor channel of the three-dimensional memory array; and an optional dummy electrode 57A that operates in the same manner as the word line electrode 57W but is not used for accessing data due to its proximity to the source select electrode or the drain select electrode. If formed around the word line electrode 57W, each remaining portion of the layer stack is referred to herein as a memory film 50. If formed around an electrode 57A, 57D, or 57S that is not the word line electrode 57W, each remaining portion of the layer stack is referred to herein as a layer stack 50'. Each successive combination of the electrode 57 and the memory film 50 or the layer stack 50' constitutes a laterally insulated electrode structure 58.

[0055] Each semiconductor material layer 44L is converted into a vertically perforated semiconductor layer (44, 42) including a plurality of source regions 42 and a semiconductor layer 44 of a first conductivity type. Each insulating layer 32 includes a plurality of elongated perforations therethrough, and each vertically perforated semiconductor layer (44, 42) includes a plurality of elongated perforations therethrough. Each perforation through the insulating layer 32 and the vertically perforated semiconductor layer (44, 42) extends along a first horizontal direction hd1, has a lateral width undulation along a second horizontal direction hd2, and contains and laterally surrounds a corresponding lateral alternating sequence (58, 20) of a lateral insulating electrode structure 58 and a dielectric isolation column structure 20. Generally speaking, the lateral alternating sequence (58, 20) of the lateral insulating electrode structure 58 and the dielectric isolation column structure 20 can be formed through an alternating stack of the insulating layer 32 and semiconductor material layers, and these semiconductor material layers are the vertically perforated semiconductor layers (44, 42).

[0056] Thus, the alternating stack of the insulating layer 32 and the semiconductor material layer 44L is converted into a vertical alternating sequence {32, (44, 42)} of a vertically perforated insulating layer 32 and a vertically perforated semiconductor layer (44, 42). A plurality of elongated openings vertically extend through each of the vertically perforated insulating layer 32 and the vertically perforated semiconductor layer (44, 42) in the vertical alternating sequence {32, (44, 42)}. Each lateral alternating sequence in the lateral alternating sequence (58, 20) is located within a corresponding elongated opening among the plurality of elongated openings. A corresponding subset of the lateral insulating electrode structure 58 and a corresponding subset of the dielectric isolation column structure 20 are laterally alternating along the first horizontal direction hd1 within each lateral alternating sequence in the lateral alternating sequence (58, 20).

[0057] In one embodiment, each lateral insulating electrode structure in the lateral insulating electrode structure 58 vertically extends through each vertically perforated insulating layer in the vertically perforated insulating layer 32 and each vertically perforated semiconductor layer in the vertically perforated semiconductor layer (44, 42) in the vertical alternating sequence {32, (44, 42)}. In one embodiment, each vertically perforated insulating layer in the vertically perforated insulating layer 32 contacts each lateral insulating electrode structure in the lateral insulating electrode structure 58 and each dielectric isolation column structure in the dielectric isolation column structure 20.

[0058] In Figure 6EIn one embodiment shown, each of the lateral insulating electrode structures 58 in the lateral insulating electrode structure includes two vertical stacks of an outer surface section 58C that contacts a surface section of the vertically perforated semiconductor layer (44, 42). In one embodiment, each outer surface section within the two vertical stacks of the outer surface section 58C includes a vertically straight and laterally protruding surface section; and each surface section of the vertically perforated semiconductor layer (44, 42) that contacts a corresponding lateral insulating electrode structure 58 includes a vertically straight and laterally recessed surface section.

[0059] A first subset of the lateral insulating electrode structures 58, each including a memory film 50 and a word line electrode 58W, is referred to herein as a memory pillar structure 58M. Thus, each memory pillar structure 58M includes a memory film 50 and a word line electrode 57W (which is one of the electrodes 57). The memory film 50 may include, from the outside to the inside, a gate dielectric layer 56, a memory material layer 54, and a blocking dielectric layer 52. A second subset of the lateral insulating electrode structures 58 includes an insulating drain select pillar structure 58D that includes a layer stack 50' having the same composition as the memory film 50 and further includes a drain select electrode 57D (which is one of the electrodes 57). A third subset of the lateral insulating electrode structures 58 includes an insulating source select pillar structure 58S that includes a layer stack 50' having the same composition as the memory film 50 and further includes a source select electrode 57D (which is one of the electrodes 57). A fourth subset of the lateral insulating electrode structures 58 includes an insulating dummy memory pillar structure 58A that includes a layer stack 50' having the same composition as the memory film 50 and further includes a dummy electrode 57A (which is one of the electrodes 57).

[0060] In one embodiment, each of the vertically perforated semiconductor layers (44, 42) includes a corresponding source region 42 that contacts an end of the first-conductivity-type semiconductor layer 44 and forms a corresponding first p-n junction with the end. In one embodiment, the source region 42 may contact a plurality of surface sections of the first-conductivity-type semiconductor layer 44 that are laterally spaced apart from each other along a second horizontal direction hd2. Each first-conductivity-type semiconductor layer 44 may have a plurality of strip regions that are located between adjacent pairs of a lateral alternating sequence (58, 20) of the lateral insulating electrode structures 58 and the dielectric isolation pillar structures 20 and have a width fluctuation.

[0061] Subsequently, a stepped region 92 including a horizontal step 44S may be formed on a side of the alternating sequence (58, 20) opposite to the source line 88. The stepped region 92 may be formed by any suitable lithography and etching process.

[0062] Reference Figures 7A to 7C The second contact-level dielectric layer 90 may be formed over the first contact-level dielectric layer 80. The second contact-level dielectric layer 90 includes a dielectric material, such as silicon oxide. The thickness of the second contact-level dielectric layer 90 may range from 30 nm to 200 nm, although smaller and larger thicknesses may also be employed.

[0063] A photoresist layer (not shown) may be applied over the second contact-level dielectric layer 90 and may be lithographically patterned to form a linear opening in the region of the drain-side sacrificial fill material portion 73. An anisotropic etching process may be performed to etch the portions of the contact-level dielectric layers (80, 90), the insulating capping layer 70, and the alternating stack {32, (44, 42)} that are beneath the linear opening in the photoresist layer. Subsequently, the drain-side sacrificial fill material portion 73 may be selectively removed relative to the dielectric etch stop layer 12. The drain-side trench 79 may be formed in the volume of material from which the contact-level dielectric layers (80, 90), the insulating capping layer 70, the alternating stack {32, (44, 42)}, and the drain-side sacrificial fill material portion 73 have been removed.

[0064] Reference Figures 8A to 8D A selective isotropic etching process may be performed that selectively etches the material of the first-conductivity-type semiconductor layer 44 relative to the materials of the vertical via insulating layer 32, the dielectric etch stop layer 12, the insulating capping layer 70, and the contact-level dielectric layers (80, 90). In this case, an isotropic etchant may be introduced into the drain-side trench 79 that selectively etches the material of the first-conductivity-type semiconductor layer 44 relative to the materials of the vertical via insulating layer 32, the dielectric etch stop layer 12, the insulating capping layer 70, and the contact-level dielectric layers (80, 90). For example, if the first-conductivity-type semiconductor layer 44 includes silicon (e.g., polysilicon), a wet etching process using hot trimethyl-2-hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (“TMAH”) may be used to laterally recess the physically exposed sidewalls of the first-conductivity-type semiconductor layer 44 around the drain-side trench 79. Lateral grooves 47 are formed around the drain-side trench 79 in each volume of material from which the material of the first-conductivity-type semiconductor layer 44 has been removed.

[0065] In Figure 8DIn one embodiment shown, the drain-side trench 79 may include a plurality of longer laterally extending portions 79L that laterally extend along a first horizontal direction hd1 and one or more individual shorter portions 79S that laterally extend along a second horizontal direction hd2. In this case, portions of the first-conductivity-type semiconductor layer 44 may be completely removed between adjacent pairs of the longer laterally extending portions 79L that laterally extend along the first horizontal direction hd1. Further, portions of the first-conductivity-type semiconductor layer 44 may be cut along the first horizontal direction hd1 around each of the shorter portions 79S of the drain-side trench 79 that laterally extend along the second horizontal direction hd2. Thus, the first-conductivity-type semiconductor layer 44 does not extend along the first horizontal direction hd1 beyond the shorter portions 79S of the drain-side trench 79. The lateral recess distance of the selective isotropic etching process may be in the range of 50 nm to 400 nm (such as 100 nm to 240 nm), but smaller and larger lateral recess distances may also be employed. The remaining portions of the first-conductivity-type semiconductor layer 44 are then used as a horizontal semiconductor channel and are referred to herein as horizontal semiconductor channel strips 45.

[0066] The drain region 48 may be formed on or within a surface portion of the horizontal semiconductor channel strip 45. In one embodiment, a selective semiconductor deposition process may be performed to selectively deposit a doped semiconductor material having a second conductivity type, such as n-type polysilicon. The selective semiconductor deposition process is a semiconductor deposition process that grows semiconductor material from a physically exposed semiconductor surface while suppressing the deposition of semiconductor material from a dielectric surface. Specifically, the drain region 48 including the doped semiconductor material having the second conductivity type may grow only from the physically exposed sidewalls of the horizontal semiconductor channel strip 45.

[0067] Alternatively, the drain region 48 may be formed by doping exposed end portions of the semiconductor channel strip 45 in the lateral grooves 47. Specifically, a vapor-phase dopant (such as phosphine or arsine) may be provided into the lateral grooves 47 through the drain-side trench 79 to dope the exposed end portions of the semiconductor channel strip 45 in the lateral grooves 47.

[0068] A plurality of laterally spaced-apart drain regions 48 may be formed at each level of the horizontal semiconductor channel strip 45 (i.e., between each vertically adjacent pair of the vertical via insulating layers 32 or between the topmost vertical via insulating layer 32 and the insulating cover layer 70). The plurality of drain regions 48 form a second p-n junction with the horizontal semiconductor channel strip 45. The atomic concentration of the dopant of the second conductivity type in the drain regions 48 may be between 5.0×10 18 / cm 3 and 2.0×10 21 / cm3 (such as 1.0×10 19 / cm 3 to 1.0×10 21 / cm 3 ), but smaller and larger atomic concentrations can also be employed. The lateral extent of each drain region 48 can be in the range of 30 nm to 300 nm (such as 60 nm to 150 nm), but smaller and larger lateral extents can also be employed.

[0069] Reference Figures 9A to 9C , at least one conductive material (such as a combination of a metal nitride barrier material and a high conductivity metal) can be conformally deposited in the reserved volume of the lateral groove 47, in the peripheral portion of the drain side trench 79, and on the contact level dielectric layers (80, 90). Portions of the at least one conductive material located above the contact level dielectric layers (80, 90) or inside the drain side trench 79 can be removed by performing an etch-back process, which can include an anisotropic etch process or an isotropic etch process. Each reserved portion of the at least one conductive material filling the lateral groove 47 constitutes a conductive layer 46. In one embodiment, the conductive layer 46 can include a metal barrier liner that includes a metal nitride material (such as TiN, TaN, WN, and / or MoN) and a metal fill material (such as W, Co, Ru, Mo, Ti, Ta, Cu, etc.). Portions of the conductive material located at the same vertical level (e.g., between a vertically adjacent pair of vertical via insulating layers of the vertical via insulating layer 32) can be interconnected with each other to provide the conductive layer 46 as a single continuous structure, as Figure 10D shown and described below. Generally speaking, portions of the vertical via semiconductor layer 44 can be replaced with the conductive layer 46. Each conductive layer 46 can include a bit line that contacts the drain region 48 located at the same vertical level above the substrate 9. The conductive layer 46 includes a horizontal stepped surface 46S in the stepped region 92.

[0070] Each consecutive combination of a source region 42, a plurality of horizontal semiconductor channel strips 45, a drain region 48, and a conductive layer 46 constitutes a composite layer having a uniform thickness and having vertical vias therethrough. Each such consecutive combination is referred to herein as a vertically-perforated composite layer (45, 42, 48, 46). A vertical alternating sequence {32, (45, 42, 48, 46)} of a vertically-perforated insulating layer 32 and a vertically-perforated composite layer (45, 42, 48, 46) is formed over a substrate 9. A plurality of elongated openings vertically extend through each of the vertically-perforated insulating layer 32 and the vertically-perforated composite layer (45, 42, 48, 46) in the vertical alternating sequence {32, (45, 42, 48, 46)}. Each vertically-perforated composite layer (45, 42, 48, 46) includes a respective plurality of horizontal semiconductor channel strips 45 located between each adjacent pair of the elongated openings. The elongated openings are filled with an alternating lateral alternating sequence (58, 20) of a lateral insulating electrode structure 58 and a dielectric isolation pillar structure 20. Each elongated opening includes a plurality of vertically straight and laterally recessed surface segments that vertically extend through each layer within the vertical alternating sequence {32, (45, 42, 48, 46)} and through an insulating cover layer 70.

[0071] In summary, the lateral alternating sequence (58, 20) of the lateral insulating electrode structure 58 and the dielectric isolation pillar structure 20 is located in the elongated openings extending through the vertical alternating sequence {32, (45, 42, 48, 46)}. Each lateral alternating sequence (58, 20) is located within a respective one of the elongated openings. A respective subset of the lateral insulating electrode structure 58 and a respective subset of the dielectric isolation pillar structure 20 laterally alternate along a first horizontal direction hd1 within each lateral alternating sequence (58, 20).

[0072] In one embodiment, each vertically-perforated composite layer (45, 42, 48, 46) includes a respective source region 42 that contacts a first end of each horizontal semiconductor channel strip 45 and forms a respective first p-n junction with the first end. In one embodiment, each vertically-perforated composite layer (45, 42, 48, 46) further includes a respective plurality of drain regions 48. Each drain region of the plurality of drain regions 48 contacts a second end of a respective one of the horizontal semiconductor channel strips 45 and forms a second p-n junction with the second end.

[0073] Reference Figures 10A to 10D, a dielectric fill material (such as silicon oxide) can be deposited in the drain-side trench 79 to form a trench fill structure 77. The excess portion of the dielectric fill material may or may not be removed above the contact-level dielectric layers (80, 90). The trench fill structure 77 comprises a dielectric fill material and / or consists essentially of a dielectric fill material. The trench fill structure 77 may include a plurality of longer laterally extending portions 77L that extend laterally along a first horizontal direction hdl and one or more individual shorter portions 77S that extend laterally along a second horizontal direction hd2, as Figure 10D shown.

[0074] In one embodiment, a plurality of drain regions 48 are laterally spaced apart from each other along the second horizontal direction hd2 by a laterally alternating sequence (58, 20) of a lateral insulating electrode structure 58 and a dielectric isolation pillar structure 20, as Figure 10D shown. In one embodiment, each vertical via composite layer (45, 42, 48, 46) in the vertical via composite layer includes a single corresponding conductive layer 46 that contacts the sidewalls of the corresponding plurality of drain regions 48.

[0075] Figure 10D Shown is a memory block 100 that is part of a memory finger 200. A conductive layer (e.g., a bit line) 46 surrounds a laterally alternating sequence (58, 20) of a lateral insulating electrode structure 58 and a dielectric isolation pillar structure 20 and horizontal semiconductor channel strips 45 that alternate in the second horizontal direction in the memory block 100. In each memory finger 200, the conductive layer 46 is electrically isolated from the source region 42 and the horizontal semiconductor channel strips 45 by an end row dielectric pillar structure 20 and a memory membrane 50 or layer stack 50' located at the outer perimeter of the lateral insulating electrode structure 58. Thus, as Figure 10D shown, the first and sixth row laterally alternating sequences (58, 20) electrically isolate the conductive layer 46 from the source region 42 and the horizontal semiconductor channel strips 45. The longer laterally extending portions 77L of the trench fill structure 77 laterally isolate adjacent memory fingers 200 along the second horizontal direction hd2.

[0076] In Figure 10D one embodiment shown, at least one of the dielectric isolation pillar structures 20 includes: two vertically stacked pairs of vertically straight and laterally protruding surface segments 20X that contact the horizontal semiconductor channel strip 45; and a pair of vertically straight and laterally recessed surface segments 20V that contact an adjacent pair of lateral insulating electrode structures of the lateral insulating electrode structure 58.

[0077] Referring to Figures 11A to 11G, various contact via structures, metal interconnect structures, and additional dielectric material layers may then be formed to provide electrical wiring to the conductive layer 46 and the electrodes 57. The contact via structures may include electrode contact via structures 106 and layer contact via structures (not illustrated) that contact a respective one of the conductive layers in the conductive layer 46, as Figure 11D shown. In one embodiment, the line-level dielectric layer 110 may be formed over the contact-level dielectric layers (80, 90), and the electrode contact via structures 106 may be formed through a lower portion of the line-level dielectric layer 110 and through the second contact-level dielectric layer 90.

[0078] The word line metal lines 108 may be formed in an upper portion of the line-level dielectric layer 110 over respective subsets of the electrode contact via structures 106 that contact the word line electrodes, as Figure 11B and Figure 11E shown. Generally, the word line metal lines 108 may be formed in any configuration suitable for selectively activating portions of the horizontal semiconductor channel strips 45. In one embodiment, the word line metal lines 108 may extend laterally along the second horizontal direction hd2 and may be electrically connected along the second horizontal direction to every other word line electrode 57W. The source select metal lines 109S may be electrically connected to respective subsets of the source select electrodes 57S. The drain select metal lines 109D may be electrically connected to respective subsets of the drain select electrodes 57D. The connection metal pads 108' may be formed over subsets of the electrode contact via structures 106 that are in electrical contact with the second drain select electrode to the last drain select electrode (e.g., the SGD2 electrode) 57D at the same level as the word line metal lines 108.

[0079] The connection via structures 126 may be formed on top of the word line metal lines 108, the source select metal lines 109S, the drain select metal lines 109D, and the connection metal pads 108', as Figure 11F shown. The second line-level metal lines 128 and the second line-level metal pads 128' may be formed on the connection via structures 126, as Figure 11G shown.

[0080] Figure 12A is a schematic top view of a portion of a memory plane according to an embodiment of the present disclosure. Figure 12B is Figure 12A an enlarged view of region B of Figure 12A and Figure 12BAs shown, the memory finger 200 extends along a first horizontal direction and includes a plurality of memory blocks 100 and at least one stepped region 92. The combination of the drain region 48 and the shorter portion 77S of the trench fill structure 77, and the combination of the conductive core 87 and the source region 42 separate the horizontal semiconductor channel strip 45 along the first horizontal direction hd1. Thus, each horizontal semiconductor channel strip in the horizontal semiconductor channel strip 45 does not extend beyond the ends of each memory block 100. A common conductive core (e.g., a source line portion) 87 and a common source region 42 surrounding the common conductive core 87 may be shared between two adjacent memory blocks 100 in each memory finger 200. A single stepped region 92 can be used to provide layer contact via structures 186 for conductive layers (e.g., bit lines) 46 that extend to the plurality of memory blocks 100 in each memory finger 200.

[0081] Reference Figure 12C and Figure 12D , an additional partial perspective view of an exemplary structure is shown, which illustrates various types of first-tier metal lines 108 and layer contact via structures 186. Generally, via cavities of different depths can be formed above the stepped surface 46S of the conductive layer 46 in the stepped region 92 between adjacent pairs of shorter portions of the shorter portion 77S of the trench fill structure 77, and can be filled with optional insulating spacers and layer contact via structures 186 to provide electrical contact with the corresponding stepped surface 46S of one of the conductive layers 46. In one embodiment, each conductive layer in the conductive layer 46 of the vertical via composite layer (45, 42, 48, 46) does not include any openings therethrough and is contacted by the bottom surface of the corresponding layer contact via structure 186.

[0082] The various metal lines at the first-tier level can include word line metal lines 108, which can include the i-th word line metal line WL(i - 1), where the index i ranges from 1 to N, and N is an integer greater than 1. In the illustrated example, N is 4. For example, a memory plane can include from 100 to 10,000 memory fingers 200. Each memory finger 200 can include from 100 to 500 vertically stacked conductive layers (e.g., bit lines) 46. For example, a memory plane can include 500 memory fingers 200, and each memory finger 200 includes 200 bit lines 46. This results in each memory plane including 100,000 bit lines.

[0083] The various metal lines at the first line level may further include a source select metal line 109S, which may include a channel-end source select gate metal line SGSB and at least one additional source select gate metal line SGS. The at least one additional source select gate metal line SGS may include two sections that are not electrically connected to each other in each memory block. The various metal lines at the first line level may further include a drain select metal line 109D, which may include a channel-end drain select gate metal line SGDT and a plurality of drain select gate metal lines (SGD0-A, SGD0-B, SGD1-A, SGD1-B). In addition, the various metal lines at the first line level may further include a dummy word line metal line DWL. The second line level metal line 128 may include source select gate metal lines and drain select gate metal lines, such as SGS and SGD2 lines.

[0084] Reference Figure 13A , a schematic vertical cross-sectional view of an exemplary structure during the programming step of a memory cell C1 is illustrated without programming a memory C2 that shares the same word line as the memory cell C1. The NAND string includes a horizontal semiconductor channel strip 45 controlled by a source select electrode 57S and a drain select electrode 57D. In Figure 13B is shown for Figure 13A the programming table of the structure. The SGS source select electrode 57S is turned off (e.g., by applying 0V thereto). A pass voltage for turning on the horizontal semiconductor channel strip 45 is applied to each pass word line electrode 57WP (i.e., applied to each unselected word line electrode), and a programming voltage is applied to the selected word line electrode 57WS. Both the selected memory cell Cl and the unselected memory cell C2 share the selected word line electrode 57WS. Thus, the drain select electrodes 57D (SGD0 / 1 and SGD2) of the NAND string including the selected memory cell C1 are turned on (e.g., by applying a positive voltage, such as 2.5V), while the drain select electrodes 57D (SGD0 / 1 and SGD2) of the NAND string including the unselected memory cell C2 are turned off (e.g., by applying 0V thereto). The selected bit lines 46 of the levels of the selected memory cell C1 and the unselected memory cell C2 are turned on (e.g., by applying 0V), while the unselected bit lines 46 of the remaining levels are turned off (e.g., by applying a high positive voltage, which is, for example, greater than 2.5V applied to the drain select gate metal line of the electrode 57D).

[0085] Figure 14A Illustrates during the programming operation Figure 12DSchematic diagram of the drain selection electrodes (SGD0-A, SGD0-B, SGD1-A, SGD1-B, SGD2) shown. Each first-row first-type electrode 57_0A can be electrically connected to the first-row first-type drain selection gate metal line SGD0-A; each first-row second-type electrode 57_0B can be electrically connected to the first-row second-type drain selection gate metal line SGD0-B; each second-row first-type electrode 57_1A can be electrically connected to the second-row first-type drain selection gate metal line SGD1-A; and each second-row second-type electrode 57_1B can be electrically connected to the second-row second-type drain selection gate metal line SGD1-B.

[0086] Reference Figure 14B , for Figure 14A The drain selection electrodes illustrated in exemplify various bias conditions for selectively turning on (i.e., for generating a "pass" condition) a selected subset of the horizontal semiconductor channel strips 45 while turning off (i.e., for generating a "suppress" condition) an unselected subset of the horizontal semiconductor channel strips 45. In each of the four bias conditions, one of the first-row first-type drain selection gate metal line SGD0-A electrically connected to the corresponding first-row first-type electrode 57_0A and the first-row second-type drain selection gate metal line SGD0-B electrically connected to the corresponding first-row second-type electrode 57_0B is biased with an "on" voltage, while the other of the first-row first-type drain selection gate metal line SGD0-A and the first-row second-type drain selection gate metal line SGD0-B is biased with an "off" voltage. In addition, one of the second-row first-type drain selection gate metal line SGD1-A electrically connected to the corresponding second-row first-type electrode 57_1A and the second-row second-type drain selection gate metal line SGD1-B electrically connected to the corresponding second-row second-type electrode 57_1B is biased with an "on" voltage, while the other of the second-row first-type drain selection gate metal line SGD1-A and the second-row second-type drain selection gate metal line SGD0-B is biased with an "off" voltage.

[0087] Figure 15A is during the read operation of the selected memory cell C1 Figure 13A Schematic vertical cross-sectional view of the exemplary structure shown, while Figure 15B is for Figure 15A the read table of the exemplary structure of.

[0088] Reference Figure 16, illustrates the formation of an inversion region 45_I around an electrically biased electrode (e.g., a word line) 57. The electric field generated by the electrode 57 forms an inversion region within the surface portion of the horizontal semiconductor channel strip 45 that is close to the interface between the horizontal semiconductor channel strip 45 and the tunneling dielectric layer 56. An increase in the magnitude of the voltage can increase the volume of the inversion region 45_I. Also illustrated is the maximum extent 45_Imax of the inversion region 45_I under maximum voltage conditions.

[0089] Reference Figures 1A to 16 And in accordance with various embodiments of the present disclosure, a semiconductor device includes: a vertical alternating sequence {32, (45, 42, 48, 46)} of vertical via insulating layers 32 and vertical via composite layers (45, 42, 48, 46); and a horizontal alternating sequence (58, 20) of horizontal insulating electrode structures 58 and dielectric isolation pillar structures 20. A plurality of elongate openings vertically extend through each of the vertical via insulating layers 32 and the vertical via composite layers (45, 42, 48, 46) in the vertical alternating sequence {32, (45, 42, 48, 46)}. Each vertical via composite layer (45, 42, 48, 46) includes a corresponding plurality of horizontal semiconductor channel strips 45. Each horizontal semiconductor channel strip of the corresponding plurality of horizontal semiconductor channel strips 45 is located between each adjacent pair of the plurality of elongate openings. Each horizontal alternating sequence (58, 20) is located within a corresponding one of the plurality of elongate openings. A corresponding subset of the horizontal insulating electrode structures 58 and a corresponding subset of the dielectric isolation pillar structures 20 laterally alternate within each horizontal alternating sequence (58, 20) along a first horizontal direction hd1.

[0090] In one embodiment, each vertical via composite layer (45, 42, 48, 46) further includes a corresponding source region 42 that contacts a first end of each horizontal semiconductor channel strip 45 of the corresponding plurality of horizontal semiconductor channel strips 45 and forms a corresponding first p-n junction with the first end. In one embodiment, each vertical via composite layer (45, 42, 48, 46) further includes a corresponding plurality of drain regions 48, where each drain region 48 within the corresponding plurality of drain regions 48 contacts a second end of a corresponding one of the horizontal semiconductor channel strips 45 and forms a second p-n junction with the second end.

[0091] In one embodiment, a respective source region 42 contacts each of a respective plurality of horizontal semiconductor channel strips 45; and the respective plurality of drain regions 48 are laterally spaced from each other by a lateral alternating sequence (58, 20) of a lateral insulating electrode structure 58 and a dielectric isolation pillar structure 20. In one embodiment, each of the vertical via composite layers (45, 42, 48, 46) further includes a respective conductive layer (e.g., a horizontal bit line) 46 that is located between a vertically separated pair of vertical via insulating layers 32 and contacts sidewalls of the respective plurality of drain regions 48. In one embodiment, each of the conductive layers 46 of the vertical via composite layers (45, 42, 48, 46) forms a stepped region 92 and does not include any openings therethrough, and is contacted by a bottom surface of a contact via structure 186 by a respective layer in the stepped region 92.

[0092] In one embodiment, a three-dimensional memory device includes a source line 88 that extends vertically through each layer within a vertical alternating sequence {32, (45, 42, 48, 46)} and includes: a doped semiconductor spacer 82 that includes a vertically extending wall portion and contacts each of the source regions 42 of the vertical via composite layers (45, 42, 48, 46); and a conductive core 87 that contacts an inner sidewall of the doped semiconductor spacer.

[0093] In one embodiment, a first subset of the lateral insulating electrode structures 58 includes memory pillar structures, each memory pillar structure including a memory film 50 and a word line electrode 57. In one embodiment, the memory film 50 includes, from outside to inside, a tunneling dielectric layer 56, a memory material layer 54, and a blocking dielectric layer 52. In one embodiment, a second subset of the lateral insulating electrode structures 58 includes insulating drain select pillar structures, the insulating drain select pillar structures including a layer stack 50' having the same composition as the memory film 50 and further including drain select electrodes.

[0094] In one embodiment, each of the lateral insulating electrode structures 58 extends vertically through each of the vertical via insulating layers 32 and each of the vertical via composite layers (45, 42, 48, 46) within the vertical alternating sequence {32, (45, 42, 48, 46)}. In one embodiment, each of the vertical via insulating layers 32 contacts each of the lateral insulating electrode structures 58 and each of the dielectric isolation pillar structures 20.

[0095] In one embodiment, each of the lateral insulating electrode structures 58 includes two vertical stacks of outer surface segments that contact two vertical stacks of surface segments of the horizontal semiconductor channel strip 45. In one embodiment, each outer surface segment within the two vertical stacks of outer surface segments includes a vertically straight and laterally protruding surface segment; and each surface segment of the two vertical stacks of the horizontal semiconductor channel strip 45 that contacts a corresponding lateral insulating electrode structure 58 includes a vertically straight and laterally recessed surface segment.

[0096] In one embodiment, one, more, and / or each of the dielectric isolation pillar structures 20 includes: a pair of vertically straight and laterally protruding surface segments that contact two vertical stacks of the horizontal semiconductor channel strip 45; and a pair of vertically straight and laterally recessed surface segments that contact an adjacent pair of the lateral insulating electrode structures 58 of the lateral insulating electrode structures.

[0097] Various embodiments of the present disclosure can be used to provide a three-dimensional memory device that includes a horizontal semiconductor channel strip 45 that extends laterally between adjacent pairs of a lateral alternating sequence (58, 20) of lateral insulating electrode structures 58 and dielectric isolation pillar structures 20. A high-density NAND memory device can be provided. Additionally, if the number of vertical device levels is increased, the channel length does not change.

[0098] Although the foregoing relates to specific preferred embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art can envision various modifications to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed among all embodiments that are not mutually substitutable. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of" or "consisting of" replace the words "comprising" or "including". Whenever two or more elements are listed as alternatives in the same paragraph or different paragraphs, a Markush group comprising the list of two or more elements is also implicitly disclosed. Whenever the auxiliary verb "can" is used in the present disclosure to describe the formation of an element or the execution of a processing step, embodiments in which such element or such processing step is not executed are also clearly contemplated, provided that the resulting device or apparatus can provide an equivalent result. Accordingly, whenever the omission of the formation of such element or such processing step can provide the same result or an equivalent result, the auxiliary verb "can", as applied to the formation of an element or the execution of a processing step, should also be interpreted as "may" or "may, or may not", and these equivalent results include slightly superior results and slightly inferior results. In cases where embodiments employing a specific structure and / or configuration are illustrated in the present disclosure, it should be understood that the present disclosure can be practiced with any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or otherwise known to be impossible to those of ordinary skill in the art. If publications, patent applications, and / or patents are cited herein, each such document is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: a vertical alternating sequence of a vertical through - hole insulating layer and a vertical through - hole composite layer, wherein a plurality of elongated openings vertically extend through each of the vertical through - hole insulating layer and the vertical through - hole composite layer in the vertical alternating sequence; each vertical through - hole composite layer in the vertical through - hole composite layers includes a corresponding plurality of horizontal semiconductor channel strips; and each horizontal semiconductor channel strip in the corresponding plurality of horizontal semiconductor channel strips is located between each adjacent pair of the plurality of elongated openings; and a horizontal alternating sequence of a horizontal insulating electrode structure and a dielectric isolation pillar structure, wherein each horizontal alternating sequence in the horizontal alternating sequence is located within a corresponding elongated opening of the plurality of elongated openings; and a corresponding subset of the horizontal insulating electrode structure and a corresponding subset of the dielectric isolation pillar structure are laterally alternating along a first horizontal direction within each horizontal alternating sequence in the horizontal alternating sequence.

2. The semiconductor device according to claim 1, wherein each vertical through - hole composite layer in the vertical through - hole composite layers further comprises: a corresponding source region that contacts a first end of each horizontal semiconductor channel strip in the corresponding plurality of horizontal semiconductor channel strips; and a corresponding plurality of drain regions that contact a second end of a corresponding one of the corresponding plurality of horizontal semiconductor channel strips.

3. The semiconductor device according to claim 2, wherein: the corresponding source region forms a first p - n junction with the first end of each horizontal semiconductor channel strip in the corresponding plurality of horizontal semiconductor channel strips; and the corresponding plurality of drain regions form a second p - n junction with the second end of the corresponding one of the corresponding plurality of horizontal semiconductor channel strips.

4. The semiconductor device according to claim 3, wherein: the corresponding source region contacts each horizontal semiconductor channel strip in the corresponding plurality of horizontal semiconductor channel strips; and the corresponding plurality of drain regions are laterally spaced apart from each other through the horizontal alternating sequence of the horizontal insulating electrode structure and the dielectric isolation pillar structure.

5. The semiconductor device according to claim 3, wherein each vertical through - hole composite layer in the vertical through - hole composite layers includes a corresponding conductive layer that contacts the sidewalls of the corresponding plurality of drain regions.

6. The semiconductor device according to claim 5, wherein each conductive layer in the conductive layers of the vertical through - hole composite layer forms a stepped region that does not include any opening passing through it and is contacted by the bottom surface of a corresponding layer - contacting via structure.

7. The semiconductor device according to claim 2, further comprising a source line that extends through each layer within the vertical alternating sequence and includes: a doped semiconductor spacer that includes a vertically extending wall portion and contacts each source region in the source regions of the vertical through - hole composite layer; and a conductive core that contacts the inner sidewall of the doped semiconductor spacer.

8. The semiconductor device according to claim 1, wherein the first subset of the lateral insulating electrode structures includes memory pillar structures, each memory pillar structure including a memory film and a word line electrode.

9. The semiconductor device according to claim 8, wherein the memory film includes a tunneling dielectric layer, a memory material layer, and a blocking dielectric layer from outside to inside.

10. The semiconductor device according to claim 8, wherein the second subset of the lateral insulating electrode structures includes an insulating drain select pillar structure, the insulating drain select pillar structure including a layer stack having the same composition as the memory film and further including a drain select electrode.

11. The semiconductor device according to claim 1, wherein each of the lateral insulating electrode structures in the lateral insulating electrode structures vertically extends through each of the vertically perforated insulating layers and each of the vertically perforated composite layers in the vertical alternating sequence.

12. The semiconductor device according to claim 1, wherein each of the vertically perforated insulating layers contacts each of the lateral insulating electrode structures in the lateral insulating electrode structures and each of the dielectric isolation pillar structures in the dielectric isolation pillar structures.

13. The semiconductor device according to claim 1, wherein each of the lateral insulating electrode structures includes two vertical stacks of outer surface segments, the outer surface segments contacting surface segments of two vertical stacks of a horizontal semiconductor channel strip.

14. The semiconductor device according to claim 13, wherein: each outer surface segment in the two vertical stacks of the outer surface segments includes a vertically straight and laterally protruding surface segment; and each surface segment of the two vertical stacks of the horizontal semiconductor channel strip contacting a corresponding lateral insulating electrode structure includes a vertically straight and laterally recessed surface segment.

15. The semiconductor device according to claim 1, wherein one of the dielectric isolation pillar structures includes: a pair of vertically straight and laterally protruding surface segments contacting two vertical stacks of a horizontal semiconductor channel strip; and a pair of vertically straight and laterally recessed surface segments contacting an adjacent pair of lateral insulating electrode structures in the lateral insulating electrode structures.

16. A method of forming a three-dimensional memory device, comprising: forming an alternating stack of an insulating layer and a semiconductor material layer on a substrate; and forming a lateral alternating sequence of lateral insulating electrode structures and dielectric isolation pillar structures through the alternating stack, wherein at least a portion of the lateral insulating electrode structures each includes a memory film and a word line electrode.

17. The method according to claim 16, wherein after the step of forming the lateral alternating sequence of lateral insulating electrode structures and dielectric isolation pillar structures through the alternating stack, a remaining portion of the semiconductor material layer includes a horizontal semiconductor channel strip.

18. The method according to claim 17, further comprising: doping a first end of the horizontal semiconductor channel strip to form a common source layer contacting the horizontal semiconductor channel strip; and Dope a second end portion of the horizontal semiconductor channel strip to form a plurality of laterally spaced drain regions.

19. The method according to claim 18, further comprising: Forming a horizontal bit line in contact with the plurality of laterally spaced drain regions; And Forming a via structure for layer contact that contacts a top surface of a respective one of the bit lines.

20. The method according to claim 16, further comprising: Forming isolation openings through the alternating stack; Forming the dielectric isolation column structure in the isolation openings; Forming electrode openings through the alternating stack such that the electrode openings cut through a peripheral portion of the dielectric isolation column structure; And Forming the laterally insulated electrode structure in the electrode openings.

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