Oscilloscope intelligent trigger setting method

Abstract

The application discloses a method for setting an intelligent trigger of an oscilloscope, which comprises the following steps: collecting input signals by using an ADC in the oscilloscope to obtain sampling signals; calculating the maximum amplitude V max and the minimum amplitude V min of all sampling points by using a histogram; obtaining an initial trigger level V initial by adding the amplitudes of all sampling points and then averaging the sum; and realizing the setting of the rising edge trigger, the pulse width trigger, the slope trigger and the quartile method intelligent trigger of the intelligent oscilloscope based on the maximum amplitude V max , the minimum amplitude V min and the initial trigger level V initial , so that the debugging time is shortened and the debugging efficiency is improved.

Description

Technical Field

[0001] This invention belongs to the field of oscilloscope technology, and more specifically, relates to a method for setting triggers in an intelligent oscilloscope. Background Technology

[0002] With the continuous improvement of technology and the increasing complexity of acquisition systems, the capture of certain special signals has become extremely important. The trigger module is an indispensable part of this, as it can capture some sudden and minute abnormal signals, making it easier for scientists or circuit enthusiasts to find signals that are difficult to observe with the naked eye and display them stably, thereby improving the efficiency of hardware circuit debugging or facilitating the observation of some complex signals.

[0003] Different trigger types are suitable for signals with different characteristics. Edge triggering can be used for some periodic signals with steep edges; pulse width triggering can be used for some signals with specific pulse widths; slope triggering can be used to capture rapidly changing and steep signals. Automatically selecting the appropriate trigger type can not only capture the waveform of interest faster, but also quickly locate the problem, which is the advantage of intelligence.

[0004] In communication networks, intelligent triggering can be used to monitor and analyze various communication signals. For example, it can automatically identify and capture signal pulse widths, signal level transition edges, or signal change slopes that conform to specific protocols to detect signal transmission quality and identify abnormal signals. In motor control and monitoring, intelligent triggering can automatically select appropriate triggering methods to monitor motor current, voltage, or speed signals during motor operation. In medical equipment, such as electrocardiogram (ECG) and electroencephalogram (EEG) monitoring devices, intelligent triggering can automatically select triggering methods based on the characteristics of human physiological signals, accurately capturing and analyzing electrical activity signals of organs such as the heart and brain, assisting doctors in disease diagnosis and treatment.

[0005] When using traditional triggers, users need to set trigger conditions based on the signal being measured and the characteristics of the signal they are interested in. First, they need to select the appropriate trigger type based on the waveform characteristics, and then further set the trigger conditions. Many oscilloscope users have limited understanding of trigger functions and find it difficult to accurately set conditions to capture waveforms. Previously, they relied on the oscilloscope's automatic setup function to configure triggers, but this only allows setting conditions related to edge triggers. When faced with complex signals requiring different types of triggers for observation, users still face challenges in setting appropriate trigger conditions. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide an intelligent trigger setting method for oscilloscopes. Based on statistical laws, the optimal trigger mode is selected, which solves the problem of automatic identification of trigger conditions for complex and ever-changing arbitrary signals.

[0007] To achieve the above-mentioned objective, the present invention provides an intelligent trigger setting method for an oscilloscope, characterized by comprising the following steps:

[0008] (1) Initial settings of the oscilloscope;

[0009] (2) Use the ADC in the oscilloscope to acquire the input signal and obtain the sampled signal;

[0010] (3) Calculate the maximum amplitude V among all sampling points using a histogram. max Minimum amplitude V min The initial trigger level V is obtained by summing the amplitudes of all sampled points and averaging them. initial ;

[0011] (4) Based on the maximum amplitude V of the sampled signal max Minimum amplitude V min and the initial trigger level V initial Enables intelligent triggering settings for rising edge triggering, pulse width triggering, slope triggering, and quartile method for intelligent oscilloscopes.

[0012] The objective of this invention is achieved as follows:

[0013] This invention discloses an intelligent trigger setting method for an oscilloscope. First, the oscilloscope's ADC is used to acquire the input signal to obtain a sampled signal; then, the maximum amplitude V among all sampled points is statistically analyzed using a histogram. max Minimum amplitude V min The initial trigger level V is obtained by summing the amplitudes of all sampled points and averaging them. initial Finally, based on the maximum amplitude V of the sampled signal... max Minimum amplitude V min and the initial trigger level V initial This enables intelligent oscilloscopes to be set to trigger on rising edge, pulse width, slope, and quartile method, thereby shortening debugging time and improving debugging efficiency.

[0014] Meanwhile, the oscilloscope trigger setting method of the present invention also has the following beneficial effects:

[0015] (1) This invention can quickly and accurately locate abnormal features in waveforms, making it convenient for users to quickly locate triggers and select the optimal triggering method. It solves the problem of automatic identification of triggering conditions for complex and ever-changing arbitrary signals, thereby shortening debugging time and improving debugging efficiency. It has an incomparable advantage over manually setting triggering conditions.

[0016] (2) For beginners who are new to oscilloscopes and technicians who do not use oscilloscopes often, this intelligent triggering algorithm can help users get started quickly without having to look up the complicated triggering condition settings, thereby improving the user experience. Attached Figure Description

[0017] Figure 1 This is a flowchart of an oscilloscope trigger setting method according to the present invention;

[0018] Figure 2 This is a schematic diagram of a pulse width comparator circuit;

[0019] Figure 3 This is a schematic diagram of a positive pulse;

[0020] Figure 4 This is a schematic diagram of a slope comparison circuit;

[0021] Figure 5 This is a schematic diagram of a pulse with both positive and negative slope polarities. Detailed Implementation

[0022] The specific embodiments of the present invention will now be described with reference to the accompanying drawings to enable those skilled in the art to better understand the invention. It should be particularly noted that in the following description, detailed descriptions of known functions and designs that might obscure the main content of the invention will be omitted here.

[0023] Example

[0024] In this embodiment, as Figure 1 As shown, this invention provides an intelligent trigger setting method for an oscilloscope. The measured waveform is sampled by an ADC and sent to an intelligent trigger algorithm module. After obtaining the appropriate trigger type and trigger conditions, the method sends the results to the trigger module within the FPGA for triggering. Finally, the waveform stored in the storage module is displayed through the display module. The specific process is described in detail below, including the following steps:

[0025] (1) Initial settings of the oscilloscope;

[0026] (1.1) Set the oscilloscope to work in the highest sampling rate mode, and use the ADC in the oscilloscope to acquire the input signal to obtain the sampled signal;

[0027] (1.2) Calculate the difference ΔV between the maximum and minimum amplitude values ​​in the sampled signal by using histogram statistics;

[0028] (1.3) Calculate the amplitude V of the entire oscilloscope screen. range=b*h, where b is the total number of divisions for vertical sensitivity or horizontal sensitivity on the oscilloscope screen, and h is the vertical sensitivity; in this embodiment, the vertical sensitivity and horizontal sensitivity on the oscilloscope screen each have 10 divisions.

[0029] Calculate the proportion of the sampled signal waveform to the entire oscilloscope screen: α = ΔV / V range ;

[0030] The intelligent trigger module will automatically adjust the vertical sensitivity according to the ratio α, so that α≥0.8, that is, the waveform of the sampled signal occupies more than 80% of the entire screen. At this point, the amplitude level setting is completed.

[0031] (1.4) Determine whether the sampled signal is a periodic signal. If the sampled signal is a periodic signal, the intelligent trigger module automatically identifies the period T of the waveform and adjusts the horizontal sensitivity g so that 10*g≥4T, that is, the waveform of the sampled signal is displayed on the screen for more than 4 cycles. If the waveform is a non-periodic signal, the intelligent trigger module automatically adjusts to the real-time mode.

[0032] (2) Use the ADC in the oscilloscope to acquire the input signal and obtain the sampled signal, denoted as {x1, x2, ..., x...}. i ,…x N}, x i This represents the i-th sampling point, and N is the number of sampling points;

[0033] (3) Calculate the maximum amplitude V among all sampling points using a histogram. max Minimum amplitude V min The initial trigger level is obtained by summing the amplitudes of the N sampling points and then averaging them.

[0034]

[0035] Among them, V i For x i The amplitude;

[0036] (4) Rising edge trigger setting;

[0037] Determine whether the sampled signal is a periodic signal. If the sampled signal is a periodic signal, then use V... initial The trigger level and rising edge are used as trigger conditions and sent to the FPGA to end the trigger setting; otherwise, proceed to step (5).

[0038] (5) Pulse width trigger setting;

[0039] (5.1) Extract the positive and negative pulses from the sampled signal;

[0040] Through pulse width comparison circuit, such as Figure 2As shown, the sampled signal is compared with the initial trigger level using a comparator. If the amplitude of a certain sampling point in the sampled signal is greater than the initial trigger level V, the signal is considered a trigger signal. initial Then the counter starts counting, and when it is less than the initial trigger level V... initial When the counter stops counting, a positive pulse is obtained; if the amplitude of a certain sampling point in the sampled signal is less than the initial trigger level V... initial Then the counter starts counting, and when it exceeds the initial trigger level V... initial When the counter stops counting, a negative pulse is obtained;

[0041] (5.2) After all sampling points in the sampled signal are compared, assume that m positive pulses and k negative pulses are obtained;

[0042] (5.3) Count the number of sampling points in each positive pulse as the positive pulse width value. If a unique positive pulse width value appears, then use V as the value. initial A unique positive pulse width value is sent to the FPGA as the trigger level, and the trigger setting ends; otherwise, the number of sampling points in each negative pulse is counted as the negative pulse width value. If a unique negative pulse width value is found, then V is used as the trigger level. initial The trigger level and a unique negative pulse width value are sent to the FPGA as the trigger condition, and the trigger setting ends; if there is no unique width value in either the positive or negative pulse, then proceed to step (5);

[0043] In this embodiment, the initial trigger level V is... initial As a reference voltage, a counter is used to capture either positive or negative pulses, and then the pulse width count values ​​of the positive or negative pulses are statistically analyzed. This embodiment uses a positive pulse as an example to set the pulse width triggering. All captured positive pulses are as follows: Figure 3 As shown;

[0044] In this embodiment, assuming 5 positive pulses are obtained, if the positive pulse width values ​​of the 5 positive pulses are (5, 3, 4, 5, 4), and a unique positive pulse width value of 3 appears, then V initial The trigger level and a unique positive pulse width value of 3 are sent to the FPGA as the trigger condition; if the positive pulse width values ​​of the 5 positive pulses are (5,5,4,5,4), and no unique pulse width value appears, then step (6) is required;

[0045] (6) Slope trigger settings;

[0046] (6.1) Set the voltage difference Δy = (V max +V min ) / 8;

[0047] Set the high-level threshold V h =(V max +V min ) / 16;

[0048] Set low-level threshold V l =-(V max +V min ) / 16;

[0049] (6.2) The sampled signal passes through a slope comparison circuit, such as... Figure 4 As shown, by iterating through the amplitude of each sampling point in the sampled signal, if the sampled signal first passes through the low-level threshold and then passes through the high-level threshold, a positive pulse with a positive slope polarity is obtained through the counter. That is, the counter starts from the first value greater than V. l The counting starts from the sampling point and continues until the first sampling point is less than V. h Stop counting the sampling points and truncate V. l ≤V i ≤V h By continuously sampling points, a positive pulse representing a positive slope is obtained; if the sampled signal first passes through a high-level threshold and then a low-level threshold, a pulse with a negative slope polarity is obtained through the counter, that is: the counter starts from the first value less than V... h The counting begins from the sampling point, up to the first sampling point greater than V. l The sampling points stop counting, and V is truncated. l ≤V i ≤V h By continuously sampling points, a negative pulse representing a negative slope is obtained;

[0050] In this embodiment, after comparing each sampling point in the sampled signal with high and low level thresholds, we can extract pulses with two slope polarities, such as... Figure 5 As shown;

[0051] (6.3) After all sampling points in the sampled signal have been traversed, assume that n positive pulses and q negative pulses are obtained;

[0052] (6.4) Calculate the positive slope of each positive pulse;

[0053]

[0054] Calculate the negative slope of each negative pulse;

[0055]

[0056] Where λ is the number of sampling points in the positive pulse, α is the number of sampling points in the negative pulse, and Δt is the sampling interval between two adjacent sampling points;

[0057] (6.5) If a unique positive slope value appears among n positive slope values, then V is the positive slope value. h V lA unique positive slope value is sent to the FPGA as the trigger level, and the trigger setting ends; otherwise, the count continues among q negative slope values. If a unique negative slope value appears, then V is used as the trigger level. h V l The trigger level and a unique negative slope value are sent to the FPGA as the trigger condition, and the trigger setting ends; if no unique slope value appears among all positive and negative slope values, then proceed to step (7);

[0058] In this embodiment, assuming five pulses with positive slopes are obtained, if the slopes of the five pulses with positive slopes are (3, 3, 0.5, 0.5, 15), and the only slope value is 15, then V... h V l The trigger level and slope of 15 are used as the trigger conditions to send signals to the FPGA. If the slope values ​​of the five pulses with positive polarity are (0.5, 0.5, 0.4, 0.5, 0.4), and no unique positive slope value appears, then the count continues to check if a unique negative slope value appears among the negative slope values. If a unique negative slope value appears, then V... h V l The trigger level and negative slope value are used as trigger conditions to send to the FPGA; otherwise, step (7) is required.

[0059] (7) Adjust the pulse width trigger condition;

[0060] (7.1) Set the initial trigger level V initial The adjustment step ΔV = (V max +V min ) / 64, set the adjustment range to [V min V max ];

[0061] (7.2) Calculate the variance of the obtained positive and negative pulse widths respectively. If the variance of the positive pulse width is large, then within the adjustment range [V min V max Inside, V initial Increase ΔV, otherwise reduce V initial Decrease ΔV, then repeat step (5). If a unique width value appears, then use V. initial +ΔV or V initial -ΔV is sent to the FPGA as the trigger level and a unique pulse width value as the trigger condition, and the trigger setting ends; otherwise, proceed to step (8);

[0062] (8) Adjust the slope trigger condition;

[0063] (8.1) Set the high / low level adjustment step ΔV' = (V max +V min) / 32, set the adjustment range to [V min V max ];

[0064] (8.2) Calculate the variance of the obtained positive and negative slopes respectively. If the variance of the positive slope is large, then within the adjustment range [V]... min V max Within [the specified range], the high and low level thresholds V h V l Simultaneously increase ΔV', otherwise reduce the high and low level thresholds V. h V l Simultaneously decrease ΔV', then repeat steps (6.2) to (6.4). If a unique slope value appears, then use V' as the slope value. h +ΔV'、V l +ΔV' or V h -ΔV'、V l -ΔV' is the trigger level, and the unique slope value is sent to the FPGA as the trigger condition, and the trigger setting ends; otherwise, return to step (7);

[0065] (9) Intelligent setting of trigger conditions using the quartile method;

[0066] If the adjustment range is [V] min V max If neither a unique pulse width value nor a unique slope value is found within the range, then the level V of the last adjustment is used. last Based on this, repeat steps (5.1) to (5.3) to count the positive pulse width of each positive pulse;

[0067] The quartile method is used to detect whether the positive pulse width value of each positive pulse is an outlier: an outlier threshold ρ is set, and when the positive pulse width value of a positive pulse is greater than the outlier threshold ρ, the positive pulse width value is determined to be an outlier.

[0068] Count the number of outliers. If only one positive pulse has a pulse width greater than the threshold outlier ρ, then use V... last The trigger level is set, and the positive pulse width value is used as the trigger condition. If multiple positive pulses have a positive pulse width value greater than the outlier threshold ρ, then the largest positive pulse width value is selected from the multiple positive pulse width values ​​greater than the outlier threshold ρ, and then V is used as the trigger level. last The trigger level and maximum positive pulse width are sent to the FPGA as trigger conditions, and the trigger setting is complete.

[0069] In this embodiment, it is assumed that the trigger level V last Five positive pulses are obtained. If the pulse widths of the five positive pulses are (3, 6, 5, 4, 11), and the outlier threshold ρ is calculated to be 9 using the quartile method, then the pulse width of the positive pulse 11 is greater than 9, and therefore this positive pulse is an outlier. Then, V...last The trigger level is set to a positive pulse width of 11, which is sent to the FPGA as the trigger condition. If the pulse widths of the five positive pulses are (2, 6, 1, 8, 11), and the outlier threshold ρ is calculated to be 5 using the quartile method, then the pulse widths of the positive pulses 6, 8, and 11 are all greater than 5. The largest positive pulse width value satisfying the outlier characteristic is selected as the trigger condition, and V... last The trigger level and positive pulse width of 11 are used as trigger conditions to send the signal to the FPGA; otherwise, step (7) needs to be performed.

[0070] Finally, after the trigger type and trigger conditions are sent to the trigger module in the FPGA for triggering, the waveform in the storage module can be displayed through the display module.

[0071] Although the illustrative specific embodiments of the present invention have been described above to enable those skilled in the art to understand the invention, it should be understood that the invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the invention as defined and determined by the appended claims, and all inventions utilizing the concept of the present invention are protected.

Claims

1. A method for setting intelligent triggers on an oscilloscope, characterized in that, Includes the following steps: (1) Initial settings of the oscilloscope; (1.1) Set the oscilloscope to work in the highest sampling rate mode, and use the ADC in the oscilloscope to acquire the input signal to obtain the sampled signal; (1.2) Calculate the difference ΔV between the maximum and minimum amplitude values ​​in the sampled signal by using histogram statistics; (1.3) Calculate the amplitude V of the entire oscilloscope screen. range =b*h, where b is the total number of divisions on the oscilloscope screen for vertical or horizontal sensitivity, and h is the vertical sensitivity; Calculate the proportion of the sampled signal waveform to the entire oscilloscope screen: α = ΔV / V range ; The intelligent trigger module will automatically adjust the vertical sensitivity according to the ratio α, so that α≥0.8, that is, the waveform of the sampled signal occupies more than 80% of the entire screen. At this point, the amplitude level setting is completed. (1.4) Determine whether the sampled signal is a periodic signal. If the sampled signal is a periodic signal, the intelligent trigger module automatically identifies the period T of the waveform and adjusts the horizontal sensitivity g so that 10*g≥4T, that is, the waveform of the sampled signal is displayed on the screen for more than 4 cycles. If the waveform is a non-periodic signal, the intelligent trigger module automatically adjusts to the real-time mode. (2) Use the ADC in the oscilloscope to acquire the input signal and obtain the sampled signal, denoted as {x1, x2, ..., x...}. i ,…x N }, x i This represents the i-th sampling point, and N is the number of sampling points; (3) Calculate the maximum amplitude V among all sampling points using a histogram. max Minimum amplitude V min The initial trigger level is obtained by summing the amplitudes of the N sampling points and then averaging them. Among them, V i For x i The amplitude; (4) Rising edge trigger setting; Determine whether the sampled signal is a periodic signal. If the sampled signal is a periodic signal, then use V... initial The trigger level and rising edge are used as trigger conditions and sent to the FPGA to end the trigger setting; otherwise, proceed to step (5). (5) Pulse width trigger setting; (5.1) Extract the positive and negative pulses from the sampled signal; The sampled signal is compared with the initial trigger level using a comparator. If the amplitude of a certain sampling point in the sampled signal is greater than the initial trigger level V... initial Then the counter starts counting, and when it is less than the initial trigger level V... initial When the counter stops counting, a positive pulse is obtained; if the amplitude of a certain sampling point in the sampled signal is less than the initial trigger level V... initial Then the counter starts counting, and when it exceeds the initial trigger level V... initial When the counter stops counting, a negative pulse is obtained; (5.2) After all sampling points in the sampled signal are compared, assume that m positive pulses and k negative pulses are obtained; (5.3) Count the number of sampling points in each positive pulse as the positive pulse width value. If a unique positive pulse width value appears, then use V as the value. initial A unique positive pulse width value is sent to the FPGA as the trigger level, and the trigger setting ends; otherwise, the number of sampling points in each negative pulse is counted as the negative pulse width value. If a unique negative pulse width value is found, then V is used as the trigger level. initial The trigger level and a unique negative pulse width value are sent to the FPGA as the trigger condition, and the trigger setting ends; if there is no unique width value in either the positive or negative pulse, then proceed to step (6); (6) Slope trigger settings; (6.1) Set the voltage difference Δy = (V max +V min ) / 8; Set the high-level threshold V h =(V max +V min ) / 16; Set low-level threshold V l =-(V max +V min ) / 16; (6.2) Iterate through the amplitude of each sampling point in the sampled signal, and start the counter from the first one greater than V. l The counting starts from the sampling point and continues until the first sampling point is less than V. h The sampling points stop counting, and V is truncated. l ≤V i ≤V h By continuously sampling points, a positive pulse representing a positive slope is obtained; the counter starts from the first pulse less than V. h The counting begins from the sampling point, up to the first sampling point greater than V. l The sampling points stop counting, and V is truncated. l ≤V i ≤V h By continuously sampling points, a negative pulse representing a negative slope is obtained; (6.3) After all sampling points in the sampled signal have been traversed, assume that n positive pulses and q negative pulses are obtained; (6.4) Calculate the positive slope of each positive pulse; Calculate the negative slope of each negative pulse; Where λ is the number of sampling points in the positive pulse, α is the number of sampling points in the negative pulse, and Δt is the sampling interval between two adjacent sampling points; (6.5) If a unique positive slope value appears among n positive slope values, then V is the positive slope value. h V l A unique positive slope value is sent to the FPGA as the trigger level, and the trigger setting ends; otherwise, the count continues among q negative slope values. If a unique negative slope value appears, then V is used as the trigger level. h V l The trigger level and a unique negative slope value are sent to the FPGA as the trigger condition, and the trigger setting ends; if no unique slope value appears among all positive and negative slope values, then proceed to step (7); (7) Adjust the pulse width trigger condition; (7.1) Set the initial trigger level V initial The adjustment step ΔV = (V max +V min ) / 64, set the adjustment range to [V min V max ]; (7.2) Calculate the variance of the positive and negative pulse width values ​​obtained in step (5). If the variance of the positive pulse width value is large, then within the adjustment range [V min V max Inside, V initial Increase ΔV; otherwise, decrease V. initial Decrease ΔV, then repeat step (5). If a unique pulse width value appears, then use V. initial +ΔV or V initial -ΔV is sent to the FPGA as the trigger level and a unique pulse width value as the trigger condition, and the trigger setting ends; otherwise, proceed to step (8); (8) Adjust the slope trigger condition; (8.1) Set the high / low level adjustment step ΔV' = (V max +V min ) / 32, set the adjustment range to [V min V max ]; (8.2) Calculate the variance of the positive and negative slope values ​​obtained in step (6). If the variance of the positive slope is large, then within the adjustment range [V min V max Within [the specified range], the high and low level thresholds V h V l Simultaneously increase ΔV'; otherwise, set the high and low level thresholds V. h V l Simultaneously decrease ΔV', then repeat steps (6.2) to (6.4). If a unique slope value appears, then use V' as the slope value. h +ΔV'、V l +ΔV' or V h -ΔV'、V l -ΔV' is the trigger level, and the unique slope value is sent to the FPGA as the trigger condition, and the trigger setting ends; otherwise, return to step (7); (9) Intelligent setting of trigger conditions using the quartile method; If the adjustment range is [V] min V max If neither a unique pulse width value nor a unique slope value is found within the range, then the level V of the last adjustment is used. last Based on this, repeat steps (5.1) to (5.3) to count the positive pulse width of each positive pulse; The quartile method is used to detect whether the positive pulse width value of each positive pulse is an outlier: an outlier threshold ρ is set, and when the positive pulse width value of a positive pulse is greater than the outlier threshold ρ, the positive pulse width value is determined to be an outlier. Count the number of outliers. If only one positive pulse has a pulse width greater than the threshold outlier ρ, then use V... last The trigger level is set, and the positive pulse width value is used as the trigger condition. If multiple positive pulses have a positive pulse width value greater than the outlier threshold ρ, then the largest positive pulse width value is selected from the multiple positive pulse width values ​​greater than the outlier threshold ρ, and then V is used as the trigger level. last The trigger level and maximum positive pulse width are sent to the FPGA as trigger conditions, and the trigger setting is complete.

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