Phased array transmitted pulse detection and automatic correction device and method based on FPGA

Abstract

The invention provides a phased array transmitted pulse detection and automatic correction device and method based on an FPGA. The device comprises a pulse and parameter input interface, a crystal oscillator, an FPGA device and a correction pulse and alarm parameter output interface. The pulse and parameter input interface is used for inputting transmission pulses and detection parameters; the crystal oscillator is used for providing a reference clock signal for the FPGA device; the FPGA device is used for detecting and correcting a transmission pulse based on a detection parameter under a reference clock signal, and outputting a source transmission pulse or the corrected transmission pulse and an alarm parameter to the corrected pulse and alarm parameter output interface; and the corrected pulse and alarm parameter output interface is used for outputting source transmission pulses or corrected transmission pulses and alarm parameters. The device is small in size, simple in circuit, high in transportability, high in reliability and high in detection precision, and provides an automatic pulse correction function.

Description

Technical Field

[0001] The present invention relates to the technical field of phased array radar signal detection and embedded control, and more specifically, to a phased array transmit pulse detection and automatic correction device and method based on FPGA. Background Art

[0002] Active phased array radar technology is an important direction in the development of modern radar technology and is widely applied in communication, meteorological observation, and electronic warfare systems. An active phased array radar can interfere with signals in a specified direction within a short time, can also achieve multi-beam wide-airspace long-distance detection, and in addition, it can form a low sidelobe and high-gain beam to achieve long-distance operation.

[0003] The core to achieve the above characteristics is that each antenna unit channel of the active phased array radar is provided with a solid-state transmit / receive module, that is, a T / R module. The T / R module is equivalent to an ordinary RF head, which has both a transmit power amplifier, a low-noise amplifier, a phase shifter, a beam control circuit and other functional circuits. The core devices among them are vacuum tubes and solid-state amplifiers, and the price is very expensive. While obtaining a high transmit signal power through this highly integrated transmitter method, the heat generated instantaneously by the large-scale array and high-density integration during high-power transmit signals has become a hidden danger for ensuring the reliable operation of the active phased array. The core devices, the vacuum tube and the solid-state amplifier, both work in a pulsed state. Abnormal conditions such as the trigger pulse duty cycle exceeding the limit and continuous operation in an over-limit state will cause damage to key devices such as the vacuum tube and the solid-state amplifier. When an abnormal condition occurs, it is necessary to protect the T / R module in a timely manner. Therefore, improving the real-time detection and automatic correction capabilities of parameters such as the transmit pulse width and pulse duration of the phased array radar is of great significance for enhancing the reliability of the phased array and reducing the damage risk.

[0004] Currently, the duty cycle detection or pulse detection mostly adopts the implementation method of small-scale integrated circuits, or the implementation method of building a detection circuit using a detector, an inverter, a coupler, a bistable trigger circuit, a comparator, a transmitter, etc.

[0005] The current pulse detection methods have the following main disadvantages:

[0006] 1. Large volume: Using this method requires adding peripheral integrated circuits such as detectors, inverters, couplers, bistable flip-flops, transmitters, capacitors, and resistors in the circuit, which does not meet the miniaturization requirements of modern radars.

[0007] 2. Complex circuit: When adopting this method, the peripheral circuit needs to be designed strictly according to the working characteristics of various types of electronic components. Taking the bistable flip-flop as an example only, two sets of steady-state circuits are required. Each set of steady-state circuits needs power supply, flip-flop, capacitor, resistor, diode, inverter, etc. The number and types of components involved are numerous, which do not meet the requirements of simplicity and light weight of modern radars.

[0008] 3. Poor portability: When adopting this method, the parameter requirements for peripheral devices are very strict. The ideal output result must be obtained by precisely adjusting the sizes of capacitors and resistors. When the input pulse frequency changes, the device parameters need to be readjusted, and the adaptability is not high, which does not conform to the characteristics of wide range and multiple states of modern radars.

[0009] 4. Poor reliability: When adopting this method, it involves various devices such as capacitors, resistors, and diodes that are sensitive to temperature characteristics. Moreover, the probability of problems such as capacitor leakage and operational amplifier voltage offset is relatively high, which does not meet the requirements of high reliability for modern radars. Summary of the Invention

[0010] The present invention aims to provide a phased array transmit pulse detection and automatic correction device and method based on FPGA to solve at least one of the above-mentioned existing pulse detection methods and devices. Additionally, while solving the problems of the existing pulse detection methods and devices, the present invention provides an automatic pulse correction function.

[0011] In a first aspect, the present invention provides a phased array transmit pulse detection and automatic correction device based on FPGA, including a pulse and parameter input interface, a crystal oscillator, an FPGA device, and a corrected pulse and alarm parameter output interface;

[0012] The pulse and parameter input interface is used to input transmit pulses and detection parameters;

[0013] The crystal oscillator is used to provide a reference clock signal to the FPGA device;

[0014] The FPGA device is used to detect and correct the transmit pulse based on the detection parameters under the reference clock signal, and output the source transmit pulse or the corrected transmit pulse and alarm parameters to the corrected pulse and alarm parameter output interface;

[0015] The corrected pulse and alarm parameter output interface is used to output the source transmit pulse or the corrected transmit pulse and alarm parameters.

[0016] In some embodiments, a clock frequency division module and a parameter setting detection module, a pulse width detection module, a duty cycle detection module, an overlimit detection module, and a transmit pulse correction and output selection module are sequentially connected inside the FPGA device;

[0017] The clock frequency division module is used to generate a counting reference clock by frequency multiplication based on the reference clock signal provided by the crystal oscillator for each module of the FPGA device to use;

[0018] The parameter setting detection module is used to detect the received input emission pulse and detection parameters, and output a parameter setting reminder flag;

[0019] The pulse width detection module is used to receive the input emission pulse and detection parameters, count the high level of a single emission pulse of the emission pulse to obtain a pulse width count value, and output the pulse width count value to the overlimit detection module;

[0020] The duty cycle detection module is used to receive the input emission pulse and detection parameters, count the high level of the emission pulse according to a set period to obtain a duty cycle count value, and output the duty cycle count value to the overlimit detection module;

[0021] The overlimit detection module is used to compare the pulse width count value and the duty cycle count value with corresponding threshold values, and output an overlimit flag and a forced shutdown flag;

[0022] The emission pulse correction and output selection module is used to detect the received forced output flag, the overlimit flag output by the overlimit detection module, and the forced shutdown flag, and output an emission pulse or a corrected emission pulse.

[0023] In some embodiments, the parameter setting detection module is specifically used to detect the received input emission pulse and detection parameters, and judge whether the pulse width threshold value, the duty cycle threshold value of the emission pulse, as well as the period of the emission pulse, the forced shutdown detection period, and the abnormal threshold value within the forced shutdown detection period are 0. If it is 0, an abnormal signal is output to the correction pulse and alarm parameter output interface; otherwise, a normal signal is output to the correction pulse and alarm parameter output interface.

[0024] In some embodiments, the overlimit detection module is specifically used for:

[0025] Compare the pulse width count value with the set pulse width threshold value according to the set forced shutdown detection period. If it is greater than the pulse width threshold value, generate a pulse width overlimit flag; otherwise, output a normal flag;

[0026] Compare the duty cycle count value with the set duty cycle threshold value. If it is greater than the duty cycle threshold value, generate a duty cycle overlimit flag; otherwise, output a normal flag;

[0027] Compare the pulse width overlimit flag and the duty cycle overlimit flag with a preset forced shutdown threshold value; if it is greater than the forced shutdown threshold value, generate a forced shutdown flag; otherwise, output a normal flag;

[0028] Output the pulse width overrun flag, duty cycle overrun flag, and forced shutdown flag to the emission pulse correction and output selection module.

[0029] In some embodiments, the emission pulse correction and output selection module is specifically configured to:

[0030] Determine whether the forced output parameter is 1. If so, directly output the source emission pulse to the corrected pulse and alarm parameter output interface; otherwise, determine whether the forced shutdown flag is 1. If so, output 0 to the corrected pulse and alarm parameter output interface; otherwise, determine whether the duty cycle overrun flag is 1. If so, output 0 to the corrected pulse and alarm parameter output interface; otherwise, determine whether the pulse width overrun flag is 1. If so, output 0 to the corrected pulse and alarm parameter output interface; otherwise, directly output the source emission pulse to the corrected pulse and alarm parameter output interface.

[0031] In a second aspect, the present invention provides a phased array emission pulse detection and automatic correction method based on FPGA, including:

[0032] Input the emission pulse and detection parameters;

[0033] Provide a reference clock signal;

[0034] Under the reference clock signal, detect and correct the emission pulse based on the detection parameters;

[0035] Output the source emission pulse or the corrected emission pulse and alarm parameters.

[0036] In some embodiments, the step of detecting and correcting the emission pulse based on the detection parameters under the reference clock signal includes:

[0037] Based on the reference clock signal, generate a counting reference clock by frequency doubling for subsequent use;

[0038] Detect the received emission pulse and detection parameters, and output a parameter setting reminder flag;

[0039] Count the high level of a single emission pulse of the emission pulse to obtain a pulse width count value;

[0040] Count the high level of the emission pulse at a set period to obtain a duty cycle count value;

[0041] Compare the pulse width count value and the duty cycle count value with the corresponding threshold values, and output an overrun flag and a forced shutdown flag;

[0042] Detect the received forced output flag, overrun flag, and forced shutdown flag, and output the emission pulse or the corrected emission pulse.

[0043] In some embodiments, detecting the received transmitted pulse and detection parameters and outputting a parameter setting reminder flag includes:

[0044] Detect the received transmitted pulse and detection parameters, and determine whether the pulse width threshold value, duty cycle threshold value, period of the transmitted pulse, forced shutdown detection period, and abnormal threshold value within the forced shutdown detection period of the transmitted pulse are 0. If they are 0, output an abnormal signal to the correction pulse and alarm parameter output interface; otherwise, output a normal signal to the correction pulse and alarm parameter output interface.

[0045] In some embodiments, comparing the pulse width count value and duty cycle count value with the corresponding threshold values and outputting an overlimit flag and a forced shutdown flag includes:

[0046] According to the set forced shutdown detection period, compare the pulse width count value with the set pulse width threshold value. If it is greater than the pulse width threshold value, generate a pulse width overlimit flag; otherwise, output a normal flag.

[0047] Compare the duty cycle count value with the set duty cycle threshold value. If it is greater than the duty cycle threshold value, generate a duty cycle overlimit flag; otherwise, output a normal flag.

[0048] Compare the pulse width overlimit flag and duty cycle overlimit flag with the preset forced shutdown threshold value; if it is greater than the forced shutdown threshold value, generate a forced shutdown flag; otherwise, output a normal flag.

[0049] Output the pulse width overlimit flag, duty cycle overlimit flag, and forced shutdown flag.

[0050] In some embodiments, detecting the received forced output flag, overlimit flag, and forced shutdown flag includes:

[0051] Determine whether the forced output parameter is 1. If it is, directly output the source transmitted pulse; otherwise, determine whether the forced shutdown flag is 1. If it is, output 0; otherwise, determine whether the duty cycle overlimit flag is 1. If it is, output 0; otherwise, determine whether the pulse width overlimit flag is 1. If it is, output 0; otherwise, directly output the source transmitted pulse.

[0052] In summary, due to the adoption of the above technical solutions, the beneficial effects of the present invention are:

[0053] 1. Small volume and simple circuit: This solution does not require additional circuits and can be embedded in the transmitter beam control system.

[0054] 2. Strong portability: The present invention is mainly carried in the FPGA inside the beam control system and is implemented through a hardware description language. The transmitted pulse detection parameters can be configured online through the system.

[0055] 3. High reliability: The present invention is mainly implemented through digital logic in the FPGA, with fewer peripheral devices and less affected by environmental factors such as temperature and electromagnetic interference.

[0056] 4. High detection accuracy: The detection accuracy of the present invention is mainly related to the counting reference clock frequency. When using a 100 MHz clock as the reference clock, an accuracy range of ±10 ns can be achieved, enabling high-precision detection and protection.

[0057] 5. The present invention can be applied to the control and protection system of phased array transmitters and is also applicable to other similar pulse detection and protection scenarios.

[0058] 6. While solving the problems of the prior art, the present invention additionally solves the problem that the prior art only targets pulse anomaly detection and cannot correct abnormal pulses. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 FIG. is a schematic diagram of a phased array transmit pulse detection and automatic correction device based on FPGA proposed in an embodiment of the present invention.

[0060] Figure 2 FIG. is a flowchart of a phased array transmit pulse detection and automatic correction method based on FPGA proposed in an embodiment of the present invention.

[0061] Figure 3 FIG. is a pulse timing diagram in a transmit pulse correction and output selection module in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0062] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. Usually, the components of the embodiments of the present invention described and illustrated herein can be arranged and designed in various different configurations.

[0063] Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0064] As Figure 1 shown, an embodiment of the present invention proposes a phased array transmit pulse detection and automatic correction device based on FPGA, including a pulse and parameter input interface, a crystal oscillator, an FPGA device, and a corrected pulse and alarm parameter output interface;

[0065] The pulse and parameter input interface is used to input emission pulses and detection parameters;

[0066] The crystal oscillator is used to provide a reference clock signal to the FPGA device;

[0067] The FPGA device is used to detect and correct the emission pulses based on the detection parameters under the reference clock signal, and output the source emission pulses or the corrected emission pulses and alarm parameters to the corrected pulse and alarm parameter output interface;

[0068] The corrected pulse and alarm parameter output interface is used to output the source emission pulses or the corrected emission pulses and alarm parameters.

[0069] In some embodiments, a clock frequency division module, a parameter setting and detection module, a pulse width detection module, a duty cycle detection module, an overlimit detection module, and an emission pulse correction and output selection module are sequentially connected inside the FPGA device. Specifically:

[0070] The clock frequency division module is used to generate a counting reference clock for each module of the FPGA device by frequency doubling based on the reference clock signal provided by the crystal oscillator;

[0071] The parameter setting and detection module is used to detect the received input emission pulses and detection parameters, and output a parameter setting reminder flag; specifically: determine whether the pulse width threshold value, duty cycle threshold value, period of the emission pulse, forced turn-off detection period, and abnormal threshold value within the forced turn-off detection period of the emission pulse are 0. If they are 0, an abnormal signal is output to the corrected pulse and alarm parameter output interface; otherwise, a normal signal is output to the corrected pulse and alarm parameter output interface;

[0072] The pulse width detection module is used to receive the input emission pulses and detection parameters, count the high level of a single emission pulse of the emission pulses to obtain a pulse width count value, and output the pulse width count value to the overlimit detection module;

[0073] The duty cycle detection module is used to receive the input emission pulses and detection parameters, count the high level of the emission pulses according to a set period to obtain a duty cycle count value, and output the duty cycle count value to the overlimit detection module;

[0074] The overrun detection module is used to compare the pulse width count value and the duty cycle count value with the corresponding threshold values, and output an overrun flag and a forced shutdown flag; specifically: according to the set forced shutdown detection period, compare the pulse width count value with the set pulse width threshold value, if it is greater than the pulse width threshold value, generate a pulse width overrun flag, otherwise output a normal flag; compare the duty cycle count value with the set duty cycle threshold value, if it is greater than the duty cycle threshold value, generate a duty cycle overrun flag, otherwise output a normal flag; compare the pulse width overrun flag and the duty cycle overrun flag with the preset forced shutdown threshold value; if it is greater than the forced shutdown threshold value, generate a forced shutdown flag, otherwise output a normal flag; output the pulse width overrun flag, the duty cycle overrun flag and the forced shutdown flag to the transmit pulse correction and output selection module.

[0075] The transmit pulse correction and output selection module is used to detect the forced output flag, the overrun flag and the forced shutdown flag output by the overrun detection module, and output a transmit pulse or a corrected transmit pulse. Specifically: judge whether the forced output parameter is 1, if so, directly output the source transmit pulse to the corrected pulse and alarm parameter output interface; otherwise, judge whether the forced shutdown flag is 1, if so, output 0 to the corrected pulse and alarm parameter output interface; otherwise, judge whether the duty cycle overrun flag is 1, if so, output 0 to the corrected pulse and alarm parameter output interface; otherwise, judge whether the pulse width overrun flag is 1, if so, output 0 to the corrected pulse and alarm parameter output interface; otherwise, directly output the source transmit pulse to the corrected pulse and alarm parameter output interface.

[0076] Based on the same technical concept, as Figure 2 shown, an embodiment of the present invention provides a phased array transmit pulse detection and automatic correction method based on FPGA, including:

[0077] S101, input a transmit pulse and detection parameters;

[0078] S102, provide a reference clock signal;

[0079] S103, under the reference clock signal, detect and correct the transmit pulse based on the detection parameters;

[0080] S104, output the source transmit pulse or the corrected transmit pulse and alarm parameters.

[0081] In some embodiments, as Figure 3 shown, the detecting and correcting the transmit pulse based on the detection parameters under the reference clock signal includes:

[0082] S31, based on the reference clock signal, generate a counting reference clock by frequency doubling for subsequent use;

[0083] S32. Detect the received transmitted pulse and detection parameters, and output a parameter setting reminder flag. Specifically, it includes: detecting the received transmitted pulse and detection parameters, and determining whether the pulse width threshold value, duty cycle threshold value, the period of the transmitted pulse, the forced turn-off detection period, and the abnormal threshold value within the forced turn-off detection period of the transmitted pulse are 0. If they are 0, an abnormal signal is output to the corrected pulse and alarm parameter output interface; otherwise, a normal signal is output to the corrected pulse and alarm parameter output interface.

[0084] S33. Count the high level of a single transmitted pulse of the transmitted pulse to obtain a pulse width count value.

[0085] S34. Count the high level of the transmitted pulse at a set period to obtain a duty cycle count value.

[0086] S35. Compare the pulse width count value and the duty cycle count value with the corresponding threshold values, and output an overlimit flag and a forced turn-off flag. Specifically, it includes: according to the set forced turn-off detection period, compare the pulse width count value with the set pulse width threshold value. If it is greater than the pulse width threshold value, a pulse width overlimit flag is generated; otherwise, a normal flag is output. Compare the duty cycle count value with the set duty cycle threshold value. If it is greater than the duty cycle threshold value, a duty cycle overlimit flag is generated; otherwise, a normal flag is output. Compare the pulse width overlimit flag, the duty cycle overlimit flag with the preset forced turn-off threshold value. If it is greater than the forced turn-off threshold value, a forced turn-off flag is generated; otherwise, a normal flag is output. Output the pulse width overlimit flag, the duty cycle overlimit flag and the forced turn-off flag.

[0087] S36. Detect the received forced output flag, overlimit flag and forced turn-off flag, and output the transmitted pulse or the corrected transmitted pulse. Specifically, it includes: determining whether the forced output parameter is 1. If it is, directly output the source transmitted pulse; otherwise, determine whether the forced turn-off flag is 1. If it is, output 0; otherwise, determine whether the duty cycle overlimit flag is 1. If it is, output 0; otherwise, determine whether the pulse width overlimit flag is 1. If it is, output 0; otherwise, directly output the source transmitted pulse.

[0088] Each step in the above method corresponds to the working principle of each functional module in the device embodiment. The working principle and method of the above device are described below with a specific example as follows:

[0089] 1. Clock division module

[0090] Based on the reference clock signal provided by the crystal oscillator, the clock division module generates a 10 ns counting reference clock through frequency multiplication for each module of the FPGA device to use.

[0091] 2. Parameter setting and detection module:

[0092] (1) The FPGA device sets a parameter - setting detection exception variable E1, a pulse - width threshold constant P1, a duty - cycle threshold constant P2, a period constant P3 of the transmitted pulse, a forced - turn - off detection period constant P4, an exception threshold constant P5 within the forced - turn - off detection period, and a forced - output constant P6;

[0093] (2) Determine whether P1, P2, P3, P4, and P5 satisfy the following relational expression:

[0094] (P1, P2, P3, P4, P5)=0;

[0095] If satisfied, set the parameter - setting detection exception variable E1 to 1; otherwise, set the parameter - setting detection exception variable E1 to 0. (For convenience of description, "1" (high level) represents an exception, and "0" (low level) represents normal.)

[0096] 3. Pulse - width detection module:

[0097] (1) The FPGA device sets a pulse - width detection exception variable E2 and a single - pulse - width count variable C1;

[0098] (2) The FPGA device sets two rising - edge detection variables H1 and H2. At each rising edge of the 10 - ns counting reference clock, the transmitted pulse is non - blocking assigned to H1, and H1 is non - blocking assigned to H2;

[0099] (3) At each rising edge of the 10 - ns counting reference clock, determine whether H1 == 0 and H2 == 1 hold. If so, set the single - pulse - width count variable C1 to 0;

[0100] (4) At each rising edge of the 10 - ns counting reference clock, determine whether the transmitted pulse is at a high level. If so, increment the single - pulse - width count variable C1 by 1;

[0101] (5) At each rising edge of the 10 - ns counting reference clock, determine whether the variable C1 > P1 holds. If so, set the pulse - width detection exception variable E2 to 1; otherwise, set it to 0.

[0102] 4. Duty - cycle detection module:

[0103] (1) The FPGA device sets a duty - cycle detection exception variable E3, a duty - cycle count variable C2, and a pulse - width period count variable C3;

[0104] (2) At each rising edge of the 10 - ns counting reference clock, determine whether the transmitted pulse is at a high level. If so, increment the duty - cycle count variable C2 by 1;

[0105] (3) At the rising edge of each 10 ns counting reference clock, the FPGA device increments the pulse width period counting variable C3 by 1.

[0106] (4) At the rising edge of each 10 ns counting reference clock, the FPGA device determines whether C3 == P3 holds. If so, it sets the duty cycle counting variable C2 and the pulse width period counting variable C3 to 0.

[0107] (5) At the rising edge of each 10 ns counting reference clock, the FPGA device determines whether C3 == P3 and the variable C2 > P2 hold. If so, it sets the pulse width detection abnormal variable E3 to 1; otherwise, it sets it to 0.

[0108] 5. Overrun detection module:

[0109] (1) The FPGA device sets a forced shutdown variable E4, an abnormal count variable C4 within a forced shutdown period, and a forced shutdown period counting variable C5.

[0110] (2) At the rising edge of each 10 ns counting reference clock, the FPGA device determines whether the variables E2 and E3 are at a high level. If so, it increments the abnormal count variable C4 within the forced shutdown period by 1.

[0111] (3) At the rising edge of each 10 ns counting reference clock, the FPGA device increments the forced shutdown period counting variable C5 by 1.

[0112] (4) At the rising edge of each 10 ns counting reference clock, the FPGA device determines whether C5 == P4 holds. If so, it sets the forced shutdown period counting variable C5 to 0.

[0113] (5) At the rising edge of each 10 ns counting reference clock, the FPGA device determines whether C5 == P4 and the variable C4 ≥ P5 hold. If so, it sets the pulse width detection abnormal variable E4 to 1; otherwise, it sets it to 0.

[0114] 6. Transmitted pulse correction and output selection module:

[0115] (1) The FPGA device sets a corrected pulse output variable M1.

[0116] (2) At the rising edge of each 10 ns counting reference clock, the FPGA device determines whether the forced output constant P6 == 1 holds. If so, the corrected pulse output variable M1 directly outputs the externally input transmitted pulse; otherwise, it proceeds to step (3).

[0117] (3) At the rising edge of each 10 ns counting reference clock, the FPGA device determines whether the variable E4 == 1 holds. If so, it sets the corrected pulse output variable M1 to 0; otherwise, it proceeds to step (4).

[0118] (5) At the rising edge of each 10 ns counting reference clock, the FPGA device determines whether the variable E3 == 1 holds. If so, the corrected pulse output variable M1 is set to 0; otherwise, it proceeds to step (5).

[0119] (6) At the rising edge of each 10 ns counting reference clock, the FPGA device determines whether the variable E2 == 1 holds. If so, the corrected pulse output variable M1 is set to 0; otherwise, it directly outputs the external emission pulse. The final emission pulse output timing is as Figure 3 shown, Figure 3 where T is one counting reference clock period.

[0120] The detection and automatic correction of the emission pulse can be achieved through the above steps.

[0121] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are as follows:

[0122] 1. Small size and simple circuit: This solution does not require additional circuits and can be embedded into the transmitter beam control system.

[0123] 2. Strong portability: The present invention is mainly implemented in the FPGA inside the beam control system through a hardware description language, and the emission pulse detection parameters can be configured online through the system.

[0124] 3. High reliability: The present invention is mainly implemented through digital logic in the FPGA, with few peripheral devices and little influence from environmental factors such as temperature and electromagnetic interference.

[0125] 4. High detection accuracy: The detection accuracy of the present invention is mainly related to the counting reference clock frequency. When using a 100 MHz clock as the reference clock, an accuracy range of ±10 ns can be achieved, enabling high-precision detection and protection.

[0126] 5. The present invention can be applied to the phased array transmitter control and protection system, and is also applicable to other similar pulse detection and protection scenarios.

[0127] 6. While solving the problems of the existing technology, the present invention additionally solves the problem that the existing technology only targets pulse anomaly detection and cannot correct abnormal pulses.

[0128] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A phased array transmit pulse detection and automatic correction device based on FPGA, characterized in that It includes a pulse and parameter input interface, a crystal oscillator, an FPGA device, and a corrected pulse and alarm parameter output interface; The pulse and parameter input interface is used to input the emission pulse and detection parameters; The crystal oscillator is used to provide a reference clock signal to the FPGA device; The FPGA device is used to detect and correct the emission pulse based on the detection parameters under the reference clock signal, and output the source emission pulse or the corrected emission pulse and alarm parameters to the corrected pulse and alarm parameter output interface; The corrected pulse and alarm parameter output interface is used to output the source emission pulse or the corrected emission pulse and alarm parameters.

2. The phased array transmit pulse detection and automatic correction method based on FPGA according to claim 1, characterized in that Inside the FPGA device, there is a clock frequency division module, and a parameter setting and detection module, a pulse width detection module, a duty cycle detection module, an overlimit detection module, and an emission pulse correction and output selection module connected in sequence; The clock frequency division module is used to generate a counting reference clock by frequency doubling based on the reference clock signal provided by the crystal oscillator for each module of the FPGA device to use; The parameter setting and detection module is used to detect the received input emission pulse and detection parameters, and output a parameter setting reminder flag; The pulse width detection module is used to receive the input emission pulse and detection parameters, count the high level of a single emission pulse of the emission pulse to obtain a pulse width count value, and output the pulse width count value to the overlimit detection module; The duty cycle detection module is used to receive the input emission pulse and detection parameters, count the high level of the emission pulse according to a set period to obtain a duty cycle count value, and output the duty cycle count value to the overlimit detection module; The overlimit detection module is used to compare the pulse width count value and the duty cycle count value with the corresponding threshold values, and output an overlimit flag and a forced shutdown flag; The emission pulse correction and output selection module is used to detect the received forced output flag, the overlimit flag output by the overlimit detection module, and the forced shutdown flag, and output the emission pulse or the corrected emission pulse.

3. The method for phased array transmit pulse detection and automatic correction based on FPGA according to claim 2, wherein Specifically, the parameter setting and detection module is used to detect the received input emission pulse and detection parameters, and judge whether the pulse width threshold value, the duty cycle threshold value, the period of the emission pulse, the forced shutdown detection period, and the abnormal threshold value within the forced shutdown detection period of the emission pulse are 0. If they are 0, an abnormal signal is output to the corrected pulse and alarm parameter output interface; Otherwise, a normal signal is output to the corrected pulse and alarm parameter output interface.

4. The method for phased array transmit pulse detection and automatic correction based on FPGA according to claim 2, characterized in that, Specifically, the overlimit detection module is used for: According to the set forced shutdown detection period, compare the pulse width count value with the set pulse width threshold value. If it is greater than the pulse width threshold value, generate a pulse width overlimit flag, otherwise output a normal flag; Compare the duty cycle count value with the set duty cycle threshold value. If it is greater than the duty cycle threshold value, generate a duty cycle overlimit flag, otherwise output a normal flag; Compare the pulse width overlimit flag and the duty cycle overlimit flag with a preset forced shutdown threshold value; If it is greater than the forced shutdown threshold value, generate a forced shutdown flag, otherwise output a normal flag; Output the pulse width overrun flag, duty cycle overrun flag, and forced shutdown flag to the emission pulse correction and output selection module.

5. The method for phased array emission pulse detection and automatic correction based on FPGA according to claim 4, characterized in that The emission pulse correction and output selection module is specifically configured to: Determine whether the forced output parameter is 1. If so, directly output the source emission pulse to the corrected pulse and alarm parameter output interface; otherwise, determine whether the forced shutdown flag is 1. If so, output 0 to the corrected pulse and alarm parameter output interface; Otherwise, determine whether the duty cycle overrun flag is 1. If so, output 0 to the corrected pulse and alarm parameter output interface; Otherwise, determine whether the pulse width overrun flag is 1. If so, output 0 to the corrected pulse and alarm parameter output interface; Otherwise, directly output the source emission pulse to the corrected pulse and alarm parameter output interface.

6. A phased array transmit pulse detection and automatic correction method based on FPGA, characterized in that, It includes: Input the emission pulse and detection parameters; Provide a reference clock signal; Under the reference clock signal, detect and correct the emission pulse based on the detection parameters; Output the source emission pulse or the corrected emission pulse and alarm parameters.

7. The method for phased array transmit pulse detection and automatic correction based on FPGA according to claim 6, characterized in that, The detecting and correcting the emission pulse based on the detection parameters under the reference clock signal includes: Based on the reference clock signal, generate a counting reference clock by frequency doubling for subsequent use; Detect the received emission pulse and detection parameters, and output a parameter setting reminder flag; Count the high level of a single emission pulse of the emission pulse to obtain a pulse width count value; Count the high level of the emission pulse at a set period to obtain a duty cycle count value; Compare the pulse width count value and the duty cycle count value with the corresponding threshold values, and output an overrun flag and a forced shutdown flag; Detect the received forced output flag, overrun flag, and forced shutdown flag, and output the emission pulse or the corrected emission pulse.

8. The method for phased array emission pulse detection and automatic correction based on FPGA according to claim 7, wherein The detecting the received emission pulse and detection parameters and outputting a parameter setting reminder flag includes: Detect the received emission pulse and detection parameters, and determine whether the pulse width threshold value, duty cycle threshold value, period of the emission pulse, forced shutdown detection period, and abnormal threshold value within the forced shutdown detection period of the emission pulse are 0. If so, output an abnormal signal to the corrected pulse and alarm parameter output interface; otherwise, output a normal signal to the corrected pulse and alarm parameter output interface.

9. The method for phased array transmit pulse detection and automatic correction based on FPGA according to claim 7, wherein, The comparing the pulse width count value and the duty cycle count value with the corresponding threshold values and outputting an overrun flag and a forced shutdown flag includes: According to the set forced shutdown detection period, compare the pulse width count value with the set pulse width threshold value. If it is greater than the pulse width threshold value, generate a pulse width overrun flag; otherwise, output a normal flag; Compare the duty cycle count value with the set duty cycle threshold value. If it is greater than the duty cycle threshold value, generate a duty cycle overrun flag; otherwise, output a normal flag; Compare the pulse width overrun flag and the duty cycle overrun flag with a preset forced shutdown threshold value; if it is greater than the forced shutdown threshold value, generate a forced shutdown flag; otherwise, output a normal flag; Output the pulse width overrun flag, duty cycle overrun flag, and forced shutdown flag.

10. The method for phased array transmit pulse detection and automatic correction based on FPGA according to claim 9, wherein The detecting the received forced output flag, overrun flag, and forced shutdown flag includes: Judge whether the forced output parameter is 1. If it is, directly output the source emission pulse; otherwise, judge whether the forced turn-off flag is 1. If it is, output 0; otherwise, judge whether the duty cycle overrun flag is 1. If it is, output 0; otherwise, judge whether the pulse width overrun flag is 1. If it is, output 0; otherwise, directly output the source emission pulse.

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