Low-dropout linear voltage stabilizing circuit, circuit architecture and electronic equipment

Abstract

The invention provides a low-dropout linear voltage stabilizing circuit, a circuit framework and electronic equipment, in the low-dropout linear voltage stabilizing circuit, an overshoot suppression module can output a first suppression current to the output end of an error amplification module, so that the voltage difference between an error amplification voltage and a power supply voltage is reduced, and the voltage stability of the circuit framework is improved. The driving control unit can output the driving current according to the difference value between the accessed power supply voltage and the error amplification voltage accessed by the driving module, and the driving current is in positive correlation with the difference value between the power supply voltage and the error amplification voltage accessed by the driving module. Thus, the magnitude of the driving current can be limited by limiting the magnitude of the difference between the error amplification voltage and the power supply voltage. The output voltage of the low-dropout linear voltage stabilizing circuit is generated according to the driving current, so that the overshoot amplitude of the output voltage of the low-dropout linear voltage stabilizing circuit can be limited by limiting the size of the driving current.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and particularly to a low dropout linear voltage regulator circuit, a circuit architecture, and an electronic device. Background Art

[0002] A low dropout linear regulator is a special linear regulator that can operate normally when the voltage difference between the input voltage and the output voltage is very small. When the low dropout linear regulator is powered on and starts up, its output voltage will gradually rise to the rated voltage. However, when the output voltage reaches the rated voltage, the control loop requires a certain response time to start regulating the output voltage. During this short response time, the output voltage will still gradually rise, resulting in an overshoot phenomenon. Summary of the Invention

[0003] The present invention provides a low dropout linear voltage regulator circuit, a circuit architecture, and an electronic device to reduce the overshoot phenomenon of the output voltage of the low dropout linear voltage regulator circuit.

[0004] According to the technical solution of the present invention, a low dropout linear voltage regulator circuit is provided, including:

[0005] A driving module, the first input end of the driving module is connected to a supply voltage, and the driving module is configured to output a driving current according to the supplied supply voltage and the signal at the first input end of the driving module, and the driving current is positively correlated with the difference between the supplied supply voltage and the voltage at the first input end of the driving module;

[0006] A feedback module for generating an output voltage according to the driving current;

[0007] A first bias current unit, the first end of the first bias current unit is connected to a supply voltage, and the second end of the first bias current unit is configured to output a first bias current;

[0008] An error amplification module for amplifying the difference between a reference voltage and the output voltage according to the input first bias current and outputting a corresponding error amplification voltage, and the first input end of the driving module is connected to the error amplification voltage;

[0009] An overshoot suppression module for outputting a first suppression current to the output end of the error amplification module to reduce the difference between the error amplification voltage and the supply voltage.

[0010] Optionally, the error amplification module includes:

[0011] An input unit, which is configured to compare the reference voltage and the output voltage according to the first bias current and output a first current and a second current correspondingly. The first input terminal and the second input terminal of the output unit are respectively configured to connect to the reference voltage and the output voltage, and the first output terminal and the second output terminal of the output unit are respectively configured to output the first current and the second current;

[0012] A second bias current unit, the first output terminal and the second output terminal of the second bias current unit are respectively configured to output a second bias current and a third bias current. The magnitudes of the second bias current and the third bias current are the same. Moreover, the first input terminal of the second bias current unit is connected to the first output terminal of the input unit, the second input terminal of the second bias current unit is connected to the second output terminal of the input unit, and both the first output terminal and the second output terminal of the second bias current unit are grounded;

[0013] A first current mirror unit, the input terminal of the first current mirror unit is connected to the power supply voltage. The first output terminal and the second output terminal of the first current mirror unit are respectively configured to output a third current and a fourth current. The first output terminal of the first current mirror unit is coupled to the first input terminal of the second bias current unit, and the second output terminal of the first current mirror unit is coupled to the second input terminal of the second bias current unit. Moreover, the first output terminal of the first current mirror unit also serves as the output terminal of the error amplification module, and the magnitudes of the third current and the fourth current are the same.

[0014] Optionally, the overshoot suppression module includes a second current mirror unit, and the second current mirror unit includes:

[0015] An eighth PMOS transistor, the drain terminal of the eighth PMOS transistor is connected to the second output terminal of the first current mirror unit and is configured to output a second suppression current, and the magnitude of the second suppression current is the same as that of the first suppression current;

[0016] A ninth PMOS transistor, the drain terminal of the ninth PMOS transistor is connected to the first output terminal of the first current mirror unit and is configured to output a first suppression current. The gate terminal of the ninth PMOS transistor is connected to the gate terminal of the eighth PMOS transistor, and the gate terminal of the ninth PMOS transistor is connected to its own drain terminal;

[0017] A tenth PMOS transistor, the drain terminal of the tenth PMOS transistor is connected to the source terminal of the eighth PMOS transistor;

[0018] The eleventh PMOS transistor, the drain terminal of the eleventh PMOS transistor is connected to the source terminal of the ninth PMOS transistor, the gate terminal of the eleventh PMOS transistor is connected to the gate terminal of the tenth PMOS transistor, and the gate terminal of the eleventh PMOS transistor is connected to its own drain terminal;

[0019] The twelfth PMOS transistor, the drain terminal of the twelfth PMOS transistor is connected to the source terminal of the tenth PMOS transistor;

[0020] The thirteenth PMOS transistor, the drain terminal of the thirteenth PMOS transistor is connected to the source terminal of the eleventh PMOS transistor, the gate terminal of the thirteenth PMOS transistor is connected to the gate terminal of the twelfth PMOS transistor, and the gate terminal of the thirteenth PMOS transistor is connected to its own drain terminal, the source terminal of the thirteenth PMOS transistor is connected to the source terminal of the twelfth PMOS transistor and is connected to the power supply voltage.

[0021] Optionally, the input unit includes:

[0022] The first PMOS transistor, the gate terminal of the first PMOS transistor is connected to the reference voltage, the drain terminal of the first PMOS transistor is used to output the first current, and the source terminal of the first PMOS transistor is connected to the output terminal of the first bias current unit;

[0023] The second PMOS transistor, the gate terminal of the second PMOS transistor is connected to the output voltage, the drain terminal of the second PMOS transistor is used to output the second current, and the source terminal of the second PMOS transistor is connected to the output terminal of the first bias current unit.

[0024] Optionally, the second bias current unit includes:

[0025] The first bias current source, the output terminal of the first bias current source is used as the first output terminal of the second bias current unit, and the input terminal of the first bias current source is used as the first input terminal of the second bias current unit;

[0026] The second bias current source, the output terminal of the second bias current source is used as the second output terminal of the second bias current unit, and the input terminal of the second bias current source is used as the second input terminal of the second bias current unit.

[0027] Optionally, the first current mirror unit includes:

[0028] The third PMOS transistor, the drain terminal of the third PMOS transistor is used as the second output terminal of the first current mirror unit;

[0029] The fourth PMOS transistor, the drain terminal of the fourth PMOS transistor is used as the first output terminal of the first current mirror unit, and the gate terminal of the fourth PMOS transistor is connected to the gate terminal of the third PMOS transistor;

[0030] The fifth PMOS transistor, the drain terminal of the fifth PMOS transistor is connected to the source terminal of the third PMOS transistor;

[0031] The sixth PMOS transistor, the drain terminal of the sixth PMOS transistor is connected to the source terminal of the fourth PMOS transistor, the gate terminal of the sixth PMOS transistor is connected to the gate terminal of the fifth PMOS transistor and is connected to the drain terminal of the third PMOS transistor, and the source terminal of the sixth PMOS transistor is connected to the source terminal of the fifth PMOS transistor and is used as the input terminal of the first current mirror unit.

[0032] Optionally, the error amplification module further includes:

[0033] The first NMOS transistor, the source terminal of the first NMOS transistor is connected to the second input terminal of the second bias current unit, and the drain terminal of the first NMOS transistor is connected to the second output terminal of the first current mirror unit;

[0034] The second NMOS transistor, the source terminal of the second NMOS transistor is connected to the first input terminal of the second bias current unit, the drain terminal of the second NMOS transistor is connected to the first output terminal of the first current mirror unit, and the gate terminal of the second NMOS transistor is connected to the gate terminal of the first NMOS transistor.

[0035] Optionally, the driving module includes:

[0036] A driving control unit for outputting a control voltage according to the error amplification voltage, and the control voltage decreases as the error amplification voltage increases;

[0037] A power transistor, the control terminal of the power transistor is connected to the control voltage, the first terminal of the power transistor is connected to the supply voltage, and the second terminal of the power transistor is used to output a driving current according to the control voltage.

[0038] Optionally, the power transistor is an NMOS transistor, the first terminal of the power transistor is the drain terminal of the NMOS transistor, the second terminal of the power transistor is the source terminal of the NMOS transistor, and the control terminal of the power transistor is the gate terminal of the NMOS transistor;

[0039] The driving control unit includes:

[0040] The seventh PMOS transistor, the gate terminal of the seventh PMOS transistor is connected to the output terminal of the error amplification module, the source terminal of the seventh PMOS transistor is connected to the supply voltage, and the drain terminal of the seventh PMOS transistor is used as the output terminal of the drive control unit;

[0041] The control resistor, the first end of the control resistor is connected to the drain terminal of the seventh PMOS transistor, and the second end of the control resistor is connected to the ground.

[0042] Optionally, the feedback module includes:

[0043] The feedback resistor, the first end of the feedback resistor is connected to the output terminal of the drive module, and the second end of the feedback resistor is connected to the ground;

[0044] The output capacitor, the first end of the output capacitor is connected to the output terminal of the drive module, and the second end of the output capacitor is connected to the ground.

[0045] According to the technical solution of the present invention, a circuit architecture is further provided, including the above-mentioned low-dropout linear voltage regulator circuit.

[0046] According to the technical solution of the present invention, an electronic device is further provided, including the above-mentioned circuit architecture.

[0047] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0048] In a low-dropout linear voltage regulator circuit provided by the technical solution of the present invention, since the overshoot suppression module can output a first suppression current to the output terminal of the error amplification module, the voltage difference between the error amplification voltage and the supply voltage is reduced. Also, since the drive control unit can output a drive current according to the difference between the applied supply voltage and the voltage at the first input terminal of the drive module, and the first input terminal of the drive module is connected to the error amplification voltage, the drive current is positively correlated with the difference between the applied supply voltage and the voltage at the first input terminal of the drive module. Therefore, by limiting the magnitude of the difference between the error amplification voltage and the supply voltage, the magnitude of the drive current can be limited. Since the output voltage of the low-dropout linear voltage regulator circuit is generated according to the drive current, limiting the magnitude of the drive current can limit the overshoot amplitude of the output voltage of the low-dropout linear voltage regulator circuit. Description of the Drawings

[0049] Figure 1 It is a block diagram of a low-dropout linear voltage regulator circuit provided by an embodiment of the present invention;

[0050] Figure 2 It is a schematic circuit diagram of a low-dropout linear voltage regulator circuit provided by an embodiment of the present invention;

[0051] Figure 3 It is a schematic circuit diagram of a low dropout linear voltage regulator circuit provided by another embodiment of the present invention.

[0052] Reference numerals:

[0053] 10 - First bias current unit;

[0054] 20 - Error amplification module;

[0055] 30 - Overshoot suppression unit;

[0056] 40 - Driver module;

[0057] 41 - Driver control unit;

[0058] 50 - Feedback module;

[0059] 21 - First current mirror unit;

[0060] 22 - Input unit;

[0061] 23 - Second bias current unit;

[0062] Q - Power transistor;

[0063] VREF - Reference voltage;

[0064] VOUT - Output voltage;

[0065] PWR - Supply voltage;

[0066] VDD - Power supply voltage;

[0067] DC1 - First bias current source;

[0068] DC2 - Second bias current source;

[0069] DC3 - Third bias current source;

[0070] QP1 - First PMOS transistor;

[0071] QP2 - Second PMOS transistor;

[0072] QP3 - Third PMOS transistor;

[0073] QP4 - Fourth PMOS transistor;

[0074] QP5 - Fifth PMOS transistor;

[0075] QP6 - Sixth PMOS transistor;

[0076] QP7 - Seventh PMOS transistor;

[0077] QP8 - Eighth PMOS transistor;

[0078] QP9 - The ninth PMOS transistor;

[0079] QP10 - The tenth PMOS transistor;

[0080] QP11 - The eleventh PMOS transistor;

[0081] QP12 - The twelfth PMOS transistor;

[0082] QP13 - The thirteenth PMOS transistor;

[0083] QN1 - The first NMOS transistor;

[0084] QN2 - The second NMOS transistor;

[0085] R1 - Control resistor;

[0086] R2 - Feedback resistor;

[0087] C - Output capacitor. Detailed implementation manners

[0088] As described in the background art, the low dropout linear regulator circuit is prone to overshoot phenomenon.

[0089] In view of this, the technical solution of the present invention creatively provides a low dropout linear regulator circuit, including:

[0090] A driving module, the first input end of the driving module is connected to the supply voltage, and the driving module is configured to output a driving current according to the difference between the connected supply voltage and the voltage at the first input end of the driving module, and the driving current is positively correlated with the difference between the connected supply voltage and the voltage at the first input end of the driving module;

[0091] A feedback module, configured to generate an output voltage according to the driving current;

[0092] A first bias current unit, the first end of the first bias current unit is connected to the supply voltage, and the second end of the first bias current unit is configured to output a first bias current;

[0093] An error amplification module, configured to amplify the difference between the reference voltage and the output voltage according to the input first bias current and output a corresponding error amplification voltage, and the error amplification voltage decreases as the current at the output end of the error amplification module increases, and the first input end of the driving module is connected to the error amplification voltage;

[0094] An overshoot suppression module, configured to output a first suppression current to the output end of the error amplification module to reduce the difference between the error amplification voltage and the supply voltage.

[0095] Since the overshoot suppression module can output a first suppression current to the output terminal of the error amplification module, the voltage difference between the error amplification voltage and the supply voltage is reduced. Also, since the drive control unit can output a drive current according to the difference between the connected supply voltage and the voltage at the first input terminal of the drive module, and the first input terminal of the drive module is connected to the error amplification voltage, the drive current is positively correlated with the difference between the connected supply voltage and the voltage at the first input terminal of the drive module. Therefore, by limiting the magnitude of the voltage difference between the error amplification voltage and the supply voltage, the magnitude of the drive current can be limited. Since the output voltage of the low-dropout linear voltage regulator circuit is generated based on the drive current, limiting the magnitude of the drive current can limit the overshoot amplitude of the output voltage of the low-dropout linear voltage regulator circuit.

[0096] Next, the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present invention. The terms "first", "second", "third", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0097] Please refer to Figure 1 and Figure 2 , the low-dropout linear voltage regulator circuit includes: a drive module 40, a feedback module 50, a first bias current unit 10, an error amplification module 20, and an overshoot suppression module 30.

[0098] The first input terminal of the drive module 40 is connected to the supply voltage PWR, and the drive module 40 is configured to output a drive current according to the difference between the connected supply voltage PWR and the voltage at the first input terminal of the drive module 40. The drive current is positively correlated with the difference between the connected supply voltage PWR and the voltage at the first input terminal of the drive module 40. Wherein, the voltage at the first input terminal of the drive module 40 is the error amplification voltage.

[0099] The driving module 40 includes: a driving control unit 41 and a power transistor Q. Specifically, the driving control unit 41 is configured to output a control voltage according to the difference between the error amplified voltage and the supply voltage PWR. The first end of the power transistor Q is connected to the supply voltage PWR, the second end of the power transistor Q is configured to output a driving current, and the control end of the power transistor Q is connected to the output end of the driving control unit 41 and receives the control voltage.

[0100] In this embodiment, the driving control unit 41 includes a seventh PMOS transistor QP7 and a control resistor R1. Specifically, the gate terminal of the seventh PMOS transistor QP7 is connected to the third end of the first current mirror unit 21, the source terminal of the seventh PMOS transistor QP7 is connected to the supply voltage PWR, the drain terminal of the seventh PMOS transistor QP7 serves as the output end of the driving control unit 41, the first end of the control resistor R1 is connected to the drain terminal of the seventh PMOS transistor QP7, and the second end of the control resistor R1 is connected to the ground. Therefore, when the gate-source voltage of the seventh PMOS transistor QP7 decreases, that is, when the difference between the error amplified voltage and the supply voltage PWR decreases, the current output from the drain terminal of the seventh PMOS transistor QP7 decreases, so that the control voltage generated across the control resistor R1 after the current output from the drain terminal of the seventh PMOS transistor QP7 flows through the control resistor R1 decreases.

[0101] In this embodiment, the power transistor Q is an NMOS transistor. The drain terminal of the NMOS transistor serves as the first end of the power transistor Q and is connected to the supply voltage PWR. The source terminal of the NMOS transistor serves as the second end of the power transistor Q, and the gate terminal of the NMOS transistor serves as the control end of the power transistor Q and receives the control voltage. When the control voltage decreases, that is, when the voltage at the gate terminal of the NMOS transistor decreases, the current output from the source terminal of the NMOS transistor can be reduced, that is, the driving current decreases.

[0102] The feedback module 50 is configured to generate an output voltage VOUT according to the driving current.

[0103] In this embodiment, the feedback module 50 includes a feedback resistor R2 and an output capacitor C. Specifically, the first end of the feedback resistor R2 is connected to the output end of the driving module 40, the second end of the feedback resistor R2 is connected to the ground, the first end of the output capacitor C is connected to the output end of the driving module 40, and the second end of the output capacitor C is connected to the ground. Among them, since the driving current flows through the feedback resistor R2, a voltage can be generated across the feedback resistor R2 as the output voltage VOUT. Similarly, since the driving current flows through the output capacitor C and the output capacitor C can be used to store charge, based on the driving transistor continuously outputting the driving current, the voltage across the output capacitor C can continuously increase with time, that is, the output voltage VOUT can gradually increase.

[0104] The first end of the first bias current unit 10 is connected to the supply voltage PWR, and the second end of the first bias current unit 10 is used to output a first bias current.

[0105] In this embodiment, the first bias current unit 10 includes a third bias current source DC3. The input end of the third bias current source DC3 serves as the first end of the first bias current unit 10, and the output end of the third bias current source DC3 serves as the second end of the first bias current unit 10.

[0106] The error amplification module 20 is configured to amplify the difference between the reference voltage VREF and the output voltage VOUT according to the input first bias current and output a corresponding error amplification voltage.

[0107] In this embodiment, the error amplification module 20 includes: an input unit 22, a second bias current unit 23, and a first current mirror unit 21.

[0108] The input unit 22 is configured to compare the reference voltage and the output voltage according to the first bias current and output a first current and a second current correspondingly. The first input end and the second input end of the output unit 22 are respectively configured to be connected to the reference voltage VREF and the output voltage VOUT, and the first output end and the second output end of the output unit 22 are respectively configured to output the first current and the second current.

[0109] In this embodiment, the input unit 22 includes: a first PMOS transistor QP1 and a second PMOS transistor QP2. Specifically, the gate terminal of the first PMOS transistor QP1 is connected to the reference voltage VREF, the drain terminal of the first PMOS transistor QP1 is used to output the first current, and the source terminal of the first PMOS transistor QP1 is connected to the output end of the first bias current unit. The gate terminal of the second PMOS transistor QP2 is connected to the output voltage VOUT, the drain terminal of the second PMOS transistor QP2 is used to output the second current, and the source terminal of the second PMOS transistor QP2 is connected to the output end of the first bias current unit.

[0110] The first output end and the second output end of the second bias current unit 23 are respectively used to output a second bias current and a third bias current. The magnitudes of the second bias current and the third bias current are the same. Moreover, the first input end of the second bias current unit 23 is connected to the first output end of the input unit, the second input end of the second bias current unit 23 is connected to the second output end of the input unit, and both the first output end and the second output end of the second bias current unit 23 are grounded.

[0111] In this embodiment, the second bias current unit 23 includes: a first bias current source DC1 and a second bias current source DC2. Specifically, the output terminal of the first bias current source DC1 serves as the first output terminal of the second bias current unit 23, and the input terminal of the first bias current source DC1 serves as the first input terminal of the second bias current unit 23. The output terminal of the second bias current source DC2 serves as the second output terminal of the second bias current unit 23, and the input terminal of the second bias current source DC2 serves as the second input terminal of the second bias current unit 23.

[0112] The input terminal of the first current mirror unit 21 is connected to the supply voltage PWR. The first output terminal and the second output terminal of the first current mirror unit 21 are respectively used to output a third current and a fourth current. The first output terminal of the first current mirror unit 21 is coupled to the first input terminal of the second bias current unit 23, and the second output terminal of the first current mirror unit 21 is coupled to the second input terminal of the second bias current unit 23. Moreover, the first output terminal of the first current mirror unit 21 also serves as the output terminal of the error amplification module 20, and the magnitudes of the third current and the fourth current are the same.

[0113] In this embodiment, the first current mirror unit 21 includes: a third PMOS transistor QP3, a fourth PMOS transistor QP4, a fifth PMOS transistor QP5, and a sixth PMOS transistor QP6. Specifically, the drain terminal of the third PMOS transistor QP3 serves as the second output terminal of the first current mirror unit 21; the drain terminal of the fourth PMOS transistor QP4 serves as the first output terminal of the first current mirror unit 21, and the gate terminal of the fourth PMOS transistor QP4 is connected to the gate terminal of the third PMOS transistor QP3; the drain terminal of the fifth PMOS transistor QP5 is connected to the source terminal of the third PMOS transistor QP3; the drain terminal of the sixth PMOS transistor QP6 is connected to the source terminal of the fourth PMOS transistor QP4, the gate terminal of the sixth PMOS transistor QP6 is connected to the gate terminal of the fifth PMOS transistor QP5 and is connected to the drain terminal of the third PMOS transistor QP3, and the source terminal of the sixth PMOS transistor QP6 is connected to the source terminal of the fifth PMOS transistor QP5 and serves as the input terminal of the first current mirror unit. Among them, since the channel lengths of the third PMOS transistor QP3, the fourth PMOS transistor QP4, the fifth PMOS transistor QP5, and the sixth PMOS transistor QP6 are the same, therefore, the first current mirror unit 21 can be used to copy the fourth current at the second output terminal of the first current mirror unit to the first output terminal of the first current mirror to generate a third current, that is, the magnitudes of the third current and the fourth current are the same.

[0114] The overshoot suppression module 30 includes a second current mirror unit, and the second current mirror unit is a cascaded current mirror. Specifically, the second current mirror unit includes: an eighth PMOS transistor QP8, a ninth PMOS transistor QP9, a tenth PMOS transistor QP10, an eleventh PMOS transistor QP11, a twelfth PMOS transistor QP12, and a thirteenth PMOS transistor QP13. Specifically, the drain terminal of the eighth PMOS transistor QP8 is connected to the second output terminal of the first current mirror unit 21 for outputting a second suppression current, and the drain terminal of the ninth PMOS transistor QP9 is connected to the first output terminal of the first current mirror unit 21 for outputting a first suppression current. The gate terminal of the ninth PMOS transistor QP9 is connected to the gate terminal of the eighth PMOS transistor QP8, and the gate terminal of the ninth PMOS transistor QP9 is connected to its own drain terminal. The drain terminal of the tenth PMOS transistor QP10 is connected to the source terminal of the eighth PMOS transistor QP8, the drain terminal of the eleventh PMOS transistor QP11 is connected to the source terminal of the ninth PMOS transistor QP9, the gate terminal of the eleventh PMOS transistor QP11 is connected to the gate terminal of the tenth PMOS transistor QP10, and the gate terminal of the eleventh PMOS transistor QP11 is connected to its own drain terminal. The drain terminal of the twelfth PMOS transistor QP12 is connected to the source terminal of the tenth PMOS transistor QP10, the drain terminal of the thirteenth PMOS transistor QP13 is connected to the source terminal of the eleventh PMOS transistor QP11, the gate terminal of the thirteenth PMOS transistor QP13 is connected to the gate terminal of the twelfth PMOS transistor QP12, and the gate terminal of the thirteenth PMOS transistor QP13 is connected to its own drain terminal. The source terminal of the thirteenth PMOS transistor QP13 is connected to the source terminal of the twelfth PMOS transistor QP12 and is connected to the power supply voltage VDD. Wherein, the channel lengths of the eighth PMOS transistor QP8, the ninth PMOS transistor QP9, the tenth PMOS transistor QP10, the eleventh PMOS transistor QP11, the twelfth PMOS transistor QP12, and the thirteenth PMOS transistor QP13 are the same, so that the second current mirror unit can copy the first suppression current generated at the drain terminal of the ninth PMOS transistor QP9 to the drain terminal of the eighth PMOS transistor QP8, generate a second suppression current and output it, that is, the magnitudes of the second suppression current and the first suppression current are the same.

[0115] The working principle of the low dropout linear regulator circuit will be described below.

[0116] When the low dropout linear regulator circuit is not started, the drive current is 0, and the output voltage VOUT is also 0.

[0117] At the moment when the low-dropout linear voltage regulator circuit starts up, since the output voltage VOUT is 0, the second current is equal in magnitude to the first bias current. Moreover, the error amplification module 20 outputs a corresponding error amplification voltage at its output terminal, and the gate terminal of the seventh PMOS transistor QP7 is connected to the error amplification voltage, causing the seventh PMOS transistor QP7 to conduct. As a result, the drain current generated by the seventh PMOS transistor QP7 passes through the control resistor R1, and the control voltage generated across the control resistor R1 is used as the gate voltage of the power transistor Q, causing the power transistor Q to conduct and thus output a drive current. Since the feedback module 50 includes an output capacitor C, the voltage across the output capacitor C will gradually increase according to the drive current, that is, the output voltage VOUT gradually increases. When the output voltage VOUT is greater than 0, the first bias current is approximately equal to the sum of the first current and the second current, and the subsequent working principle is the same as that at the moment when the low-dropout linear voltage regulator circuit starts up, which will not be elaborated here. When the output voltage VOUT rises to the same voltage value as the reference voltage VREF, the first current and the second current are equal in magnitude, causing the current in the error amplification module to reach balance.

[0118] Among them, before the output terminal of the error amplification module 20 outputs the corresponding error amplification voltage, according to Kirchhoff's current law, the fourth current is equal to the difference between the second bias current and the second current. After the output terminal of the error amplification module 20 outputs the corresponding error amplification voltage, the seventh PMOS transistor QP7 conducts, and the first output terminal of the overshoot suppression module 30 outputs a first suppression current, that is, the first suppression current will flow through the series-connected ninth PMOS transistor QP9, eleventh PMOS transistor QP11, and thirteenth PMOS transistor QP13. According to Kirchhoff's current law, the sum of the fourth current and the second suppression current is equal to the difference between the second bias current and the second current. Therefore, after the overshoot suppression module 30 starts to work, the fourth current will decrease, thereby reducing the source-drain voltage of the PMOS transistors in the first current mirror unit 21, and thus reducing the difference between the error amplification voltage and the supply voltage. Since the gate terminal of the seventh PMOS transistor QP7 is connected to the error amplification voltage, after the difference between the error amplification voltage and the supply voltage decreases, the gate-source voltage of the seventh PMOS transistor QP7 will decrease, thereby reducing the drain current of the seventh PMOS transistor QP7. Furthermore, the control voltage generated across the control resistor R1 after the drain current of the seventh PMOS transistor QP7 passes through the control resistor R1 will decrease. Since the control terminal of the power transistor Q is connected to the control voltage and the power transistor Q is an NMOS transistor, a decrease in the control voltage can cause the drive current output by the power transistor Q to decrease. Therefore, a decrease in the drive current can limit the rising speed of the voltage across the output capacitor C, that is, the rising speed of the output voltage VOUT is limited, so that the overshoot amplitude of the output voltage VOUT of this low-dropout linear voltage regulator circuit can be limited.

[0119] Further, when the load in the feedback module 50 is large, it is necessary to reduce the on-resistance of the seventh PMOS transistor QP7 to increase the gate voltage of the power transistor Q. At this time, if the gate-source voltage of the seventh PMOS transistor QP7 increases, the right branch of the overshoot suppression module 30 (the ninth PMOS transistor QP9, the eleventh PMOS transistor QP11, and the thirteenth PMOS transistor QP13 connected in series) may be slightly turned on, resulting in a small leakage current. However, the second current mirror unit can copy this leakage current to the left branch of the overshoot suppression module 30 (the eighth PMOS transistor QP8, the tenth PMOS transistor QP10, and the twelfth PMOS transistor QP12 connected in series), thereby reducing the equivalent input offset of the error amplification module 20.

[0120] In another embodiment, please refer to Figure 3 , the low dropout linear voltage regulator circuit further includes a first NMOS transistor QN1 and a second NMOS transistor QN2. Specifically, the source terminal of the first NMOS transistor QN1 is connected to the input terminal of the first bias current source DC1, the drain terminal of the first NMOS transistor QN1 is connected to the first output terminal of the first current mirror unit 21, the source terminal of the second NMOS transistor QN2 is connected to the input terminal of the second bias current source DC2, the drain terminal of the second NMOS transistor QN2 is connected to the second output terminal of the first current mirror unit 21, and the gate terminal of the second NMOS transistor QN2 is connected to the gate terminal of the first NMOS transistor QN1. Among them, the gate terminals of the first NMOS transistor QN1 and the second NMOS transistor QN2 are connected, so that the gate terminal voltages of the first NMOS transistor QN1 and the second NMOS transistor QN2 are the same, so that the source voltages of the first NMOS transistor QN1 and the second NMOS transistor QN2 are the same, thereby reducing the current offset caused by the source voltage difference, and further improving the gain of the error amplification module 20.

[0121] In yet another embodiment, the low dropout linear voltage regulator circuit further includes a frequency compensation module. One end of the frequency compensation module is connected to the supply voltage PWR, and the other end is connected to the output terminal of the error amplification module 20. The frequency compensation module is used to change the frequency characteristics of the error amplification module, reduce the phase difference and frequency error, and make the output voltage connected to the error amplification module and the output error amplification voltage synchronized, so as to ensure the stable operation of the low dropout linear voltage regulator circuit. Among them, the design methods of the frequency compensation module include zero-pole cancellation method, the method of combining amplification and filtering, and phase-locked loop technology, etc., and the present invention does not limit this.

[0122] In summary, in the low-dropout linear voltage regulator circuit, since the overshoot suppression module can output the first suppression current to the output terminal of the error amplification module, the voltage difference between the error amplification voltage and the supply voltage is reduced. Also, since the drive control unit can output a drive current according to the difference between the connected supply voltage and the voltage at the first input terminal of the drive module, and the first input terminal of the drive module is connected to the error amplification voltage, there is a positive correlation between the drive current and the difference between the connected supply voltage and the voltage at the first input terminal of the drive module. Therefore, by limiting the magnitude of the difference between the error amplification voltage and the supply voltage, the magnitude of the drive current can be limited. Since the output voltage of the low-dropout linear voltage regulator circuit is generated based on the drive current, limiting the magnitude of the drive current can limit the overshoot amplitude of the output voltage of the low-dropout linear voltage regulator circuit.

[0123] An embodiment of the present invention further provides a circuit architecture, including the above-mentioned low-dropout linear voltage regulator circuit.

[0124] An embodiment of the present invention further provides an electronic device, including the above-mentioned circuit architecture.

[0125] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A low dropout linear voltage regulator circuit, characterized in that, Including: A driving module, a first input end of the driving module is connected to a supply voltage, and the driving module is configured to output a driving current according to a difference between the accessed supply voltage and a voltage of the first input end of the driving module, and the driving current is positively correlated with the difference between the accessed supply voltage and the voltage of the first input end of the driving module; A feedback module, configured to generate an output voltage according to the driving current; A first bias current unit, a first end of the first bias current unit is connected to the supply voltage, and a second end of the first bias current unit is configured to output a first bias current; An error amplification module, configured to amplify a difference between a reference voltage and the output voltage according to the input first bias current and output a corresponding error amplification voltage, and the first input end of the driving module is connected to the error amplification voltage; An overshoot suppression module, configured to output a first suppression current to an output end of the error amplification module to reduce a difference between the error amplification voltage and the supply voltage.

2. The low dropout linear voltage regulator circuit according to claim 1, wherein The error amplification module includes: An input unit, the input unit is configured to compare the reference voltage and the output voltage according to the first bias current and output a first current and a second current correspondingly, a first input end and a second input end of the output unit are respectively configured to be connected to the reference voltage and the output voltage, and a first output end and a second output end of the output unit are respectively configured to output the first current and the second current; A second bias current unit, a first output end and a second output end of the second bias current unit are respectively configured to output a second bias current and a third bias current, magnitudes of the second bias current and the third bias current are the same, and a first input end of the second bias current unit is connected to the first output end of the input unit, a second input end of the second bias current unit is connected to the second output end of the input unit, and the first output end and the second output end of the second bias current unit are both grounded; A first current mirror unit, an input end of the first current mirror unit is connected to the supply voltage, a first output end and a second output end of the first current mirror unit are respectively configured to output a third current and a fourth current, the first output end of the first current mirror unit is coupled to the first input end of the second bias current unit, the second output end of the first current mirror unit is coupled to the second input end of the second bias current unit, and the first output end of the first current mirror unit also serves as an output end of the error amplification module, and magnitudes of the third current and the fourth current are the same.

3. The low dropout linear voltage regulator circuit according to claim 2, wherein The low dropout linear voltage regulator circuit according to claim 2, wherein the overshoot suppression module includes a second current mirror unit, and the second current mirror unit includes: An eighth PMOS transistor, a drain terminal of the eighth PMOS transistor is connected to the second output end of the first current mirror unit and configured to output a second suppression current, and magnitudes of the second suppression current and the first suppression current are the same; The ninth PMOS transistor, the drain terminal of the ninth PMOS transistor is connected to the first output terminal of the first current mirror unit for outputting a first suppression current, the gate terminal of the ninth PMOS transistor is connected to the gate terminal of the eighth PMOS transistor, and the gate terminal of the ninth PMOS transistor is connected to its own drain terminal; The tenth PMOS transistor, the drain terminal of the tenth PMOS transistor is connected to the source terminal of the eighth PMOS transistor; The eleventh PMOS transistor, the drain terminal of the eleventh PMOS transistor is connected to the source terminal of the ninth PMOS transistor, the gate terminal of the eleventh PMOS transistor is connected to the gate terminal of the tenth PMOS transistor, and the gate terminal of the eleventh PMOS transistor is connected to its own drain terminal; The twelfth PMOS transistor, the drain terminal of the twelfth PMOS transistor is connected to the source terminal of the tenth PMOS transistor; The thirteenth PMOS transistor, the drain terminal of the thirteenth PMOS transistor is connected to the source terminal of the eleventh PMOS transistor, the gate terminal of the thirteenth PMOS transistor is connected to the gate terminal of the twelfth PMOS transistor, and the gate terminal of the thirteenth PMOS transistor is connected to its own drain terminal, and the source terminal of the thirteenth PMOS transistor is connected to the source terminal of the twelfth PMOS transistor and is connected to the power supply voltage.

4. The low dropout linear voltage regulator circuit according to claim 2, wherein The input unit includes: The first PMOS transistor, the gate terminal of the first PMOS transistor is connected to the reference voltage, the drain terminal of the first PMOS transistor is used to output the first current, and the source terminal of the first PMOS transistor is connected to the output terminal of the first bias current unit; The second PMOS transistor, the gate terminal of the second PMOS transistor is connected to the output voltage, the drain terminal of the second PMOS transistor is used to output the second current, and the source terminal of the second PMOS transistor is connected to the output terminal of the first bias current unit.

5. The low dropout linear voltage regulator circuit according to claim 2, wherein The second bias current unit includes: The first bias current source, the output terminal of the first bias current source is used as the first output terminal of the second bias current unit, and the input terminal of the first bias current source is used as the first input terminal of the second bias current unit; The second bias current source, the output terminal of the second bias current source is used as the second output terminal of the second bias current unit, and the input terminal of the second bias current source is used as the second input terminal of the second bias current unit.

6. The low dropout linear voltage regulator circuit according to claim 2, wherein The first current mirror unit includes: The third PMOS transistor, the drain terminal of the third PMOS transistor is used as the second output terminal of the first current mirror unit; The fourth PMOS transistor, the drain terminal of the fourth PMOS transistor is used as the first output terminal of the first current mirror unit, and the gate terminal of the fourth PMOS transistor is connected to the gate terminal of the third PMOS transistor; The fifth PMOS transistor, the drain terminal of the fifth PMOS transistor is connected to the source terminal of the third PMOS transistor; The sixth PMOS transistor, the drain terminal of the sixth PMOS transistor is connected to the source terminal of the fourth PMOS transistor, the gate terminal of the sixth PMOS transistor is connected to the gate terminal of the fifth PMOS transistor and is connected to the drain terminal of the third PMOS transistor, and the source terminal of the sixth PMOS transistor is connected to the source terminal of the fifth PMOS transistor and serves as the input terminal of the first current mirror unit.

7. The low dropout linear voltage regulator circuit according to claim 2, characterized in that, The error amplification module further includes: The first NMOS transistor, the source terminal of the first NMOS transistor is connected to the second input terminal of the second bias current unit, and the drain terminal of the first NMOS transistor is connected to the second output terminal of the first current mirror unit; The second NMOS transistor, the source terminal of the second NMOS transistor is connected to the first input terminal of the second bias current unit, the drain terminal of the second NMOS transistor is connected to the first output terminal of the first current mirror unit, and the gate terminal of the second NMOS transistor is connected to the gate terminal of the first NMOS transistor.

8. The low dropout linear voltage regulator circuit according to claim 1, wherein The driving module includes: A driving control unit for outputting a control voltage according to the error amplification voltage, and the control voltage decreases as the error amplification voltage increases; A power transistor, the control terminal of the power transistor is connected to the control voltage, the first terminal of the power transistor is connected to the power supply voltage, and the second terminal of the power transistor is used to output a driving current according to the control voltage.

9. The low dropout linear voltage regulator circuit according to claim 8, wherein The power transistor is an NMOS transistor, the first terminal of the power transistor is the drain terminal of the NMOS transistor, the second terminal of the power transistor is the source terminal of the NMOS transistor, and the control terminal of the power transistor is the gate terminal of the NMOS transistor; The driving control unit includes: The seventh PMOS transistor, the gate terminal of the seventh PMOS transistor is connected to the output terminal of the error amplification module, the source terminal of the seventh PMOS transistor is connected to the power supply voltage, and the drain terminal of the seventh PMOS transistor serves as the output terminal of the driving control unit; A control resistor, the first terminal of the control resistor is connected to the drain terminal of the seventh PMOS transistor, and the second terminal of the control resistor is connected to the ground.

10. The low dropout linear voltage regulator circuit according to claim 1, wherein The feedback module includes: A feedback resistor, the first terminal of the feedback resistor is connected to the output terminal of the driving module, and the second terminal of the feedback resistor is connected to the ground; An output capacitor, the first terminal of the output capacitor is connected to the output terminal of the driving module, and the second terminal of the output capacitor is connected to the ground.

11. A circuit architecture, characterized in that, Including the low dropout linear voltage regulator circuit according to any one of claims 1-10.

12. An electronic device, characterized in that, Including the circuit architecture according to claim 11.

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