Vector configuration instruction implementation method and system and storage medium

Abstract

The invention is suitable for the technical field of processors, and particularly relates to a vector configuration instruction implementation method and system and a storage medium. The implementation system comprises an instruction fetching unit, a decoding unit, a vector configuration instruction execution unit, an execution management unit and a vector execution unit. The vector configuration instruction execution unit is used for obtaining the number of the idle register, renaming the received vector configuration instruction according to the number of the idle register to obtain a renamed vector configuration instruction and renaming information, and executing the renamed vector configuration instruction to obtain the renamed vector configuration instruction. And generating vector configuration information according to the execution result and sending the vector configuration information to a vector execution unit. Compared with the prior art, the vector configuration instruction is realized by introducing a register renaming technology, and simple and quick recovery can be carried out when speculative execution errors occur while the speculative execution capability is reserved, so that the design complexity can be reduced and the execution efficiency of the instruction can be improved while the performance is considered.

Description

Technical Field

[0001] The present invention is applicable to the field of processor technology, and particularly relates to a method, a system and a storage medium for implementing a vector configuration instruction. Background Art

[0002] A processor is the computing and control core of an information processing system. With the continuous increase in computing power requirements, the performance requirements of processors are also constantly improving. Traditional processor design methods mainly focus on improving the instruction-level parallelism (ILP) to enable the processor to issue and execute multiple instructions at once as much as possible, thereby improving the performance of the processor. Data-level parallelism (DLP) improves the performance of the processor by enabling an instruction to process multiple data simultaneously, effectively reducing the number of instruction fetches and instruction issues. Currently, there are mainly two ways to improve the data-level parallelism of a single processor core: single instruction - multiple data (SIMD) instructions and vector instructions. SIMD instructions process data with a fixed bit width, while vector instructions support processing data with variable bit widths, which is more flexible and convenient for programming. Currently, the main vector instruction sets mainly include two: the Scalable Vector Extension (SVE) of Arm and the Vector Extension of the fifth-generation Reduced Instruction Set Computing (RISC-V). The former requires specific authorization for development, while the latter is open source and free. And because the latter was introduced relatively late, it has fully absorbed the historical experience of the development of vector instructions and has many advantages such as more concise and efficient instructions.

[0003] Before the vector instructions of the fifth-generation Reduced Instruction Set Computing are executed, it is necessary to first set the vector-related control and status registers (CSRs) through dedicated vector configuration instructions, including the vector type register (vtype) and the vector length register (vl). Vector instructions need to read the values of these two control and status registers before they can start execution. Therefore, how to implement vector configuration instructions and handle related dependencies has become one of the keys in the implementation of the vector extension of the fifth-generation Reduced Instruction Set Computing. There are mainly two existing implementation methods for the fifth-generation reduced instruction set vector configuration instructions. One is to implement this type of instruction as a normal control and status register instruction. Generally, after recognizing the vector configuration instruction, this implementation method needs to wait for all the previous instructions to be executed before starting to execute the vector configuration instruction, and during the execution process, it is necessary to pause the execution of subsequent instructions until this instruction is executed. This method is simple to implement and can reuse the existing control and status register execution path, so it can save additional area overhead. The other is to directly predict the execution result of the instruction based on the execution history information of the vector configuration instruction, which can support speculative execution of the vector configuration instruction. This method can enable subsequent vector instructions to be executed without blocking, and can greatly improve the efficiency of instruction execution. When the prediction is incorrect, it is necessary to restore the execution state of the processor and at the same time restore and adjust the state of the predictor. This prediction mechanism is usually integrated with the branch predictor, and the execution result of the vector configuration instruction is predicted by adding additional information to the existing branch predictor.

[0004] There are the following problems with the two main existing implementation methods for the fifth-generation reduced instruction set vector configuration instructions: First, for the implementation method based on normal control and status register instructions, the vector configuration instruction needs to be executed in a blocking manner, so it will seriously affect the performance of vector instruction execution. Second, for the implementation method based on prediction, it is necessary to develop a dedicated prediction mechanism and error recovery mechanism, which increases the design complexity.

[0005] Therefore, there is an urgent need for a new implementation method, system and storage medium for vector configuration instructions to solve the above technical problems. Summary of the Invention

[0006] The present invention provides an implementation method, system and storage medium for vector configuration instructions. The present invention aims to implement vector configuration instructions by introducing register renaming technology, which can retain the ability of speculative execution while being able to recover simply and quickly when the speculative execution is incorrect. Therefore, it can reduce the design complexity while taking into account performance.

[0007] In a first aspect, the present invention provides an implementation system for vector configuration instructions. The implementation system includes an instruction fetching unit, a decoding unit, a vector configuration instruction execution unit, an execution management unit, and a vector execution unit; The instruction fetching unit is used to fetch the instruction to be executed from the memory and send the instruction to be executed to the decoding unit; The decoding unit is used to identify the received instruction to be executed, extract the vector configuration instruction in the instruction to be executed and send it to the vector configuration instruction execution unit, and extract the vector instruction in the instruction to be executed and send it to the vector execution unit; The vector configuration instruction execution unit is used to obtain the free register number, rename the received vector configuration instruction according to the free register number to obtain a renamed vector configuration instruction and rename information, and further execute the renamed vector configuration instruction to obtain an execution result; it is also used to generate vector configuration information according to the execution result and send it to the vector execution unit, and send the rename information to the execution management unit; The execution management unit is used to manage the execution status of the renamed vector configuration instruction according to the received rename information, and perform error recovery when the execution of the renamed vector configuration instruction fails; The vector execution unit is used to execute the vector instruction according to the received vector configuration information.

[0008] Preferably, the vector configuration instruction execution unit includes a free register list, a speculative register rename mapping table, an architecture register rename mapping table, a vector configuration instruction functional unit, and a vector configuration register bank; The free register list is used to manage the free register number; The speculative register rename mapping table is used to save the mapping relationship between the latest renamed vector configuration instruction and the registers in the vector configuration register bank; The architecture register rename mapping table is used to save the mapping relationship between the renamed vector configuration instruction and the registers in the vector configuration register bank when the submission of the renamed vector configuration instruction is successful; The vector configuration instruction functional unit is used to execute the renamed vector configuration instruction; The vector configuration register bank is used to store the execution result and generate the vector configuration information, and send the vector configuration information to the vector execution unit.

[0009] Preferably, when the submission of the renamed vector configuration instruction is successful, the execution management unit is also used to return the register number of the renamed vector configuration instruction in the previous mapping to the free register list.

[0010] Preferably, when the speculative execution of the renamed vector configuration instruction fails, the execution management unit is also used to restore the free register list to the state before the execution of the renamed vector configuration instruction.

[0011] Preferably, after the vector configuration instruction execution unit renames the vector configuration instruction, the speculative register rename mapping table is also used to update the mapping relationship between the renamed vector configuration instruction and the corresponding registers in the vector configuration register bank.

[0012] Preferably, when the renaming vector configuration instruction is successfully submitted, the execution management unit is further configured to update the mapping relationship between the renaming vector configuration instruction in the architecture register renaming mapping table and the registers in the vector configuration register file.

[0013] Preferably, when the execution management unit fails to speculatively execute the renaming vector configuration instruction, the information in the architecture register renaming mapping table is updated to the speculative register renaming mapping table.

[0014] In a second aspect, the present invention further provides a method for implementing a vector configuration instruction. The implementation method is based on the vector configuration instruction implementation system as described in the above embodiments, and the implementation method includes the following steps: S1. Obtain the instruction to be executed through the instruction fetch unit, and identify the instruction to be executed through the decoding unit, and extract the vector configuration instruction and the vector instruction in the instruction to be executed; S2. Obtain the free register number through the free register list of the vector configuration instruction execution unit, rename the vector configuration instruction according to the free register number to obtain a renamed vector configuration instruction and renaming information; S3. Write the mapping relationship between the renamed vector configuration instruction and the corresponding free register number into the speculative register renaming mapping table; S4. Execute the renamed vector configuration instruction through the vector configuration instruction functional unit to obtain an execution result; S5. Generate vector configuration information through the vector configuration register file according to the execution result, and the vector execution unit executes the vector instruction according to the vector configuration information; S6. Manage the execution status of the renamed vector configuration instruction through the execution management unit according to the renaming information, and perform error recovery when the renamed vector configuration instruction fails to execute; S7. Determine whether the speculative execution is successful: if so, perform step S8; if not, the execution management unit restores the free register list to the state before the speculative execution of the renamed vector configuration instruction, and updates the information in the architecture register renaming mapping table to the speculative register renaming mapping table; S8. When the renamed vector configuration instruction is successfully submitted, the execution management unit returns the register number of the renamed vector configuration instruction in the previous mapping to the free register list, and updates the register number corresponding to the renamed vector configuration instruction to the architecture register renaming mapping table.

[0015] In a third aspect, the present invention further provides a computer device, including: a memory, a processor, and an implementation program of vector configuration instructions stored on the memory and executable on the processor. When the processor executes the implementation program of the vector configuration instructions, the steps in the implementation method of the vector configuration instructions as described in the above embodiments are implemented.

[0016] In a fourth aspect, the present invention further provides a computer-readable storage medium, on which an implementation program of vector configuration instructions is stored. When the implementation program of the vector configuration instructions is executed by a processor, the steps in the implementation method of the vector configuration instructions as described in the above embodiments are implemented.

[0017] Compared with the prior art, the present invention realizes vector configuration instructions by introducing register renaming technology. While retaining the ability of speculative execution, it can be simply and quickly restored when speculative execution is incorrect. Therefore, it can reduce the design complexity while taking into account performance and improve the execution efficiency of instructions. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present invention will be described in detail below with reference to the drawings. Through the detailed description in combination with the following drawings, the above or other aspects of the present invention will become clearer and easier to understand. In the drawings: Figure 1 is a schematic structural diagram of an implementation system of vector configuration instructions provided by an embodiment of the present invention; Figure 2 is a flowchart of an implementation method of vector configuration instructions provided by an embodiment of the present invention; Figure 3 is a schematic structural diagram of a computer device provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0020] Embodiment 1 An embodiment of the present invention provides an implementation system of vector configuration instructions. Please refer to Figure 1 , Figure 1 is a schematic structural diagram of an implementation system 100 of vector configuration instructions provided by an embodiment of the present invention, which includes: an instruction fetching unit 1, a decoding unit 2, a vector configuration instruction execution unit 3, an execution management unit 4, and a vector execution unit 5; The instruction fetching unit 1 is configured to fetch an instruction to be executed from a memory and send the instruction to be executed to the decoding unit 2.

[0021] The decoding unit 2 is configured to identify the received instruction to be executed, extract the vector configuration instruction in the instruction to be executed, and send it to the vector configuration instruction execution unit 3, and extract the vector instruction in the instruction to be executed and send it to the vector execution unit 5.

[0022] The vector configuration instruction execution unit 3 is configured to obtain the free register number, rename the received vector configuration instruction according to the free register number to obtain a renamed vector configuration instruction and renaming information, and further execute the renamed vector configuration instruction to obtain an execution result; it is also configured to generate vector configuration information according to the execution result and send it to the vector execution unit 5, and send the renaming information to the execution management unit 4.

[0023] In an embodiment of the present invention, the vector configuration instruction execution unit 3 includes a free register list 31, a speculative register renaming mapping table 32, an architecture register renaming mapping table 33, a vector configuration instruction functional unit 34, and a vector configuration register bank 35.

[0024] The free register list 31 is used to manage the free register number.

[0025] The speculative register renaming mapping table 32 is used to save the mapping relationship between the latest renamed vector configuration instruction and the registers in the vector configuration register bank 35.

[0026] The architecture register renaming mapping table 33 is used to save the mapping relationship between the renamed vector configuration instruction and the registers in the vector configuration register bank 35 when the submission of the renamed vector configuration instruction is successful; The vector configuration instruction functional unit 34 is used to execute the renamed vector configuration instruction, and its execution result is written into the corresponding entry of the vector configuration register bank 35.

[0027] The vector configuration register bank 35 is used to store the execution result and generate the vector configuration information, and send the vector configuration information to the vector execution unit 5. Wherein, each entry in the vector configuration register bank 35 contains two registers, namely the vector length and the vector type. Specifically, the vector configuration register bank 35 obtains the latest vector configuration register mapping relationship from the speculative register renaming mapping table 32, and obtains the vector configuration information from its corresponding entry and sends it to the vector execution unit 5 for subsequent execution of vector instructions.

[0028] The execution management unit 4 is configured to manage the execution status of the rename vector configuration instruction according to the received rename information, and perform error recovery when the execution of the rename vector configuration instruction fails.

[0029] The vector execution unit 5 is configured to execute the vector instruction according to the received vector configuration information. It should be noted that the vector configuration instruction is an instruction used to set the execution environment, data layout, or hardware parameters of the vector processor, and does not directly participate in data operations. The vector instruction is an instruction that performs the same operation (such as addition, multiplication) on multiple data elements simultaneously to achieve data-level parallelism.

[0030] In an embodiment of the present invention, when the submission of the rename vector configuration instruction is successful, the execution management unit 4 is further configured to return the register number of the rename vector configuration instruction in the previous mapping to the free register list 31 for the renaming of subsequent instructions. It should be noted that the submission of the rename vector configuration instruction means that the execution result of the rename vector configuration instruction is permanently written into a register or memory.

[0031] In an embodiment of the present invention, when the speculative execution of the rename vector configuration instruction fails, the execution management unit 4 is further configured to restore the free register list 31 to the state before the execution of the rename vector configuration instruction.

[0032] In an embodiment of the present invention, after the vector configuration instruction execution unit 3 renames the vector configuration instruction, the speculative register renaming mapping table 32 is further configured to update the mapping relationship between the rename vector configuration instruction and the corresponding register in the vector configuration register bank 35. Specifically, when the vector configuration instruction is renamed, it is synchronously updated to the speculative register renaming mapping table 32 to indicate which register in the vector configuration register bank 35 the vector configuration register corresponding to the most recently renamed vector configuration instruction corresponds to.

[0033] In an embodiment of the present invention, when the submission of the rename vector configuration instruction is successful, the execution management unit 4 is further configured to update the mapping relationship between the rename vector configuration instruction in the architecture register renaming mapping table 33 and the register in the vector configuration register bank 35, that is, update the register number corresponding to the rename vector configuration instruction that is being speculatively executed to the architecture register renaming mapping table 33.

[0034] In an embodiment of the present invention, when the execution management unit 4 speculatively executes the rename vector configuration instruction unsuccessfully, the information in the architecture register rename mapping table 33 is updated to the speculative register rename mapping table 32, so as to restore the speculative register rename mapping table 32 to the state before the execution of the rename vector configuration instruction.

[0035] Compared with the prior art, the present invention realizes the vector configuration instruction by introducing the register renaming technology. While retaining the ability of speculative execution, it can be simply and quickly restored when the speculative execution is incorrect. Therefore, it can reduce the design complexity while taking into account the performance and improve the execution efficiency of the instruction.

[0036] Embodiment 2 Please refer to Figure 2 , the present invention also provides a method for implementing a vector configuration instruction, and the implementation method includes the following steps: S1. Obtain the instruction to be executed through the fetch unit 1, and identify the instruction to be executed through the decoding unit 2, and extract the vector configuration instruction and the vector instruction in the instruction to be executed; S2. Obtain the free register number through the free register list 31 of the vector configuration instruction execution unit 3, rename the vector configuration instruction according to the free register number to obtain a renamed vector configuration instruction and rename information; S3. Write the mapping relationship between the renamed vector configuration instruction and the corresponding free register number into the speculative register rename mapping table 32; S4. Execute the renamed vector configuration instruction through the vector configuration instruction functional unit 34 to obtain an execution result; S5. Generate vector configuration information through the vector configuration register file 35 according to the execution result, and the vector execution unit 5 executes the vector instruction according to the vector configuration information; S6. Manage the execution state of the renamed vector configuration instruction through the execution management unit 4 according to the rename information, and perform error recovery when the renamed vector configuration instruction fails to execute; S7. Judge whether the speculative execution is successful: if so, perform step S8; if not, the execution management unit 4 restores the free register list 31 to the state before the speculative execution of the renamed vector configuration instruction, and updates the information in the architecture register rename mapping table 33 to the speculative register rename mapping table 32; S8. When the renaming vector configuration instruction is successfully submitted, the execution management unit 4 returns the register number of the renaming vector configuration instruction in the previous mapping to the free register list 31, and updates the register number corresponding to the renaming vector configuration instruction to the architecture register renaming mapping table 33.

[0037] The implementation method is based on the vector configuration instruction implementation system 100 described in the above embodiments, and can achieve the same technical effects. Refer to the description in the above embodiments, and details are not repeated here.

[0038] Embodiment III The embodiment of the present invention further provides a computer device. Please refer to Figure 3 , Figure 3 which is a schematic structural diagram of the computer device provided by the embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and an implementation program of the vector configuration instruction stored on the memory 302 and executable on the processor 301.

[0039] The processor 301 calls the implementation program of the vector configuration instruction stored in the memory 302 and executes the steps in the implementation method of the vector configuration instruction provided by the embodiment of the present invention. Please refer to Figure 1 , specifically including the following steps: S1. Obtain the instruction to be executed through the instruction fetch unit 1, and identify the instruction to be executed through the decoder unit 2, and extract the vector configuration instruction in the instruction to be executed; S2. Obtain the free register number from the free register list 31 of the vector configuration instruction execution unit 3, rename the vector configuration instruction according to the free register number, and obtain the renamed vector configuration instruction and the renaming information; S3. Write the mapping relationship between the renamed vector configuration instruction and the corresponding free register number into the speculative register renaming mapping table 32; S4. Execute the renamed vector configuration instruction through the vector configuration instruction functional unit 34 to obtain the execution result; S5. Generate vector configuration information through the vector configuration register bank 35 according to the execution result, and the vector execution unit 5 executes the vector instruction according to the vector configuration information; S6. Manage the execution status of the renamed vector configuration instruction through the execution management unit 4 according to the renaming information, and perform error recovery when the renamed vector configuration instruction fails to execute; S7. Determine whether speculative execution is successful: If so, proceed to step S8; if not, restore the free register list 31 to the state before the speculative execution of the rename vector configuration instruction through the execution management unit 4, and update the information in the architecture register rename mapping table 33 to the speculative register rename mapping table 32; S8. When the rename vector configuration instruction is successfully committed, return the register number of the rename vector configuration instruction in the previous mapping to the free register list 31 through the execution management unit 4, and update the register number corresponding to the rename vector configuration instruction to the architecture register rename mapping table 33;

[0040] The computer device 300 provided by the embodiments of the present invention can implement the steps in the method for implementing a vector configuration instruction in the above embodiments, and can achieve the same technical effects. Refer to the descriptions in the above embodiments, and details are not repeated here.

[0041] Embodiment 4 The embodiments of the present invention further provide a computer-readable storage medium, on which a program for implementing a vector configuration instruction is stored. When the program for implementing a vector configuration instruction is executed by a processor, it implements each process and step in the method for implementing a vector configuration instruction provided by the embodiments of the present invention, and can achieve the same technical effects. To avoid repetition, details are not repeated here.

[0042] Those of ordinary skill in the art can understand that all or part of the processes of implementing the methods in the above embodiments can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc.

[0043] It should be noted that in this article, the term "including", "comprising" or any other variation thereof is intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without further limitations, an element defined by the statement "including a..." does not exclude the existence of another identical element in the process, method, article or device including that element.

[0044] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases, the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to enable a terminal (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in various embodiments of the present invention.

[0045] The embodiments of the present invention have been described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiments of the present invention. However, the present invention is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present invention, those of ordinary skill in the art can also make many equivalent changes in form without departing from the purpose of the present invention and the scope protected by the claims, and all belong to the protection scope of the present invention.

Claims

1. An implementation system for vector configuration instructions, characterized in that, The implementation system includes an instruction fetch unit, a decoding unit, a vector configuration instruction execution unit, an execution management unit, and a vector execution unit; The instruction fetch unit is used to fetch the instruction to be executed from the memory and send the instruction to be executed to the decoding unit; The decoding unit is used to identify the received instruction to be executed, extract the vector configuration instruction in the instruction to be executed and send it to the vector configuration instruction execution unit, and extract the vector instruction in the instruction to be executed and send it to the vector execution unit; The vector configuration instruction execution unit is used to obtain the free register number, rename the received vector configuration instruction according to the free register number to obtain the renamed vector configuration instruction and the renaming information, further execute the renamed vector configuration instruction to obtain the execution result; it is also used to generate vector configuration information according to the execution result and send it to the vector execution unit, and send the renaming information to the execution management unit; The execution management unit is used to manage the execution status of the renamed vector configuration instruction according to the received renaming information and perform error recovery when the renamed vector configuration instruction fails to execute; The vector execution unit is used to execute the vector instruction according to the received vector configuration information.

2. The implementation system of the vector configuration instruction according to claim 1, characterized in that, The vector configuration instruction execution unit includes a free register list, a speculative register renaming mapping table, an architectural register renaming mapping table, a vector configuration instruction functional unit, and a vector configuration register file; The free register list is used to manage the free register number; The speculative register renaming mapping table is used to save the mapping relationship between the latest renamed vector configuration instruction and the register in the vector configuration register file; The architectural register renaming mapping table is used to save the mapping relationship between the renamed vector configuration instruction and the register in the vector configuration register file when the renamed vector configuration instruction is successfully committed; The vector configuration instruction functional unit is used to execute the renamed vector configuration instruction; The vector configuration register file is used to store the execution result and generate the vector configuration information, and send the vector configuration information to the vector execution unit.

3. The implementation system of the vector configuration instruction according to claim 2, wherein When the renamed vector configuration instruction is successfully committed, the execution management unit is also used to return the register number of the renamed vector configuration instruction in the previous mapping to the free register list.

4. The implementation system of the vector configuration instruction according to claim 2, wherein When the renamed vector configuration instruction fails to execute speculatively, the execution management unit is also used to restore the free register list to the state before the renamed vector configuration instruction is executed.

5. The implementation system of the vector configuration instruction according to claim 2, wherein After the vector configuration instruction execution unit renames the vector configuration instruction, the speculative register renaming mapping table is also used to update the mapping relationship between the renamed vector configuration instruction and the corresponding register in the vector configuration register file.

6. The implementation system of the vector configuration instruction according to claim 2, characterized in that, When the submission of the rename vector configuration instruction is successful, the execution management unit is further configured to update the mapping relationship between the rename vector configuration instruction in the architecture register rename mapping table and the registers in the vector configuration register file.

7. The implementation system of the vector configuration instruction according to claim 2, characterized in that, When the execution management unit speculatively executes the rename vector configuration instruction and fails, it updates the information in the architecture register rename mapping table to the speculative register rename mapping table.

8. A method for implementing a vector configuration instruction, characterized in that The implementation method is based on the vector configuration instruction implementation system as described in claims 2-7. The implementation method includes the following steps: S1. Obtain the instruction to be executed through the fetch unit, and identify the instruction to be executed through the decode unit, and extract the vector configuration instruction and vector instruction in the instruction to be executed. S2. Obtain the free register number through the free register list of the vector configuration instruction execution unit, and rename the vector configuration instruction according to the free register number to obtain the renamed vector configuration instruction and rename information. S3. Write the mapping relationship between the renamed vector configuration instruction and the corresponding free register number into the speculative register rename mapping table. S4. Execute the renamed vector configuration instruction through the vector configuration instruction functional unit to obtain an execution result. S5. Generate vector configuration information through the vector configuration register file according to the execution result, and the vector execution unit executes the vector instruction according to the vector configuration information. S6. Manage the execution status of the renamed vector configuration instruction through the execution management unit according to the rename information, and perform error recovery when the execution of the renamed vector configuration instruction fails. S7. Determine whether the speculative execution is successful: if so, proceed to step S8; if not, the execution management unit restores the free register list to the state before the speculative execution of the renamed vector configuration instruction, and updates the information in the architecture register rename mapping table to the speculative register rename mapping table. S8. When the submission of the renamed vector configuration instruction is successful, the execution management unit returns the register number of the renamed vector configuration instruction in the previous mapping to the free register list, and updates the register number corresponding to the renamed vector configuration instruction to the architecture register rename mapping table.

9. A computer device, characterized in that, Including: A memory, a processor, and an implementation program of vector configuration instructions stored on the memory and executable on the processor. When the processor executes the implementation program of vector configuration instructions, it implements the steps in the implementation method of vector configuration instructions as described in claim 8.

10. A computer-readable storage medium, characterized in that, An implementation program of vector configuration instructions is stored on the computer-readable storage medium. When the implementation program of vector configuration instructions is executed by the processor, it implements the steps in the implementation method of vector configuration instructions as described in claim 8.

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