CPU capable of precise delay control and precise delay control method
By introducing components such as instruction decoder, adder, counter and delay controller into the CPU and combining them with a frequency divider counter, high-precision and low-power delay control is achieved, which solves the problems of uncertainty in delay results and waste of resources in the existing technology and improves the reliability and portability of delay control.
Patent Information
- Application Number
- CN202510835276.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-20
- Publication Date
- 2025-09-12
- Estimated Expiration
- 2045-06-20
AI Technical Summary
The existing technology has problems such as uncertainty in delay control results, waste of resources, high development complexity, strong hardware dependence and unreliable delay results. It is difficult to achieve high-precision and low-power delay control, especially in embedded systems.
A CPU structure capable of precise delay control is adopted, including an instruction decoder, an adder, a counter, a delay monitor and a delay controller. Precise delay control is achieved through instruction matching and counter decrement, and delay accuracy is improved by combining a frequency division counter.
It achieves high-precision, low-power, and low-complexity delay control, adapts to different hardware platforms, reduces resource competition and development complexity, and improves the reliability and portability of delay results.
Smart Images
Figure CN120335872B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of processor design, and in particular relates to a CPU capable of precise delay control and a precise delay control method. Background Art
[0002] Delay functions are almost indispensable in programming and are often used in embedded systems, real-time control, communication protocols, and user interfaces. There are two main implementation methods in existing technologies: loop implementation and hardware timer implementation. Both of these implementation methods have the following drawbacks:
[0003] 1. Defects of implementing delay function in loop body:
[0004] (1) High processor occupancy. Using a loop (such as an empty loop) to implement delays puts the CPU in a busy-waiting state, resulting in wasted resources and inability to execute other tasks, reducing system response and throughput.
[0005] (2) Increased power consumption. Continuous repeated instruction fetching and execution leads to increased power consumption, which is particularly noticeable in power-sensitive devices (such as battery-powered embedded systems) and may shorten battery life.
[0006] (3) Uncertainty of delay results. The delay effect is affected by many factors, such as the processor's instruction fetch speed, pipeline length, and branch prediction. This leads to large differences in delay results under different conditions, affecting the predictability of the program.
[0007] (4) Unable to meet high-precision requirements. For applications that require precise control, the dry loop cannot provide sufficient delay accuracy, which may lead to system instability or functional failure.
[0008] 2. Defects of hardware timer in implementing delay function:
[0009] (1) High implementation complexity. Hardware timers require register configuration and interrupt service routine management, which increases development complexity and the risk of errors.
[0010] (2) Occupy hardware resources. Resource-constrained systems may not have sufficient hardware resources to configure and use timers, limiting their applicability.
[0011] (3) Uncertainty of delay results. Hardware timers rely on the processor's execution speed during configuration, flag query, or interrupt processing, including instruction fetch speed, compilation conditions, and interrupt response time, which may lead to unreliable delay results.
[0012] (4) Strong hardware dependency. The hardware timer implementation depends on the specific hardware platform. Differences in timer configuration between different platforms may make it impossible to directly migrate the code.
[0013] (5) Resource competition problem. In a multi-tasking environment, there may be competition for the same timer resource, resulting in uncertainty and uncontrollability of delay. Summary of the Invention
[0014] Purpose of the invention: In order to solve the uncertainty of delay control results in the prior art and improve the accuracy of delay control, the present invention provides a CPU capable of precise delay control and a precise delay control method.
[0015] Technical solution: A CPU capable of precise delay control, including:
[0016] An instruction decoder, configured to decode a valid delay instruction, obtain instruction information, and output a delay request, wherein the instruction information includes a first delay value, a second delay value, and instruction matching information;
[0017] An adder, the input end of which inputs the first delay number and the second delay number, and the output end of which is connected to the counter;
[0018] a counter, configured to reload the output value of the adder, count down, and output the counting result to the delay controller upon receiving a delay request;
[0019] a delay monitor, configured to detect the pipeline, receive instruction matching information, match the detected pipeline instructions according to the instruction matching information, match the detected pipeline privileges according to preset privilege information, and transmit the matching results to the delay controller;
[0020] The delay controller is used to receive the delay request and instruction matching information output by the instruction decoder, store the instruction matching information in a register and output it to the delay monitor, receive the counting result output by the counter, receive the matching result output by the delay monitor, switch the delay working state, and output a pause request to the CPU pipeline controller or cancel the pause request.
[0021] Furthermore, the counter includes a delay counter and a frequency division counter; the instruction information also includes frequency division count enable on and frequency division count enable off, the delay counter and the frequency division counter are both connected to the delay controller, the input end of the delay counter is connected to the output end of the adder, the input end of the frequency division counter is connected to the control register, the control register is used to store the pre-frequency division value, and the delay counter is reloaded to the output value of the adder when receiving a delay request;
[0022] When the frequency division count enable is off, the delay counter works, the frequency division counter does not work, and the delay counter decreases by 1 per cycle; when the frequency division count enable is on, both the delay counter and the frequency division counter work. The frequency division counter is reloaded to the pre-division value when it receives a delay request or decreases to 0, and the frequency division counter decreases by 1 per cycle. Whenever the frequency division counter decreases to 0, the delay counter decreases by 1.
[0023] Furthermore, the instruction matching information includes one or more of a read instruction, a write instruction, an arbitrary instruction, a delayed instruction, and a preset instruction.
[0024] Furthermore, the first delay number and the second delay number are operands or delayed immediate numbers; a general register is also included, the general register is used to pre-store operands, the instruction decoder decodes the operand register label, and then obtains the operand through the register.
[0025] Furthermore, it also includes a selector, wherein the first input end of the selector is connected to the register, the second input end is connected to the decoder, and is controlled by the selection of the instruction decoder, and the output end is connected to the adder.
[0026] A method for accurately controlling a CPU delay capable of accurate delay control comprises the following steps:
[0027] Step 1: Assume that in the tth clock cycle, t is a positive integer greater than 0, the CPU executes a valid delay instruction, decodes the delay instruction, obtains instruction information, and outputs a delay request. The instruction information includes a first delay value, a second delay value, and instruction matching information. At the same time, the following operations are performed:
[0028] The adder adds the first delay number and the second delay number and provides an output value to the counter;
[0029] The counter receives the delay request and reloads the output value of the adder;
[0030] The delay controller receives the delay request and instruction matching information, switches the delay working state to the busy state, saves the instruction matching information in the register and outputs it to the delay monitor;
[0031] Step 2: From the t+1th clock cycle onwards, the CPU continues to execute subsequent instructions and performs the following operations:
[0032] The counter counts down and outputs the counting result to the delay controller;
[0033] The delay monitor detects the pipeline in real time, matches the detected pipeline instructions according to the received instruction matching information, matches the pipeline privileges according to the preset privilege matching information, and transmits the matching results to the delay controller. When both the pipeline instructions and pipeline privileges are matched successfully, the matching result is valid;
[0034] When the delay controller is in the busy state and the matching result is valid, it sends a pause request to the CPU pipeline controller; when the counting result returns to zero, the delay controller switches the delay working state to the idle state and cancels the pause request to the CPU pipeline controller, and the delay ends.
[0035] Furthermore, in step 1, the instruction information further includes frequency division counting enable on and frequency division counting enable off; the counter includes a delay counter and a frequency division counter, and the delay counter is reloaded to the output value of the adder upon receiving a delay request;
[0036] When the frequency division count enable is off, the delay counter works, the frequency division counter does not work, and the delay counter decreases by 1 per cycle; when the frequency division count enable is on, both the delay counter and the frequency division counter work, and the frequency division counter is reloaded to the pre-division value when it receives a delay request or decreases to 0, and the frequency division counter decreases by 1 per cycle; whenever the frequency division counter decreases to 0, the delay counter decreases by 1.
[0037] Furthermore, in step 2, the delay controller switches to an idle state when the counting result returns to zero, specifically including: when the frequency division counting enable is turned off, when the counting result of the delay counter is 0, the delay working state switches to the idle state; when the frequency division counting enable is turned on, when the counting results of the delay counter and the frequency division counter are both 0, the delay working state switches to the idle state.
[0038] Furthermore, in step 2, the instruction matching information includes one or more of a read instruction, a write instruction, all instructions, a delayed instruction, and a preset instruction.
[0039] Furthermore, in step 1, the first delay number and the second delay number are delayed immediate numbers or operands stored in a general register. If they are operands, the instruction decoder decodes the operand register number and then obtains the operand through the register.
[0040] Compared with the prior art, the CPU and method for precise delay control provided by the present invention have the following beneficial effects:
[0041] (1) There is no need to execute the loop body, nor is there any need to perform flag and interrupt response processes. Therefore, its delay effect does not depend on the influence of instruction fetch speed, instruction execution speed, interrupt response speed, etc. The delay accuracy is high and the result can be determined;
[0042] (2) The actual delay time mainly depends on the main frequency. Therefore, when the delay instruction is executed at the same frequency on chips of different systems with the same core, the delay time is almost the same. This avoids the influence of system bus structure, bus delay, timer configuration differences, etc. on the delay to the greatest extent, and has good portability.
[0043] (3) Only one instruction is needed to complete various delays, with low complexity and intuitive user interface, which reduces development complexity and the risk of errors;
[0044] (4) The processor has high utilization and low power consumption, and will not increase power consumption due to repeated instruction fetching and execution;
[0045] (5) For existing technologies, whether it is a loop or a hardware timer delay solution, the speed of instruction fetching and execution will have a significant impact on the actual delay time. The loop needs to calculate the average time of each instruction based on this, and the hardware timer needs to balance the interrupt response speed and the flag query speed. In contrast, the delay control of this solution is executed synchronously with the CPU operation, and once a matching instruction is detected (this instruction is often set to be the first instruction after the expected delay ends), a pause request is immediately issued to the pipeline, without the need for interrupt response and other steps. Therefore, it has a higher tolerance for instruction fetching and execution delays. BRIEF DESCRIPTION OF THE DRAWINGS
[0046] Figure 1 This is a partial structural block diagram of a CPU capable of precise delay control;
[0047] Figure 2 Partial structural block diagram of an expanded CPU capable of precise delay control. DETAILED DESCRIPTION
[0048] The present invention will be further explained below with reference to the accompanying drawings and specific embodiments.
[0049] A CPU capable of precise delay control, such as Figure 1 Shown, including:
[0050] An instruction decoder, configured to decode a valid delay instruction, obtain instruction information, and output a delay request, wherein the instruction information includes a first delay value, a second delay value, and instruction matching information;
[0051] An adder, the input end of which inputs the first delay number and the second delay number, and the output end of which is connected to the counter;
[0052] a counter, configured to reload the output value of the adder, count down, and output the counting result to the delay controller upon receiving a delay request;
[0053] The delay monitor is used to detect the pipeline, receive instruction matching information, match the detected pipeline instructions according to the instruction matching information, match the detected pipeline privileges according to the preset privilege information, and transmit the matching results to the delay controller. The instruction matching information can be one or more of a read instruction, a write instruction, an arbitrary instruction, a delay instruction, and a preset instruction. When the detected pipeline instruction can match the instruction matching information, the instruction match is considered valid. Pipeline privilege matching is used to match privilege modes, such as machine mode, supervisor mode, and user mode. When the detected pipeline privilege matches the preset privilege mode, the privilege match is considered valid.
[0054] The delay controller is used to receive the delay request and instruction matching information output by the instruction decoder, store the instruction matching information in a register and output it to the delay monitor, receive the counting result output by the counter, receive the matching result output by the delay monitor, switch the delay working state, and output a pause request to the CPU pipeline controller or cancel the pause request.
[0055] In order to further improve the delay accuracy, the frequency division timing function can be added on this basis, that is, the timing is divided into two gears, such as Figure 2 The counter includes a delay counter and a frequency division counter. The frequency division counter is used for pre-division counting. The instruction information also includes frequency division counting enable opening and frequency division counting enable closing. The delay counter and the frequency division counter are both connected to the delay controller. The input end of the delay counter is connected to the output end of the adder, and the input end of the frequency division counter is connected to the control register. Figure 2 As shown in , the control register is used to store the prescaler value, and the delay counter is reloaded with the output value of the adder when a delay request is received.
[0056] When the frequency division count enable is off, the delay counter works, the frequency division counter does not work, and the delay counter decreases by 1 per cycle; when the frequency division count enable is on, both the delay counter and the frequency division counter work. The frequency division counter is reloaded to the pre-division value when it receives a delay request or decreases to 0, and the frequency division counter decreases by 1 per cycle. Whenever the frequency division counter decreases to 0, the delay counter decreases by 1.
[0057] The first delay number and the second delay number can be operands stored in a register, or can be immediate numbers directly; it also includes a general register, the operand is pre-stored in the register, the instruction decoder first decodes the operand register label, and then obtains the operand in the register through the operand register label.
[0058] If the first delay number is required to support both operands and immediate numbers, a selector should also be included. The first input end of the selector is connected to the register, the second input end is connected to the decoder, and is controlled by the selection of the instruction decoder. The output end is connected to the adder.
[0059] like Figure 1 and Figure 2 The registers can be further divided into general registers and control registers. General registers store delay numbers (operands). Control registers store preset control words, including preset frequency division coefficients, preset match data, preset match masks, preset machine privileges, etc.
[0060] A method for accurately controlling a CPU delay capable of accurate delay control comprises the following steps:
[0061] Step 1: Assume that in the tth clock cycle, t is a positive integer greater than 0, the CPU executes a valid delay instruction, decodes the delay instruction, obtains instruction information, and outputs a delay request. The instruction information includes a first delay value, a second delay value, and instruction matching information. At the same time, the following operations are performed:
[0062] The adder adds the first delay number and the second delay number and provides an output value to the counter;
[0063] The counter receives the delay request and reloads the output value of the adder;
[0064] The delay controller receives the delay request and instruction matching information, switches the delay working state to the busy state, saves the instruction matching information in the register and outputs it to the delay monitor;
[0065] Step 2: From the t+1th clock cycle onwards, the CPU continues to execute subsequent instructions and performs the following operations:
[0066] The counter counts down and outputs the counting result to the delay controller;
[0067] The delay monitor detects the pipeline in real time, matches the detected pipeline instructions according to the received instruction matching information, matches the pipeline privileges according to the preset privilege matching information, and transmits the matching results to the delay controller. When both the pipeline instructions and pipeline privileges are matched successfully, the matching result is considered valid;
[0068] When the delay controller is in the busy state and the matching result is valid, it sends a pause request to the CPU pipeline controller; when the counting result returns to zero, the delay controller switches the delay working state to the idle state and cancels the pause request to the CPU pipeline controller, and the delay ends.
[0069] To further improve delay accuracy, the counter can be set to two levels. In step 1, the instruction information also includes frequency division counting enable on and frequency division counting enable off; the counter includes a delay counter and a frequency division counter, and the delay counter is reloaded with the output value of the adder when receiving a delay request.
[0070] When the frequency division count enable is off, the delay counter works, the frequency division counter does not work, and the delay counter decreases by 1 per cycle; when the frequency division count enable is on, both the delay counter and the frequency division counter work, and the frequency division counter is reloaded to the pre-division value when it receives a delay request or decreases to 0, and the frequency division counter decreases by 1 per cycle; whenever the frequency division counter decreases to 0, the delay counter decreases by 1.
[0071] In step 2, the delay controller switches to the idle state when the counting result returns to zero. There are two cases depending on whether the frequency division counting enable is turned on: when the frequency division counting enable is turned off, when the counting result of the delay counter is 0, the delay working state switches to the idle state; when the frequency division counting enable is turned on, when the counting results of the delay counter and the frequency division counter are both 0, the delay working state switches to the idle state.
[0072] An example of this method: Assume the instruction stream is I1, I2, and I3, and a 1µs delay needs to be inserted between I1 and I2. Configure the control register CSR_DIV_VAL to the current main frequency (for example, if it's 144MHz, write 144). Insert a delay instruction (delay) between I1 and I2. The first delay value is the operand, and the register number encoding of the first delay value is 5'b00000 (x0 register, the RISCV specification defines x0 register as hardware connection 0); the second delay value is the immediate value, and the immediate value encoding is 1; the divide count function is enabled, and the divide count enable (DIV_EN) is 1; the instruction match information is all instructions, and the delay match enable (DLY_MODE) enables all instruction matches (AM). After the delay is inserted, the instruction stream becomes I1, DLY, I2, and I3.
[0073] To further verify the effectiveness of this method, the existing method and this method are used to insert a delay of 5 main frequency cycles between the IO flip codes:
[0074] PA = 0<<24;
[0075] PA = 1<<24;
[0076] The above is a simple IO (PA) flip C code, which inserts a 5-clock frequency cycle delay between flips. The existing technology is as follows:
[0077] PA = 0<<24;
[0078] __NOP__;
[0079] __NOP__;
[0080] __NOP__;
[0081] __NOP__;
[0082] __NOP__;
[0083] PA = 1<<24;
[0084] That is, between IO flip codes, null instructions are inserted to achieve the purpose of delay. As mentioned in the background technology, the execution of null instructions depends on instruction fetch and execution delay, and the delay result is uncertain, which cannot meet high-precision requirements; PA = 1<<24, whether the C code is a single instruction or multiple instructions after compilation depends on the compilation options and additional factors such as the instruction encoding format. A single instruction can often be completed in a single cycle, while multiple instructions mean that more cycles are required to complete. Therefore, during the debugging stage, it is necessary to reduce or increase the number of __NOP__ according to the actual situation. At the same time, executing these null instructions temporarily consumes system resources and wastes power.
[0085] This method only requires inserting a delay instruction between two instructions, such as:
[0086] PA = 0<<24;
[0087] asm("dly.i x0, 5, SM"); / / Disable frequency division, match STORE, delay number 5.
[0088] PA = 1<<24;
[0089] After processing by this method, asm("dly.i x0, 5, SM") has a higher tolerance for instruction value fetching and execution delays, and is better adaptable to the delay end point (PA = 1<<24;).
Claims
1. A CPU capable of precise delay control, characterized in that: include: An instruction decoder, configured to decode a valid delay instruction, obtain instruction information, and output a delay request, wherein the instruction information includes a first delay value, a second delay value, and instruction matching information; An adder, the input end of which inputs the first delay number and the second delay number, and the output end of which is connected to the counter; a counter, configured to reload the output value of the adder, count down, and output the counting result to the delay controller upon receiving a delay request; a delay monitor, configured to detect the pipeline, receive instruction matching information, match the detected pipeline instructions according to the instruction matching information, match the detected pipeline privileges according to preset privilege information, and transmit the matching results to the delay controller; The delay controller is used to receive the delay request and instruction matching information output by the instruction decoder, store the instruction matching information in a register and output it to the delay monitor, receive the counting result output by the counter, receive the matching result output by the delay monitor, switch the delay working state, output a pause request to the CPU pipeline controller or cancel the pause request. When the delay controller receives the delay request and instruction matching information, it switches the delay working state to a busy state. In the busy state, if the matching result is valid, it sends a pause request to the CPU pipeline controller. When the counting result returns to zero, the delay controller switches the delay working state to an idle state and cancels the pause request to the CPU pipeline controller.
2. The CPU capable of precise delay control according to claim 1, characterized in that: The counter includes a delay counter and a frequency division counter; the instruction information also includes frequency division counting enable on and frequency division counting enable off, the delay counter and the frequency division counter are both connected to the delay controller, the input end of the delay counter is connected to the output end of the adder, the input end of the frequency division counter is connected to the control register, the control register is used to store the pre-frequency division value, and the delay counter is reloaded to the output value of the adder when receiving the delay request; When the frequency division count enable is off, the delay counter works, the frequency division counter does not work, and the delay counter decreases by 1 per cycle; when the frequency division count enable is on, both the delay counter and the frequency division counter work. The frequency division counter is reloaded to the pre-division value when it receives a delay request or decreases to 0, and the frequency division counter decreases by 1 per cycle. Whenever the frequency division counter decreases to 0, the delay counter decreases by 1.
3. The CPU capable of precise delay control according to claim 1 or 2, characterized in that: The instruction matching information includes one or more of a read instruction, a write instruction, an arbitrary instruction, a delayed instruction, and a preset instruction.
4. The CPU capable of precise delay control according to claim 1 or 2, characterized in that: The first delay number and the second delay number are operands or delayed immediate numbers; a general register is also included, the general register is used to pre-store operands, the instruction decoder decodes the operand register label, and then obtains the operand through the register.
5. The CPU capable of precise delay control according to claim 4, characterized in that: It also includes a selector, wherein the first input end of the selector is connected to the register, the second input end is connected to the decoder, and the selector is controlled by the selection of the instruction decoder, and the output end is connected to the adder.
6. A method for accurately controlling a CPU delay capable of accurate delay control, characterized in that: The following steps are involved: Step 1: Assume that in the tth clock cycle, t is a positive integer greater than 0, the CPU executes a valid delay instruction, decodes the delay instruction, obtains instruction information, and outputs a delay request. The instruction information includes a first delay value, a second delay value, and instruction matching information. At the same time, the following operations are performed: The adder adds the first delay number and the second delay number and provides an output value to the counter; The counter receives the delay request and reloads the output value of the adder; The delay controller receives the delay request and instruction matching information, switches the delay working state to the busy state, saves the instruction matching information in the register and outputs it to the delay monitor; Step 2: From the t+1th clock cycle onwards, the CPU continues to execute subsequent instructions and performs the following operations: The counter counts down and outputs the counting result to the delay controller; The delay monitor detects the pipeline in real time, matches the detected pipeline instructions according to the received instruction matching information, matches the pipeline privileges according to the preset privilege matching information, and transmits the matching results to the delay controller. When both the pipeline instructions and pipeline privileges are matched successfully, the matching result is valid; When the delay controller is in the busy state and the matching result is valid, it sends a pause request to the CPU pipeline controller; when the counting result returns to zero, the delay controller switches the delay working state to the idle state and cancels the pause request to the CPU pipeline controller, and the delay ends.
7. The CPU precise delay control method capable of precise delay control according to claim 6, characterized in that: In step 1, the instruction information further includes frequency division counting enable on and frequency division counting enable off; the counter includes a delay counter and a frequency division counter, and the delay counter is reloaded to the output value of the adder when receiving a delay request; When the frequency division count enable is off, the delay counter works, the frequency division counter does not work, and the delay counter decreases by 1 per cycle; when the frequency division count enable is on, both the delay counter and the frequency division counter work, and the frequency division counter is reloaded to the pre-division value when it receives a delay request or decreases to 0, and the frequency division counter decreases by 1 per cycle; whenever the frequency division counter decreases to 0, the delay counter decreases by 1.
8. The CPU precise delay control method capable of precise delay control according to claim 7, characterized in that: In step 2, the delay controller switches to the idle state when the counting result returns to zero, specifically including: when the frequency division counting enable is turned off, when the counting result of the delay counter is 0, the delay working state switches to the idle state; when the frequency division counting enable is turned on, when the counting results of the delay counter and the frequency division counter are both 0, the delay working state switches to the idle state.
9. The CPU precise delay control method capable of precise delay control according to any one of claims 6 to 8, characterized in that: In step 2, the instruction matching information includes one or more of a read instruction, a write instruction, all instructions, a delay instruction, and a preset instruction.
10. The CPU precise delay control method capable of precise delay control according to any one of claims 6 to 8, characterized in that: In step 1, the first delay number and the second delay number are delayed immediate numbers or operands stored in a general register. If they are operands, the instruction decoder decodes the operand register number and then obtains the operand through the register.
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