Method for entering and exiting DFT (Discrete Fourier Transform) mode only through multiplexing function pin

Abstract

The invention discloses a method for entering a DFT (Discrete Fourier Transform) quit mode only through a multiplexing function pin. The method comprises the following steps: S1, entering a reset state when an NRST pin is pulled down; s2, accessing an external clock signal by using a PA12 data pin, and respectively sampling input sequences of a PA13 data pin and a PA4 data pin; s3, when the two input sequences both meet the triggering conditions, enabling signals are generated, and a DFT mode is entered; and S4, when the PA0 pin is at a high level, executing the step S2 and re-judging whether the two input sequences meet the trigger condition, and if so, pulling down the enable signal and exiting the DFT mode. After the NRST pin is pulled down to enter the reset state, the external clock signal is introduced, the input sequences of the two data pins are detected, the DFT mode can be entered or quitted when the trigger condition is met, the function of entering the DFT mode is completed by multiplexing the existing pin, and the situation of mistaken touch is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic chips, and particularly relates to a method for entering and exiting the DFT mode only by multiplexing functional pins. Background Art

[0002] Design for Test means design for testability, abbreviated as DFT. It inserts various hardware logics for improving the testability of the chip in the original chip design, thereby making the chip easy to test, greatly saving the cost of chip testing, and at the same time avoiding irreparable losses in economy or other aspects caused by defective chips flowing into the hands of customers.

[0003] With the continuous development of the Internet of Things technology, MCUs play a very important role in it, and more and more miniaturized packaged MCUs have been widely used. For mature mass-produced miniaturized packaged MCU products, the importance of DFT design is self-evident.

[0004] When designing DFT for miniaturized packaged MCUs, a dedicated pin is usually required to enter and exit the DFT mode. This pin cannot be multiplexed for normal peripheral functions. If other functional pins are multiplexed, it may cause users to accidentally touch and enter the DFT mode during normal use, directly affecting the normal function, and accidentally trigger the exit of the DFT mode during machine testing, affecting DFT testing. However, the pin resources of miniaturized packaged MCUs are very limited. The solution of setting up a dedicated DFT pin means losing other functions, and the product power of this MCU will be greatly reduced. Therefore, how to enter and exit the DFT mode by multiplexing functional pins and at the same time solve the problems of users accidentally touching and entering the DFT mode during normal use and accidentally triggering the exit of the DFT mode during machine testing is particularly important. Summary of the Invention

[0005] In view of the above problems, the object of the present invention is to propose a method for entering and exiting the DFT mode only by multiplexing functional pins. After pulling down the NRST pin to enter the reset state, an external clock signal is introduced and the input sequences of two data pins are detected respectively. When the trigger conditions are met, the DFT mode can be entered or exited. This not only completes the function of entering the DFT mode by multiplexing the existing data pins of the MCU, effectively improving the resource utilization rate of the MCU, but also reduces the situation of accidental touch by users.

[0006] It is achieved through the following technical solutions: A method for entering and exiting the DFT mode only by multiplexing functional pins, used for MCU testing, includes the following steps: Step S1: When the NRST pin is pulled low, the MCU enters the reset state; Step S2: Connect an external data signal to the PA12 data pin as the clock signal, and then sample the input sequences of the PA13 data pin and the PA4 data pin respectively; Step S3: When the input sequences of the PA13 data pin and the PA4 data pin both meet the trigger conditions, the control device inside the MCU generates a scan_mode enable signal and enters the DFT mode; Step S4: After entering the DFT mode, select any unused signal pin for use; when the PA0 signal pin is at a high level, execute Step S2 again and re-determine whether the input sequences of the PA13 data pin and the PA4 data pin meet the trigger conditions. If the trigger conditions are met, the state machine inside the MCU pulls down the scan_mode enable signal and exits the DFT mode.

[0007] Preferably, after entering the DFT mode in Step S3, lock the state of the PA0 signal pin through a hardware locking mechanism to prevent accidental exit from the DFT mode; when exiting the DFT mode in Step S4, unlock the PA0 signal pin. Through the hardware locking mechanism, the situation of accidental touch can be further reduced.

[0008] Preferably, the control device in Step S3 is the DFT control logic module or the state machine inside the MCU. Both the DFT control logic module and the state machine can generate and control the scan_mode enable signal, thereby effectively controlling the DFT process.

[0009] Preferably, when entering the DFT mode in Step S3, the MCU uses the PA5 signal pin to output a high level to indicate that the MCU is in the DFT mode. Reusing an existing signal pin in the MCU can indicate whether the MCU is in the DFT mode, thereby assisting relevant personnel to more clearly understand whether the current state of the MCU meets the expectations.

[0010] Preferably, when exiting the DFT mode in Step S4, use the PA5 signal pin to output a low level to indicate that the MCU has exited the DFT mode. Reusing an existing signal pin in the MCU and using high and low levels to represent different states enables relevant personnel to more clearly understand whether the MCU is in the DFT mode.

[0011] Preferably, the trigger condition in Step S4 is that the level change sequence and the level change period of the PA13 data pin and the PA4 data pin both correspond to the clock signal. Both the level change sequence and the period can correspond to the clock signal, thereby improving the reliability and simplicity of the trigger condition.

[0012] Preferably, when S2 is executed again in step S4, the input sequences of the PA13 data pin and the PA4 data pin are synchronously detected. When any error sequence is detected, the error count of the error counter inside the MCU is incremented by 1; when the error count exceeds the set threshold, the DFT mode is locked until a reset occurs.

[0013] The beneficial effects of the present invention compared with the prior art are as follows: According to the technical solution of the present invention, after pulling down the NRST pin to enter the reset state, an external clock signal is introduced and the input sequences of the two data pins are detected. When the triggering conditions are met, the DFT mode can be entered or exited. This not only completes the function of entering the DFT mode by multiplexing the existing data pins of the MCU, effectively improving the resource utilization rate of the MCU, but also reduces the situation of accidental touch during user operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a flowchart of a method for entering and exiting the DFT mode only by multiplexing function pins; Figure 2 is a timing comparison diagram when entering the DFT mode; Figure 3 is a timing comparison diagram when exiting the DFT mode. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0015] The following will combine the accompanying drawings in the embodiments of the present invention Figures 1 to 3 to describe the technical solutions in the embodiments of the present invention in detail.

[0016] As Figure 1 shown, it is a flowchart of a method for entering and exiting the DFT mode only by multiplexing function pins, used for MCU testing. By multiplexing the existing pins of the MCU to detect the input sequences, the internal control device is used to control the corresponding enable signals to enter or exit the DFT mode, effectively reducing the situation of accidental touch; specifically including the following steps: Step S1: When the NRST pin is pulled low, the MCU enters the reset state. The NRST pin is the reset pin. When pulled low, the MCU will perform an initial reset. At this time, the MCU cannot work properly, so no other external excitation will be input into the MCU, which is convenient for testing.

[0017] Step S2: Use the PA12 data pin to access an external data signal as the clock signal, and then sample the input sequences of the PA13 data pin and the PA4 data pin respectively. When the NRST pin is pulled low, the internal clock signal of the MCU may be unstable. If the internal clock signal of the MCU is directly used for testing, it is difficult to ensure the stability and reliability of the test. Therefore, an external stable clock signal, such as the clock signal of a signal generator or a test station, is received through the PA12 data pin to be used as the timing reference during testing, which can ensure the accuracy of the test.

[0018] Step S3: When the input sequences of the PA13 data pin and the PA4 data pin both meet the trigger conditions, the MCU first defines the scan_mode enable signal using the netlist internally, and then the control device receives the scan_mode enable signal, indicating that the DFT test is ready to be performed, so that the MCU enters the DFT mode.

[0019] In this embodiment, after entering the DFT mode in step S3, the hardware locking mechanism can also be set through the state machine in the MCU to lock the state of the PA0 signal pin to prevent accidental exit from the DFT mode; when exiting the DFT mode in step S4, the PA0 signal pin is unlocked again. Through the hardware locking mechanism, the situation of accidental touch can be further reduced.

[0020] In this embodiment, the control device in step S3 is the DFT control logic module or the state machine inside the MCU. The MCU usually has a DFT control logic module and a state machine internally. Using either the DFT control logic module or the state machine can generate and control the scan_mode enable signal, thus effectively controlling the DFT process.

[0021] In this embodiment, when entering the DFT mode in step S3, the MCU can also select a signal pin for indication. For example, the PA5 signal pin is used to output a high level to indicate that the MCU is in the DFT mode. Reusing an existing signal pin in the MCU can indicate whether the MCU is in the DFT mode, so as to assist relevant personnel in further confirming whether the current state of the MCU meets the expectations through the level of the indication.

[0022] As Figure 2As shown, it is a timing comparison diagram when entering the DFT mode. The dashed line in the figure is only used for the timing comparison of different signals. When the NRST pin is pulled low, the PA12 data pin is used to access the external clock signal, so that the DFT test can be carried out stably, reducing the probability of errors caused by unstable internal clock signals. Then, sample the input sequences of the PA13 data pin and the PA4 data pin respectively. If both can meet the trigger conditions of a specific sequence, the state machine or DFT control logic module inside the MCU chip outputs a stable scan_mode enable signal. Since the chip is in a reset state with the NRST pin pulled low and the MCU cannot work properly, the user does not input excitation to the MCU. At the same time, it is basically impossible for PA12, PA13, and PA4 to generate a specific input sequence with a phase relationship from the perspective of pin functions, which can avoid accidentally triggering and entering the DFT mode during normal use. It should be noted that PA12, PA13, and PA4 can be multiplexed function pins or other non-multiplexed pins, and the numbers involved in the pins are only used to distinguish different pins.

[0023] Step S4: After entering the DFT mode, select any unused signal pin for use, such as the PA0 signal pin. When the PA0 signal pin is at a high level, execute step S2 again and re-determine whether the input sequences of the PA13 data pin and the PA4 data pin respectively meet the trigger conditions. If the trigger conditions are met, the state machine or DFT control logic module inside the MCU pulls low the scan_mode enable signal, and the MCU exits the DFT mode.

[0024] In this embodiment, when exiting the DFT mode in step S4, use the PA5 signal pin to output a low level to indicate that the MCU has exited the DFT mode.

[0025] In this embodiment, the trigger condition in step S4 is that the level change order and level change period of the PA13 data pin and the PA4 data pin both correspond to the clock signal. The level change order and period can both correspond to the clock signal, thereby improving the reliability and simplicity of the trigger condition.

[0026] In this embodiment, when step S2 is executed again in step S4, the input sequences of the PA13 data pin and the PA4 data pin are synchronously detected. When any error sequence is detected, the error count of the error counter built in the MCU is incremented by 1; when the error count exceeds the set threshold, the DFT mode is locked until reset. The error counter can effectively detect whether there are errors in the sequence. When there are many errors, that is, when the threshold set by the user is reached, it means that there is a problem with the input sequence this time and it needs to be retested to ensure accuracy.

[0027] Such as Figure 3As shown, it is a timing comparison diagram when exiting the DFT mode. The dashed line in the figure is only for the timing comparison of different signals. When the PA0 pin is high, continue to use the PA12 data signal pin to access a new external clock signal, sample the input sequences of PA13 and PA4, and if a specific sequence is satisfied, exit the DFT mode and pull down the scan_mode signal. The new external clock signal can be the same signal as the Figure 2 clock signal shown, or it can be a different signal, as long as the phase requirements of PA13 and PA4 can meet a specific sequence. Since the unused PA0 pin is used as the key signal for exiting, it can avoid the PA12, PA13, and PA14 pins being accidentally triggered to exit the DFT mode during the DFT vector test of the machine, thereby outputting a stable scan_mode enable signal during the DFT test.

[0028] In summary, after pulling down the NRST pin to enter the reset state, the present invention introduces an external clock signal and detects the input sequences of two data pins respectively. When the triggering conditions are met, it can enter or exit the DFT mode. It not only completes the function of entering the DFT mode by multiplexing the existing data pins of the MCU, effectively improving the resource utilization rate of the MCU, but also reduces the accidental touch situation during user use, having significant progressiveness.

[0029] The above embodiments are only used to illustrate the technical idea of the present invention, and the protection scope of the present invention cannot be limited thereby. Any changes made on the basis of the technical solution according to the technical idea proposed by the present invention fall within the protection scope of the present invention.

Claims

1. A method for entering and exiting the DFT mode only by multiplexing function pins for MCU testing, characterized in that It includes the following steps: Step S1: When the NRST pin is pulled low, the MCU enters the reset state; Step S2: Use the PA12 data pin to access an external data signal as the clock signal, and then sample the input sequences of the PA13 data pin and the PA4 data pin respectively; Step S3: When the input sequences of the PA13 data pin and the PA4 data pin both meet the trigger conditions, the control device inside the MCU generates a scan_mode enable signal and enters the DFT mode; Step S4: After entering the DFT mode, select any unused signal pin for use; when the PA0 signal pin is at a high level, execute Step S2 again and re-determine whether the input sequences of the PA13 data pin and the PA4 data pin meet the trigger conditions. If the trigger conditions are met, the state machine inside the MCU pulls low the scan_mode enable signal and exits the DFT mode.

2. The method according to claim 1, wherein After entering the DFT mode in Step S3, lock the state of the PA0 signal pin through a hardware locking mechanism to prevent accidental exit from the DFT mode; when exiting the DFT mode in Step S4, unlock the PA0 signal pin again.

3. The method according to claim 1, wherein The control device in Step S3 is the DFT control logic module or the state machine inside the MCU.

4. The method according to claim 1, wherein When entering the DFT mode in Step S3, the MCU uses the PA5 signal pin to output a high level to indicate that the MCU is in the DFT mode.

5. The method according to claim 4, wherein When exiting the DFT mode in Step S4, use the PA5 signal pin to output a low level to indicate that the MCU has exited the DFT mode.

6. The method according to claim 1, wherein The trigger condition in Step S4 is that the level change sequence and the level change period of the PA13 data pin and the PA4 data pin both correspond to the clock signal.

7. The method according to claim 1, wherein When executing S2 again in Step S4, synchronously detect the input sequences of the PA13 data pin and the PA4 data pin respectively. When any error sequence is detected, the error count of the error counter inside the MCU is incremented by 1; when the error count exceeds the set threshold, lock the DFT mode until reset.

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