A memory testing method, device and medium based on AI technology

Abstract

This invention discloses a memory testing method, device, and medium based on AI technology, comprising the following steps: 1) obtaining structural analysis data and memory type description information of the memory to be tested, and generating a test intent vector for expressing the test target; 2) using the test intent vector as input, generating a test stimulus sequence; 3) executing the test stimulus sequence to perform multi-cycle testing on the memory array, forming a multimodal response feature set; 4) inputting the multimodal response feature set into a graph neural network to perform fault type identification and causal path reasoning, generating a fault label sequence and an inference path graph; 5) updating the weight parameters of a deep generative model based on the feature differences between the inference path graph and the test stimulus sequence; and 6) generating a test stimulus sequence based on the updated deep generative model for memory testing. This invention can effectively improve the intelligence level and test coverage of memory testing.

Description

Technical Field

[0001] The present invention relates to integrated circuit testing technology, and in particular to a memory testing method, device, and medium based on AI technology. Background Art

[0002] As memory chips develop toward higher capacity, higher speed, and higher integration, their structural complexity and manufacturing process precision continue to increase. Traditional test methods based on rule-driven and static stimulus testing are no longer able to fully cover potential failure risks. This is especially true when testing high-speed memories with heterogeneous structures, such as SRAM, DRAM, and MRAM. Key challenges include:

[0003] First, current test methods lack in-depth analysis of chip structural level information, making it difficult to identify structurally sensitive areas such as bit crossings, edge effects, and process anomalies, resulting in insufficient fault stimulus coverage.

[0004] Second, test strategies generally rely on manual experience configuration and are unable to generate expressive stimulus sequences with fault-driving capabilities based on the target structure, making it difficult to achieve targeted fault triggering and behavior coverage.

[0005] Third, response data collection is mostly single-modal, failing to fully integrate multi-source information such as operational behavior, electrical response, and environmental disturbances, limiting the accuracy of fault classification and the integrity of the reasoning path.

[0006] Fourth, the current system model lacks dynamic feedback mechanisms and adaptive capabilities. It cannot automatically optimize test strategies based on test results, and it is difficult to achieve efficient migration and deployment of models between different hardware platforms.

[0007] Therefore, there is an urgent need for a rapid testing method that integrates structural analysis, semantic modeling, multimodal response fusion, and feedback optimization mechanisms to build an AI testing system with intelligent generation, precise judgment, and cross-platform self-evolution capabilities to improve the testing efficiency, accuracy, and deployment flexibility of modern memory products. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a memory testing method, device and medium based on AI technology to address the defects in the existing technology.

[0009] The technical solution adopted by the present invention to solve the technical problem is: a fast memory testing method based on AI, comprising the following steps:

[0010] 1) obtaining structural parsing data and memory type description information of the memory to be tested, and generating a test intent vector for expressing the test target based on the structural parsing data and memory type description information of the memory to be tested;

[0011] The structural analysis data includes the memory cell arrangement matrix, bit line word line structure and redundancy mapping relationship of the memory to be tested;

[0012] 2) Taking the test intent vector as input, combined with the memory target fault mode database, inputting it into a preset deep generative model, constructing a fault coverage semantic representation, and generating a test stimulus sequence;

[0013] 3) executing the test stimulus sequence, performing a multi-cycle test on the storage array, collecting electrical signal data, operation timing traces, and operating environment parameters during the test process, and forming a multimodal response feature set;

[0014] 4) Inputting the multimodal response feature set into a graph neural network to perform fault type identification and causal path reasoning, generating a fault label sequence and a reasoning path graph;

[0015] 5) Based on the feature differences between the inference path graph and the test stimulus sequence, the deviation vector is calculated and back-propagated to obtain the feedback gradient and update the weights of the deep generative model;

[0016] 6) Generate test stimulus sequences based on the updated deep generative model for memory testing.

[0017] According to the above scheme, the structural analysis data is obtained by hierarchically expanding the physical structure information of the memory to be tested, and constructing the memory cell arrangement matrix, bit line word line structure and redundant mapping relationship through layout structure analysis;

[0018] The physical structure information includes the layout netlist, physical address mapping diagram, redundant structure configuration table, bit line layout file, and word line group structure information.

[0019] According to the above solution, the type description information includes attribute information including memory type, process node, number of stacking layers, dielectric type, and transistor type.

[0020] According to the above scheme, the test intent vector for expressing the test target is generated based on the structural parsing data and memory type description information of the memory to be tested; specifically as follows:

[0021] Based on the structural analysis data, key structural sensitive area features are extracted to form a structural sensitivity feature vector; based on the structural sensitivity feature vector and memory type description information, a test construction objective function is constructed to generate a test intent vector for expressing the test target.

[0022] According to the above scheme, based on the structural analysis data, the key structural sensitive area features are extracted to form a structural sensitivity feature vector, which specifically includes:

[0023] Identification of process weaknesses: Identify areas prone to unstable behavior during the process, including high-density bit intersections, critical dimension error regions, and PMOS and NMOS boundary transition regions. Using lithography models combined with residual mapping technology, the coordinate points of the corresponding logic cells are extracted to form a set of process anomaly locations.

[0024] Edge cell area extraction: locate the storage cell group at the boundary of the row and column matrix, record its redundant mapping quantity and fault history statistics, and form an edge cell feature set;

[0025] Extraction of dense bit crossing areas: Counting the integration density of bit lines and word lines in the crossing area, and marking error-prone nodes based on the coupling capacitance threshold to form a set of crossing interference areas;

[0026] Based on the above three sets, a unified structure-sensitive region feature representation tensor is constructed and the tensor is encoded as a structure-sensitive feature vector ,The structural sensitivity feature vector contains the following fields: node density statistics, ,structure type identification, fault history weight, and process anomaly probability estimation.

[0027] According to the above scheme, test the intent vector The fields included are: Target access zone index , address hopping frequency control items , Fault-induced potential score , concurrent conflict warning weight .

[0028] According to the above scheme, the fault coverage semantic representation is constructed and the test stimulus sequence is generated; specifically: Accurately drive the deep generative model, perform semantic-level modeling and access path construction on the target fault coverage pattern, and ultimately generate a test stimulus sequence with precise coverage, controllable paths, and traceable indexes. ;

[0029] right Perform position embedding to obtain a structural semantic representation sequence ,in, Represents the embedding result of the corresponding dimension; then, the structural semantic representation sequence is combined with the fault coverage task label vector , generate structure-fault correlation vector map , used to capture the prior features of structural regions and historical fault mapping.

[0030] Representing structural semantics as a sequence Structure-fault correlation vector map Input into the multi-layer Transformer encoder of the deep generative model for vector parsing, and the output vector parsing result is a set of semantic attention values and position weight distribution vector ;

[0031] Based on the vector analysis results and target fault type sample characteristics, construct an access path logic diagram for triggering the target sensitive area;

[0032] Expand the access path logic diagram to generate the test intent vector Corresponding test stimulus sequence .

[0033] According to the above scheme, the access path logic diagram for triggering the target sensitive area is constructed as follows:

[0034] Get semantic attention value and position weight distribution , combined with the structural excitation paradigm vector in the fault type sample library ,construction of a logical graph of access paths to the execution structure.

[0035] Specifically, the fault type sample library is extracted from the fault type sample library. and Matching target fault type feature subset ,The features include typical access order, fan-out path, register perturbation sequence, and interleaved address mapping rules;

[0036] Combined with semantic attention value , perform the initial topology extraction of the access path, The access method in is mapped to the target structure region coordinates The physical location pointed to, based on this, using the location weight distribution Control the segment depth, number of concurrent nodes, and address jump range of the access path to build the access path logic graph ;

[0037] Access path logic diagram It is a directed graph structure, in which nodes represent access actions, edges represent timing and control dependencies, and edge weights include indicators such as access delay, coupling interference, and logic coverage.

[0038] According to the above scheme, the access path logic diagram is structurally expanded to generate the test intention vector Corresponding test stimulus sequence ; The details are as follows:

[0039] First, based on The timing dependency constraints and access instruction classification in the graph are used to perform depth-first traversal of the graph structure, and the access nodes in the graph are linearly sorted according to the control dependency order to obtain the access path sequence. ;

[0040] For each path segment in the access path sequence , the system combines the original structure sensitive area indicators and jump control parameters , generate access control blocks ,The access control block contents include address jump mode, word line selection flag, read and write control bits, and precharge cycle mask;

[0041] All access control blocks are spliced together in sequence to form a test stimulus sequence:

[0042] ;

[0043] Among them, each element in the set represents a structured intention vector Mapping control, target fault type feature subset Adapted and position distribution vector A set of test control instructions for constraint generation.

[0044] According to the above scheme, the multimodal response feature set is as follows:

[0045]

[0046] in:

[0047] For the The electrical response characteristics within a cycle; Indicates the The voltage within a cycle, Indicates the Current in a cycle Indicates the Capacitance within a cycle;

[0048] is the operation timing field of the i-th stimulus instruction; For timestamp, For operation type, is the row and column address; among them, the i-th excitation instruction corresponds to the Cycle of excitation instructions;

[0049] is the environmental state variable of the i-th cycle; is the chip surface temperature sequence; is the power supply voltage fluctuation sequence; is the space electromagnetic interference index sequence;

[0050] For the Cyclic generated fusion response feature unit.

[0051] According to the above scheme, the multimodal response feature set is input into the graph neural network model to perform graph structure feature encoding and generate a fault feature graph vector;

[0052] Perform fault classification processing on the fault feature map vector to obtain the corresponding fault type label sequence;

[0053] Based on the fault feature graph vector and the node nesting path information, a reasoning path graph is generated to represent the causal path of the test stimulus triggering the fault.

[0054] According to the above scheme, the multimodal response feature set is input into the graph neural network to perform fault type identification and causal path reasoning, and generate a fault label sequence and reasoning path graph;

[0055] Perform causal path analysis on the graph structure and construct the reasoning path diagram during the test triggering process .

[0056] The system first extracts all node pairs from the graph structure , the node pairs satisfy the following conditions:

[0057] Time sequence is established: ;

[0058] Space adjacent: and The difference is less than the preset threshold ;

[0059] The possibility of failure impact is: belong A set of possible triggering consequences (based on historical path statistics).

[0060] For node pairs that meet the above conditions, build a path edge set , and define the reasoning path diagram as follows:

[0061] Reasoning path diagram generation:

[0062]

[0063] in:

[0064] is the set of subgraph nodes containing predicted fault nodes; Indicates the Layer The feature vector of each node;

[0065] A set of directed edges that satisfy the time-space-causal reasoning conditions;

[0066] Is a causal verification function used to determine the node Is it possible to affect the node .

[0067] According to the above scheme, based on the feature differences between the inference path graph and the test stimulus sequence, the deviation vector is calculated and back-propagated to obtain the feedback gradient and update the weights of the deep generative model;

[0068] The following method is used to calculate the deviation vector:

[0069] Measuring fault nodes based on inference path graphs through feature matching Stimulus instructions with test stimulus sequence The path similarity and trigger correlation between them; the characteristics include address overlap, time alignment and operation type consistency;

[0070] By accumulating feature differences, we can obtain the matching deviation vector , where each in the matching deviation vector express Middle The size of the matching error between the instructions and the related nodes in the reasoning path graph.

[0071] According to the above scheme, memory testing is to build a model adaptation vector and generate a platform customized model based on the updated deep generative model and the current test platform parameter configuration;

[0072] The platform customized model is deployed to the target test platform or edge node, the model execution engine configuration is completed, and the adaptive execution of a new round of test tasks is realized.

[0073] The present invention further provides an electronic device, comprising:

[0074] one or more processors;

[0075] as well as

[0076] a storage device for storing one or more programs,

[0077] When the one or more programs are executed by the one or more processors, the one or more processors execute the method described in any one of the above solutions.

[0078] The present invention also provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the method described in any one of the above solutions is implemented.

[0079] The beneficial effects produced by the present invention are:

[0080] 1. The present invention achieves matching between the test and the target memory structure by constructing a structural sensitivity feature vector and generating a test intent vector based on the test construction objective function, thereby accurately identifying potential fault areas before the test sequence is generated. Compared with traditional experience-driven or general test vector construction methods, this method significantly improves the targetedness and coverage efficiency of test stimulus generation, and is particularly suitable for detecting minor faults in complex heterogeneous storage structures.

[0081] 2. This invention integrates multimodal response features (including electrical signals, time series traces, and environmental parameters) into a graph neural network to generate fault labels and infer causal paths. This method enables visualization of structural-level causal chains and interpretable fault analysis, resolving the difficulty of existing methods in locating the root cause of faults in complex interaction scenarios and improving the ability to understand complex fault patterns.

[0082] 3. Implement adaptive optimization of test strategies and platform migration deployment. By updating the weights of the deep generative model through a feedback gradient mechanism and constructing a model adaptation vector based on platform parameters, model customization and deployment are completed, enabling the test system to have continuous evolution capabilities and broad platform adaptability. Compared to static model testing methods, this invention offers greater versatility and deployment flexibility, making it suitable for distributed automatic testing requirements across multiple process and multi-chip platforms. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] The present invention will be further described below with reference to the accompanying drawings and embodiments, in which:

[0084] Figure 1 It is a flow chart of a method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0085] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0086] like Figure 1 As shown, an embodiment of the present invention provides a fast memory testing method based on AI technology, the method comprising the following steps:

[0087] S100, extracting structural sensitive area features of the memory based on the structure parsing data and type description information of the memory to be tested, and generating a test intention vector TIV for test construction;

[0088] S110, obtaining physical structure information and type description information of the memory to be tested;

[0089] In this step, the underlying structural information and process description data related to the target test chip are first extracted from the memory design data and process database. Structural information includes the layout netlist, physical address map, redundant structure configuration table, bitline layout file, and wordline group structure information. Type description information is the memory classification label and process node parameters, specifically including basic attributes such as memory type (such as SRAM, DRAM, MRAM, ReRAM), process node (such as 28nm, 14nm, 7nm), number of stack layers, dielectric type, and transistor type.

[0090] S120, hierarchically expand the physical structure information, perform layout structure analysis, obtain a storage cell arrangement matrix, a bit line word line structure, and a redundant bit mapping relationship, obtain structure analysis data, and convert it into a readable matrix format; the specific steps are as follows:

[0091] Generate a storage unit arrangement matrix, wherein the matrix is used to express the relative spatial position and logical association of each storage unit in a two-dimensional layout;

[0092] Extract the bit line and word line structure information and identify the actual connected control signal paths in each row and column;

[0093] Constructing a redundant bit mapping relationship diagram, which is used to record the jump logic between the standard address space and the redundant address space;

[0094] The structural analysis data obtained in this step will be used as the input data set for subsequent sensitive area extraction and named as the structural analysis data set. , which contains multi-dimensional feature structures such as physical location information, redundancy compensation relations, and address mapping rules. It serves as the basic data for extracting feature vectors in the subsequent S130 stage.

[0095] S130, extract key sensitive area features from the memory structure information, including process weakness bits, edge unit area extraction, and bit cross-dense area extraction, to generate a structural sensitivity feature vector ;

[0096] Obtaining a structure elucidation dataset Then, in step S130, the physical areas that may cause test blind spots or easily trigger hidden faults are analyzed to extract structural sensitive parameters that are highly correlated with test defect triggering. Specifically, feature extraction includes the following three dimensions:

[0097] Identification of process weaknesses: Identify areas prone to unstable behavior in the process, including high-density bit intersection areas, critical dimension error sections, PMOS and NMOS boundary transition areas, etc. Utilize the lithography model combined with residual mapping technology to extract the coordinate points of the corresponding logic units and form a process abnormality location set. ;

[0098] Edge cell area extraction: locate the storage cell group at the boundary of the row and column matrix, record its redundant mapping quantity and fault history statistics, and form an edge cell feature set ;

[0099] Extraction of dense bit crossing areas: Count the integration density of bit lines and word lines in the crossing area, and mark the error-prone nodes in combination with the coupling capacitance threshold to form a cross-interference area set. ;

[0100] Based on the above three sets, the system constructs a unified structure-sensitive region feature representation tensor .

[0101] The tensor Compression coding as structure sensitivity feature vector , the vector is a one-dimensional representation, containing the following fields: node density statistics, structure type identification, fault history weight, process abnormality probability estimation, etc. It will be directly used as the core input parameter of step S140 and participate in the modeling of the objective function and the construction of the expression vector.

[0102] S140, based on structural sensitivity feature vector With the memory type description information, construct the test construction target function, perform preliminary expression encoding on the target function, and generate the test intention vector .

[0103] In this step, the structural sensitivity vector is constructed based on the completion of the feature vector construction. Together with the previously acquired memory type description information, it is input into the test construction objective function to generate an expressive vector that can be recognized by the deep model, namely the test intent vector .

[0104] Specifically, first construct the test construction objective function , which is defined as the structure vector This function fuses, transforms, and compresses the type description information to express the intended coverage area, stimulus sequence characteristics, trigger circuit structure, and other information about the current test target. This function uses a structure consisting of embedding layers, convolutional layers, and attention modules to deeply map structural features to semantic labels.

[0105] In the expression process, the function The output is an intermediate expression tensor, which is further linearly stretched and normalized to form a test intent vector. The test intention vector can be set to a fixed length in terms of dimension (such as 128 dimensions, 256 dimensions, etc.), and each dimension corresponds to a type of structural sensitive trigger path, fault pattern matching category, or incentive strategy classification.

[0106] The test intent vector It will be directly used as the input of the subsequent deep generative model to generate the target test stimulus sequence .

[0107] Through the complete execution of S100, a deep analysis of the memory structure, process weaknesses and fault trigger characteristics to be tested is completed during the test task initialization phase, and a unified structural sensitivity feature vector is constructed. , and further construct a test intention vector with semantic expression ability This vector not only accurately reflects the current structural state of the memory and potential fault risk areas, but also provides basic structural semantic support for test stimulus generation, multimodal data acquisition, fault path reasoning, and model feedback optimization in subsequent steps, ensuring the continuity, intelligence, and closed-loop collaboration of the test process.

[0108] S200 , inputting the test intention vector TIV into a preset deep generation model, adaptively modeling the target fault coverage pattern, and generating a test stimulus sequence TES.

[0109] The AI technology used in this embodiment includes deep generative models in the field of deep learning;

[0110] Step S200 includes the following steps:

[0111] S210, the test intention vector Input into the preset deep generation model built based on the Transformer structure for vector parsing.

[0112] Specifically, after completing the feature encoding in S130, the structure-driven test intention vector is obtained. , which contains the following fields: target access area index , address hopping frequency control items , Fault-induced potential score , concurrent conflict warning weight This vector is used as a key input feature and is input into the deep generation model built based on the Transformer network structure.

[0113] The deep generative model uses a multi-head attention mechanism, a multi-layer encoder structure, and a positional encoding submodule, and has the ability to memorize contextual features and learn temporal structures. The parsing process is as follows:

[0114] Call the pre-trained model weights in the deep generative model and load the initialization state parameters , execute the vector parsing process.

[0115] During the vector analysis process, first Perform position embedding to obtain a structural semantic representation sequence ,in Indicates the The embedding result of dimensions; then, the structural semantics represents the sequence Combined fault coverage task label vector , generate structure-fault correlation vector map , used to capture the prior features of structural regions and historical fault mapping.

[0116] Furthermore, the structural semantics represents the sequence Structure-fault correlation vector map Input to the multi-layer Transformer encoder for vector parsing. After completing the vector parsing, the deep generative model outputs a set of semantic attention values and position weight distribution vector , which is used to guide the construction of the access path logic graph in the next stage.

[0117] S220: Based on the vector analysis result and target fault type sample characteristics, construct an access path logic diagram for triggering the target sensitive area.

[0118] After completing the vector parsing, get the semantic attention value and position weight distribution , further combined with the structural excitation paradigm vector in the fault type sample library ,construction of a logical graph of access paths to the execution structure.

[0119] Specifically, the fault type sample library is extracted from the fault type sample library. and Matching target fault type feature subset ,The features include typical access order, fan-out path, register perturbation sequence, interleaved address mapping rules, etc.

[0120] Combined with the semantic attention value obtained from S210 , perform the initial topology extraction of the access path, The access method in is mapped to the target structure region coordinates The physical location pointed to. Based on this, the position weight distribution is used Control the segment depth, number of concurrent nodes, and address jump range of the access path to build the access path logic graph .

[0121] The access path logic diagram The system is a directed graph structure, where nodes represent access actions (such as write 0, write 1, read, precharge, and retain), edges represent timing and control dependencies, and edge weights represent metrics such as access latency, coupling interference, and logic coverage. During graph construction, the system incorporates an address sequence constraint and a bitline conflict detection module to ensure path logic executableness and target fault induction effectiveness.

[0122] The output of this step It is the direct input object for subsequent test stimulus sequence generation.

[0123] S230: Expand the access path logic diagram to generate a test intent vector Corresponding test stimulus sequence .

[0124] After building the access path logic diagram After that, the path expansion and test sequence generation process is further executed. Specifically, first based on The timing dependency constraints and access instruction classification in the graph are used to perform depth-first traversal of the graph structure, and the access nodes in the graph are linearly sorted according to the control dependency order to obtain the access path sequence. .

[0125] For each path segment in the access path sequence , the system combines the original structure sensitive area indicators and jump control parameters , generate access control blocks .

[0126] Splice all access control blocks sequentially and introduce timing boundary interpolation factors and address perturbation weight , and finally form the test stimulus sequence:

[0127]

[0128] Among them, each Represents a structured intent vector Mapping control, fault-induced template Adapted and position distribution vector A set of control instructions for constraint generation.

[0129] In this embodiment, in order to meet the test execution and response collection requirements in the subsequent step S300, the system An index identifier and a path traceability tag are embedded at the end of each control block to assist in the subsequent one-to-one mapping of response data and stimulus instructions, ensuring the traceability of the test execution path.

[0130] The sequence It will be used as input data for executing the stimulus process in S300 and used for calling the actual test task.

[0131] Through the implementation of S200 above, it is possible to Accurately drive the deep generative model, perform semantic-level modeling and access path construction on the target fault coverage pattern, and ultimately generate a test stimulus sequence with precise coverage, controllable paths, and traceable indexes. , providing highly adaptable test input support for subsequent rapid testing, fault collection and intelligent judgment, and forming a key feedforward information flow element in the AI-driven closed-loop system.

[0132] S300 , executing the test excitation sequence TES, collecting response data under the corresponding test cycle, including electrical signal data, operation timing data and operating environment parameters, and constructing a multimodal response feature set MRF.

[0133] S310: Execute the test stimulus sequence In the memory array, the voltage, current, and capacitance change values in each cycle during the test are collected to generate an electrical signal sequence .

[0134] This step receives the test stimulus sequence generated in S230 Then, the sequence is gradually applied to the target memory array through the test control engine. It is a sequence of operation instructions expanded by time step, including the operation type identifier , access address information , write / read flag and control timing parameters ,in Indicates the timing cycle of the current instruction.

[0135] During the test execution, the system Synchronous acquisition of target unit electrical parameters, including voltage values , current value and local capacitance fluctuations , generate the corresponding signal observation vector .

[0136] System for continuous The signal vectors collected in the excitation cycle are spliced to generate an electrical signal sequence , used to reflect the storage array in Dynamic electrical response characteristics under excitation.

[0137] Electrical signal acquisition construction method:

[0138]

[0139] in:

[0140] Indicates the The voltage measurement value of the target memory cell in the cycle;

[0141] Indicates the current change value on the bit line in the corresponding period;

[0142] Represents the capacitance perturbation data of the measurement point;

[0143] Indicates the total number of execution cycles of the test stimulus sequence.

[0144] This formula ensures that the collected electrical response signal has time continuity and physical meaning, providing a basis for constructing high-dimensional dynamic response characteristics, so that subsequent models can learn abnormal behavior patterns from changing trends, and is suitable for dealing with soft errors and occasional breakdown defects.

[0145] S320: Extract access operation traces from the test stimulus execution process, including access timestamps, operation types, row and column addresses, and construct operation timing sequences. ;

[0146] In this step, the system executes At the same time, the instruction execution flow is analyzed for operation traces, timing control information and spatial access paths are extracted, and timing operation sequences are generated. This sequence is used to express the timing characteristics and access logic order of the stimulus sequence at the execution level, and is the key intermediate data for the subsequent construction of the timing-response fusion model.

[0147] Specifically, the system extracts the following information fields:

[0148] Accessing the timestamp vector : Record the physical time (or system clock cycle) that each operation instruction is executed;

[0149] Operation type identification vector : Indicates that each instruction is read (R), write (W), erase (E), etc.;

[0150] Access address vector : Include row address , column address , used to indicate the spatial position of the operated unit.

[0151] After combining the above three vectors, the system constructs the operation timing sequence :

[0152] Operation timing sequence construction method:

[0153]

[0154] in:

[0155] For the The execution timestamp of the stimulus instruction;

[0156] Instruction type, the value range includes R, W, E, etc.

[0157] and are the target row and column addresses respectively.

[0158] Technical Effect: This formula establishes a mapping between the incentive flow in the physical address space and the execution timeline, provides strong timing constraints for multimodal fusion modeling, and supports path backtracking and time-synchronized mapping in subsequent graph models.

[0159] S330, based on the electrical signal sequence With the operation timing sequence , combined with real-time temperature, voltage, electromagnetic interference parameters and other operating state variables, to generate a multimodal response feature set .

[0160] After completing the electrical response data and operational behavior trajectory After the collection, the system further integrates the real-time operation state variables to generate a high-dimensional feature set. The operation state variables are collected by the environment perception unit and include:

[0161] Chip surface temperature series ;

[0162] Power supply voltage fluctuation sequence ;

[0163] Space electromagnetic interference index series .

[0164] The system uniformly models the above operating state variables as an environmental state vector set and compare it with and Fusion to form a multimodal response feature set with a unified structure .

[0165] Multimodal response feature set fusion method:

[0166]

[0167] in:

[0168] For the The electrical response characteristics within a cycle; Indicates the The voltage within a cycle, Indicates the Current in a cycle Indicates the Capacitance within a cycle;

[0169] is the operation timing field of the i-th stimulus instruction; For timestamp, For operation type, is the row and column address; among them, the i-th excitation instruction corresponds to the Cycle of excitation instructions;

[0170] is the environmental state variable of the i-th cycle; is the chip surface temperature sequence; is the power supply voltage fluctuation sequence; is the space electromagnetic interference index sequence;

[0171] For the Cyclic generated fusion response feature unit.

[0172] Technical effect: This formula realizes synchronous mapping of cross-domain data, integrates electrical signals, operational behaviors and environmental variables into a unified data structure, improves the consistency of data space, temporal resolution and input feature density, and enables subsequent graph neural network processing to have context-aware capabilities.

[0173] Traditional methods collect test responses and store them in the form of single signals, ignoring the coupling effects between operation sequences and environmental factors. This results in weak generalization of fault discrimination models and low soft error recognition rates. By introducing the above-mentioned fusion model, the system has the following advantages:

[0174] Supports graph modeling structure construction; explicitly preserves access semantics; and accurately maps the impact of process environment on fault behavior.

[0175] Through the execution of S300, the system realizes the full-link test data acquisition process from physical excitation application to multimodal response expression, and generates The feature set has high temporal resolution, high-dimensional multi-channel and cross-domain fusion characteristics, which not only improves the perception depth of the fault detection model, but also enhances the system's ability to identify complex coupled faults. The data structure has good structural scalability while maintaining temporal consistency. It is suitable for various AI discrimination architectures such as graph neural networks, causal graph modeling, and structural variation reasoning, ensuring data compatibility and feature integrity in the subsequent processing stages of the system.

[0176] S400, input the multimodal response feature set MRF into the graph neural network model, perform fault type identification and root cause reasoning, and output the fault discrimination label and reasoning path graph RPG;

[0177] S410, the multimodal response feature set Input into the graph neural network model, encode the graph structure features, and generate the fault feature graph vector .

[0178] In this step, the system receives the multimodal response feature set output by S330 , and construct the input graph structure of the graph neural network in the form of node features, and perform node feature encoding and relationship construction. Each record in Contains the following fields: Voltage , current , capacitance disturbance , timestamp , Operation Type , row and column addresses , environmental parameters .

[0179] First, the system For node features, construct input graph , where the node set , edge set It is established based on the temporal sequence and the degree of overlap of the spatial address.

[0180] Furthermore, a multi-head graph attention network (GAT) is used to fuse the embedding features of each node. The formula is as follows:

[0181] Graph node feature encoding formula:

[0182]

[0183] in:

[0184] Indicates the Layer The feature vector of each node;

[0185] Indicates The set of all nodes adjacent to a node;

[0186] For the Nodes in the layer and The attention weight of

[0187] For the The weight matrix of the layer;

[0188] is the activation function, such as ReLU or GELU.

[0189] The above feature propagation process is executed After the layer, the system obtains the feature vector set after the full image encoding , used for subsequent fault identification and cause-effect diagram construction.

[0190] In this embodiment, the graph attention mechanism can effectively mine multiple semantic relationships between nodes based on time sequence, spatial overlap, signal similarity, etc., to form graph-level fault coding features with high expressiveness, and enhance the model's perception of abnormal response patterns.

[0191] S420, the fault feature map vector Perform fault classification processing and obtain the corresponding fault type label sequence .

[0192] After completing the graph node feature representation After encoding, this step uses the fault discrimination classifier to perform label inference on each node representation vector to obtain the corresponding fault type prediction label sequence .

[0193] First, define the fault classification label set , where each Indicates a fault type, such as transient interference, stable breakdown, data retention anomaly, soft error, coupling interference, etc.

[0194] Specifically, a multi-layer perceptron (MLP) with attention enhancement is used to perform multi-classification discrimination on each node embedding vector. The formula is as follows:

[0195] Fault label prediction formula:

[0196]

[0197] in:

[0198] is the classification weight matrix;

[0199] is the bias vector;

[0200] For nodes Final graph embedding vector;

[0201] Representation node Corresponding fault type label;

[0202] Indicates that the category index with the maximum probability is selected.

[0203] The above tag sequence The output is sent to the user visual layer and the model feedback layer as the fault identification result, which is used for root cause tracing analysis and the error reverse optimization module in S500.

[0204] In S430 , it will be used as a node identification field in the path graph, and in S500 , it will also be used as a reference vector for difference calculation to constitute the model error objective function.

[0205] The fault label prediction formula maps high-dimensional graph embedding vectors to the category space, and realizes the automatic identification and quantitative classification of multiple types of memory fault phenomena while maintaining spatial semantic continuity.

[0206] S430, based on the fault feature map vector Nested path information with nodes to generate reasoning path graph , used to represent the causal path of the test stimulus triggering the fault.

[0207] In this step, after obtaining the complete graph node encoding With the corresponding label After that, the graph structure is further analyzed for causal paths to construct the reasoning path diagram during the test triggering process. .

[0208] First, extract all node pairs from the graph structure The following conditions are met:

[0209] Time sequence is established: ;

[0210] Space adjacent: and Difference less than threshold ;

[0211] The possibility of failure impact is: belong A set of possible triggering consequences (based on historical path statistics).

[0212] For node pairs that meet the above conditions, build a path edge set , and define the reasoning path diagram as follows:

[0213] Reasoning path diagram generation:

[0214]

[0215] in:

[0216] is the set of subgraph nodes containing predicted fault nodes;

[0217] A set of directed edges that satisfy the time-space-causal reasoning conditions;

[0218] Is a causal verification function used to determine the node Is it possible to affect the node .

[0219] This graph structure captures the spatiotemporal causal relationship between test stimuli and fault manifestations, supports multi-path concurrency, multi-cause and multi-effect simulation of actual storage fault logic, and is a key intermediate representation for system feedback learning and path closure.

[0220] Step S400 achieves the goal of transforming multimodal response data by introducing graph neural network structure and graph reasoning algorithm. Go to the Fault Type tab and reasoning path diagram The complete structural mapping has the following technical features and effects:

[0221] A multi-head graph attention mechanism is used to extract local abnormal features, achieving joint fault representation in multiple dimensions such as time, space, and signal strength.

[0222] Utilize graph classification mechanism to categorize complex fault phenomena and realize automatic identification of multiple types of faults;

[0223] Construct a reasoning path graph structure to model the implicit causal chain of "test stimulus-response behavior-fault type" to support subsequent optimization and deployment migration;

[0224] Improved the system's ability to perceive and respond to sporadic faults, complex soft errors, and coupling phenomena;

[0225] The above steps S100 to S400 implement a closed-loop process from structural sensitivity analysis, stimulus generation, response collection, and fault reasoning, providing causal evidence support for the model self-evolution optimization in the subsequent step S500.

[0226] S500 , calculating a feedback gradient based on a difference vector between the reasoning path graph RPG and a test excitation sequence TES, and updating weight parameters of the deep generative model.

[0227] S510: Obtain the reasoning path diagram Test stimulus sequence The feature matching deviation between them is calculated to obtain the deviation vector .

[0228] In this step, after obtaining the inference path diagram output from S400, Afterwards, the node sequence, causal edge weight relationship and corresponding fault label sequence contained in the graph are extracted The path diagram It reflects the causal triggering path of the test stimulus to the fault behavior and can be regarded as a causal chain representation of "response-reasoning".

[0229] At the same time, call the test stimulus sequence generated in step S230 , get the operation type identifier it contains , access address vector and execution timestamp , construct the incentive behavior vector sequence , where each correspond An incentive instruction Behavioral description.

[0230] To characterize the actual test path (by Definition) and system identification path (defined by Definition), constructing feature matching functions Used to measure faulty nodes With motivational instructions The path similarity and trigger correlation between them include address overlap, time alignment and operation type consistency.

[0231] Furthermore, the matching deviation vector is obtained by accumulating the feature differences , where each express Middle The error between the instruction and the corresponding node in the inference path graph. This deviation vector will be used as the target input for subsequent gradient calculations.

[0232] What you need for this step Output result for S430, Output results of S230, both of which are key structural outputs of the system; The building blocks of the loss function are introduced into the gradient propagation process in S520.

[0233] S520, based on the deviation vector Backpropagate to a specific parameter layer in the deep generative model to calculate the feedback gradient vector .

[0234] This step is to obtain the deviation vector After that, we further calculate its propagation path in the deep generative model and construct a gradient backpropagation framework based on this path to obtain the feedback gradient vector .

[0235] Specifically, we first trace back to the deep generative model architecture adopted by S200 , the model consists of multiple layers of embedding layers, Transformer attention mechanism layers, and semantic reconstruction decoders. For the output vector of each layer, the system is based on Construct hierarchical residual terms for computing local partial derivatives.

[0236] On this basis, through the chain partial derivative relationship, the error signal is fed back layer by layer, and the system obtains the corresponding feedback gradient components on each parameter layer. All components are summarized to form the gradient vector , where each Indicates the Layer Parameters Feedback correction value on .

[0237] In order to improve stability and convergence rate, the system introduces the historical gradient mean and exponentially weighted momentum coefficients , integrating historical update trends with current feedback to control the range of single-step gradient changes. Related parameter values are as follows: , , ,The data can come from the back-testing experience of existing test models or training set statistics.

[0238] S530, feedback gradient vector Perform weighted fusion, update the weight parameters in the deep generative model, and generate an optimized test generative model .

[0239] The feedback gradient vector is calculated Afterwards, the system generates a model for the original test The parameter weights are updated to form an optimized version To ensure the robustness and generalization ability of the update process, the system performs weighted fusion processing on the feedback gradients and adopts the following strategy:

[0240] Introducing the learning rate vector , each dimension To control the model The update rate of the layer;

[0241] Combined structural sensitivity vector (S120 output) as a structural sensitivity factor to weight the response of different structural layers;

[0242] Introducing target coverage vector (S220 output) serves as the semantic attention weight to ensure that the optimized model maintains semantic consistency.

[0243] Finally, all parameters are synthesized and the corresponding parameters in the original model are iteratively updated to generate the optimized model. The model will be further deployed in S600 to edge nodes or heterogeneous test platforms to support the next round of adaptive testing tasks.

[0244] By executing step S500, based on the inference graph structure ( ) and incentive strategies ( ) between the structural deviations, forming an error vector ( , and generates feedback gradients through the back-propagation mechanism ( ), and finally complete the deep generation model ( ) to the optimized version ( ) strategy iteration, providing high-quality, dynamically adjusted model parameter support for subsequent cross-platform deployment, and improving the robustness and generalization ability of the overall system.

[0245] S600: Based on the updated deep generative model and the current test platform configuration parameters, a test deployment configuration plan is constructed, and the deep generative model is migrated and deployed across platforms.

[0246] S610: Generate a model based on the optimized test Configure the hardware parameters of the test platform to build a model adaptation configuration vector .

[0247] In this step, the system first obtains the optimized test generation model updated in step S530 , the model has integrated the feedback gradient vector in S500 Sensitivity to historical structures , target fault coverage semantics And other key characteristic parameters, it has the ability to generate the optimal test strategy for the current task.

[0248] Specifically, the system reads the software and hardware configuration of the target deployment platform, including the following parameter information:

[0249] Processor architecture information (e.g., x86, ARM, RISC-V);

[0250] Memory capacity and cache level distribution;

[0251] Instruction set support (such as SIMD / NEON / AVX);

[0252] The number of parallel threads supported and the maximum model loading size;

[0253] Network connection bandwidth and edge node communication protocol stack.

[0254] Furthermore, the above information is constructed into a platform parameter representation in a dimensional vector format. . Subsequently, according to The network structure configuration (including the number of layers, number of attention heads, input and output dimensions, and parameter space occupied) in the static graph is analyzed to construct the internal structure representation of the model .

[0255] By fusion function and Perform adaptation modeling and generate model adaptation configuration vector , which represents strategies such as resource mapping, precision adjustment, computing power allocation, and channel pruning during model deployment. It will serve as the input for subsequent platform migration modules to guide the efficient adaptation of the model in heterogeneous environments.

[0256] Output from S530, for The structural abstraction Will be used as the input configuration vector of S620; parameter and It is also introduced as a reference for model behavior during the fusion process.

[0257] S620: Adapt the model to the configuration vector With the model Input into the platform migration scheduling module to complete the model migration adaptation and generate the migration model instance .

[0258] After completing the model adaptation configuration vector After construction, in this step, the system calls the platform migration scheduling module to generate the deep model Perform structural adjustments and computational graph optimization to generate migration model instances that can be executed on the target test platform .

[0259] The platform migration scheduling module includes the following core sub-functions:

[0260] Structural cutting: based on The acceptable parameter scale, delay budget and computing resource ratio specified in Channel pruning and structural quantization are performed on each Transformer sub-layer, attention head, fully connected channel, etc.

[0261] Weight reconstruction: For low-capacity platforms, some sparse structures are reconstructed using low-rank matrix approximation to ensure the stability of the basic functions of the model under volume compression.

[0262] Graph operator replacement: Based on the operator types supported by the target platform, some special activation functions and tensor operations in the original model are converted into equivalent operators that can be run on the target platform.

[0263] Finally, the adapted and translated model instance is output It has the complete functions of generating test stimulus sequences, scheduling test strategies and calling feedback data in a specified platform, and is compatible with the original model. Preserve semantic equivalence.

[0264] and Co-provided by S610, This is output in this step and loaded into the edge node or the scheduling manager as a deployment entity in S630.

[0265] S630: Migrate the model instance Deploy to the designated test platform or edge node to complete the test system configuration and prepare for a new round of test task execution.

[0266] After completing the model instance After the migration is built, the system deploys the model instance to the target test node according to the test task scheduling plan and platform deployment strategy, completing the final packaging of the system configuration. Deployment platform types include:

[0267] Embedded hardware test terminal (supports MCU / FPGA);

[0268] High-performance computing platform (CPU / GPU cluster);

[0269] Cloud task center and edge collaboration node.

[0270] During the deployment process, the system will Load it into the local model execution engine and complete the following key initialization steps:

[0271] Register the interface between the stimulus generation submodule and the response acquisition module;

[0272] Load historical test intent vector library , used to construct a new round of task seeds;

[0273] Establish a test status feedback channel with the main control scheduling platform to support closed-loop feedback path monitoring;

[0274] Initialize the output buffer to receive future generated Sequence and corresponding response data ;

[0275] Check the model version compatibility to ensure that the test strategy generation module is supported by the current node.

[0276] After the above steps are completed, the deployment node enters the standby state, waiting for the scheduling module to initiate a new round of test task instructions. As the core, we will participate in the next round of AI testing closed-loop process of "structure-incentive-response-reasoning-feedback" to achieve a systematic upgrade of the continuous testing strategy.

[0277] By executing step S600, the test generation model after feedback optimization is generated. , after parameter structure adaptation, migration scheduling and platform mapping, it is built into a platform customized version , and deployed to designated edge nodes. It has the following technical effects:

[0278] Enable seamless model migration between heterogeneous test platforms, improving system deployment flexibility;

[0279] Support based on Vectors automatically adapt platform parameters to reduce manual intervention;

[0280] Ensure semantic consistency of test strategies, applicable to test migration tasks across product generations, different process or packaging versions;

[0281] It has the ability to quickly switch test tasks and provide local execution feedback, enabling closed-loop deployment of test strategies.

[0282] The above steps S100 to S600 build a full-link intelligent testing framework from structural modeling, strategy generation, response collection, discriminant reasoning, feedback optimization and migration deployment, thereby improving the overall automation level and portability of the system.

[0283] In an embodiment of the present application, a computer-readable storage medium is also provided, which stores computer instructions. When the computer instructions stored in the computer-readable storage medium are executed by a computer device, the computer device executes the above-mentioned AI technology-based fast memory testing method.

[0284] In an embodiment of the present application, an electronic device is also provided, including: one or more processors; and a storage device for storing a computer program product of one or more instructions, which, when executed on a computer device, enables the computer device to execute the above-mentioned AI-based fast memory testing method.

[0285] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described herein are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated therein. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive).

[0286] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all such improvements and changes should fall within the scope of protection of the appended claims of the present invention.

Claims

1. A memory testing method based on AI technology, characterized in that: The following steps are involved: 1) obtaining structural parsing data and memory type description information of the memory to be tested, and generating a test intent vector for expressing the test target based on the structural parsing data and memory type description information of the memory to be tested; The structural analysis data includes the memory cell arrangement matrix, bit line word line structure and redundancy mapping relationship of the memory to be tested; 2) Taking the test intent vector as input, combined with the memory target fault mode database, inputting it into a preset deep generative model, constructing a fault coverage semantic representation, and generating a test stimulus sequence; 3) executing the test stimulus sequence, performing a multi-cycle test on the storage array, collecting electrical signal data, operation timing traces, and operating environment parameters during the test process, and forming a multimodal response feature set; 4) Inputting the multimodal response feature set into a graph neural network to perform fault type identification and causal path reasoning, generating a fault label sequence and a reasoning path graph; 5) Update the weight parameters of the deep generative model based on the feature differences between the inference path graph and the test stimulus sequence; 6) Generate test stimulus sequences based on the updated deep generative model for memory testing.

2. The memory testing method based on AI technology according to claim 1, characterized in that: The structural analysis data is obtained by hierarchically expanding the physical structure information of the memory to be tested, and constructing the memory cell arrangement matrix, bit line word line structure and redundant mapping relationship through layout structure analysis; The physical structure information includes the layout netlist, physical address mapping diagram, redundant structure configuration table, bit line layout file, and word line group structure information.

3. The memory testing method based on AI technology according to claim 1, characterized in that: The type description information includes attribute information including memory type, process node, number of stacking layers, dielectric type, and transistor type.

4. The memory testing method based on AI technology according to claim 1, characterized in that: The test intent vector for expressing the test target is generated based on the structural parsing data and memory type description information of the memory to be tested; specifically as follows: Based on the structural analysis data, key structural sensitive area features are extracted to form a structural sensitivity feature vector; based on the structural sensitivity feature vector and memory type description information, a test construction objective function is constructed to generate a test intent vector for expressing the test target.

5. The memory testing method based on AI technology according to claim 4, characterized in that: The extracting of key structural sensitive area features based on the structural analysis data to form a structural sensitivity feature vector specifically includes: Identification of process weaknesses: Identify areas prone to unstable behavior during the process, including high-density bit intersections, critical dimension error regions, and PMOS and NMOS boundary transition regions. Utilize lithography models combined with residual mapping technology to extract the coordinates of corresponding logic cells and form a set of process anomaly locations. Edge cell area extraction: locate the storage cell group at the boundary of the row and column matrix, record its redundant mapping quantity and fault history statistics, and form an edge cell feature set; Extraction of dense bit crossing areas: Counting the integration density of bit lines and word lines in the crossing area, and marking error-prone nodes based on the coupling capacitance threshold to form a set of crossing interference areas; Based on the three sets of process abnormality location set, edge unit feature set and cross-interference area set, a unified structural sensitive area feature representation tensor is constructed and the tensor is encoded into a structural sensitivity feature vector ,The structural sensitivity feature vector contains the following fields: node density statistics, ,structure type identification, fault history weight, and process anomaly probability estimation.

6. The memory testing method based on AI technology according to claim 1, characterized in that: Testing Intent Vectors The fields included are: Target access zone index , address hopping frequency control items , Fault-induced potential score , concurrent conflict warning weight .

7. The memory testing method based on AI technology according to claim 1, characterized in that: Construct fault coverage semantic representation and generate test stimulus sequence; specifically: Based on the test intent vector, drive the deep generation model, perform semantic level modeling and access path construction on the target fault coverage pattern, and generate test stimulus sequence ; Test intent vector Perform position embedding to obtain the structural semantic representation sequence, and transform the structural semantic representation sequence into Combined fault coverage task label vector , generate structure-fault correlation vector map , used to capture the prior features of the mapping between structural regions and historical faults; Representing structural semantics as a sequence Structure-fault correlation vector map Input into the deep generative model for vector parsing, and the output vector parsing result is a set of semantic attention values and position weight distribution vector ; Based on the vector analysis results and target fault type sample characteristics, construct an access path logic diagram for triggering the target sensitive area; Expand the access path logic diagram to generate the test intent vector Corresponding test stimulus sequence .

8. The memory testing method based on AI technology according to claim 1, characterized in that: The access path logic diagram for triggering the target sensitive area is constructed as follows: Get semantic attention value and position weight distribution , combined with the structural excitation paradigm vector in the fault type sample library ,construction of a logical graph of execution structure access paths; Extract the fault type sample library and the current and Matching target fault type feature subset ,The features include typical access order, fan-out path, register perturbation sequence, and interleaved address mapping rules; Combined with semantic attention value , perform the initial topology extraction of the access path, The access method in is mapped to the target structure region coordinates The physical location pointed to, based on this, using the location weight distribution Control the segment depth, number of concurrent nodes, and address jump range of the access path to build the access path logic graph ; Access path logic diagram It is a directed graph structure, in which nodes represent access actions, edges represent timing and control dependencies, and edge weights include indicators such as access delay, coupling interference, and logic coverage.

9. The memory testing method based on AI technology according to claim 7, characterized in that: The access path logic diagram is structurally expanded to generate the test intention vector Corresponding test stimulus sequence ; The details are as follows: First, based on The timing dependency constraints and access instruction classification in the graph are used to perform depth-first traversal of the graph structure, and the access nodes in the graph are linearly sorted according to the control dependency order to obtain the access path sequence. ; For each path segment in the access path sequence , the system combines the original structure sensitive area indicators and jump control parameters , generate access control blocks ,The access control block contents include address jump mode, word line selection flag, read and write control bits, and precharge cycle mask; All access control blocks are spliced together in sequence to form a test stimulus sequence: 。 10. The memory testing method based on AI technology according to claim 1, characterized in that: The multimodal response feature set is as follows: in: For the The electrical response characteristics within a cycle; Indicates the The voltage within a cycle, Indicates the Current in a cycle Indicates the Capacitance within a cycle; is the operation timing field of the i-th stimulus instruction; For timestamp, For operation type, is the row and column address; among them, the i-th excitation instruction corresponds to the Cycle of excitation instructions; is the environmental state variable of the i-th cycle; is the chip surface temperature sequence; is the power supply voltage fluctuation sequence; is the space electromagnetic interference index sequence; For the Cyclic generated fusion response feature unit.

11. The memory testing method based on AI technology according to claim 1, characterized in that: Inputting the multimodal response feature set into a graph neural network model to perform graph structure feature encoding and generate a fault feature graph vector; The fault feature map vector Perform fault classification processing and obtain the corresponding fault type label sequence ; Based on the fault feature map vector Nested path information with nodes to generate reasoning path graph , used to represent the causal path of the test stimulus triggering the fault.

12. The memory testing method based on AI technology according to claim 11, characterized in that: The fault feature map vector Nested path information with nodes to generate reasoning path graph , as follows: First, extract all node pairs from the graph structure , the node pairs satisfy the following conditions: Time sequence is established: ; Space adjacent: and The difference is less than the preset threshold ; The possibility of failure affecting: belong A set of possible triggering consequences, wherein the set of possible triggering consequences is obtained based on historical path statistics; For node pairs that meet the above conditions, build a path edge set , and define the reasoning path diagram as follows: Reasoning path diagram generation: in: is the set of subgraph nodes containing predicted fault nodes; is the set of directed edges that satisfy the inference conditions; Is a causal verification function used to determine the node Is it possible to affect the node .

13. The memory testing method based on AI technology according to claim 1, characterized in that: Based on the feature differences between the inference path graph and the test stimulus sequence, the deviation vector is calculated and back-propagated to obtain the feedback gradient and update the weights of the deep generative model; The following method is used to calculate the deviation vector: Measuring fault nodes based on inference path graphs through feature matching Stimulus instructions with test stimulus sequence The path similarity and trigger correlation between them; the characteristics include address overlap, time alignment and operation type consistency; By accumulating feature differences, we can obtain the matching deviation vector , where each in the matching deviation vector express Middle The size of the matching error between the instructions and the related nodes in the reasoning path graph.

14. The memory testing method based on AI technology according to claim 1, characterized in that: Memory testing is performed by building a model adaptation vector and generating a platform-customized model based on the updated deep generative model and the current test platform parameter configuration; The platform customized model is deployed to the target test platform or edge node, the model execution engine configuration is completed, and the adaptive execution of a new round of test tasks is realized.

15. An electronic device, characterized in that: include: one or more processors; as well as a storage device for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors are enabled to perform the method according to any one of claims 1 to 14.

16. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 14 is implemented.

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