Multi-core processor request processing method, multi-core processor, product and server

Abstract

This invention discloses a request processing method for multi-core processors, a multi-core processor, a product, and a server, relating to the field of multi-core processor technology. In this method, the master node queries a directory based on the request and obtains the query results, then responds to the request using different request-response strategies based on the query results. This uses a directory-based approach to maintain the consistency of non-inclusive shared caches, increasing the utilization of the shared cache and reducing the chip area occupied by the cache within a given cache capacity. Secondly, the non-inclusive shared cache architecture allows data to be stored simultaneously in both private and shared caches, avoiding excessive data exchange problems caused by cache swapping in exclusive architectures. It also allows the private cache to retain data not present in the shared cache, avoiding the reverse invalidation problem in inclusive models. Therefore, this method improves the utilization of shared caches, reduces data exchange volume, and lowers the maintenance cost of cache consistency.

Description

Technical Field

[0001] This invention relates to the field of multi-core processor technology, and in particular to a request processing method for a multi-core processor, a multi-core processor, a product, and a server. Background Technology

[0002] With the continuous development of computer technology, in order to reduce the latency of the Central Processing Unit (CPU) accessing memory, multiple layers of cache are set up between the processor and memory. Multi-level cache architecture can be divided into three modes: inclusive, exclusive, and non-inclusive.

[0003] In the included cache mode, different cache levels store the same data; data in a higher-level cache is guaranteed to exist in a lower-level cache, but data in a lower-level cache may not exist in a higher-level cache, leading to low utilization of lower-level cache space. In the exclusive cache mode, data in different cache levels is guaranteed to be different; the same cache copy can only be stored in a single cache level. Because data cannot coexist across multiple cache levels in exclusive mode, when the processor needs to access a block of data, it may trigger data movement between cache levels, resulting in high data exchange volume and high cache consistency maintenance costs.

[0004] Therefore, improving the utilization of low-level cache space, reducing the amount of data exchange when accessing data, and reducing the cost of cache consistency maintenance are technical problems that urgently need to be solved by people in this field. Summary of the Invention

[0005] The purpose of this invention is to provide a request processing method, a multi-core processor, a product, and a server for a multi-core processor, in order to solve the technical problems of low utilization of low-level cache space, large data exchange volume when accessing data, and high cost of cache consistency maintenance.

[0006] To address the aforementioned technical problems, this invention provides a request processing method for a multi-core processor, applied to a master node; comprising:

[0007] Get the request sent by the requesting node;

[0008] The request queries the directory and retrieves the query results; wherein each directory entry includes at least the address, data status, cache level, and the status of the private cache of the slave node; the cache level includes the level where data is stored in the shared cache, the level where data is stored in the private cache, and the level where data is stored in both the shared cache and the private cache.

[0009] If the query result is a directory not found, the target data corresponding to the request is retrieved from memory and transmitted to the private cache of the request node after passing through the shared cache, in order to respond to the request;

[0010] If the query result is a shared cache hit, the target data corresponding to the request is obtained from the shared cache, and the target data is transferred to the private cache of the request node to respond to the request;

[0011] If the query result indicates that other private caches have been hit, then the other private caches that have been hit will transfer the target data corresponding to the request to the private cache of the request node in order to respond to the request; wherein, the other private caches are all private caches except the private cache of the request node.

[0012] On the one hand, before obtaining the request sent by the requesting node, it also includes:

[0013] The requesting node determines whether its own request hits its own private cache; if so, the requesting node responds to the request using the target data corresponding to the request stored in its own private cache and ends the process; if not, it sends a request to the master node.

[0014] On the other hand, if the request is a read request, the response to the request includes:

[0015] From the moment the requesting node receives the target data from its private cache, the requesting node retrieves the target data from its own private cache within a preset time period and responds to the request using the target data.

[0016] On the other hand, after retrieving the target data corresponding to the request from memory and transmitting the target data to the private cache of the request node via a shared cache, the method further includes:

[0017] The cache hierarchy of the cache line corresponding to the address of the read request in the directory is the hierarchy where the data is stored in both the shared cache and the private cache;

[0018] Determine the target state of the private cache of the requesting node based on the request;

[0019] The state of the private cache of the request node is controlled to the target state.

[0020] On the other hand, after obtaining the target data corresponding to the request from the shared cache and transferring the target data to the private cache of the request node, the method further includes:

[0021] Change the cache hierarchy of the cache line corresponding to the address of the directory read request from the level where the data is stored in the shared cache to the level where the data is stored in both the shared cache and the private cache;

[0022] Determine the target state of the private cache of the requesting node based on the request;

[0023] The state of the private cache of the request node is controlled to the target state.

[0024] On the other hand, after the other private caches that have been hit by the control transfer the target data corresponding to the request to the private cache of the request node, the process further includes:

[0025] Keep the cache level of the cache line containing the address corresponding to the read request in the directory unchanged;

[0026] The request determines the first target state of the private cache of the requesting node, and the second target state of other private caches that are hit.

[0027] The state of the private cache of the request node is controlled to the first target state, and the state of other private caches that are hit is controlled to the second target state.

[0028] On the other hand, the request is a write request, and the target data is the write address corresponding to the write request; the response to the request includes:

[0029] The private cache of the request node is controlled to be in an exclusive state;

[0030] If the private cache of the requesting node is detected to be in an exclusive state, the requesting node is controlled to write the data corresponding to the write request to its own private cache.

[0031] On the other hand, before the request node writes the data corresponding to the write request to its own private cache, the method further includes:

[0032] If it is detected that the private cache of the requesting node is full, the requesting node is controlled to evict shared cache lines according to the least recently used strategy and the strategy of prioritizing the eviction of shared data in the private cache of the requesting node.

[0033] After evicting shared state data, the process proceeds to the step of controlling the requesting node to write the data corresponding to the write request to the requesting node's own private cache.

[0034] On the other hand, after evicting shared-state data and before proceeding to the step of controlling the requesting node to write the data corresponding to the write request to the requesting node's own private cache, the method further includes:

[0035] Obtain the relationship between the remaining space in the private cache and the space occupied by the data corresponding to the write request;

[0036] If the remaining space in the private cache is detected to be greater than or equal to the space occupied by the data corresponding to the write request, then proceed to the step of controlling the request node to write the data corresponding to the write request to the request node's own private cache.

[0037] If the remaining space in the private cache is detected to be less than the space occupied by the data corresponding to the write request, then the exclusive cache line is evicted, and the process returns to the step of obtaining the size relationship between the remaining space in the private cache and the space occupied by the data corresponding to the write request.

[0038] On the other hand, before transmitting the target data to the private cache of the requesting node, the method further includes:

[0039] If it is detected that the private cache of the requesting node is full, the requesting node is controlled to evict shared cache lines according to the least recently used strategy and the strategy of prioritizing the eviction of shared data in the private cache of the requesting node.

[0040] After evicting shared state data, obtain the size relationship between the remaining space in the private cache and the space occupied by the target data;

[0041] If the remaining space in the private cache is detected to be greater than or equal to the space occupied by the target data, then proceed to the step of transferring the target data to the private cache of the requesting node;

[0042] If the remaining space in the private cache is detected to be less than the space occupied by the target data, the exclusive cache line is evicted, and the process returns to the step of obtaining the size relationship between the remaining space in the private cache and the space occupied by the target data.

[0043] On the other hand, before transferring the target data to the shared buffer, the process also includes:

[0044] If the shared cache is detected to be full, the target cache line is evicted according to the least recently used policy and the policy of prioritizing the eviction of cache lines in the shared cache whose cache level is where the data is stored in both the shared cache and the private cache and whose data state is clean.

[0045] Change the caching hierarchy of the target cache line described in the catalog from one where data is stored in both shared and private caches to one where data is stored only in the private cache;

[0046] Proceed to the step of transferring the target data to the shared cache.

[0047] On the other hand, when multiple target cache lines are determined based on a least recently used strategy and a strategy of prioritizing the eviction of cache lines in the shared cache where the data is stored in both the shared cache and the private cache and the data is in a clean state, the eviction of target cache lines includes:

[0048] Retrieve the cache hierarchy of each target cache line recorded in the directory;

[0049] If any of the target cache lines contains a target cache line whose cache level is such that the data is stored in both the shared cache and the private cache, then evict the target cache line whose cache level is such that the data is stored in both the shared cache and the private cache.

[0050] If none of the target cache lines contain a cache level where the data is stored in both shared and private caches, then the target cache line is randomly evicted.

[0051] On the other hand, it also includes:

[0052] The address of the next request is determined based on the address corresponding to the previous request;

[0053] The system controls the shared cache to prefetch data corresponding to the address of the next request, and stores the prefetched data corresponding to the address of the next request in the shared cache.

[0054] On the other hand, before storing the data corresponding to the address of the next prefetched request in the shared cache, the process also includes:

[0055] If the shared cache is detected to be full, the target cache line is evicted according to the least recently used policy and the policy of prioritizing the eviction of cache lines in the shared cache whose cache level is where the data is stored in both the shared cache and the private cache and whose data state is clean.

[0056] Change the caching hierarchy of the target cache line described in the catalog from one where data is stored in both shared and private caches to one where data is stored in the shared cache.

[0057] Proceed to the step of storing the data corresponding to the address of the next request, which has been prefetched, in the shared cache.

[0058] On the other hand, before evicting cache lines, the following also applies:

[0059] Obtain pre-established arrays representing the data status in the private cache and arrays representing the data status in the shared cache; wherein each row in the array includes at least an address, the cache status corresponding to the address, and the number of times the address is used;

[0060] The evicted cache line includes:

[0061] Based on the array used to characterize the data situation in the private cache or the array used to characterize the data situation in the shared cache, cache lines are evicted according to the least recently used policy and the priority eviction policy.

[0062] On the other hand, if the shared cache is detected to be full, the requested content is writing data to memory, and the data corresponding to the write request is in a dirty data state, the method further includes:

[0063] Pre-configure the bypass cache corresponding to the shared cache;

[0064] Control the request node to transfer the write request data to the bypass cache corresponding to the shared cache;

[0065] The data of the write request is written back to memory through the bypass cache.

[0066] To address the aforementioned technical problems, this invention also provides a multi-core processor, comprising: a master node, slave nodes, a shared cache, memory, and private caches corresponding to each node, wherein the master node is connected to the slave nodes; the master node is used for:

[0067] Get the request sent by the requesting node;

[0068] The request queries the directory and retrieves the query results; wherein each directory entry includes at least the address, data status, cache level, and the status of the private cache of the slave node; the cache level includes the level where data is stored in the shared cache, the level where data is stored in the private cache, and the level where data is stored in both the shared cache and the private cache.

[0069] If the query result is a directory not found, the target data corresponding to the request is retrieved from memory and transmitted to the private cache of the request node after passing through the shared cache, in order to respond to the request;

[0070] If the query result is a shared cache hit, the target data corresponding to the request is obtained from the shared cache, and the target data is transferred to the private cache of the request node to respond to the request;

[0071] If the query result indicates that other private caches have been hit, then the other private caches that have been hit will transfer the target data corresponding to the request to the private cache of the request node in order to respond to the request; wherein, the other private caches are all private caches except the private cache of the request node.

[0072] To address the aforementioned technical problems, the present invention also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the request processing method of the multi-core processor described above.

[0073] To address the aforementioned technical problems, the present invention also provides a server, comprising:

[0074] memory for storing computer programs;

[0075] A processor, used to implement the steps of the above-described request processing method for a multi-core processor when executing the computer program.

[0076] To address the aforementioned technical problems, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the above-described request processing method for a multi-core processor.

[0077] The beneficial effects of this invention are as follows: First, the caching hierarchy in this method includes a hierarchy where data is stored in a shared cache, a hierarchy where data is stored in a private cache, and a hierarchy where data is simultaneously stored in both a shared cache and a private cache. This means that data can exist simultaneously in both a private cache and a shared cache, or it can be stored separately in either a private cache or a shared cache. Therefore, the method provided by this invention is based on a non-inclusive shared cache architecture. After receiving a request from a requesting node, the master node queries the directory based on the request and obtains the query results. Then, it adopts different request response strategies to respond to the request based on the query results. This uses a directory structure to maintain the consistency of the non-inclusive shared cache. Assuming the multi-core system has N cores, a private cache capacity of C1, and a shared cache capacity of C2, the ratio S1 of the number of directory entries N1 required using the directory structure to the number of entries N2 required by the inclusive shared cache architecture is: (N×C1+C2) / C2; the ratio of shared cache utilization is: C2 / (C2-N×C1); the ratio S3 of the increased overhead of the directory structure to the increased cache capacity is: (C2 / (C2-N×C1) ... 2 -(N×C1) 2 ) / C2 2Generally, the shared cache capacity is greater than the capacity of all cores' private caches, so the value of S3 is greater than 0 and less than 1, proving that the increased shared cache capacity resulting from the overhead of adding a directory is cost-effective. That is, compared to maintaining consistency with shared caches, the method provided in this invention for maintaining consistency with non-inclusive shared caches using a directory increases the utilization of shared caches and reduces the chip area occupied by the cache when the cache capacity is fixed. Secondly, since the method provided in this invention is based on a non-inclusive shared cache architecture, data can exist simultaneously in both private and shared caches, and data can also be stored separately in either the private or shared cache. Allowing data to be stored simultaneously in both private and shared caches avoids excessive data exchange issues arising from cache swapping in exclusive architectures. It also allows the private cache to retain data not present in the shared cache, avoiding the reverse invalidation problem in containment patterns. Therefore, this method improves the utilization of the shared cache and reduces the amount of data exchange, thus lowering the maintenance cost of cache consistency. Furthermore, by employing different request-response strategies to respond to requests based on query results, it achieves flexibility in request processing. When a query result is hit by another private cache, it uses a cache-to-cache data transfer method. Compared to the transfer method between two-level caches, the method provided by this invention reduces transmission latency and improves the efficiency of request response.

[0078] Furthermore, before receiving a request from a requesting node, the requesting node first determines whether its own request hits its own private cache. If so, the requesting node directly uses the target data corresponding to the request stored in its own private cache to respond to the request and ends the process. If not, it then sends the request to the master node. Since the requesting node's own private cache is closer to the requesting node than the shared cache and other private caches, when a request from a requesting node hits its own private cache, its own private cache directly responds to the request, which improves the efficiency of request response.

[0079] Starting from the moment the requesting node receives the target data from its private cache, the requesting node retrieves the target data from its own private cache within a preset time period; it then uses the target data to respond to the read request. This method implements the response to read requests.

[0080] After retrieving the target data corresponding to the request from memory and transferring it to the private cache of the request node via the shared cache, the cache level of the cache line containing the address corresponding to the read request is marked in the directory as the level at which data is stored simultaneously in the shared cache and the private cache. The state of the private cache of the request node is also updated according to the request. After retrieving the target data corresponding to the request from the shared cache and transferring it to the private cache of the request node, the cache level of the cache line containing the address corresponding to the read request in the directory is updated, and the state of the private cache of the request node is updated according to the request. After other private caches that have been hit transfer the target data corresponding to the request to the private cache of the request node, the cache level of the cache line containing the address corresponding to the read request in the directory remains unchanged, while the private cache states of the request core and the response core are changed, thus achieving cache consistency maintenance.

[0081] The system controls the private cache of the request node to be in an exclusive state. Upon detecting that the private cache of the request node is in an exclusive state, the system controls the request node to write the data corresponding to the write request to its own private cache. This ensures that data is written to the private cache only when it is in an exclusive state, thus maximizing cache consistency.

[0082] Before the requesting node writes the data corresponding to the write request to its own private cache, if the requesting node's private cache is full, then according to the least recently used strategy and the strategy of prioritizing the eviction of shared cache lines from the requesting node's own private cache, data is written to the private cache. That is, when the private cache is full, data can be written to the private cache by eviction of cache lines; shared data is evicted first because it exists in other private caches, and when a node (i.e., the core) needs the cache line again, it can still obtain a copy of the cache through cache-to-cache transmission; the data transmission latency from cache to cache is lower than the transmission latency between two levels of cache.

[0083] After evicting shared-state data, if the remaining space in the private cache is less than the space occupied by the data corresponding to the write request, then the exclusive cache line is evicted. That is, shared-state data is evicted first, and exclusive cache lines are evicted last, reserving a higher priority for exclusive data to avoid being evicted.

[0084] During a read or write operation, if the private cache is full before the target data is transferred to the requesting node's private cache, then shared cache lines are evicted according to the least recently used strategy and the strategy of prioritizing the eviction of shared data in the requesting node's own private cache. Similarly, shared data is evicted first because it still exists in other private caches. When a node (i.e., the core) needs the cache line again, it can still obtain a copy of the cache through cache-to-cache transfer. The data transfer latency between caches is lower than that between two levels of caches, and exclusive data is reserved for higher levels of protection against eviction.

[0085] Before transferring the target data to the shared cache, if the shared cache is full, the target cache line is evicted according to the least recently used strategy and the strategy of prioritizing the eviction of cache lines in the shared cache that are stored in both the shared cache and the private cache and whose data is in a clean state. This method changes the cache level of the target cache line in the directory without simultaneously evicting the data of the same cache line in the private cache. This method avoids reverse invalidation, which greatly increases memory access time. If the data to be reverse invalidated is dirty, the cache line can only be invalidated after the dirty data is written back to memory, and the shared cache can only get a copy of the data requested by the new request. Therefore, this method adopts a multi-level cache maintenance strategy to avoid reverse invalidation, which can reduce the memory access time when the cache misses.

[0086] Based on the Least Recently Used (LRU) policy and the strategy of prioritizing the eviction of cache lines in the shared cache where the data is stored in both the shared and private caches and the data is in a clean state, multiple target cache lines are identified. The cache line to be evicted is then determined by combining the cache levels recorded in the directory. Target cache lines where the data is stored in both the shared and private caches are prioritized for eviction because the shared state data still exists in other private caches. When a core needs the cache line again, it can still obtain a copy of the cache through cache-to-cache transfer.

[0087] The method determines the address of the next request based on the address corresponding to the previous request; it controls the shared cache to prefetch the data corresponding to the address of the next request and stores the prefetched data in the shared cache. By prefetching more cache line copies that meet the requirements, the number of cache misses can be reduced.

[0088] In scenarios where shared cache actively prefetches data, if the shared cache is full, the target cache line is evicted according to the least recently used strategy and a strategy that prioritizes evicting cache lines in the shared cache whose cache level contains data stored in both the shared and private caches and whose data state is clean. The cache level of the target cache line in the directory is then changed. Because the evicted data is stored in both the shared and private caches, the data remains in the private cache after the target cache line is evicted. When a core needs the cache line again, it can still obtain a copy of the cache line through cache-to-cache transfer.

[0089] Pre-established arrays characterize the data status in private caches and shared caches. When evicting a cache line, the cache line is evicted based on either the array characterizing the data status in the private cache or the array characterizing the data status in the shared cache, according to the least recently used policy and the priority eviction policy. Since each row in the array includes at least an address, the cache status corresponding to the address, and the usage count corresponding to the address, the cache status and usage count corresponding to each address can be intuitively obtained, improving the efficiency of finding the cache line to be evicted.

[0090] When the shared cache is full, requests to write dirty data to memory are handled by a write-back path from the private cache to the bypass cache and back to memory. The bypass cache avoids the shared cache being passively replaced when it is full due to active write-backs from the private cache, thus reducing the impact of the private cache on the shared cache.

[0091] In addition, the present invention also provides a multi-core processor, a computer program product, a server, and a computer-readable storage medium, which have the same or corresponding technical features as the request processing method of the multi-core processor mentioned above, and have the same effect. Attached Figure Description

[0092] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0093] Figure 1 A schematic diagram of an eight-core, two-level cache system architecture provided in an embodiment of the present invention;

[0094] Figure 2 A flowchart illustrating a request processing method for a multi-core processor, provided as an embodiment of the present invention;

[0095] Figure 3 A schematic diagram of a catalog entry provided for an embodiment of the present invention;

[0096] Figure 4 A schematic diagram of a private cache tag array provided in an embodiment of the present invention;

[0097] Figure 5 A schematic diagram of a shared cache tag array provided in an embodiment of the present invention;

[0098] Figure 6 A schematic diagram of a directory array provided in an embodiment of the present invention;

[0099] Figure 7 This is a structural diagram of a server provided in an embodiment of the present invention. Detailed Implementation

[0100] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0101] The core of this invention is to provide a request processing method for a multi-core processor, a multi-core processor, a product, and a server to solve the technical problems of low utilization of low-level cache space, large data exchange volume when accessing data, and high cost of cache consistency maintenance.

[0102] With the continuous development of computer technology, processor performance has significantly improved, while the growth in main memory access speed has lagged behind. This means that the processor's computing power far exceeds its speed of retrieving data from memory, leading to a widening performance gap between the processor and memory, resulting in the "memory wall" problem. To address this problem, multi-level caching technology was introduced, deploying multiple caches at different levels to improve data access speed and efficiency. Setting up multiple layers of cache between the processor and memory reduces the latency of CPU accessing memory. The closer the cache is to the CPU, the smaller its capacity, the faster the access speed, and the higher the cost. Multi-level caching architectures can be divided into three modes: containment mode, exclusive mode, and non-containment mode. In containment mode, different levels of cache store the same data; data in the upper-level cache must exist in the lower-level cache, but data in the lower-level cache may not exist in the upper-level cache, leading to low utilization of lower-level cache space. In exclusive mode, the data exchange volume is large, and the cost of maintaining cache consistency is high. Considering the flexibility of non-containment mode, data in the upper-level cache may or may not be in the lower-level cache; that is, it does not strictly require whether data in different levels of cache is contained. Therefore, this invention uses a multi-level caching architecture based on a non-inclusive mode to handle requests. The following description uses an eight-core, two-level caching system architecture as an example to illustrate the multi-core processing system provided by this invention. Figure 1 This is a schematic diagram of an eight-core, two-level cache system architecture provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the eight cores are designated as Core 0, Cores 1 through 7, and the two cache levels are Level 1 (L1) and Level 2 (L2). The Level 1 cache is the cache corresponding to each core, also known as a private cache. Each core has its own Level 1 cache controller, Level 1 cache instructions, and Level 1 cache data. The Level 2 cache is a shared cache. A corresponding Level 2 cache controller exists for each Level 2 cache. Memory has a corresponding memory controller, and the Level 2 cache controller is connected to the memory controller. The Level 1 and Level 2 caches operate in a non-inclusive mode. It is worth noting that this invention is not limited to the number of cache levels; it can be two, three, or four levels, as long as the shared last-level cache is a non-inclusive shared architecture. The cache architecture between other levels can be chosen arbitrarily. The shared cache described in this invention is the shared last-level cache (LLC).

[0103] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Figure 2 This is a flowchart illustrating a request processing method for a multi-core processor, provided in an embodiment of the present invention. This method is applied to a master node. It should be noted that both the master node and slave node are processor cores. The selection of the master node is not limited and is determined based on actual circumstances. The method includes:

[0104] S10: Get the request sent by the requesting node.

[0105] A requesting node can be either a master node or a slave node. The request can be a read request or a write request. Since a requesting node's own private cache is closer to the requesting node than shared caches or other private caches, to improve request response efficiency, before retrieving the request sent by the requesting node, the process includes: the requesting node determining whether its own request hits its own private cache; if so, the requesting node responds to the request using the target data corresponding to the request stored in its own private cache and ends the process; if not, it sends a request to the master node, which then receives the request.

[0106] It should be noted that when determining whether a request hits the cache, since the request carries the requested address and the cache also contains the address corresponding to the stored data, if the requested address can be found in the address corresponding to the stored data, then the request hits the cache; otherwise, the request misses the cache.

[0107] S11: Query the directory according to the request and obtain the query results.

[0108] Each directory entry includes at least the address, data status, cache hierarchy, and the status of the slave node's private cache; the cache hierarchy includes the hierarchy where data is stored in the shared cache, the hierarchy where data is stored in the private cache, and the hierarchy where data is stored in both the shared cache and the private cache.

[0109] In a shared last-level cache in a non-containment architecture, a directory is used to maintain consistency between the last-level cache and its parent cache. Figure 3 A schematic diagram of a directory entry provided in an embodiment of the present invention, such as... Figure 3As shown, there are N private caches. Each directory entry contains an address, whether it is exclusive (occupying 1 bit, 1 indicates exclusive, 0 indicates shared), cache level (occupying 2 bits, 01 indicates the data is in the last-level cache (i.e., shared cache), 10 indicates the data is in the private cache, 11 indicates the data exists in both the last-level cache and the private cache), whether the last-level cache is dirty (occupying 1 bit, 1 indicates dirty data, 0 indicates clean data), and N (N is the number of cores) private cache states (occupying 2 bits, the number of bits depends on the consistency protocol used). For example, address xxxx000 is dirty data, the data is in the last-level cache, and all private caches are in an invalid state (represented as state I); address xxxx001 is clean data, the data is in a private cache, the states of private cache 1 and private cache 2 are both in a shared clean state (represented as state SC), and the state of private cache N is invalid; address xxxx111 is dirty data, the data exists in both the last-level cache and the private cache, the state of private cache 1 is exclusive (represented as state U), and the states of other private caches are invalid.

[0110] The request includes an address, and the directory also records the address, cache level, and private cache status. Therefore, the directory can be queried to determine how the request will be responded to.

[0111] S12: Respond to the request with different strategies based on the query results.

[0112] Step S12 specifically includes:

[0113] S120: If the query result is a directory not found, retrieve the target data corresponding to the request from memory and transmit the target data to the private cache of the request node after passing through the shared cache, in order to respond to the request.

[0114] S121: If the query result is a shared cache hit, then retrieve the target data corresponding to the request from the shared cache and transfer the target data to the private cache of the request node to respond to the request.

[0115] S122: If the query result is a hit in another private cache, then the other private cache that is hit will transfer the target data corresponding to the request to the private cache of the request node in order to respond to the request.

[0116] Among them, other private caches are all private caches except for the private cache of the request node.

[0117] It's important to note that when the request is a read request, the target data corresponds to the data itself; when the request is a write request, the target data corresponds to the address of the write request. If the directory is not found, the target data corresponding to the request is retrieved from memory and first transferred to the shared cache, then from the shared cache to the request node's private cache to respond to the request. If the shared cache is hit, the target data corresponding to the request is retrieved from the shared cache and transferred to the request node's private cache to respond to the request. If other private caches are hit, the other hit private caches (the cores corresponding to the other hit private caches are called response cores) transfer the target data to the request node's private cache to respond to the request.

[0118] Once the target data is received in the private cache of the requesting node, if it is a read request, the response request includes:

[0119] Starting from the moment the requesting node receives the target data from its private cache, the requesting node retrieves the target data from its own private cache within a preset time period and responds to the request using the target data.

[0120] There is no limit to the preset duration; it is determined based on the actual situation.

[0121] To maintain cache consistency, after retrieving the target data corresponding to the request from memory and transferring the target data to the private cache of the request node via the shared cache, the following steps are also included:

[0122] The cache hierarchy of the cache line corresponding to the address of the read request in the directory is the hierarchy where the data is stored in both the shared cache and the private cache;

[0123] Determine the target state of the private cache of the requesting node based on the request;

[0124] The state of the private cache of the control request node is set to the target state.

[0125] If the request is in SC state, then the state of the private cache of the requesting node will be changed to SC state.

[0126] After retrieving the target data corresponding to the request from the shared cache and transferring the target data to the private cache of the request node, the process also includes:

[0127] Change the cache hierarchy of the cache line corresponding to the address of the directory read request from the level where the data is stored in the shared cache to the level where the data is stored in both the shared cache and the private cache;

[0128] Determine the target state of the private cache of the requesting node based on the request;

[0129] The state of the private cache of the control request node is set to the target state.

[0130] After other private caches that have been hit control the transfer of the target data corresponding to the request to the private cache of the request node, the following steps are also included:

[0131] Keep the cache level of the cache line containing the address corresponding to the read request in the directory unchanged;

[0132] Determine the first target state of the private cache of the requesting node, and the second target state of other private caches that are hit, based on the request.

[0133] The state of the private cache of the request node is controlled as the first target state, and the state of other private caches that are hit is controlled as the second target state.

[0134] If the response core is core 2 and the request core is core 1, and core 2 is in state U, and core 1 is currently in state I, and core 1 requests state U, then core 1 will be changed from state I to state U, and core 2 will be changed from state U to state I.

[0135] The above described the process of handling read requests. The following section will reiterate the entire process of reading request processing. The entire process of handling a read request includes:

[0136] 1. When the kernel initiates a read request and the private cache is hit, the private cache directly replies to the kernel;

[0137] 2. When a read request initiated by the kernel misses the private cache, the read request is sent to the directory to check if any other private cache or last-level cache hits it. If all misses occur, a data copy is retrieved from memory and transferred to the LLC and private cache. The cache level of this cache line is marked as 11 in the directory, and the private cache state of the request kernel is set. If a hit occurs in the LLC, the data copy is transferred to the private cache corresponding to the request kernel, the cache level is changed from 01 to 11, and the private cache state of the request kernel is set. If a hit occurs in another private cache, the data copy is directly transferred to the kernel that initiated the request via cache-to-cache transfer. The cache level remains unchanged, but the private cache states of the request kernel and response kernel are changed.

[0138] The following explains the processing of write requests. The request is a write request, and the target data is the write address corresponding to the write request; the response request includes:

[0139] The private cache of the control request node is in an exclusive state;

[0140] If the state of the private cache of the requesting node is detected to be exclusive, the requesting node is controlled to write the data corresponding to the write request to its own private cache.

[0141] During the write request processing, after the write request core's private cache obtains exclusive status, it directly writes the data to the private cache, adopting a write-back strategy to reduce the operation of writing data back to memory.

[0142] The entire process of writing a request includes:

[0143] 1. If the requesting node's own private cache is hit, then the data is written to its own private cache;

[0144] 2. If the directory is not hit, the data is retrieved from memory, the private cache of the request node acquires exclusive access, and the data is written to the cache. If the shared cache is hit, the data corresponding to the write request address in the shared cache is read into the private cache of the write request core and acquires exclusive access. The data corresponding to the write request is written to the private cache corresponding to the write request core. If other private caches are hit, the data is written to its own private cache after other private caches become invalid.

[0145] During request processing, there may be situations where the private cache is full and / or the shared cache is full. In such cases, in order to ensure that data can be written to the private or shared cache, cache lines are evicted so that new data can be written to the cache.

[0146] The following section explains how to handle situations where the private cache is full.

[0147] Specifically, in one implementation, before the control request node writes the data corresponding to the write request to the request node's own private cache, the method further includes:

[0148] If it is detected that the private cache of the requesting node is full, control the requesting node to evict shared cache lines according to the Least Recently Used (LRU) policy and the policy of prioritizing the eviction of shared cache lines in the private cache of the requesting node itself.

[0149] After evicting shared-state data, the process moves to the step where the control request node writes the data corresponding to the write request to its own private cache.

[0150] In practice, after evicting shared-state data, the remaining space in the private cache may be less than the space occupied by the data corresponding to the write request. Similarly, to ensure that data can be written to the private cache, after evicting shared-state data and before the step of controlling the request node to write the data corresponding to the write request to the request node's own private cache, the following steps are also included:

[0151] Get the relationship between the remaining space in the private cache and the space occupied by the data corresponding to the write request;

[0152] If the remaining space in the private cache is detected to be greater than or equal to the space occupied by the data corresponding to the write request, then the step of controlling the request node to write the data corresponding to the write request to the request node's own private cache is entered.

[0153] If the remaining space in the private cache is detected to be less than the space occupied by the data corresponding to the write request, the exclusive cache line is evicted, and the step of obtaining the size relationship between the remaining space in the private cache and the space occupied by the data corresponding to the write request is returned.

[0154] In this method, before the requesting node writes the data corresponding to the write request to its own private cache, if the requesting node's private cache is full, then according to the least recently used strategy and the strategy of prioritizing the eviction of shared cache lines from the requesting node's own private cache, shared cache lines are evicted. Only then is data written to the private cache. That is, when the private cache is full, eviction of cache lines ensures that data can be written to the private cache; shared data is evicted first because it still exists in other private caches, and when a node (i.e., the core) needs the cache line again, it can still obtain a copy of the cache through cache-to-cache transmission; the data transmission latency from cache to cache is lower than the transmission latency between two levels of cache. After evicting shared data, if it is detected that the remaining space in the private cache is less than the space occupied by the data corresponding to the write request, then the exclusive cache line is evicted. That is, shared data is evicted first, and exclusive cache lines are evicted last, reserving a higher priority for exclusive data to not be evicted.

[0155] In another implementation, the method further includes: before transmitting the target data to the requesting node's private cache.

[0156] If it is detected that the private cache of the requesting node is full, control the requesting node to evict shared cache lines according to the least recently used policy and the policy of prioritizing the eviction of shared data in the private cache of the requesting node itself.

[0157] After evicting shared-state data, obtain the size relationship between the remaining space in the private cache and the space occupied by the target data;

[0158] If the remaining space in the private cache is detected to be greater than or equal to the space occupied by the target data, then proceed to the step of transferring the target data to the private cache of the requesting node;

[0159] If the remaining space in the private cache is detected to be less than the space occupied by the target data, the exclusive cache line is evicted, and the step of obtaining the size relationship between the remaining space in the private cache and the space occupied by the target data is returned.

[0160] During the reading or writing process, before the target data is transmitted to the private cache of the requesting node, the effect of evicting cache lines after the private cache is full is the same as the effect of the above embodiment, and will not be repeated here.

[0161] To help those skilled in the art better understand the handling method for when the private cache is full, the handling method for when the private cache is full will be explained again below.

[0162] When a private cache is full and new cache line data needs to be stored, while following the LRU cache replacement algorithm, shared state data is evicted first, because shared state data still exists in other private caches. When a core needs the cache line again, it can still obtain the cache copy through cache-to-cache transfer. The data transfer latency between caches is lower than the transfer latency between two levels of caches. Finally, exclusive cache lines are evicted to reserve higher privileges for exclusive data not to be evicted.

[0163] Secondly, the handling method when the shared cache is full will be explained.

[0164] Specifically, in one embodiment, before transferring the target data to the shared buffer, the method further includes:

[0165] If the shared cache is detected to be full, the target cache line is evicted according to the least recently used policy and the policy of prioritizing the eviction of cache lines in the shared cache whose cache level is where the data is stored in both the shared cache and the private cache and whose data state is clean.

[0166] Change the caching hierarchy of target cache lines in the directory from one where data is stored in both shared and private caches to one where data is stored only in the private cache.

[0167] Proceed to the step of transferring the target data to the shared cache.

[0168] In practice, based on the least recently used strategy and the strategy of prioritizing the eviction of cache lines in the shared cache that are stored in both the shared and private caches and whose data is in a clean state, multiple target cache lines may be identified. In order to evict the appropriate target cache lines, the cache level of each target cache line recorded in the directory is obtained in the implementation.

[0169] If any of the target cache lines contains a target cache line whose cache level is such that the data is stored in both the shared cache and the private cache, then evict the target cache line whose cache level is such that the data is stored in both the shared cache and the private cache.

[0170] If none of the target cache lines contain a cache level where the data is stored in both shared and private caches, then the target cache line is randomly evicted.

[0171] When the shared cache is full and new cache line data needs to be stored, while following the LRU cache replacement algorithm, the cache line with cache level 11 and that is clean is evicted first, and the cache level of that cache line in the directory is changed to 10. It is not necessary to evict the same cache line in the private cache at the same time. This method can avoid reverse invalidation, which will greatly increase memory access time. If the data to be reverse invalidated is dirty, the cache line can only be invalidated after the dirty data is written back to memory, and the LLC can only get the data copy of the new request. Therefore, this architecture adopts a multi-level cache maintenance strategy to avoid reverse invalidation, which can reduce the memory access time when the cache misses.

[0172] To improve the probability of cache hits, multi-core processors also include the following request processing methods:

[0173] The address for the next request is determined based on the address corresponding to the previous request;

[0174] Control the shared cache to prefetch the data corresponding to the address of the next request, and store the prefetched data corresponding to the address of the next request in the shared cache.

[0175] If the current request is for address 01, the next request might be for address 02. Therefore, the data corresponding to address 02 is pre-fetched and placed in the shared cache. This method pre-fetches more cache line copies that meet the requirements by placing the data for the next request in the shared cache based on the address of the current request, thus reducing the number of cache misses.

[0176] In LLC (Limited Locked Cache) proactive data prefetching scenarios, the shared cache may become full during the writing process. To ensure data is written to the shared cache, before storing the data corresponding to the address of the next prefetched request in the shared cache, the following steps are also included:

[0177] If the shared cache is detected to be full, the target cache line is evicted according to the least recently used policy and the policy of prioritizing the eviction of cache lines in the shared cache whose cache level is where the data is stored in both the shared cache and the private cache and whose data state is clean.

[0178] Change the caching hierarchy of target cache lines in the directory from one where data is stored in both shared and private caches to one where data is stored only in the shared cache.

[0179] Proceed to the step of storing the data corresponding to the address of the next request, which has been prefetched, in the shared cache.

[0180] In this method, if LLC actively prefetches data, it does not need to transfer the data to the private cache; it only needs to be stored in the last-level cache. Data marked as cache level 01 and evicted from cache level 11 remains in the private cache. By prefetching more cache line copies that meet the requirements, the number of cache misses can be reduced. Therefore, prioritizing the eviction of data at cache level 11 can fully utilize the capacity of the multi-level cache, shorten the cache miss time, and reduce the number of cache misses.

[0181] To improve the efficiency of finding the cache line to be evicted, the following steps are included before evicting the cache line:

[0182] Obtain a pre-established array representing the data status in the private cache and an array representing the data status in the shared cache; wherein each row in the array includes at least an address, the cache status corresponding to the address, and the usage count corresponding to the address (i.e., the least recently used value (LRU value)).

[0183] Evicting cache lines includes:

[0184] Evict cache lines based on an array used to characterize the data situation in a private cache or an array used to characterize the data situation in a shared cache, and according to a least recently used policy and a priority eviction policy.

[0185] The methods for evicting cache lines based on the least recently used policy and the priority eviction policy have been described in detail above and will not be repeated here.

[0186] When the shared cache is full, a request writes dirty data to memory. When a private cache's active write-back causes the LLC to become full, the LLC is passively replaced, meaning the private cache affects the shared cache. To reduce the impact of the private cache on the shared cache, in implementation, when the shared cache is detected to be full, the requested content is writing data to memory, and the data corresponding to the write request is in a dirty state, the method further includes:

[0187] Pre-configure the bypass cache corresponding to the shared cache;

[0188] The control request node transfers the write request data to the bypass cache corresponding to the shared cache;

[0189] The data for write requests is written back to memory via a bypass cache.

[0190] like Figure 1In this section, a corresponding bypass cache is set up for the second-level cache. A bypass cache is designed for the shared last-level cache to be used when the LLC is full and the private cache initiates a dirty data write-back to memory. The dirty data is written back to memory via the write-back path from the private cache to the bypass cache and then to memory. The bypass cache can avoid passive cache replacement of the LLC when it is full due to the private cache's active write-back, reducing the impact of the private cache on the shared cache.

[0191] The method provided by this invention maintains the consistency of multi-level caches in a non-inclusive architecture by using a directory approach. This marks the cache level where data resides, allowing data to exist simultaneously in both private and shared caches, or to be stored separately in either a private or shared cache. Allowing data to reside in both private and shared caches avoids excessive data exchange issues caused by cache swapping in a dedicated architecture. It also allows the private cache to retain data not present in the shared cache, avoiding the reverse invalidation problem in an inclusive architecture. Furthermore, while using a directory approach to maintain the consistency of non-inclusive shared caches incurs directory overhead compared to maintaining the consistency of inclusive shared caches, it increases the utilization rate of the shared last-level cache and reduces the chip area occupied by the cache within a given cache capacity. Assuming the multi-core system has N cores, a private cache capacity of C1, and a shared cache capacity of C2, the ratio S1 of the number of directory entries required using the directory approach (N1) to the number of entries required by the included shared cache architecture (N2) is: (N×C1+C2) / C2; the ratio of shared cache utilization is: C2 / (C2-N×C1); the ratio S3 of the overhead of the directory approach to the increase in cache capacity is: (C2) / (C2-N×C1 ... 2 -(N×C1) 2 ) / C2 2 Generally, the shared cache capacity is greater than the capacity of all core private caches. Therefore, the value of S3 is greater than 0 and less than 1, proving that the increased shared cache capacity resulting from the increased overhead of the directory is cost-effective. The specific resources occupied by the directory and the increased last-level cache capacity need to be calculated based on the address width and the size of the private cache and the shared last-level cache.

[0192] The following continues with Figure 1 Taking the eight-core, two-level cache system shown as an example, this illustrates how the method provided in this invention increases the utilization of the shared last-level cache. The eight-core system has a 32-bit address width and an addressable range of 4GB. The system architecture diagram is shown above. Figure 1As shown, in the two-level cache system, the L1 and L2 caches operate in a non-inclusive mode. L1 is a private cache, divided into a data cache and an instruction cache, each 32KB in size. L2 is a shared cache, 2MB in size, with each cache line being 64 bytes. Using the non-inclusive last-level cache of this invention, the available space for the last-level cache is 2MB, requiring 40960 directory entries ((64KB×8 + 2MB) / 64Byte=40960). Each directory entry needs to record a 26-bit address, a 1-bit dirty flag, a 2-bit cache level flag, and a 2×8-bit cache status flag. Each entry is 45 bits, and the directory occupies a total of 225KB for storage. If the two-level cache architecture is in an inclusive mode, the required number of directory entries is 32768 (2MB / 64Byte=32768). Each directory entry, excluding the cache level flag, requires 43 bits, and the directory requires 172KB of resources for storage. Compared to the included mode, the non-included mode requires an additional 53KB of storage resources to store the directory, while the last-level cache can utilize up to 512KB of resources (assuming that all cache lines in the private cache are different and have data copies in the shared cache). This invention uses 2.5% of the resources and increases the space utilization of the last-level cache by 34%.

[0193] Figure 4 This is a schematic diagram of a private cache tag array provided in an embodiment of the present invention. The tag array is also known as a tag array. Figure 4The table only shows the status bits required for this invention; other status bits are not listed. The status of address xxxx000 is Exclusive Dirty State (UD), with a Least Recently Used (LRU) value of 6; the status of address xxxx001 is Shared Clean State (SC), with a Least Recently Used (LRU) value of 5; the status of address xxxx010 is Shared Dirty State (SD), with a Least Recently Used (LRU) value of 4; the status of address xxxx011 is Exclusive Clean State (UC), with a Least Recently Used (LRU) value of 3; the status of address xxxx100 is Shared Clean State (SC), with a Least Recently Used (LRU) value of 2; the status of address xxxx101 is Exclusive Clean State (UC), with a Least Recently Used (LRU) value of 1; the status of address xxxx110 is Exclusive Clean State (UC), with a Least Recently Used (LRU) value of 5; and the status of address xxxx111 is Shared Clean State (SC), with a Least Recently Used (LRU) value of 1. Assuming Core 1's private cache is full, Core 1 initiates a read request for address xxx1000. L1 cache misses, and the request is sent to the directory. The directory shows the data copy is in L2's shared cache. L2 transfers the data to L1's cache, but L1's cache is full, requiring the eviction of a cache line to store the new data. According to the LRU rule, caches with smaller LRU values ​​are evicted first. This invention proposes, while satisfying the LRU rule, prioritizing the replacement of shared-state data. Figure 4 In the scenario shown, both xxxx101 and xxxx111 have an LRU value of 1. xxxx101 is in state UC, and xxxx111 is in state SC. Therefore, the cache line for xxxx111 is evicted first to store a cache copy of xxx1000. Subsequently, when both the L1 and L2 caches are full, and core 1 initiates a write-back request for address xxxx000, which is in state UD and needs to be written back to memory, the data is transferred to the bypass cache of the L2 cache, and then written back to memory from the bypass cache, avoiding passive replacement of the shared L2 cache.

[0194] Figure 5 This is a schematic diagram of a shared cache tag array provided in an embodiment of the present invention. When the system runs to... Figure 5 As shown, the shared cache is full. Core 1 initiates a read request for address xxx1111. Both L1 and L2 caches miss, so a cache copy needs to be retrieved from memory. This requires evicting a cache line from the shared cache to store the data copy for address xxxx1111. The LRU values ​​for addresses xxxx100 and xxxx110 in the shared cache are both 1, and both are clean cache lines. Therefore, it is necessary to combine the cache hierarchy recorded in the directory to make a judgment. Figure 6 This invention provides a schematic diagram of a directory array. (See diagram below.) Figure 6As shown, the cache level of address xxxx100 is 01, and the cache level of address xxxx110 is 11. Therefore, the cache line of address xxxx110 will be evicted first to store the data copy of address xxx1111.

[0195] The method provided by this invention makes full use of the capacity of multi-level cache, improves the utilization rate of shared last-level cache, and optimizes the memory access process of multi-core system.

[0196] The request processing method for a multi-core processor was described above. This embodiment also provides a multi-core processor, including: a master node, slave nodes, a shared cache, memory, and a private cache corresponding to each node. The master node is connected to the slave nodes. The master node is used for:

[0197] Get the request sent by the requesting node;

[0198] The system queries the directory based on the request and retrieves the query results. Each directory entry includes at least the address, data status, cache level, and the status of the private cache of the slave node. The cache level includes the level where data is stored in the shared cache, the level where data is stored in the private cache, and the level where data is stored in both the shared cache and the private cache.

[0199] If the query result is a directory not found, the target data corresponding to the request is retrieved from memory and then transmitted to the private cache of the requesting node after passing through the shared cache, in order to respond to the request;

[0200] If the query result is a shared cache hit, the target data corresponding to the request is retrieved from the shared cache and the target data is transferred to the private cache of the request node to respond to the request;

[0201] If the query result indicates a hit in another private cache, then the other private cache that hits the query will transfer the target data corresponding to the request to the private cache of the requesting node in response to the request; where other private caches are all private caches except the private cache of the requesting node.

[0202] The slave node is used to send requests and respond to requests based on the target data in its own private cache. When sending a read request, it responds to the request using the target data in its own private cache; when sending a write request, it writes the data to its own private cache after it has been put into exclusive use.

[0203] The multi-core processor provided in this embodiment has the same or corresponding technical features as the request processing method of the multi-core processor described above, and will not be repeated here. The effect is the same as above.

[0204] In the above embodiments, the request processing method for multi-core processors has been described in detail. This invention also provides embodiments of a request processing apparatus for multi-core processors and a computer-readable storage medium. It should be noted that this invention describes the apparatus embodiments from two perspectives: one based on functional modules, and the other based on hardware.

[0205] The request processing apparatus for a multi-core processor provided in this embodiment of the invention, based on the perspective of functional modules, includes:

[0206] The first acquisition module is used to acquire requests sent by the requesting node;

[0207] The query and retrieval module is used to query the directory based on the request and retrieve the query results; each directory entry includes at least the address, data status, cache level, and the status of the private cache of the slave node; the cache level includes the level where data is stored in the shared cache, the level where data is stored in the private cache, and the level where data is stored in both the shared cache and the private cache.

[0208] The first acquisition and transmission module is used to acquire the target data corresponding to the request from memory and transmit the target data to the private cache of the request node after passing through the shared cache if the query result is a directory not found, in order to respond to the request.

[0209] The second acquisition and transmission module is used to acquire the target data corresponding to the request from the shared cache if the query result is a shared cache hit, and transmit the target data to the private cache of the request node to respond to the request.

[0210] The first control module is used to control other private caches to transmit the target data corresponding to the request to the private cache of the request node in order to respond to the request if the query result is a hit in other private caches; wherein, other private caches are all private caches except the private cache of the request node.

[0211] In some embodiments, the request is a read request, and the request processing apparatus of the multi-core processor includes a response module for responding to the request.

[0212] The response module specifically includes:

[0213] The response submodule is used to retrieve the target data from the private cache of the requesting node within a preset time period, starting from the time the requesting node receives the target data; and then responds to the request using the target data.

[0214] In some embodiments, the request processing apparatus for a multi-core processor further includes:

[0215] The tagging module is used to mark the cache level of the cache line where the address corresponding to the read request is located in the directory as the level where the data is stored in both the shared cache and the private cache;

[0216] The first determining module is used to determine the target state of the private cache of the requesting node based on the request.

[0217] The second control module is used to control the state of the private cache of the request node to the target state.

[0218] In some embodiments, the request processing apparatus for a multi-core processor further includes:

[0219] The first modification module is used to change the cache hierarchy of the cache line containing the address corresponding to the read request in the directory from the level where the data is stored in the shared cache to the level where the data is stored in both the shared cache and the private cache.

[0220] The second determining module is used to determine the target state of the private cache of the requesting node based on the request.

[0221] The third control module is used to control the state of the private cache of the request node to the target state.

[0222] In some embodiments, the request processing apparatus for a multi-core processor further includes:

[0223] The preservation module is used to keep the cache level of the cache line corresponding to the address of the read request in the directory unchanged;

[0224] The third determination module is used to determine the first target state of the private cache of the requesting node and the second target state of other private caches that are hit, based on the request.

[0225] The fourth control module is used to control the state of the private cache of the request node to the first target state, and to control the state of other private caches that are hit to the second target state.

[0226] In some embodiments, the request is a write request, and the response module specifically includes:

[0227] The fifth control module is used to control the private cache of the request node to be in an exclusive state;

[0228] The sixth control module is used to control the request node to write the data corresponding to the write request to its own private cache when the private cache of the request node is detected to be in an exclusive state.

[0229] In some embodiments, the request processing apparatus for a multi-core processor further includes:

[0230] The seventh control module is used to control the request node to evict shared cache lines according to the least recently used strategy and the strategy of prioritizing the eviction of shared cache lines in the request node's own private cache when the private cache of the request node is detected to be full.

[0231] After the shared state data is evicted, the sixth control module is triggered.

[0232] In some embodiments, the request processing apparatus for a multi-core processor further includes:

[0233] The third acquisition module is used to obtain the size relationship between the remaining space of the private cache and the space occupied by the data corresponding to the write request;

[0234] The first detection and triggering module is used to trigger the sixth control module if it detects that the remaining space of the private cache is greater than or equal to the space occupied by the data corresponding to the write request.

[0235] The first detection and eviction module is used to evict the exclusive cache line if it detects that the remaining space of the private cache is less than the space occupied by the data corresponding to the write request, and then return to trigger the third retrieval module.

[0236] In some embodiments, the request processing apparatus for a multi-core processor further includes:

[0237] The eighth control module is used to control the request node to evict shared cache lines according to the least recently used strategy and the strategy of prioritizing the eviction of shared cache lines in the request node's own private cache when the private cache of the request node is detected to be full.

[0238] The fourth acquisition module is used to obtain the size relationship between the remaining space of the private cache and the space occupied by the target data after the shared state data is evicted.

[0239] The second detection and triggering module is used to trigger the transmission module in the second acquisition and transmission module if the remaining space of the private cache is detected to be greater than or equal to the space occupied by the target data.

[0240] The second detection and eviction module is used to evict exclusive cache lines and trigger the fourth retrieval module if the remaining space of the private cache is less than the space occupied by the target data.

[0241] In some embodiments, the request processing apparatus for a multi-core processor further includes:

[0242] The first eviction module is used to evict the target cache line when the shared cache is detected to be full, based on the least recently used policy and the policy of prioritizing the eviction of cache lines in the shared cache whose cache level is the same as that of data stored in both the shared cache and the private cache, and whose data state is clean.

[0243] The second modification module is used to change the caching hierarchy of the target cache line in the directory from a hierarchy where data is stored in both shared and private caches to a hierarchy where data is stored in the private cache.

[0244] The triggering module is used to trigger the transmission module in the first acquisition and transmission module; the first acquisition and transmission module is used to transmit the target data to the shared cache.

[0245] In some embodiments, the request processing apparatus of a multi-core processor includes a second eviction module for eviction of a target cache line.

[0246] The second expulsion module includes:

[0247] The fifth acquisition module is used to acquire the cache level of each target cache line recorded in the directory;

[0248] The first eviction submodule is used to evict the target cache line whose cache level is both shared cache and private cache if there is a target cache line among all target cache lines whose cache level is both shared cache and private cache.

[0249] The second eviction submodule is used to randomly evict target cache lines if none of the target cache lines contain target cache lines whose cache level is the same as the level where the data is stored in both shared cache and private cache.

[0250] In some embodiments, the request processing apparatus for a multi-core processor further includes:

[0251] The fourth determination module is used to determine the address of the next request based on the address corresponding to the previous request;

[0252] The storage module is used to control the shared cache to prefetch the data corresponding to the address of the next request and store the prefetched data corresponding to the address of the next request in the shared cache.

[0253] In some embodiments, the request processing apparatus for a multi-core processor further includes:

[0254] The third eviction module is used to evict target cache lines when the shared cache is detected to be full, based on the least recently used policy and the policy of prioritizing the eviction of cache lines in the shared cache whose cache level is the same as that of the data stored in both the shared cache and the private cache, and whose data state is clean.

[0255] The third modification module is used to change the caching hierarchy of the target cache line in the directory from a hierarchy where data is stored in both shared and private caches to a hierarchy where data is stored in the shared cache; this triggers the storage module.

[0256] In some embodiments, the request processing apparatus for a multi-core processor further includes:

[0257] The sixth acquisition module is used to acquire pre-established arrays representing the data status in the private cache and arrays representing the data status in the shared cache; wherein each row in the array includes at least an address, the cache status corresponding to the address, and the number of times the address is used.

[0258] In some embodiments, the request processing apparatus for a multi-core processor further includes:

[0259] The configuration module is used to pre-configure the bypass cache corresponding to the shared cache;

[0260] The ninth control module is used to control the request node to transfer the write request data to the bypass cache corresponding to the shared cache;

[0261] The write-back module is used to write the data requested by write back to memory via a bypass cache.

[0262] Since the embodiments of the apparatus and the embodiments of the method correspond to each other, please refer to the description of the embodiments of the method for the embodiments of the apparatus, which will not be repeated here.

[0263] Figure 7 This is a structural diagram of a server provided in an embodiment of the present invention. This embodiment is based on a hardware perspective, such as... Figure 7 As shown, the server includes:

[0264] Memory 20 is used to store computer programs;

[0265] The processor 21 is configured to implement the steps of the request processing method for a multi-core processor as described in the above embodiments when executing a computer program.

[0266] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one hardware form selected from Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array. The processor 21 may also include a main processor and a coprocessor. The main processor, also known as the CPU, is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0267] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 20 is used to store at least the following computer program 201, which, after being loaded and executed by the processor 21, is capable of implementing the relevant steps of the request processing method of the multi-core processor disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, and the storage method may be temporary storage or permanent storage. The operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, the data involved in the request processing method of the multi-core processor mentioned above.

[0268] In some embodiments, the server may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

[0269] Those skilled in the art will understand that Figure 7 The structure shown does not constitute a limitation on the server and may include more or fewer components than illustrated.

[0270] The server provided in this embodiment of the invention includes a memory and a processor. When the processor executes a program stored in the memory, it can implement the following method: a request processing method for a multi-core processor, with the same effect as above.

[0271] This invention also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the request processing method for a multi-core processor described above.

[0272] Finally, the present invention also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, performs the steps described in the above method embodiments.

[0273] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0274] The computer-readable storage medium provided by this invention includes the request processing method for the multi-core processor mentioned above, and has the same effect.

[0275] The above provides a detailed description of the request processing method, multi-core processor, product, and server for a multi-core processor provided by this invention. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this invention without departing from the principles of this invention, and these improvements and modifications also fall within the protection scope of this invention.

[0276] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

Claims

1. A request processing method for a multi-core processor, characterized in that, Applied to the master node; including: Get the request sent by the requesting node; The query directory is queried according to the request and the query results are obtained; wherein, each directory entry includes at least an address, data status, cache level, and the status of the private cache of the slave node; the cache level includes the level where data is stored in the shared cache, the level where data is stored in the private cache, and the level where data is stored in both the shared cache and the private cache; the data status is used to characterize whether the data is dirty or whether the data is exclusive. If the query result is a directory not found, the target data corresponding to the request is retrieved from memory and transmitted to the private cache of the request node after passing through the shared cache, in order to respond to the request; If the query result is a shared cache hit, the target data corresponding to the request is obtained from the shared cache, and the target data is transferred to the private cache of the request node to respond to the request; If the query result indicates that other private caches have been hit, then the other private caches that have been hit will transfer the target data corresponding to the request to the private cache of the request node in order to respond to the request; wherein, the other private caches are all private caches except the private cache of the request node.

2. The request processing method for a multi-core processor according to claim 1, characterized in that, Before obtaining the request sent by the requesting node, the following is also included: The requesting node determines whether its own request hits its own private cache; if so, the requesting node responds to the request using the target data corresponding to the request stored in its own private cache and ends the process; if not, it sends a request to the master node.

3. The request processing method for a multi-core processor according to claim 2, characterized in that, The request is a read request, and the response to the request includes: From the moment the requesting node receives the target data from its private cache, the requesting node retrieves the target data from its own private cache within a preset time period and responds to the request using the target data.

4. The request processing method for a multi-core processor according to claim 3, characterized in that, After retrieving the target data corresponding to the request from memory and transmitting the target data to the private cache of the request node via a shared cache, the method further includes: The cache hierarchy of the cache line corresponding to the address of the read request in the directory is the hierarchy where the data is stored in both the shared cache and the private cache; Determine the target state of the private cache of the requesting node based on the request; The state of the private cache of the request node is controlled to the target state.

5. The request processing method for a multi-core processor according to claim 3, characterized in that, After retrieving the target data corresponding to the request from the shared cache and transferring the target data to the private cache of the request node, the method further includes: Change the cache hierarchy of the cache line corresponding to the address of the directory read request from the level where the data is stored in the shared cache to the level where the data is stored in both the shared cache and the private cache; Determine the target state of the private cache of the requesting node based on the request; The state of the private cache of the request node is controlled to the target state.

6. The request processing method for a multi-core processor according to claim 3, characterized in that, After the other private caches that have been hit by the control transfer the target data corresponding to the request to the private cache of the request node, the process further includes: Keep the cache level of the cache line containing the address corresponding to the read request in the directory unchanged; The request determines the first target state of the private cache of the requesting node, and the second target state of other private caches that are hit. The state of the private cache of the request node is controlled to the first target state, and the state of other private caches that are hit is controlled to the second target state.

7. The request processing method for a multi-core processor according to claim 2, characterized in that, The request is a write request, and the target data is the write address corresponding to the write request; The response to the request includes: The private cache of the request node is controlled to be in an exclusive state; If the private cache of the requesting node is detected to be in an exclusive state, the requesting node is controlled to write the data corresponding to the write request to its own private cache.

8. The request processing method for a multi-core processor according to claim 7, characterized in that, Before the step of controlling the request node to write the data corresponding to the write request to the request node's own private cache, the method further includes: If it is detected that the private cache of the requesting node is full, the requesting node is controlled to evict shared cache lines according to the least recently used strategy and the strategy of prioritizing the eviction of shared data in the private cache of the requesting node. After evicting shared state data, the process proceeds to the step of controlling the requesting node to write the data corresponding to the write request to the requesting node's own private cache.

9. The request processing method for a multi-core processor according to claim 8, characterized in that, After evicting shared-state data and before proceeding to the step of controlling the requesting node to write the data corresponding to the write request to the requesting node's own private cache, the method further includes: Obtain the relationship between the remaining space in the private cache and the space occupied by the data corresponding to the write request; If the remaining space in the private cache is detected to be greater than or equal to the space occupied by the data corresponding to the write request, then proceed to the step of controlling the request node to write the data corresponding to the write request to the request node's own private cache. If the remaining space in the private cache is detected to be less than the space occupied by the data corresponding to the write request, then the exclusive cache line is evicted, and the process returns to the step of obtaining the size relationship between the remaining space in the private cache and the space occupied by the data corresponding to the write request.

10. The request processing method for a multi-core processor according to claim 1, characterized in that, Before transmitting the target data to the private cache of the requesting node, the method further includes: If it is detected that the private cache of the requesting node is full, the requesting node is controlled to evict shared cache lines according to the least recently used strategy and the strategy of prioritizing the eviction of shared data in the private cache of the requesting node. After evicting shared state data, obtain the size relationship between the remaining space in the private cache and the space occupied by the target data; If the remaining space in the private cache is detected to be greater than or equal to the space occupied by the target data, then proceed to the step of transferring the target data to the private cache of the requesting node; If the remaining space in the private cache is detected to be less than the space occupied by the target data, the exclusive cache line is evicted, and the process returns to the step of obtaining the size relationship between the remaining space in the private cache and the space occupied by the target data.

11. The request processing method for a multi-core processor according to claim 1, characterized in that, Before transferring the target data to the shared cache, the following is also included: If the shared cache is detected to be full, the target cache line is evicted according to the least recently used policy and the policy of prioritizing the eviction of cache lines in the shared cache whose cache level is where the data is stored in both the shared cache and the private cache and whose data state is clean. Change the caching hierarchy of the target cache line described in the catalog from one where data is stored in both shared and private caches to one where data is stored only in the private cache; Proceed to the step of transferring the target data to the shared cache.

12. The request processing method for a multi-core processor according to claim 11, characterized in that, When multiple target cache lines are determined based on a least recently used policy and a policy of prioritizing the eviction of cache lines in the shared cache that are stored in both shared and private caches and whose data state is clean, the eviction of target cache lines includes: Retrieve the cache hierarchy of each target cache line recorded in the directory; If any of the target cache lines contains a target cache line whose cache level is such that the data is stored in both the shared cache and the private cache, then evict the target cache line whose cache level is such that the data is stored in both the shared cache and the private cache. If none of the target cache lines contain a cache level where the data is stored in both shared and private caches, then the target cache line is randomly evicted.

13. The request processing method for a multi-core processor according to claim 1, characterized in that, Also includes: The address of the next request is determined based on the address corresponding to the previous request; The system controls the shared cache to prefetch data corresponding to the address of the next request, and stores the prefetched data corresponding to the address of the next request in the shared cache.

14. The request processing method for a multi-core processor according to claim 13, characterized in that, Before storing the data corresponding to the address of the next prefetched request in the shared cache, the method also includes: If the shared cache is detected to be full, the target cache line is evicted according to the least recently used policy and the policy of prioritizing the eviction of cache lines in the shared cache whose cache level is where the data is stored in both the shared cache and the private cache and whose data state is clean. Change the caching hierarchy of the target cache line described in the catalog from one where data is stored in both shared and private caches to one where data is stored in the shared cache. Proceed to the step of storing the data corresponding to the address of the next request, which has been prefetched, in the shared cache.

15. The request processing method for a multi-core processor according to any one of claims 8 to 11, characterized in that, Before evicting cache lines, the following is also included: Obtain pre-established arrays representing the data status in the private cache and arrays representing the data status in the shared cache; wherein each row in the array includes at least an address, the cache status corresponding to the address, and the number of times the address is used; The evicted cache line includes: Based on the array used to characterize the data situation in the private cache or the array used to characterize the data situation in the shared cache, cache lines are evicted according to the least recently used policy and the priority eviction policy.

16. The request processing method for a multi-core processor according to claim 1, characterized in that, If the shared cache is detected to be full, the requested content is to write data to memory, and the data corresponding to the write request is in a dirty data state, the method further includes: Pre-configure the bypass cache corresponding to the shared cache; Control the request node to transfer the write request data to the bypass cache corresponding to the shared cache; The data of the write request is written back to memory through the bypass cache.

17. A multi-core processor, characterized in that, include: The system comprises a master node, slave nodes, a shared cache, memory, and private caches corresponding to each node; the master node is connected to the slave nodes; the master node is used for: Get the request sent by the requesting node; The query directory is queried according to the request and the query results are obtained; wherein, each directory entry includes at least an address, data status, cache level, and the status of the private cache of the slave node; the cache level includes the level where data is stored in the shared cache, the level where data is stored in the private cache, and the level where data is stored in both the shared cache and the private cache; the data status is used to characterize whether the data is dirty or whether the data is exclusive. If the query result is a directory not found, the target data corresponding to the request is retrieved from memory and transmitted to the private cache of the request node after passing through the shared cache, in order to respond to the request; If the query result is a shared cache hit, the target data corresponding to the request is obtained from the shared cache, and the target data is transferred to the private cache of the request node to respond to the request; If the query result indicates that other private caches have been hit, then the other private caches that have been hit will transfer the target data corresponding to the request to the private cache of the request node in order to respond to the request; wherein, the other private caches are all private caches except the private cache of the request node.

18. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instruction is executed by the processor, it implements the steps of the request processing method of the multi-core processor according to any one of claims 1 to 16.

19. A server, characterized in that, include: memory for storing computer programs; A processor, configured to implement the steps of the request processing method of a multi-core processor as described in any one of claims 1 to 16 when executing the computer program.

20. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the request processing method of a multi-core processor as described in any one of claims 1 to 16.

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