Data processing device suitable for PCIe (Peripheral Component Interconnect Express) link and communication system with same

Abstract

The invention discloses a data processing device suitable for a PCIe link and a communication system with the data processing device. A core PCIe channel module of the processing device comprises a first PCIe input interface, a second PCIe input interface, a first PCIe channel module and a second PCIe channel module, wherein the first PCIe input interface is used for receiving upstream PCIe data; the first data enhancement unit is used for enhancing the upstream PCIe data to obtain a physical layer coded data stream; the data storage unit receives and stores the data output by the first data enhancement unit through a first path; a first data input end of the first data selector receives data output by the first data enhancement unit through a second path, and a second data input end of the first data selector receives data stored in the data storage unit through a third path; the control unit controls the first data selector to selectively output data received by one of the first data input end and the second data input end; and the first PCIe output interface is used for sending the data output by the first data selector to a downstream PCIe device.

Description

Technical Field

[0001] The present invention relates to the field of PCIe communication, and particularly to a data processing device applicable to a PCIe link and a communication system having the same. Background Art

[0002] PCI Express (abbreviated as PCIe), as a high-speed serial computer expansion bus standard, is widely used in fields such as servers, storage, and networks. With the continuous increase in PCIe speed, the problem of signal integrity has become increasingly prominent, and retimers have been introduced to restore signal quality and extend the transmission distance. However, in some scenarios with extremely high requirements for data reliability, relying solely on retimers to ensure the physical layer quality of signals may not be sufficient to cope with all data transmission risks, such as burst errors caused by instantaneous link interference or upstream device failures. In the prior art, data protection is usually implemented at a higher layer of the protocol stack or at the system level, lacking an effective solution for integrating signal conditioning and lightweight data backup and recovery at the intermediate node of the PCIe physical link.

[0003] The disclosure of the above background art content is only for assisting in understanding the concept and technical solution of the present application, and it does not necessarily belong to the prior art of the present application, nor will it necessarily provide technical guidance; in the absence of clear evidence indicating that the above content was publicly available before the filing date of the present application, the above background art should not be used to evaluate the novelty and inventiveness of the present application. Summary of the Invention

[0004] The object of the present invention is to provide a data processing device applicable to a PCIe link and a communication system having the same, so as to improve the data transmission reliability and fault tolerance of the PCIe link.

[0005] To achieve the above object, the technical solution adopted by the present invention is as follows: A data processing device applicable to a PCIe link includes at least one PCIe channel module, and each PCIe channel module is configured with: A first PCIe input interface, which is configured to receive PCIe upstream data from a first PCIe device upstream; A first data enhancement unit, which is configured to enhance the PCIe upstream data to obtain a physical layer encoded data stream; A data storage unit, which is configured to receive and store the physical layer encoded data stream output by the first data enhancement unit through a first path; A first data selector with multiple data input terminals, where the first data input terminal is configured to receive the physical layer encoded data stream output by the first data enhancement unit through a second path, and the second data input terminal is configured to receive the physical layer encoded data stream stored in the data storage unit through a third path; A control unit configured to send a selection signal to the selection terminal of the first data selector, and the selection signal is for the first data selector to select and output the data received by one of the first data input terminal and the second data input terminal; A first PCIe output interface configured to send the data output by the first data selector to a downstream second PCIe device.

[0006] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the data storage unit is configured with a write operation enable terminal and a read operation enable terminal, and the control unit is also connected to the write operation enable terminal and the read operation enable terminal; If the control unit sends an enable signal to the write operation enable terminal, the first path is turned on, otherwise the data storage unit stops receiving and storing data; If the control unit sends an enable signal to the read operation enable terminal, the third path is turned on, otherwise the data storage unit stops sending data to the second data input terminal of the first data selector.

[0007] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the control unit executes different working modes according to a preset mode instruction, including: If the mode instruction is to execute the normal working mode, the control unit sends a selection signal to select the first data input terminal to the first data selector, and prohibits sending enable signals to the write operation enable terminal and the read operation enable terminal; If the mode instruction is to execute the data protection mode, the control unit sends a selection signal to select the first data input terminal to the first data selector, sends an enable signal to the write operation enable terminal, and prohibits sending an enable signal to the read operation enable terminal; If the mode instruction is to execute the data recovery mode, the control unit sends a selection signal to select the second data input terminal to the first data selector, and sends an enable signal to the read operation enable terminal.

[0008] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the mode instruction for executing the data protection mode is configured to be sent to the control unit at a preset frequency; Alternatively, the mode instruction for executing the normal working mode or the data protection mode is configured to be sent from a master controller external to the PCIe channel module to the control unit.

[0009] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, consecutive sequence numbers are assigned to each data packet of the data stream based on the PCIe link layer. If the second PCIe device receives the data packets corresponding to the consecutive sequence numbers, it returns ACK response signals to the first PCIe device one by one; If the second PCIe device does not receive the data packet corresponding to the next consecutive sequence number, it sends a NACK response signal to the PCIe channel module to which it is connected to trigger the corresponding control unit to execute the data recovery mode.

[0010] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, in PCIe communication, if the second PCIe device sends a NACK response signal, it triggers the corresponding control unit to execute the data recovery mode, including: sending a selection signal for selecting the second data input terminal to the first data selector and sending an enable signal to the read operation enable terminal.

[0011] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the operations for executing the data recovery mode further include: Parsing the corresponding sequence number from the NACK response signal, where the sequence number is the sequence number of the data packet not received by the second PCIe device; Checking whether the same sequence number exists in the data storage unit; if it exists, reading out the code stream of the data packet corresponding to the sequence number from the data storage unit and returning an ACK response signal to the first PCIe device; If it does not exist, returning a NACK response signal to the first PCIe device.

[0012] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the data storage unit is configured to store the physical layer encoded data stream output by the first data enhancement unit in the following manner: Parsing the physical layer encoded data stream, including: identifying the key layer markers therein to locate the start boundary and end boundary of each data packet; and parsing out the sequence numbers corresponding to the respective data packets; According to the start boundary and end boundary, splitting the physical layer encoded data stream into several data packet units and associating their corresponding sequence numbers; Writing the split data packet units and their corresponding sequence numbers into the memory inside the data storage unit in an associated manner.

[0013] Further, for any one of the foregoing technical solutions or a combination of multiple technical solutions, if the same serial number is found in the data storage unit and there is a subsequent serial number adjacent to this serial number, then the bitstreams of multiple data packets corresponding to multiple consecutive serial numbers starting from this serial number are read out from the data storage unit, and a corresponding ACK response signal is returned to the first PCIe device; The first PCIe device then determines the next serial number based on the last ACK response signal to continue transmitting data.

[0014] Further, for any one of the foregoing technical solutions or a combination of multiple technical solutions, after checking whether the same serial number exists in the data storage unit and returning a response signal to the first PCIe device, it further includes: The data storage unit feeds back a status signal to the control unit to drive the control unit to exit the data recovery mode and execute the normal working mode or execute the data protection mode.

[0015] Further, for any one of the foregoing technical solutions or a combination of multiple technical solutions, each PCIe channel module is further configured with a second PCIe input interface and a second PCIe output interface, wherein the second PCIe input interface is configured to be connected to the output interface of the second PCIe device, and the second PCIe output interface is configured to be connected to the input interface of the first PCIe device; The second PCIe input interface is configured to send the response signal sent by the second PCIe device to the data storage unit; The data storage unit is configured with multiple independent transmission ports, one of which is connected to the first data selector, and the other transmission port is configured to be connected to the second PCIe output interface.

[0016] Further, for any one of the foregoing technical solutions or a combination of multiple technical solutions, each PCIe channel module is further configured with a second data enhancement unit and a second data selector, wherein the second data selector is configured with a third data input terminal and a fourth data input terminal; The second data enhancement unit is configured to enhance the PCIe data received by the second PCIe input interface. The second data enhancement unit is configured with two output branches, wherein the first output branch is connected to the data storage unit, and the second output branch is connected to the third data input terminal of the second data selector; The fourth data input terminal is connected to the other transmission port of the data storage unit, and the output terminal of the second data selector is connected to the second PCIe output interface.

[0017] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the control unit is further configured to send a selection signal to the selection terminal of the second data selector, and the selection signal is for the second data selector to select and output the data received by one of the third data input terminal and the fourth data input terminal.

[0018] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the data processing device applicable to the PCIe link provided by the present invention further includes a main controller, the input end of which is connected to the communication interface of the management system outside the data processing device, and the output end of which is connected to the input ends of the control units of each PCIe channel module.

[0019] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the data processing device applicable to the PCIe link provided by the present invention further includes a power supply module, which is configured to supply power to the main controller and each PCIe channel module.

[0020] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the first data enhancement unit is configured with a retimer circuit, and the first data enhancement unit is configured to perform clock data recovery, equalization, and re-driving operations on PCIe data.

[0021] According to another aspect of the present invention, there is provided a communication system, including at least two PCIe devices and the data processing device applicable to the PCIe link as described above.

[0022] The beneficial effects brought by the technical solutions provided by the present invention are as follows: a. Realize the integration of functions such as retiming to enhance signal quality, lightweight data backup storage, and data recovery in case of failure at the intermediate node of the PCIe physical link within a single module, simplify the system design, and have a high degree of integration; b. By backing up the transmitted data in the data protection mode and supplementing the transmission in case of failure, significantly improve the data transmission reliability and fault tolerance of the PCIe link; c. Directly store and recover the physical layer encoded data stream without complex protocol layer decoding and re-encoding, with a fast response speed and a small additional delay; d. Whether it is real-time transmission or recovery and transmission from storage, the data is processed by the data enhancement module (there is data enhancement logic in the path before storage or after recovery), ensuring the quality of the transmitted signal; e. Through the logic control unit, the working mode can be flexibly switched to meet the requirements of different application scenarios such as high real-time or low resource consumption. Description of the Drawings

[0023] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments described in the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0024] Figure 1 Conceptual framework diagram of a data processing device applicable to a PCIe link provided for an exemplary embodiment of the present invention; Figure 2 Schematic diagram of the composition structure of the PCIe channel module of the data processing device provided for an exemplary embodiment of the present invention; Figure 3 Schematic diagram of the specific composition of the data processing device provided for an exemplary embodiment of the present invention; Figure 4 Schematic diagram of the composition structure of the PCIe channel module of a multi-input / output interface provided for an exemplary embodiment of the present invention; Figure 5 Compared with Figure 4 Simplified schematic diagram of the composition structure of the PCIe channel module of a multi-input / output interface provided for an exemplary embodiment of the present invention; Figure 6 Schematic diagram of the implementation process of the data recovery mode provided for an exemplary embodiment of the present invention. Detailed implementation manners

[0025] In order to enable those skilled in the art to better understand the solution of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0026] It should be noted that the terms "first", "second", etc. in the description, claims and the above-mentioned drawings of the present invention are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, device, product or equipment that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or are inherent to these processes, methods, products or equipment.

[0027] In an embodiment of the present invention, a data processing device applicable to a PCIe link is provided, including at least one PCIe channel module as shown in Figure 2 The PCIe channel module is the core of the data processing device and requires initialization and functional parameter configuration. These configurations can be sent to each PCIe channel module through an internal bus or a dedicated interface. Each PCIe channel module is configured with: A first PCIe input interface, which is configured to receive PCIe upstream data from a first PCIe device upstream. A first data enhancement unit, which is configured to enhance the PCIe upstream data to obtain a physical layer encoded data stream. Specifically, the first data enhancement unit is configured with a retimer circuit. The function of the first data enhancement unit is to recover and shape the PCIe signals that may have signal quality problems such as jitter and attenuation, including clock data recovery (CDR), signal equalization and signal re-driving operations, so as to output a high-quality serial data stream that conforms to the PCIe physical layer specification, and obtain a serial bit stream such as 8b / 10b encoding, 128b / 130b encoding or PAM4 encoding. For example, for PCIe Gen1 / Gen2, it is an 8b / 10b encoded symbol stream, and for PCIe Gen3 and above, it is a 128b / 130b (or PAM4) encoded block stream, and may remain in a scrambled state.

[0028] A data storage unit, which is configured to receive and temporarily store the physical layer encoded data stream output by the first data enhancement unit through a first path; the data storage unit can be implemented by a high-speed FIFO or DPRAM, and its capacity is determined according to the expected amount of fault recovery data and the PCIe link rate. In this embodiment, the data stored in the data storage unit is the physically encoded data that has been signal-conditioned and output by the first data enhancement module. To improve the reliability of the stored data, an ECC check logic can be integrated inside the data storage unit.

[0029] A first data selector with multiple data input terminals, where the first data input terminal is configured to receive the physical layer encoded data stream output by the first data enhancement unit through a second path, and the second data input terminal is configured to receive the physical layer encoded data stream stored in the data storage unit through a third path; in this embodiment, the first data selector is a MUX (Multiplexer), which is a basic logic unit in a digital circuit and is used to select one of multiple input signals and output it to a common channel.

[0030] It can be seen that the first data enhancement unit in this embodiment is configured with two output branches, one of which is connected to the data storage unit, and the other is connected to the first data input terminal of the first data selector.

[0031] A control unit, which is configured to send a selection signal to the selection terminal of the first data selector, and the selection signal is for the first data selector to select and output the data received by one of the first data input terminal and the second data input terminal; A first PCIe output interface, which is configured to send the data output by the first data selector to a downstream second PCIe device.

[0032] Continue to refer to Figure 2 , the data storage unit is configured with a write operation enable terminal and a read operation enable terminal, and the control unit is also connected to the write operation enable terminal and the read operation enable terminal; If the control unit sends an enable signal (En_write = 1) to the write operation enable terminal, then the first path is turned on, that is, it is possible to write the enhanced physical layer encoded data stream to the data storage unit; if En_write = 0, then the data storage unit stops receiving and storing data, that is, the data storage unit cannot perform the write operation; If the control unit sends an enable signal (En_read = 1) to the read operation enable terminal, then the third path is turned on, that is, the data read from the data storage unit is sent to the second data input terminal of the first data selector; if En_read = 0, then the data storage unit cannot perform the read operation, and further stops sending data to the second data input terminal of the first data selector.

[0033] In this embodiment, the data storage unit can be implemented by a dual-port RAM (DPRAM) and can be configured as a circular buffer. The data storage unit can integrate an error correction code (ECC) function to ensure the integrity of the stored data.

[0034] The control unit executes different working modes according to preset mode instructions. In some embodiments, a main controller external to the PCIe channel module sends specific mode instructions to the control unit. For example, through external monitoring and configuration, if the real-time requirement for communication between the current first PCIe device and the second PCIe device is relatively high, it is required that the control unit control the PCIe channel module to execute the data protection mode, that is, send a selection signal (MUX_SEL = 1) for selecting the first data input terminal to the first data selector, send an enabling signal (En_write = 1) to the write operation enabling terminal, and prohibit sending an enabling signal (En_read = 0) to the read operation enabling terminal. The data flow path in this mode is divided into a main path: the first PCIe input interface → the first data enhancement unit → the first data selector → the first PCIe output interface, and a storage path: the first PCIe input interface → the first data enhancement unit → the data storage unit, that is, send and store duplicate data at the same time; The data protection mode can improve real-time performance in that: when a specific situation occurs, such as a communication failure causing the second PCIe device to fail to successfully receive a data packet, during the waiting for resuming data transfer from the breakpoint, the data stored in the data storage unit in the data protection mode can be used to reissue data to the second PCIe device. This mode is defined as the data recovery mode, that is, the control unit sends a selection signal (MUX_SEL = 0) for selecting the second data input terminal to the first data selector, and sends an enabling signal (En_read = 1) to the read operation enabling terminal. In the data recovery mode, an enabling signal can be sent to the write operation enabling terminal, or the sending of an enabling signal to the write operation enabling terminal can be prohibited (stopping writing new data can protect the stored data to be recovered). This embodiment does not make a specific limitation. Taking the prohibition of sending an enabling signal to the write operation enabling terminal as an example, the data flow path in the data protection mode is the data storage unit → the first data selector → the first PCIe output interface.

[0035] When the command of the external monitor indicates that the real-time requirement for communication between the current first PCIe device and the second PCIe device is not so high, even if a failure occurs (the second PCIe device fails to successfully receive the data packet), the first PCIe device can retransmit a certain number of data packets that have been rolled back. In this configuration, the control unit controls the PCIe channel module to execute the normal working mode, that is, the control unit sends a selection signal (MUX_SEL = 1) to select the first data input terminal of the first data selector, and prohibits sending an enabling signal to the write operation enabling terminal and the read operation enabling terminal (En_write = 0, En_read = 0). The data flow path in this mode is: the first PCIe input interface → the first data enhancement unit → the first data selector → the first PCIe output interface. Only the standard retiming function is executed in the normal working mode.

[0036] In addition to indicating to the control unit to control the PCIe channel module to specifically execute the normal working mode or the data protection mode through external monitoring and configuration, an embodiment of the present invention also provides a control strategy according to a preset frequency. For example, the preset period is T, and the normal working mode is executed in the first 3T / 4 of each period, and the data protection mode is executed in the last 1T / 4. The technical solution of the present invention can also be achieved.

[0037] In an embodiment, the method of external triggering or internal monitoring can be used to determine whether a failure occurs, so as to switch to the data recovery mode. Among them: the external triggering method refers to monitoring the link data externally to determine whether a failure occurs. If a failure occurs, an external trigger signal is sent to trigger the control unit to set MUX_SEL = 0 and En_read = 1, that is, the PCIe channel module enters the data recovery mode.

[0038] The following details another method of internal monitoring to determine whether a failure occurs: based on the PCIe link layer, continuous serial numbers are assigned to each data packet in the data stream. If the second PCIe device receives the data packets corresponding to the continuous serial numbers, it returns an ACK response signal to the first PCIe device one by one, indicating that the second PCIe device has successfully received the data; because the serial numbers of the data packets in the data stream are continuous, when the second PCIe device does not receive the data packet corresponding to the next continuous serial number within the preset time, it will send a NACK response signal. At this time, it is considered that a failure has occurred, and the missing current data packet needs to be reissued before the continuous transmission of the data packets can be restored.

[0039] Such as Figure 5In one embodiment, each PCIe channel module is further configured with a second PCIe input interface and a second PCIe output interface. Among them, the second PCIe input interface is configured to be connected to the output interface of the second PCIe device, and the second PCIe output interface is configured to be connected to the input interface of the first PCIe device; The response signals returned by the second PCIe device are all sent out through the second PCIe input interface. For the ACK response signal, there are two ways to return it to the first PCIe device: Way 1 is to directly send the ACK response signal to the second PCIe output interface for further sending to the first PCIe device; Way 2 is to send the ACK response signal to the data storage unit, and the data storage unit sends it to the second PCIe output interface for further sending to the first PCIe device.

[0040] The key to the data recovery mode is to trigger the execution of the data recovery mode based on the NACK response signal: The second PCIe device does not receive the data packet corresponding to the next consecutive sequence number and sends a NACK response signal to the data storage unit through the second PCIe input interface; The data storage unit attempts to reissue data to the second PCIe device. If the reissue is successful, this NACK response is processed at the level of this PCIe channel module and does not need to be further passed up to the first PCIe device. At this time, the data storage unit will generate a corresponding ACK response signal according to the NACK response signal and send it to the second PCIe output interface for further sending to the first PCIe device. To avoid confusion in data sending by the data storage unit, the data storage unit in this embodiment is configured with multiple independent transmission ports TX1, TX2. One transmission port TX1 is connected to the first data selector, and the other transmission port TX2 is configured to be connected to the second PCIe output interface.

[0041] If the NACK response cannot be processed at the level of this PCIe channel module, it needs to be further passed up to the first PCIe device. At this time, the data storage unit will forward the NACK response signal to the second PCIe output interface for further sending to the first PCIe device, so that the first PCIe device can roll back to the data packet at the breakpoint and resend the data.

[0042] The operation of attempting to process the NACK response at the level of this PCIe channel module is as Figure 6 shown and is divided into a storage stage and a data recovery stage: In the storage stage, the physical layer encoded data stream output by the first data enhancement unit is stored in the following way: The data storage unit receives the enhanced encoded data stream; Parse the physically-layer encoded data stream, including: identifying key layer markers therein to locate the start boundary and end boundary of each data packet; and parsing out the sequence numbers corresponding to the respective data packets; According to the start boundary and end boundary, segment the physically-layer encoded data stream into a number of data packet units and associate their corresponding sequence numbers; this can facilitate subsequent indexing, querying, and sending based on the granularity of "packets". Write the segmented data packet units and their corresponding sequence numbers into the memory inside the data storage unit in an associated manner.

[0043] In the data recovery phase, it includes: The data storage unit receives a NACK response signal from the second PCIe device; Parse out the corresponding sequence number from this NACK response signal, and this sequence number is the sequence number of the data packet not received by the second PCIe device; Check whether the same sequence number exists in the data storage unit; if it exists, read out the code stream of the data packet corresponding to this sequence number from the data storage unit and send it to the second PCIe device to complete data retransmission, and at the same time generate an ACK response signal corresponding to this NACK response and return this ACK response signal to the first PCIe device through the second PCIe output interface; If the same sequence number does not exist in the data storage unit, forward this NACK response signal to the first PCIe device through the second PCIe output interface.

[0044] In the data protection mode, while normally sending data, store a data copy that has undergone data enhancement processing and has high quality in the data storage unit. The data storage unit is usually designed as a circular buffer. When it is full, new data will overwrite the oldest data; it is also possible to start the data aging and cleaning mode, that is, when a data is written into the data storage unit, a counter is started. When the data life cycle exceeds a preset time threshold, cleaning is triggered. Suppose the data storage window period is 500 ms and the data life cycle is 1 s. For the data received within these 500 ms, after 1 s, the data stored within these 500 ms will be cleared. This can ensure effective management of the storage space and prevent it from being filled with obsolete data indefinitely.

[0045] The data storage unit is usually implemented as a circular buffer (Circular Buffer / FIFO), which means that when the buffer is full, newly written data will automatically overwrite the oldest data. In this case, the "start timer" can be understood as the write / overwrite mechanism of the circular buffer taking effect, keeping the data in storage relatively "fresh", preferentially retaining the data that is most likely to be needed for fault recovery recently, and releasing space for new incoming data.

[0046] In the case where the same serial number is found in the data storage unit, there are two embodiments for data retransmission. The first embodiment is to send only the data packet corresponding to the one serial number to be retransmitted to the second PCIe device, and then notify the first PCIe device to continue transmitting data from the next serial number. The second embodiment is that when the same serial number is found in the data storage unit and there is a subsequent serial number adjacent to this serial number, the data stream of multiple data packets corresponding to multiple consecutive serial numbers starting from this serial number is read out from the data storage unit, and a corresponding ACK response signal is returned to the first PCIe device; the first PCIe device then determines the next serial number according to the last ACK response signal to continue transmitting data. For example, if the data packets read out from the data storage unit are those with serial numbers 100 to 105, correspondingly, the data storage unit generates response signals ACK 100 、ACK 101 、ACK 102 、ACK 103 、ACK 104 、ACK 105 and sends them to the first PCIe device, and the first PCIe device then continues transmitting data starting from serial number 106.

[0047] As Figure 2 shown, the data storage unit also feeds back a status signal to the control unit: after checking whether there is the same serial number in the data storage unit and returning a response signal to the first PCIe device, it further includes: The data storage unit feeds back a status signal to the control unit to drive the control unit to exit the data recovery mode and execute the normal working mode or the data protection mode. Whether or not to handle the NACK response at the level of this PCIe channel module, it is necessary to inform the control unit that the current data recovery mode has ended and needs to switch to the normal working mode or the data protection mode.

[0048] In the embodiment as Figure 4 shown, not only can the first PCIe device send PCIe data to the second PCIe device, but also conversely, the second PCIe device can send PCIe data to the first PCIe device: Each PCIe channel module is also configured with a second data enhancement unit and a second data selector. Among them, the second data selector is configured with a third data input terminal and a fourth data input terminal; The second data enhancement unit is configured to enhance the PCIe data received by the second PCIe input interface. The second data enhancement unit is configured with two output branches. Among them, the first output branch is connected to the data storage unit, and the second output branch is connected to the third data input terminal of the second data selector; The fourth data input terminal is connected to the other transmission port of the data storage unit, and the output terminal of the second data selector is connected to the second PCIe output interface.

[0049] The control unit is also configured to send a selection signal to the selection terminal of the second data selector. This selection signal selects and outputs the data received by one of the third data input terminal and the fourth data input terminal for the second data selector.

[0050] As Figure 4 shown, the data storage unit has two independent transmission ports TX1 and TX2. One transmission port TX1 is connected to the receiving port RX1 at the first data selector, and the other transmission port TX2 is connected to the receiving port RX2 at the second data selector. The data storage unit has a data analysis function module, which can decide whether to send data to the second PCIe device via the TX1 port or to the first PCIe device via the TX2 port according to the device to which the current data is sent.

[0051] The PCIe channel module is the core of the data processing device applicable to the PCIe link provided by the embodiment of the present invention. In addition, the data processing device also includes a main controller and a power module. As Figure 1 and Figure 3 shown, the power module is configured to supply power to the main controller and each PCIe channel module; the input terminal of the main controller is connected to the communication interface (such as I2C, SPI, Ethernet, etc.) of the management system (such as BMC, server motherboard, network management system) outside the data processing device, reports the health status of the entire platform and the status of each channel, and receives control instructions from the external system (for example, enabling a certain channel to enter a specific mode, updating firmware, etc.); the output terminal of the main controller is connected to the input terminal of the control unit of each PCIe channel module. As Figure 3 shown.

[0052] In an embodiment of the present invention, a communication system is provided, including at least two PCIe devices and the data processing device applicable to the PCIe link as described above.

[0053] Through the above structures and methods, an effective solution combining signal conditioning and data protection is provided at the key nodes of the PCIe link, significantly improving the stability and reliability of high-speed data transmission.

[0054] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0055] The above is only the specific implementation manner of this application. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of this application, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of this application.

Claims

1. A data processing device applicable to a PCIe link, characterized in that including at least one PCIe channel module, each PCIe channel module being configured with: a first PCIe input interface configured to receive PCIe upstream data from an upstream first PCIe device; a first data enhancement unit configured to enhance the PCIe upstream data to obtain a physical layer encoded data stream; a data storage unit configured to receive and store the physical layer encoded data stream output by the first data enhancement unit through a first path; a first data selector having a plurality of data input ends, the first data input end thereof being configured to receive the physical layer encoded data stream output by the first data enhancement unit through a second path, and the second data input end thereof being configured to receive the physical layer encoded data stream stored in the data storage unit through a third path; a control unit configured to send a selection signal to the selection end of the first data selector, the selection signal being for the first data selector to select and output the data received by one of the first data input end and the second data input end; a first PCIe output interface configured to send the data output by the first data selector to a downstream second PCIe device.

2. The data processing device applicable to a PCIe link according to claim 1, wherein The data storage unit is configured with a write operation enable end and a read operation enable end, and the control unit is further connected to the write operation enable end and the read operation enable end; If the control unit sends an enable signal to the write operation enable end, the first path is turned on, otherwise the data storage unit stops receiving and storing data; If the control unit sends an enable signal to the read operation enable end, the third path is turned on, otherwise the data storage unit stops sending data to the second data input end of the first data selector.

3. The data processing device applicable to a PCIe link according to claim 2, wherein The control unit executes different working modes according to a preset mode instruction, including: If the mode instruction is to execute the normal working mode, the control unit sends a selection signal for selecting the first data input end to the first data selector, and prohibits sending enable signals to the write operation enable end and the read operation enable end; If the mode instruction is to execute the data protection mode, the control unit sends a selection signal for selecting the first data input end to the first data selector, sends an enable signal to the write operation enable end, and prohibits sending an enable signal to the read operation enable end; If the mode instruction is to execute the data recovery mode, the control unit sends a selection signal for selecting the second data input end to the first data selector, and sends an enable signal to the read operation enable end.

4. The data processing device applicable to a PCIe link according to claim 3, wherein The mode instruction for executing the data protection mode is configured to be sent to the control unit at a preset frequency; Alternatively, the mode instruction for executing the normal working mode or the data protection mode is configured to be sent to the control unit by a main controller external to the PCIe channel module.

5. The data processing device applicable to a PCIe link according to claim 3, wherein Based on the PCIe link layer, consecutive sequence numbers are assigned to each data packet of the data stream. If the second PCIe device receives data packets corresponding to consecutive sequence numbers, it returns ACK response signals to the first PCIe device one by one; If the second PCIe device does not receive the data packet corresponding to the next consecutive sequence number, it sends a NACK response signal to the PCIe channel module to which it is connected, so as to trigger the corresponding control unit to execute the data recovery mode.

6. The data processing device applicable to a PCIe link according to claim 2, wherein In PCIe communication, if the second PCIe device sends a NACK response signal, it triggers the corresponding control unit to execute the data recovery mode, including: sending a selection signal for selecting the second data input terminal to the first data selector, and sending an enable signal to the read operation enable terminal.

7. The data processing device applicable to a PCIe link according to claim 5 or 6, wherein The operation of executing the data recovery mode further includes: Parsing the corresponding sequence number from the NACK response signal, where the sequence number is the sequence number of the data packet not received by the second PCIe device; Checking whether the same sequence number exists in the data storage unit; if it exists, reading the bitstream of the data packet corresponding to the sequence number from the data storage unit, and returning an ACK response signal to the first PCIe device; If it does not exist, returning a NACK response signal to the first PCIe device.

8. The data processing device applicable to a PCIe link according to claim 7, wherein The data storage unit is configured to store the physical layer encoded data stream output by the first data enhancement unit in the following manner: Parsing the physical layer encoded data stream, including: identifying the key layer markers therein to locate the start boundary and end boundary of each data packet; and parsing out the sequence number corresponding to each data packet; According to the start boundary and end boundary, splitting the physical layer encoded data stream into several data packet units, and associating their corresponding sequence numbers; Writing the split data packet units and their corresponding sequence numbers into the memory inside the data storage unit in an associated manner.

9. The data processing device applicable to a PCIe link according to claim 7, wherein If the same sequence number is found in the data storage unit and there is a subsequent sequence number adjacent to the sequence number, reading the bitstreams of multiple data packets corresponding to multiple consecutive sequence numbers starting from the sequence number from the data storage unit, and returning one-to-one ACK response signals to the first PCIe device; The first PCIe device then determines the next sequence number according to the last ACK response signal to continue transmitting data.

10. The data processing device applicable to a PCIe link according to claim 7, wherein After checking whether the same sequence number exists in the data storage unit and returning a response signal to the first PCIe device, it further includes: The data storage unit feeds back a status signal to the control unit to drive the control unit to exit the data recovery mode and execute the normal working mode or execute the data protection mode.

11. The data processing device applicable to a PCIe link according to claim 7, wherein Each PCIe channel module is further configured with a second PCIe input interface and a second PCIe output interface, where the second PCIe input interface is configured to be connected to the output interface of the second PCIe device, and the second PCIe output interface is configured to be connected to the input interface of the first PCIe device; The second PCIe input interface is configured to send the response signal sent by the second PCIe device to the data storage unit; The data storage unit is configured with a plurality of independent transmission ports, one of the transmission ports is connected to the first data selector, and the other transmission port is configured to be connected to the second PCIe output interface.

12. The data processing device applicable to a PCIe link according to claim 11, wherein Each PCIe channel module is further configured with a second data enhancement unit and a second data selector. The second data selector is configured with a third data input terminal and a fourth data input terminal. The second data enhancement unit is configured to enhance the PCIe data received by the second PCIe input interface. The second data enhancement unit is configured with two output branches. Among them, the first output branch is connected to the data storage unit, and the second output branch is connected to the third data input terminal of the second data selector. The fourth data input terminal is connected to the other transmission port of the data storage unit, and the output terminal of the second data selector is connected to the second PCIe output interface.

13. The data processing device applicable to a PCIe link according to claim 12, wherein The control unit is further configured to send a selection signal to the selection terminal of the second data selector. The selection signal selects and outputs the data received by one of the third data input terminal and the fourth data input terminal for the second data selector.

14. The data processing device applicable to a PCIe link according to claim 1, wherein It further includes a main controller, whose input terminal is connected to the communication interface of the management system outside the data processing device, and whose output terminal is connected to the input terminals of the control units of each PCIe channel module.

15. The data processing device applicable to a PCIe link according to claim 14, wherein It further includes a power supply module, which is configured to supply power to the main controller and each PCIe channel module.

16. The data processing device applicable to a PCIe link according to any one of claims 1 to 6 or any one of claims 8 to 15, characterized in that, The first data enhancement unit is configured with a retimer circuit, and the first data enhancement unit is configured to perform clock data recovery, equalization, and re-driving operations on PCIe data.

17. A communication system, characterized in that, It includes at least two PCIe devices and a data processing device applicable to a PCIe link according to any one of claims 1 to 16.

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