Optimization method for merging D-type triggers

Abstract

The invention belongs to the technical field of electronic design automation, and particularly discloses an optimization method for combining D-type triggers, which comprises the following steps of: acquiring and classifying D-type triggers in a circuit according to types; selecting D-type trigger pairs of the same type, and judging whether preset control signals are homologous or not; if the control signals are homologous, iterative structure comparison is carried out on the driving logic cones at the data input ends of the control signals; the iterative comparison is carried out by initializing a source instance container and comparing the number and the type of source instances in the container layer by layer and the source of input signals of the source instances; and if the iterative comparison result shows that the logic cone structure is equivalent, judging that the D-type trigger pair is equivalent and merging and updating the circuit. According to the method, a complex logic structure can be effectively covered, the operation efficiency is improved, loops are processed, and therefore the design area and power consumption are more effectively reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic design automation, and particularly relates to an optimization method for merging D-type flip-flops. Background Art

[0002] In digital integrated circuit design, D-type flip-flops (DFFs) are the basic units that make up sequential logic circuits, and their quantity and connection method directly affect the area, power consumption, and performance of the chip. To optimize the design, logic synthesis tools usually try to merge functionally equivalent DFFs.

[0003] Currently, the methods for merging DFFs mainly include homologous optimization and equivalence verification.

[0004] The homologous optimization method determines whether each input signal (such as data input D, clock CLOCK, set SET, reset RESET, enable ENABLE, etc.) of two DFFs comes from exactly the same signal source. If all corresponding input signals are homologous, it is considered that these two DFFs are equivalent and can be merged. However, this method has limitations: when the data input terminals (D terminals) of two DFFs are connected to combinational logic cones with different structures but equivalent functions, due to the different direct drive signal sources of the D terminals, the homologous optimization method cannot determine that these two DFFs are equivalent, thus missing the optimization opportunity. For example, the D inputs of two DFFs are driven by (A&B) and (B&A) respectively. Although logically equivalent, homologous optimization cannot recognize them.

[0005] The equivalence verification method is more complex. It first checks whether the control signals (such as CLOCK, SET, RESET, ENABLE) of two DFFs are homologous. If the control signals are homologous, it further traverses forward from the D input terminals of the two DFFs to obtain their respective combinational logic cones, and then uses an equivalence checking algorithm based on boolean logic (such as a method based on SAT solver or BDD construction) to determine whether these two logic cones are functionally equivalent. If they are equivalent, it is considered that the DFFs are equivalent and can be merged. The disadvantage of this method is that when the scale of the combinational logic cone at the D data terminal of the DFF is large, the computational complexity of boolean equivalence checking will increase sharply, resulting in too long running time and low efficiency.

[0006] In addition, both of the above two existing methods have deficiencies in dealing with the circuit structure of a loop (feedback loop) formed by DFFs and combinational logic, and it is difficult to effectively identify and merge equivalent DFFs in such structures.

[0007] Therefore, the existing technology has problems such as insufficient ability to cover complex logic structures, low processing efficiency for large-scale logic cones, and difficulty in effectively dealing with loop structures in DFF merging optimization. Summary of the Invention

[0008] Objective of the Invention: The objective of the present invention is to provide a more efficient and comprehensive optimization method for merging D flip - flops in view of the deficiencies of the existing DFF merging and optimization methods in dealing with complex logic structures, large - scale logic cones, and loop structures.

[0009] Technical Solution: The optimization method for merging D flip - flops of the present invention is applied to a circuit design including multiple D flip - flops, and the method includes the following steps: S1: Select a first D flip - flop and a second D flip - flop of the same type in the circuit design as a pair to be compared; S2: Determine whether the clock signals and preset control signals of the first D flip - flop and the second D flip - flop are all from the same source. If they are from the same source, go to S3; otherwise, determine that they are not equivalent. S3: Determine whether the data signals of the first D flip - flop and the second D flip - flop are from the same source or both come from the outputs of their respective D flip - flops. If they are from the same source or both come from the outputs of their respective D flip - flops, determine that they are equivalent; otherwise, go to S4. S4: Iteratively perform a structural comparison on the logic cones driving the data signals of the first D flip - flop and the second D flip - flop. By comparing the types, quantities, and sources of the input signals of the source instances layer by layer until it is determined to be equivalent or not equivalent. S5: If it is determined to be equivalent, connect the output of the first D flip - flop to the receiving instance of the second D flip - flop and delete the second D flip - flop.

[0010] To further improve the above - mentioned technical solution, the preset control signals in S2 include a set signal, a reset signal, and an enable signal.

[0011] Furthermore, the iterative structural comparison of the logic cone in step S4 includes: S401: Traverse the logic cones of the data signals of the first D flip - flop and the second D flip - flop forward by hierarchical breadth, obtain the source instances directly driving the data signals and store them in a first container and a second container respectively; S402: Compare the quantities and types of the source instances in the first container and the second container. If they are inconsistent, determine that they are not equivalent; otherwise, go to S403; S403: Traverse each pair of source instances at the corresponding positions of the first container and the second container, and determine whether the input signals corresponding to the source instances are from the same source or come from the outputs of their respective D flip - flops. If there are non - same - source cases and they do not come from the outputs of their respective D flip - flops, store the source instances corresponding to the input signals in a first temporary container and a second temporary container respectively; S404: After the traversal is completed, if both the first temporary container and the second temporary container are empty, determine that they are equivalent; otherwise, go to S405; S405: Replace the content in the first container and the second container with the source instances in the first temporary container and the second temporary container respectively, empty the first temporary container and the second temporary container, and repeat steps S402 to S404 until equivalence or non - equivalence is determined.

[0012] Further, the forward traversal by hierarchical breadth in step S401 includes: accessing the source instances in the logic cone level by level until reaching the cone top or the traversal depth reaches a preset threshold. The logic cone includes a cone top and a cone bottom. The cone top is a register, a top - level output, or a black - box input, and the cone bottom is a combinational logic circuit.

[0013] Further, when deleting the second D - flip - flop in step S5, the logic cone that drives the data terminal of the second D - flip - flop and is not shared by other logics is also deleted.

[0014] Further, the source instances do not include timing device instances, circuit top - level port instances, or module instances.

[0015] Further, the method is applicable to a circuit including a loop structure composed of D - type flip - flops and combinational logics. The loop structure includes a circuit path where the output of the D - type flip - flop is fed back to its data terminal through combinational logics.

[0016] Advantageous effects: Compared with the prior art, the advantages of the present invention are as follows: Stronger complex logic coverage ability: By iteratively comparing the structures of the D - input logic cones, the present invention can identify complex DFF merging scenarios with equivalent functions but different direct input sources, overcoming the limitations of traditional same - source optimization.

[0017] Higher operating efficiency: Compared with the method relying on Boolean equivalence checking, the present invention adopts structured instance comparison and iterative backtracking, avoiding complex Boolean operations, and can significantly reduce the running time for large - scale logic cones and improve the optimization efficiency.

[0018] Effectively handle loop structures: By explicitly considering whether the signal comes from the output of the DFF itself when comparing input signals and combining the iterative tracing mechanism, the present invention can effectively handle the problem of equivalent DFF merging in the feedback loop composed of DFFs and combinational logics.

[0019] Comprehensive equivalence checking: From the DFF type, the homology of control signals to the structured comparison of the D - input logic cone, a set of comprehensive equivalence judgment processes are formed.

[0020] Optimized design effect: By more effectively merging equivalent DFFs, the area of the circuit design can be further reduced, the overall power consumption can be lowered, and the design quality can be improved. Description of the Drawings

[0021] Figure 1 It is a schematic diagram of a DFF (D-type flip-flop), showing its typical input and output signals.

[0022] Figure 2 It is a schematic diagram of the homologous merging of DFFs.

[0023] Figure 3 It is a schematic diagram of the equivalent merging of DFFs, where the D input terminals of the DFFs are connected to different logic cones.

[0024] Figure 4 It is a schematic diagram of a loop structure containing DFFs.

[0025] Figure 5 It is a flowchart of an optimized method for merging DFFs according to the present invention.

[0026] Figure 6 It is a schematic diagram of applying the method of the present invention to a specific circuit example, showing the iterative comparison process of the D input logic cone. Detailed implementation manners

[0027] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings, but the protection scope of the present invention is not limited to the described embodiments.

[0028] Embodiment 1: Refer to Figure 1 The schematic diagram of the DFF shown, showing its typical input and output signals, including: (1) D, ENABLE, SET, RESET, CLOCK are input signals, and Q, QN are output signals; (2) D is a data signal, CLOCK is a clock signal, ENABLE is an enable signal, SET is a set signal, RESET is a reset signal, and Q, QN have an inverted relationship, which is the output of the DFF; (3) D and CLOCK are necessary input signals, and RESET, SET, and ENABLE are optional input signals.

[0029] As Figure 2 shown in the schematic diagram of homologous merging, the CLK and D signals of DFF1 and DFF2 are homologous and can be merged. After merging, the Q of DFF1 drives logic circuit 2 in the circuit structure.

[0030] As Figure 3 shown in the equivalent schematic diagram of DFFs, the CLK signals of DFF1 and DFF2 are homologous, and the D terminals correspond to equivalent logic cones 1 and 2. DFF1 and DFF2 are merged, and after merging, the Q of DFF1 drives logic circuit 2 in the circuit structure.

[0031] As Figure 4The shown DFF loop structure diagram is composed of four source instances: DFF, selector (MUX2), AND gate, and OR gate. The output Q of the DFF reaches the D of the DFF through OR, AND, and MUX2.

[0032] Refer to Figure 5 As shown, the optimization method for merging D-type flip-flops provided by the present invention has the following specific implementation steps: Step S1: Obtain all DFFs in the design netlist and classify them according to the DFF type.

[0033] Step S2: Select a pair of DFFs from the classified DFFs of the same type, called DFF1 and DFF2, as the merging objects.

[0034] Step S3: Determine whether the CLOCK signals of DFF1 and DFF2 are from the same source. If the CLOCK signals are not from the same source, then DFF1 and DFF2 are not equivalent, and the process terminates.

[0035] Step S4: Determine whether the other control signals (such as RESET, SET, ENABLE) of DFF1 and DFF2 are from the same source. If any of the corresponding control signals that exist are not from the same source, then DFF1 and DFF2 are not equivalent, and the process terminates.

[0036] Step S5: Determine whether the data input D1 of DFF1 and the data input D2 of DFF2 are directly from the same source, or whether D1 is directly from the output of DFF1 and D2 is directly from the output of DFF2. If this is the case, then it can be determined that DFF1 and DFF2 are equivalent, and directly enter the subsequent circuit update steps. If not, enter the next step for logic cone comparison.

[0037] Step S6: If the previous control signal checks pass and the quick D input determination does not directly determine equivalence, then start a hierarchical breadth-first traversal of the logic cone of the data signal D based on the topological depth of the source instance for DFF1 and DFF2. The logical cone includes the cone top and the cone bottom. The cone top can be a register, the top-level output, or the input of a black box, while the cone bottom is the input part, mainly the combinational logic circuit. Initialize two containers, vector1 and vector2; respectively obtain the source instances of the data signal D of DFF1 and DFF2 and store them in the containers vector1 and vector2.

[0038] Step S7: Check whether the number of source instances stored in vector1 and vector2 is equal. If not, determine that DFF1 and DFF2 are not equivalent, and the process terminates. Otherwise, enter S8.

[0039] Step S8: If the quantities are equal, then retrieve the corresponding source instances (instance1 and instance2) at the corresponding positions from vector1 and vector2 one by one for comparison, and determine whether the types of instance1 and instance2 are the same. If the types are different, it is determined that DFF1 and DFF2 are not equivalent, and the process terminates.

[0040] Step S9: If the instance types are the same, then further compare the corresponding input signals of these two instances. For each input of instance1 and the corresponding input of instance2: Determine whether the corresponding input signals of the corresponding instance are from the same source or from the output of the DFF. If they are not from the same source and not from the output of the DFF, store the sourceinstance of the input signal in the temporary containers temp_vector1 and temp_vector2. The sourceinstance does not include sequential devices, ports, and module instances. Otherwise, they are not equivalent and exit. If they are from the same source or from the output of the DFF, no processing is done and proceed to the next step.

[0041] The core of Logic Equivalence Checking is based on the static functional equivalence of combinational logic. The core idea is: Prove that the combinational logic outputs of two designs are exactly the same under the same inputs through formal methods (such as Boolean algebra, binary decision diagrams, etc.). Key premise: Assume that the changes in input signals are instantaneous and synchronous, and the timing characteristics of signals (such as clock period, setup / hold time, delay, etc.) are not considered; the functions of sequential devices (such as registers, latches, flip - flops, etc.) depend on clock signals and time sequences, and their characteristics fundamentally conflict with the premise of logic equivalence verification, so sequential devices are not included. Ports include input ports and output ports, which are the boundaries of the design, so ports are not included; Module Instance is an instantiated module, and the module may contain sequential devices, so moduleinstance is not included.

[0042] Step S10: After comparing all the inputs of all the instances in vector1 and vector2, check the temporary containers temp_vector1 and temp_vector2. If both temp_vector1 and temp_vector2 are empty, it indicates that all the inputs at the current level have been matched and there are no differences that need to be further traced. At this time, it is determined that DFF1 and DFF2 are equivalent.

[0043] If temp_vector1 or temp_vector2 (or both) is not empty, move the content in temp_vector1 to vector1, and the content in temp_vector2 to vector2, and then clear the temporary containers. Then return to steps S7 to S9 to perform the next round of iterative comparison on the instances in the new vector1 and vector2.

[0044] Step S11: If it is finally determined that DFF1 and DFF2 are equivalent, perform circuit update operations. Usually, it includes: changing the fan-out logic originally connected to the output Q (or QN) of DFF2 to be connected to the corresponding output Q (or QN) of DFF1; then deleting DFF2 itself, and the combinational logic cone that drives the D input terminal of DFF2 and is not shared by other logics.

[0045] Embodiment 2: The mainstream methods of current logic equivalence verification: (1) The method based on Binary Decision Diagram (BDD), the time complexity is , and BDD is extremely sensitive to the variable order and cannot handle ultra-large-scale designs (such as circuits with millions of gates); (2) The method based on SAT (Boolean satisfiability), the SAT problem is NP-complete, and the theoretical time complexity is , and the time complexity of the actually used SAT solvers (such as MiniSat, Glucose) is . The time complexities of the above two methods are both non-linear. The method provided by the present invention traverses the logic cones corresponding to two DFFs, and the time complexity is linear, and the time complexity is n.

[0046] Compared with the existing optimization methods, the present invention can cover complex circuit structures, such as a loop structure composed of DFF and multiple combinational logic units, can comprehensively check equivalent DFFs. After merging DFFs, it is equivalent to reducing one DFF and the corresponding combinational logic cone at the D end, reducing the devices used in the design. Correspondingly, the area of the design will be reduced accordingly. Power consumption is positively correlated with area. After the area is reduced, the power consumption will also be reduced accordingly. There is no need for a complex Boolean logic equivalence checking algorithm, reducing the running time and improving the efficiency.

[0047] Refer to Figure 6 , and give a specific application example according to the method provided in Embodiment 1. The specific steps are as follows: (1) Assume that the signals such as CLK, SET, and RESET of DFF1 and DFF2 are all from the same source.

[0048] (2) The D signals are not from the same source. Store the source instances of D in the containers vector1 = {ins0}, vector2 = {ins4}.

[0049] (3)The number of instances of vctor1 and vector2 is the same. Respective corresponding ins0 and ins4 are taken out, and the types of ins0 and ins4 and whether the input signals are from the same source are compared: It is selected that the signals S0 / S1 are from the same source.

[0050] (4)Both ins0 and ins4 are of the MUX2 type, with the same quantity and the same type. The data inputs IN0 / IN1 are not from the same source and are not from the DFF output. Their driving instances are ins1 and ins5 (AND gates), ins2 and ins6 (MUX2) respectively, and these are all combinational logics. Therefore, temp_vector1 = {ins1, ins2}, temp_vector2 = {ins5, ins6}.

[0051] Empty the containers vector1 and vector2, store the instances in temp_vector1 and temp_vector2 into the containers vector1 and vector2, and update vector1 = {ins1, ins2}, vector2 = {ins5, ins6}.

[0052] (5)The number of instances of vctor1 and vector2 is the same. Respective corresponding ins1 and ins5, ins2 and ins6 are taken out, and the types of ins1 and ins5, ins2 and ins6 and whether the input signals are from the same source are judged.

[0053] (6)Compare ins1 and ins5: Both are AND gates. One of the input signals is from the same source (signal a), and the other input signal is not from the same source (from ins3 and ins7, both of which are OR gates).

[0054] Store ins3 and ins7 into temp_vector1={ins3}, temp_vector2={ins7}; store the instances in temp_vector1 and temp_vector2 into the containers vector1 and vector2.

[0055] (7)Compare ins2 and ins6: Both are MUX2 gates, with the input from the same source, and no processing is done.

[0056] (8)The number of instances of vctor1 and vector2 is the same, and temp_vector1 and temp_vector2 are not empty. Take out the corresponding ins3 and ins7 respectively. At this time, vector1 = {ins3}, and vector2 = {ins7}.

[0057] (9)Compare ins3 and ins7: Both are OR gates. One input is from the same source (signal b); the other inputs come from the Q outputs of DFF1 and DFF2 respectively (through signal c). This meets the loop matching condition and no processing is required.

[0058] (10)At this time, the number of instances of vector1 and vector2 is 0. Therefore, it is determined that DFF1 and DFF2 are equivalent, and DFF1 and DFF2 are merged.

[0059] Through the above iterative comparison, the present invention can effectively judge the equivalence between DFFs with complex input logic cones and handle loop structures.

[0060] As described above, although the present invention has been shown and described with reference to specific preferred embodiments, it should not be construed as a limitation of the present invention itself. Various changes in form and detail may be made without departing from the spirit and scope of the present invention defined by the appended claims.

Claims

1. An optimized method for merging D flip - flops, applied to circuit designs containing multiple D flip - flops, is characterized in that, Including the following steps: S1: Select the first D flip-flop and the second D flip-flop of the same type in the circuit design as the pair to be compared; S2: Determine whether the clock signals and the preset control signals of the first D flip-flop and the second D flip-flop are all from the same source. If they are from the same source, go to S3; otherwise, determine that they are not equivalent; S3: Determine whether the data signals of the first D flip-flop and the second D flip-flop are from the same source, or both are from the outputs of their respective D flip-flops. If they are from the same source or both are from the outputs of their respective D flip-flops, determine that they are equivalent; otherwise, go to S4; S4: Iteratively perform a structural comparison on the logic cones driving the data signals of the first D flip-flop and the second D flip-flop. By comparing the types, quantities, and the sources of their input signals layer by layer until it is determined to be equivalent or not equivalent; S5: If it is determined to be equivalent, connect the output of the first D flip-flop to the receiving instance of the second D flip-flop, and delete the second D flip-flop.

2. The optimization method of the merged D flip-flop according to claim 1, characterized in that, The preset control signals in S2 include a set signal, a reset signal, and an enable signal.

3. The optimized method for merging D flip-flops according to claim 1, wherein The iterative structural comparison of the logic cone in step S4 includes: S401: Traverse the logic cones of the data signals of the first D flip-flop and the second D flip-flop forward in hierarchical breadth, obtain the source instances directly driving the data signals, and store them in the first container and the second container respectively; S402: Compare the quantities and types of the source instances in the first container and the second container. If they are inconsistent, determine that they are not equivalent; otherwise, go to S403; S403: Traverse each pair of source instances at the corresponding positions in the first container and the second container, and determine whether the input signals corresponding to the source instances are from the same source or from the outputs of their respective D flip-flops. If there are sources that are not from the same source and not from the outputs of their respective D flip-flops, store the source instances corresponding to the input signals in the first temporary container and the second temporary container respectively; S404: After the traversal is completed, if both the first temporary container and the second temporary container are empty, determine that they are equivalent; otherwise, go to S405; S405: Use the source instances in the first temporary container and the second temporary container to replace the contents in the first container and the second container respectively, empty the first temporary container and the second temporary container, and repeat steps S402 to S404 until it is determined to be equivalent or not equivalent.

4. The optimization method of the merged D flip-flop according to claim 3, characterized in that, The forward traversal in hierarchical breadth in step S401 includes: accessing the source instances in the logic cone one by one in hierarchical order until reaching the cone top or the traversal depth reaches a preset threshold. The logic cone includes a cone top and a cone bottom. The cone top is a register, a top-level output, or a black box input, and the cone bottom is a combinational logic circuit.

5. The optimization method of the merged D flip-flop according to claim 1, wherein When deleting the second D flip-flop in step S5, also delete the logic cone that drives the data terminal of the second D flip-flop and is not shared by other logics.

6. The optimization method of the merged D flip-flop according to claim 1, characterized in that The source instances do not include timing device instances, circuit top-level port instances, or module instances.

7. The optimization method of the merged D flip-flop according to claim 1, characterized in that, The method is applicable to a circuit including a loop structure composed of D flip-flops and combinational logics. The loop structure includes a circuit path where the output of the D flip-flop is fed back to its data terminal through combinational logics.

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