Layout wiring optimization method and device, computer equipment and storage medium

Abstract

The invention provides a layout and wiring optimization method and device, computer equipment and a storage medium, and belongs to the technical field of electronic design automation, the method comprises the following steps: receiving an architecture updating instruction, the architecture updating instruction at least carrying an optimization index of a target circuit area; obtaining a preset architecture model, wherein a plurality of basic algorithms, a plurality of scheduling logics and a plurality of packaging logics are stored in the architecture model; screening at least one scheduling logic according to the optimization index and the packaging logic; performing iterative optimization on the basic algorithm called by each scheduling logic based on the optimization index, and judging whether iteration continues or not according to a change value of the optimization index or an algorithm result; when it is judged that iteration is stopped, the optimized scheduling logic and the basic algorithm are packaged, and layout wiring corresponding to the target circuit area is generated and output. Through the processing scheme provided by the invention, the adaptability to different circuits is greatly improved, the maintenance cost is reduced, and the capability of improving the circuit function design in the later period is enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic design automation (EDA), and particularly to an optimization method, device, computer device and storage medium for placement and routing. Background Art

[0002] After placement or routing, it is necessary to optimize multiple metrics of the circuit based on the results of static timing analysis, which usually includes fixing timing constraint violations and converging timing, reducing circuit power consumption and cell occupancy area, and reducing signal crosstalk and noise after routing. In the above process, the automated circuit design tool calls multiple algorithms multiple times to optimize each metric one by one to find the best solution for optimizing the circuit. When a single algorithm converges in optimizing a single metric, the tool will switch to the next algorithm to continue optimizing the current metric, and iterate multiple rounds in this way until each algorithm can no longer further optimize the current metric.

[0003] The current design method of the tool has the following problems:

[0004] First, the implementation object of each algorithm is the entire layout, which is not disassembled to a more microscopic level. For example, it is impossible to optimize the pins of a certain cell. Macroscopically, this method can optimize the placement and routing to the limit that a single algorithm can reach; from a microscopic perspective, by repeatedly iterating a single algorithm to optimize a certain metric of the placement and routing, the metric will fall into a local optimum and cannot converge further.

[0005] Second, the traversal logic and optimization objectives of each algorithm for the cells in the layout are fixed, and the adjustment cost is relatively high. However, for each optimization stage of each metric in the existing requirements, the logic and optimization objectives of the algorithm for traversing each cell in the layout should be different. For example, compared with the method of first loosely optimizing all cells and then optimizing the cells with serious violations at the beginning of the optimization, directly optimizing all cells to convergence when the distance from convergence is far, since the initial states of all cells are poor, the number of iterations (running time) required will increase significantly.

[0006] Third, when implementing functional optimization on the circuit, multiple algorithms cannot be combined or their order cannot be adjusted for automatic optimization. Currently, when repairing design defects or improving functions of the circuit, engineers need to manually adjust the cell positions or insert buffers, and cannot use the tool to call a specified algorithm set to optimize a specified part of the circuit, resulting in relatively high time and labor costs. Summary of the Invention

[0007] Therefore, in order to overcome the above disadvantages of the prior art, the present invention provides an optimization method, device, computer device and storage medium for placement and routing, which can flexibly adjust each basic algorithm, scheduling logic, and encapsulation logic according to the requirements corresponding to the metrics, greatly improving the adaptability to different circuits, reducing the maintenance cost, and enhancing the ability to improve the circuit function design in the later stage.

[0008] To achieve the above object, the present invention provides an optimization method for layout and routing, including: receiving an architecture update instruction, where the architecture update instruction carries at least an optimization index of a target circuit area; obtaining a preset architecture model, where the architecture model stores multiple basic algorithms, multiple scheduling logics, and encapsulation logics, the basic algorithms are used to optimize a certain parameter index of a specific area, the scheduling logics are used to call at least one basic algorithm to optimize the parameter index of the target circuit area, the encapsulation logic includes a mapping relationship between the optimization index and the scheduling logic, and the target circuit area is not less than the specific area; screening at least one scheduling logic according to the optimization index and the encapsulation logic; iteratively optimizing the basic algorithms called by each scheduling logic based on the optimization index, and determining whether to continue the iteration according to the change value of the optimization index or the algorithm result; when it is determined to stop the iteration, encapsulating the optimized scheduling logic and the basic algorithm, and generating and outputting a layout and routing corresponding to the target circuit area.

[0009] In one embodiment, the iteratively optimizing the basic algorithms called by each scheduling logic based on the optimization index includes: determining the calling method of the basic algorithm in each scheduling logic; obtaining a corresponding candidate pin acquisition method and a candidate pin traversal method based on the scheduling logic; calling the candidate pin acquisition method to determine candidate pins, and traversing the candidate pins using the candidate pin traversal method; based on the calling method, calling the basic algorithm to optimize the candidate pins to obtain a change value or an algorithm result corresponding to the optimization index.

[0010] In one embodiment, the candidate pin acquisition method includes: screening paths with a timing margin less than the target timing margin in all data paths on the target circuit area as critical paths, and using the termination pins of the critical paths as candidate pins; or, selecting bottleneck pins with a timing margin less than the target timing margin on all data paths of the target circuit area as candidate pins; or, after stratifying the data paths of the target circuit area, selecting pins with a timing margin less than the target timing margin in each layer as candidate pins.

[0011] In one embodiment, the candidate pin traversal method includes: dividing the data paths in the target circuit area into multiple complementary and interleaved areas, taking the critical path corresponding to the area where the termination pin is located as the optimization object, traversing from the start pin of the critical path top-down, and calling the basic algorithm to optimize the critical path; or, dividing the data paths in the target circuit area into multiple non-interleaved areas, traversing the bottleneck pins in each area and calling the basic algorithm to perform optimization; or, stratifying the data paths in the target circuit area, distributing the candidate pins in each layer into multiple non-interleaved areas, traversing each layer from the start pin to the termination pin or vice versa, and calling the basic algorithm to perform optimization.

[0012] In one embodiment, the determination of whether to continue iteration according to the change value of the optimization metric or the algorithm result includes: after each round of iteration, multiplying the change value of the optimization metric or the algorithm result after the end of the previous round of optimization by a fixed coefficient with the target difference of the optimization metric to estimate the target of the current round of optimization; when the change value of the optimization metric or the algorithm result is greater than the estimated result or the number of iterations exceeds the upper limit, terminate the iteration; or, after each round of iteration, calculating the average difference of each optimization according to the change value of the optimization metric or the algorithm result, and terminating the iteration when the average difference is less than the preset threshold or the number of iterations exceeds the upper limit.

[0013] In one embodiment, the optimization metric is at least one of the total negative margin, the worst negative margin, and the optimized power and area.

[0014] In one embodiment, the screening of at least one scheduling logic according to the optimization metric and the packaging logic includes: obtaining at least one scheduling logic; modifying at least one of the candidate pin acquisition method, the candidate pin traversal method, and the optimization iteration method in the scheduling logic to generate a new scheduling logic; or assembling all the obtained scheduling logics to generate a new scheduling logic.

[0015] A layout and routing optimization device, the device comprising: an instruction receiving module, configured to receive an architecture update instruction, the architecture update instruction carrying at least an optimization metric for a target circuit area; an acquisition module, configured to acquire a preset architecture model, the architecture model storing a plurality of basic algorithms, a plurality of scheduling logics, and encapsulation logics, the basic algorithms being used to optimize a certain parameter metric of a specific area, the scheduling logics being used to call at least one basic algorithm to optimize the parameter metrics of the target circuit area, the encapsulation logics including the mapping relationship between the optimization metric and the scheduling logics, the target circuit area being not less than the specific area; a screening module, configured to screen at least one scheduling logic according to the optimization metric and the encapsulation logics; an optimization module, configured to iteratively optimize the basic algorithms called by each scheduling logic based on the optimization metric, and determine whether to continue iteration according to the change value of the optimization metric or the algorithm result; an encapsulation module, configured to, when it is determined to stop iteration, encapsulate the optimized scheduling logics and basic algorithms, and generate a layout and routing corresponding to the target circuit area and output it.

[0016] A computer device, comprising a memory and a processor, the memory storing a computer program, wherein when the processor executes the computer program, the steps of the above method are implemented.

[0017] A computer-readable storage medium, on which a computer program is stored, wherein when the computer program is executed by a processor, the steps of the above method are implemented.

[0018] Compared with the prior art, the advantages of the present invention are as follows: The scheduling logics are screened according to the optimization metric and the encapsulation logics, and the adaptability and pertinence are improved. Not only can the basic algorithms called by each scheduling logic be iteratively optimized and parameter control be added based on the optimization metric, but also the scheduling method and the organizational logic of the algorithms in the architecture model can be adjusted. Starting from the structure of the architecture model, a new set of optimization algorithms is reconstructed. This modular way improves the adaptability of the tool. And the maintenance cost is also reduced. For the optimization metric, only new encapsulation logics need to be added or the scheduling logics need to be adjusted separately, and the rest of the logic processing modules can still be reused. Therefore, the scope of adjustment during maintenance is small and the maintenance cost is low. In addition, the ability to improve the circuit function design is enhanced. Even when the circuit design needs to be changed or the circuit defects need to be repaired, the user does not need to manually adjust the unit positions or manually insert new units. For the area that needs to be optimized, the appropriate scheduling logics and basic algorithms are encapsulated to form new encapsulation logics, and the circuit can be automatically post-processed. Description of the Drawings

[0019] To more clearly illustrate the technical solutions of the embodiments of the present application, the accompanying drawings required for the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0020] Figure 1 is a schematic flowchart of the optimization method for layout and routing in the embodiments of the present invention;

[0021] Figure 2 is a flowchart of the architecture model in the embodiments of the present invention;

[0022] Figure 3 is a schematic flowchart of the iterative optimization steps in the embodiments of the present invention;

[0023] Figure 4 is a flowchart of the path-based scheduling method in the embodiments of the present invention;

[0024] Figure 5 is a structural block diagram of the layout and routing optimization device in an embodiment;

[0025] Figure 6 is an internal structure diagram of a computer device in an embodiment. Specific Embodiments

[0026] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0027] The following illustrates the implementation manners of the present application through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.

[0028] It should be noted that the following describes various aspects of embodiments within the scope of the present invention. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement a device and / or practice a method. Additionally, this device and / or method can be implemented using other structures and / or functionality in addition to one or more of the aspects set forth herein.

[0029] It should also be noted that the diagrams provided in the following embodiments only schematically illustrate the basic concept of this application. Only the components related to this application are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in its actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0030] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the aspects described can be practiced without these specific details.

[0031] As Figure 1 shown, an embodiment of this application provides an optimization method for layout and routing. This method can be applied to a terminal or a server. Among them, the terminal 102 can be, but is not limited to, various personal computers, laptop computers, smart phones, tablet computers, and portable intelligent devices. The server 104 can be implemented by an independent server or a server cluster composed of multiple servers. Taking the application of this method to a server as an example for illustration, it includes the following steps:

[0032] Step 101, receive an architecture update instruction, and this architecture update instruction carries at least an optimization metric for a target circuit area.

[0033] The architecture update instruction carries at least an optimization metric for a target circuit area. The server receives the architecture update instruction. The architecture update instruction can be issued by a user terminal.

[0034] In one embodiment, the optimization metrics include at least one of optimizing the total negative slack, optimizing the worst negative slack, and optimizing power and area. The total negative slack (TNS) is the sum of the negative slacks in all timing paths. A negative slack indicates that a signal cannot reach its destination within the specified time, resulting in a timing violation. The worst negative slack (WNS) is the worst negative slack among all timing paths, i.e., the path with the maximum delay. Power optimization: reducing the dynamic power consumption and static power consumption of the circuit. Area optimization: minimizing the area of the chip or PCB as much as possible while meeting the performance requirements.

[0035] When the optimization metrics simultaneously include optimizing the total negative slack, optimizing the worst negative slack, and optimizing power and area, as Figure 2 shown, the server can simultaneously optimize the total negative slack, optimize the worst negative slack, and optimize power and area, without the need for individual optimization, shortening the processing time. Moreover, the architecture model is abstracted into three layers, each layer is implemented independently and does not depend on each other, with high reusability.

[0036] The target circuit area can include at least one of the designed layout and wiring and circuit connection relationships within a specific area. The target circuit area can also include the pin arrangement within a specific area. Layout and wiring are key aspects in electronic design automation (EDA), which directly affect the performance, power consumption, and area of the circuit.

[0037] Step 102, obtain a preset architecture model. The architecture model stores multiple basic algorithms, multiple scheduling logics, and encapsulation logics. The basic algorithms are used to optimize a certain parameter index in a specific area. The scheduling logics are used to call at least one basic algorithm to optimize the parameter index of the target circuit area. The encapsulation logic includes the mapping relationship between the optimization metrics and the scheduling logics. The target circuit area is not smaller than the specific area.

[0038] The architecture model stores multiple basic algorithms, multiple scheduling logics, and encapsulation logics, and is also divided into three major levels: encapsulation logic, scheduling logic, and basic algorithm. The encapsulation logic can encapsulate multiple scheduling logics. The scheduling logic can call a single basic algorithm or a combination formed by multiple basic algorithms. When the target circuit area is not smaller than the specific area, the encapsulation logic can encapsulate a combination of multiple scheduling logics. The architecture model can be used for advanced process sizes such as 7nm, and can also be used for process sizes of 14nm and above, and can support the layout and wiring optimization of circuits with up to millions of units. The basic algorithms included in the architecture model are not limited, including but not limited to relocating units, duplicating units, inserting buffers, resynthesis, etc.

[0039] The basic algorithm is used to optimize a certain parameter index in a specific area. The basic algorithm is the smallest unit of the architecture model and is used to implement the algorithm for optimizing the upper-layer input pins. Anything from simple movement units or insertion buffers to complex re-logical synthesis of a region can be encapsulated in the basic algorithm. The essence of the basic algorithm is a microscopic single operator, and its specific behavior only includes optimizing the area it can cover and determining whether the changes improve the circuit's metrics. The way of obtaining pins and the way of traversing the circuit are both behaviors of the upper layer (scheduling logic). Therefore, this layer can achieve different optimization effects through any combination with the upper layer.

[0040] The scheduling logic is used to call at least one basic algorithm to optimize the parameter index of the target circuit area. The server can select a suitable algorithm group or algorithm combination as the basic algorithm according to its own characteristics and call it by the scheduling logic. The scheduling logic is responsible for obtaining candidate pins from the circuit, traversing the candidate pins, and calling a single or a group of algorithms for the pins. The scheduling logic has no association with the basic algorithm and can be combined with any reasonable basic algorithm.

[0041] The encapsulation logic contains the mapping relationship between the optimization metrics and the scheduling logic, and the target circuit area is not less than the specific area. Guided by the metrics to be optimized, the encapsulation logic selects a scheduling method that is beneficial to the optimization metrics as the scheduling logic. The main function of the encapsulation logic is to declare the combination of the scheduling logic and the basic algorithm to the tool, encapsulate them into a whole, and then execute each combination of the scheduling logic and the basic algorithm in the encapsulation order.

[0042] Step 103: Screen at least one scheduling logic according to the optimization metrics and the encapsulation logic.

[0043] The server screens at least one scheduling logic according to the optimization metrics and the encapsulation logic. The server can screen out at least one scheduling logic, then obtain the parameter data stored in the architecture model and optimize it; the server can also screen out at least one scheduling logic and then send it to the user terminal (the user terminal can be the terminal that issues the architecture update instruction or a third-party terminal), and the user terminal feeds back the parameter settings and the corresponding parameter data in the custom scheduling logic.

[0044] Step 104: Iteratively optimize the basic algorithms called by each scheduling logic based on the optimization metrics, and determine whether to continue the iteration according to the change value of the optimization metrics or the algorithm result.

[0045] The server iteratively optimizes the basic algorithms called by each scheduling logic based on the optimization metrics, and determines whether to continue the iteration according to the change value of the optimization metrics or the algorithm result. When the server enters the scheduling logic iteration, in each round of iteration, the scheduling logic first calls the candidate pin acquisition method to obtain the pins to be optimized, then traverses the candidate pins through the candidate pin traversal method bound to the scheduling logic, and calls the basic algorithm to perform optimization on the candidate pins; after the traversal ends, it is determined whether to enter the next round of scheduling logic iteration according to the change of the optimization metrics or the algorithm result.

[0046] Step 105, when it is determined to stop the iteration, encapsulate the optimized scheduling logic and the basic algorithm, and generate and output the layout and routing corresponding to the target circuit area.

[0047] When it is determined to stop the iteration, the server encapsulates the optimized scheduling logic and the basic algorithm, and generates and outputs the layout and routing corresponding to the target circuit area. Finally, the server can also restore the parameter data set in step 103, exit the scheduling logic and the encapsulation logic, and enter the next encapsulation logic to continue the optimization. There is no coupling between each type of scheduling logic and the basic algorithm, so the scheduling logic and the basic algorithm can be maintained separately, or new scheduling logic and basic algorithm can be added, and the sustainability is relatively strong. As Figure 2 shown, when the server optimizes the total negative margin, each type of basic algorithm is only responsible for optimizing a single pin passed in by the scheduling logic, and the acquisition of candidate pins and the traversal of candidate pins are implemented by the scheduling logic. Therefore, different scheduling logics and basic algorithms can be combined and encapsulated into the encapsulation logic to flexibly optimize different metrics.

[0048] For the above method, the scheduling logic is screened according to the optimization metrics and the encapsulation logic, and the adaptability and pertinence are improved. It can not only iteratively optimize the basic algorithms called by each scheduling logic based on the optimization metrics and add parameter control, but also adjust the scheduling method and the organizational logic of the algorithm in the architecture model. Starting from the structure of the architecture model, a new set of optimized algorithms is reconstructed. This modular method improves the adaptability of the tool. And the maintenance cost is also reduced. For the optimization metrics, only new encapsulation logic needs to be added, or the scheduling logic is adjusted separately, and the rest of the logic processing modules can still be reused. Therefore, the scope of adjustment during maintenance is small and the maintenance cost is low. In addition, the ability to improve the circuit function design is enhanced. Even when the circuit design needs to be changed or the circuit defects need to be repaired, the user does not need to manually adjust the unit position or manually insert new units. For the area that needs to be optimized, the appropriate scheduling logic and the basic algorithm are encapsulated to form a new encapsulation logic, and the circuit can be automatically post-processed.

[0049] As Figure 3 shown, in one embodiment, iteratively optimizing the basic algorithms called by each scheduling logic based on the optimization metrics includes the following steps:

[0050] Step 301, determine the calling methods of the basic algorithms in each scheduling logic.

[0051] The server determines the calling methods of the basic algorithms in each scheduling logic. The calling methods of multiple basic algorithms are divided into combined type and sequential type. Among them, in the combined type, multiple basic algorithms are regarded as a group, and the optimization results are evaluated after each basic algorithm is executed; in the sequential type, they are executed in sequence according to the added order. When a certain algorithm successfully optimizes the circuit, the next algorithm is not executed, but the next pin is continued to be optimized.

[0052] Step 302, obtain the corresponding candidate pin acquisition method and candidate pin traversal method based on the scheduling logic.

[0053] The server obtains the corresponding candidate pin acquisition method and candidate pin traversal method based on the scheduling logic. The main differences between different scheduling logics lie in the selection method of candidate pins, the traversal method when optimizing candidate pins, and the optimization iteration logic.

[0054] Step 303, call the candidate pin acquisition method to determine candidate pins, and use the candidate pin traversal method to traverse the candidate pins.

[0055] The server calls the candidate pin acquisition method to determine candidate pins, and uses the candidate pin traversal method to traverse the candidate pins. In one embodiment, the candidate pin acquisition method includes: i using the termination pin of the critical path as a candidate: screening the paths with a timing margin less than the target timing margin in all data paths in the target circuit area as the critical path, and using the termination pin of the critical path as the candidate pin; or, ii using the bottleneck pin as a candidate: selecting the bottleneck pin with a timing margin less than the target timing margin on all data paths in the target circuit area as the candidate pin; or, iii using the pins of a single layer as candidates: after stratifying the data paths in the target circuit area, selecting the pins with a timing margin less than the target timing margin in each layer as candidate pins. The timing margin (Slack) refers to the difference between the actual signal arrival time and the theoretically required time in timing analysis.

[0056] Step 304, based on the calling method, call the basic algorithm to optimize the candidate pins to obtain the change value corresponding to the optimization index or the algorithm result.

[0057] The server, based on the calling method, calls the basic algorithm to optimize the candidate pins to obtain the change value corresponding to the optimization index or the algorithm result. The optimization iteration logic of the server refers to the condition for determining whether to re-obtain candidate pins and enter the next round of iteration after optimizing the candidate pins.

[0058] In one embodiment, the server calls the basic algorithm to optimize the candidate pins, including the following optimization methods:

[0059] i. Path-based optimization method: Using the termination pin of the critical path as a candidate, traversing the critical path, and an iterative logic targeting the convergence metric, applicable to optimizing metrics such as the worst negative margin.

[0060] ii. Bottleneck pin-based optimization method: Using the bottleneck pin as a candidate, traversing the bottleneck pin, and an iterative logic targeting the convergence metric, applicable to be called when the metric is close to convergence.

[0061] iii. Hierarchical pin-based optimization method: Using the pins of a single layer as candidates, traversing the data path hierarchy, and an iterative logic targeting the convergence metric, applicable to algorithms with strong dependencies on the hierarchical order. For example, when replicating driving units to solve the fan-out problem, it is necessary to traverse hierarchically from the termination pin to the start pin. This optimization method can traverse forward from the lower level to the higher level or in reverse.

[0062] iv. Hierarchical bottleneck pin-based optimization method: Using the bottleneck pin as a candidate, traversing the data path hierarchy, and an iterative logic targeting the estimation result, applicable to be called when the metric is poor but the algorithm depends on the hierarchical order.

[0063] v. Optimization method for handling bottlenecks based on the estimation target: Using the bottleneck pin as a candidate, traversing the bottleneck pin, and an iterative logic targeting the estimation result, applicable to be called when the current metric is far from convergence and significant metric optimization is required.

[0064] For example, in one embodiment, the server is based on the path for Figure 4Optimize the circuit layout shown. In the initial state, Path 1 is the worst critical path, and Path 2 is the second worst. When the server obtains candidate termination pins through the scheduling logic, the D pin of Flip-Flop 6 is one of them (the other candidate termination pins are not shown in the figure, and this figure only shows all paths corresponding to a single termination pin). After traversing to Flip-Flop 6, the server first obtains the worst critical path (Path 1) related to the D pin of Flip-Flop 6 through the scheduling logic. Then, the server calls the first basic algorithm in the basic algorithm combination to optimize the path from the top to the bottom of the data path, that is, from Flip-Flop 1 to Flip-Flop 6. If all basic algorithms fail to optimize (there is no improvement in the target metric, or other metrics decline severely), the server continues to call the next basic algorithm in the basic algorithm combination to optimize the path through the scheduling logic. When a certain basic algorithm successfully optimizes a certain cell on the path, the server updates the static timing again through the scheduling logic to obtain the new worst critical path, which may be Path 2 or still Path 1 at this time, and then repeat the above steps to optimize the path. Until each basic algorithm in the basic algorithm combination fails to successfully optimize any cell on the path, the server continues to optimize the next termination pin in the candidate termination pins through the scheduling logic. When the optimization is completed, the server can store the scheduling logic and the optimized basic algorithm correspondingly to obtain the new packaging logic.

[0065] In one embodiment, the candidate pin traversal method includes the following methods:

[0066] i. Use the critical path as the traversal object: Divide the data path in the target circuit area into multiple complementary and interleaved areas, use the critical path corresponding to the termination pin in its area as the optimization object, traverse from the starting pin of the critical path from top to bottom, and call the basic algorithm to optimize the critical path. When receiving the signal that the pin optimization is successful, re-obtain the critical path corresponding to the termination pin and optimize it in the same way. Until the entire path is traversed and the basic algorithm still does not return the signal of successful optimization, the server determines that the critical path corresponding to the termination pin has reached the optimization bottleneck.

[0067] ii. Use the bottleneck pin as the traversal object: Divide the data path in the target circuit area into multiple non-interleaved areas, traverse the bottleneck pins in each area and call the basic algorithm to perform optimization.

[0068] iii. Use the data path level as the traversal object: Layer the data path in the target circuit area, allocate the candidate pins of each layer in multiple non-interleaved areas, traverse each layer from the starting pin to the termination pin or in the reverse direction, and call the basic algorithm to perform optimization.

[0069] In one embodiment, it is determined whether to continue iteration according to the change value of the optimization index or the algorithm result, including the following methods:

[0070] i. Iteration logic targeting the estimation result: After each round of iteration, multiply the change value of the optimization index or the algorithm result after the previous round of optimization by a fixed coefficient with the target difference of the optimization index to estimate the target of the current round of optimization; when the change value of the optimization index or the algorithm result is greater than the estimated result or the number of iterations exceeds the upper limit, terminate the iteration. This method is applicable when the index is far from the target, and algorithms such as optimizing fan-out violations that can significantly optimize the index are called to quickly bring the index closer to the target.

[0071] ii. Iteration logic targeting the convergence index: After each round of iteration, calculate the average difference of each optimization according to the change value of the optimization index or the algorithm result; when the average difference is less than the preset threshold or the number of iterations exceeds the upper limit, terminate the iteration. This method is applicable when using small-scale optimization algorithms for convergence towards the index.

[0072] In one embodiment, at least one scheduling logic is screened according to the optimization index and the packaging logic, including: obtaining at least one scheduling logic; modifying at least one of the candidate pin acquisition method, candidate pin traversal method, and optimization iteration method in the scheduling logic to generate a new scheduling logic; or assembling all the obtained scheduling logics to generate a new scheduling logic.

[0073] The server screens out at least one scheduling logic, then modifies at least one of the candidate pin acquisition method, candidate pin traversal method, and optimization iteration method in the scheduling logic to generate a new scheduling logic. The server can also assemble all the obtained scheduling logics to generate a new scheduling logic.

[0074] In one embodiment, as Figure 5 shown, a layout and routing optimization device is provided. The device includes an instruction receiving module 501, an acquisition module 502, a screening module 503, an optimization module 504, and a packaging module 505.

[0075] The instruction receiving module 501 is configured to receive an architecture update instruction, and the architecture update instruction carries at least the optimization index of the target circuit area.

[0076] The acquisition module 502 is configured to acquire a preset architecture model. The architecture model stores multiple basic algorithms, multiple scheduling logics, and packaging logics. The basic algorithms are used to optimize a certain parameter index of a specific area. The scheduling logics are used to call at least one basic algorithm to optimize the parameter index of the target circuit area. The packaging logic contains the mapping relationship between the optimization index and the scheduling logic. The target circuit area is not less than the specific area.

[0077] A screening module 503, configured to screen at least one scheduling logic according to an optimization metric and a packaging logic.

[0078] An optimization module 504, configured to iteratively optimize a basic algorithm invoked by each scheduling logic based on an optimization metric, and determine whether to continue the iteration according to a change value of the optimization metric or an algorithm result.

[0079] A packaging module 505, configured to, when it is determined to stop the iteration, package the optimized scheduling logic and the basic algorithm, and generate and output a layout and routing corresponding to a target circuit area.

[0080] In one embodiment, the optimization module 504 includes:

[0081] An invocation mode determination unit, configured to determine an invocation mode of a basic algorithm in each scheduling logic.

[0082] A method acquisition unit, configured to acquire a corresponding candidate pin acquisition method and a candidate pin traversal method based on the scheduling logic.

[0083] A pin traversal unit, configured to invoke a candidate pin acquisition method to determine candidate pins, and traverse the candidate pins by using a candidate pin traversal method.

[0084] An optimization unit, configured to, based on the invocation mode, invoke a basic algorithm to optimize the candidate pins, and obtain a change value or an algorithm result corresponding to the optimization metric.

[0085] In one embodiment, the optimization module 504 includes:

[0086] An estimation unit, configured to, after each round of iteration, multiply a change value or an algorithm result of the optimization metric after the end of the previous round of optimization by a fixed coefficient to estimate a target of the current round of optimization; when the change value or the algorithm result of the optimization metric is greater than the estimation result or the number of iterations exceeds an upper limit, terminate the iteration.

[0087] Alternatively, a calculation unit, configured to, after each round of iteration, calculate an average difference of each optimization according to a change value or an algorithm result of the optimization metric, and terminate the iteration when the average difference is less than a preset threshold or the number of iterations exceeds an upper limit.

[0088] In one embodiment, the screening module 503 includes:

[0089] A scheduling logic acquisition unit, configured to acquire at least one scheduling logic.

[0090] A scheduling logic generation unit, configured to modify at least one of a candidate pin acquisition method, a candidate pin traversal method, and an optimized iteration method in the scheduling logic to generate a new scheduling logic; or assemble all the acquired scheduling logics to generate a new scheduling logic.

[0091] For the specific limitations of the layout and routing optimization device, reference may be made to the limitations of the layout and routing optimization method in the foregoing text, which will not be elaborated here. Each module in the above layout and routing optimization device can be implemented in whole or in part by software, hardware, and their combination. Each of the above modules can be embedded in the processor of the computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so as to facilitate the processor to call and execute the operations corresponding to each of the above modules.

[0092] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as Figure 6 shown. The computer device includes a processor, a memory, a network interface, and a database connected by a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store architecture model data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, it implements a layout and routing optimization method.

[0093] In one embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program. When the processor executes the computer program, the following steps are implemented: receiving an architecture update instruction, where the architecture update instruction carries at least an optimization index of a target circuit area; obtaining a preset architecture model, where the architecture model stores a plurality of basic algorithms, a plurality of scheduling logics, and encapsulation logics. The basic algorithms are used to optimize a certain parameter index of a specific area, the scheduling logics are used to call at least one basic algorithm to optimize the parameter index of the target circuit area, the encapsulation logics include the mapping relationship between the optimization index and the scheduling logics, and the target circuit area is not less than the specific area; screening at least one scheduling logic according to the optimization index and the encapsulation logics; iteratively optimizing the basic algorithms called by each scheduling logic based on the optimization index, and determining whether to continue the iteration according to the change value of the optimization index or the algorithm result; when it is determined to stop the iteration, encapsulate the optimized scheduling logics and basic algorithms, and generate and output a layout and routing corresponding to the target circuit area.

[0094] In one embodiment, when the processor executes a computer program, an iterative optimization of the basic algorithms called by each scheduling logic is implemented based on an optimization metric, including: determining the calling manner of the basic algorithms in each scheduling logic; obtaining the corresponding candidate pin acquisition method and candidate pin traversal method based on the scheduling logic; calling the candidate pin acquisition method to determine candidate pins, and traversing the candidate pins by using the candidate pin traversal method; and based on the calling manner, calling the basic algorithm to optimize the candidate pins to obtain a change value corresponding to the optimization metric or an algorithm result.

[0095] In one embodiment, the candidate pin acquisition method implemented when the processor executes a computer program includes: screening paths with a timing margin less than a target timing margin in all data paths on a target circuit area as critical paths, and using the termination pins of the critical paths as candidate pins; alternatively, selecting bottleneck pins with a timing margin less than the target timing margin on all data paths of the target circuit area as candidate pins; or after stratifying the data paths of the target circuit area, selecting pins with a timing margin less than the target timing margin in each layer as candidate pins.

[0096] In one embodiment, the candidate pin traversal method implemented when the processor executes a computer program includes: dividing the data paths in a target circuit area into multiple complementary and interleaved areas, using the critical path corresponding to the termination pin in its area as the optimization object, traversing from the start pin of the critical path top-down, and calling the basic algorithm to optimize the critical path; or dividing the data paths in the target circuit area into multiple non-interleaved areas, traversing the bottleneck pins in each area and calling the basic algorithm to perform optimization; or stratifying the data paths in the target circuit area, allocating the candidate pins in each layer to multiple non-interleaved areas, traversing each layer from the start pin to the termination pin or in the reverse direction, and calling the basic algorithm to perform optimization.

[0097] In one embodiment, determining whether to continue iteration according to the change value of the optimization metric or the algorithm result when the processor executes a computer program includes: after each round of iteration, multiplying the change value of the optimization metric or the algorithm result after the end of the previous round of optimization by a fixed coefficient with the target difference of the optimization metric to estimate the target of the current round of optimization; when the change value of the optimization metric or the algorithm result is greater than the estimated result or the number of iterations exceeds the upper limit, terminating the iteration; or after each round of iteration, calculating the average difference of each optimization according to the change value of the optimization metric or the algorithm result, and terminating the iteration when the average difference is less than a preset threshold or the number of iterations exceeds the upper limit.

[0098] In one embodiment, when the processor executes a computer program, screening at least one scheduling logic according to an optimization metric and packaging logic includes: obtaining at least one scheduling logic; modifying at least one of a candidate pin acquisition method, a candidate pin traversal method, and an optimization iteration method in the scheduling logic to generate a new scheduling logic; or assembling all the obtained scheduling logics to generate a new scheduling logic.

[0099] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented: receiving an architecture update instruction that carries at least an optimization metric of a target circuit area; obtaining a preset architecture model that stores a plurality of basic algorithms, a plurality of scheduling logics, and packaging logic, where the basic algorithms are used to optimize a certain parameter metric of a specific area, the scheduling logics are used to call at least one basic algorithm to optimize the parameter metrics of the target circuit area, the packaging logic includes a mapping relationship between the optimization metric and the scheduling logic, and the target circuit area is not less than the specific area; screening at least one scheduling logic according to the optimization metric and the packaging logic; iteratively optimizing the basic algorithms called by each scheduling logic based on the optimization metric, and determining whether to continue the iteration according to the change value of the optimization metric or the algorithm result; when it is determined to stop the iteration, packaging the optimized scheduling logic and the basic algorithms, and generating and outputting a layout and routing corresponding to the target circuit area.

[0100] In one embodiment, when the computer program is executed by a processor, iteratively optimizing the basic algorithms called by each scheduling logic based on the optimization metric includes: determining the calling method of the basic algorithms in each scheduling logic; obtaining the corresponding candidate pin acquisition method and candidate pin traversal method based on the scheduling logic; calling the candidate pin acquisition method to determine candidate pins, and traversing the candidate pins using the candidate pin traversal method; based on the calling method, calling the basic algorithms to optimize the candidate pins to obtain a change value or an algorithm result corresponding to the optimization metric.

[0101] In one embodiment, the candidate pin acquisition method implemented when the computer program is executed by a processor includes: screening paths with a timing margin less than the target timing margin in all data paths on the target circuit area as critical paths, and using the termination pins of the critical paths as candidate pins; or selecting bottleneck pins with a timing margin less than the target timing margin on all data paths of the target circuit area as candidate pins; or after stratifying the data paths of the target circuit area, selecting pins with a timing margin less than the target timing margin in each layer as candidate pins.

[0102] In one embodiment, the candidate pin traversal method implemented when the computer program is executed by a processor includes: dividing the data paths in the target circuit area into multiple complementary interleaved areas, taking the critical path corresponding to the area where the pin is located as the optimization object, traversing from the starting pin of the critical path top-down, and calling the basic algorithm to optimize the critical path; or, dividing the data paths in the target circuit area into multiple non-interleaved areas, traversing the bottleneck pins in each area and calling the basic algorithm to perform optimization; or, stratifying the data paths in the target circuit area, allocating the candidate pins of each layer in multiple non-interleaved areas, traversing each layer from the starting pin to the ending pin or vice versa, and calling the basic algorithm to perform optimization.

[0103] In one embodiment, judging whether to continue iteration according to the change value of the optimization index or the algorithm result when the computer program is executed by a processor includes: after each round of iteration, multiplying the change value of the optimization index or the algorithm result after the previous round of optimization by a fixed coefficient with the target difference of the optimization index to estimate the target of the current round of optimization; when the change value of the optimization index or the algorithm result is greater than the estimated result or the number of iterations exceeds the upper limit, terminate the iteration; or, after each round of iteration, calculating the average difference of each optimization according to the change value of the optimization index or the algorithm result, and terminating the iteration when the average difference is less than the preset threshold or the number of iterations exceeds the upper limit.

[0104] In one embodiment, screening at least one scheduling logic according to the optimization index and the packaging logic when the computer program is executed by a processor includes: obtaining at least one scheduling logic; modifying at least one of the candidate pin acquisition method, the candidate pin traversal method, and the optimization iteration method in the scheduling logic to generate a new scheduling logic; or assembling all the obtained scheduling logics to generate a new scheduling logic.

[0105] As described above, the above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present application should be covered by the protection scope of the present application.

Claims

1. An optimization method for layout and routing, characterized in that, Including: Receiving an architecture update instruction that carries at least an optimization metric for a target circuit area; Obtaining a preset architecture model, which stores a plurality of basic algorithms, a plurality of scheduling logics, and encapsulation logics. The basic algorithms are used to optimize a certain parameter metric of a specific area. The scheduling logics are used to call at least one basic algorithm to optimize the parameter metrics of the target circuit area. The encapsulation logic contains the mapping relationship between the optimization metric and the scheduling logic. The target circuit area is not smaller than the specific area; Filtering at least one scheduling logic according to the optimization metric and the encapsulation logic; Iteratively optimizing the basic algorithms called by each scheduling logic based on the optimization metric, and judging whether to continue the iteration according to the change value of the optimization metric or the algorithm result; When it is determined to stop the iteration, encapsulate the optimized scheduling logic and basic algorithms, and generate and output the layout and routing corresponding to the target circuit area.

2. The optimization method according to claim 1, wherein The iteratively optimizing the basic algorithms called by each scheduling logic based on the optimization metric includes: Determining the calling mode of the basic algorithms in each scheduling logic; Obtaining a corresponding candidate pin acquisition method and a candidate pin traversal method based on the scheduling logic; Calling the candidate pin acquisition method to determine candidate pins, and traversing the candidate pins using the candidate pin traversal method; Based on the calling mode, calling the basic algorithm to optimize the candidate pins to obtain the change value or algorithm result corresponding to the optimization metric.

3. The optimization algorithm according to claim 2, wherein The candidate pin acquisition method includes: Filtering the paths with a timing margin smaller than the target timing margin in all data paths on the target circuit area as critical paths, and using the termination pins of the critical paths as candidate pins; Or, selecting the bottleneck pins with a timing margin smaller than the target timing margin on all data paths of the target circuit area as candidate pins; Or, after stratifying the data paths of the target circuit area, selecting the pins with a timing margin smaller than the target timing margin in each layer as candidate pins.

4. The optimization algorithm according to claim 2, wherein The candidate pin traversal method includes: Dividing the data paths in the target circuit area into multiple complementary and interleaved areas, using the critical path corresponding to the termination pin in its area as the optimization object, traversing from the start pin of the critical path from top to bottom, and calling the basic algorithm to optimize the critical path; Or, dividing the data paths in the target circuit area into multiple non-interleaved areas, traversing the bottleneck pins in each area and calling the basic algorithm to perform optimization; Or, stratifying the data paths in the target circuit area, allocating the candidate pins in each layer to multiple non-interleaved areas, traversing each layer from the start pin to the termination pin or in the reverse direction, and calling the basic algorithm to perform optimization.

5. The optimization algorithm according to claim 1, wherein The judging whether to continue the iteration according to the change value of the optimization metric or the algorithm result includes: After each iteration, multiply the change value of the optimization metric or the algorithm result after the end of the previous round of optimization by a fixed coefficient with the target difference of the optimization metric to estimate the target of the current round of optimization; when the change value of the optimization metric or the algorithm result is greater than the estimated result or the number of iterations exceeds the upper limit, terminate the iteration. Alternatively, after each iteration, calculate the average difference of each optimization based on the change value of the optimization metric or the algorithm result, and terminate the iteration when the average difference is less than a preset threshold or the number of iterations exceeds the upper limit.

6. The optimization algorithm according to claim 1, wherein The optimization metric is at least one of the total negative margin, the worst negative margin, and the power and area.

7. The optimization algorithm according to claim 1, wherein The screening of at least one scheduling logic according to the optimization metric and the encapsulation logic includes: Obtain at least one scheduling logic; Modify at least one of the candidate pin acquisition method, the candidate pin traversal method, and the optimized iteration method in the scheduling logic to generate a new scheduling logic; or assemble all the obtained scheduling logics to generate a new scheduling logic.

8. A layout and routing optimization device, characterized in that The device includes: An instruction receiving module, configured to receive an architecture update instruction, where the architecture update instruction carries at least the optimization metric of the target circuit area; An acquisition module, configured to acquire a preset architecture model, where the architecture model stores a plurality of basic algorithms, a plurality of scheduling logics, and encapsulation logic, the basic algorithms are used to optimize a certain parameter index of a specific area, the scheduling logics are used to call at least one basic algorithm to optimize the parameter index of the target circuit area, the encapsulation logic includes the mapping relationship between the optimization metric and the scheduling logic, and the target circuit area is not less than the specific area; A screening module, configured to screen at least one scheduling logic according to the optimization metric and the encapsulation logic; An optimization module, configured to iteratively optimize the basic algorithms called by each scheduling logic based on the optimization metric, and determine whether to continue the iteration according to the change value of the optimization metric or the algorithm result; An encapsulation module, configured to, when it is determined to stop the iteration, encapsulate the optimized scheduling logic and the basic algorithms, and generate and output a layout and routing corresponding to the target circuit area.

9. A computer device, comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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