Memristive neural network circuit based on competitive learning mechanism

Abstract

The invention discloses a memristive neural network circuit based on a competitive learning mechanism. The memristive neural network circuit comprises a forward calculation module and a reverse adjustment module. Wherein the forward calculation module is composed of a memristor cross array module and a leakage integration and discharge module, and the reverse adjustment module is composed of a weight adjustment module. The forward calculation module realizes transverse suppression and competition activation between two neurons through a win-win algorithm, and for each input, only one neuron successfully competes and then an output signal is generated. And the reverse adjustment module performs neuron weight adjustment through a Hertz learning rule to realize self-learning, receives an output signal of the forward calculation module, and then generates an adjustment signal to the forward calculation module to adjust the weight of a winning neuron. Therefore, the memristive neural network circuit based on the competitive learning mechanism provided by the invention can learn the input data and classify the input data after learning is completed.

Description

Technical Field

[0001] The present invention relates to the field of memristive neural network circuit design, and particularly to a memristive neural network circuit based on a competitive learning mechanism. Background Art

[0002] As an important branch of artificial neural networks, competitive learning neural networks simulate the competitive activation and self-learning behaviors of neurons in biological neural networks. Competitive learning includes two parts: forward calculation and backward adjustment. The forward calculation part can achieve competitive activation through the winner-takes-all algorithm, and the backward adjustment part can adjust the neuron weights through the Hebbian learning rule to achieve self-learning. Through the characteristics of competitive activation and self-learning, competitive neural networks can effectively reveal the hidden structure in data and are applicable to applications such as data classification, pattern recognition, and feature compression.

[0003] The winner-takes-all algorithm draws on the lateral inhibition and competitive activation mechanisms in biological neural networks. The working principle of this algorithm is as Figure 1 shown. Neurons in the competitive layer have the function of lateral inhibition, which can inhibit the outputs of other neurons. Each time, only one neuron can win and output. Since each input data contains different features and the weights of the synapses are also different, the responses of each neuron are different. For example, for the same input, if the response speed of neuron 2 is higher than that of neuron 4, then neuron 2 first reaches the firing threshold and inhibits neuron 4 from generating an output through the lateral inhibition function. Therefore, only neuron 2 competes successfully and generates an output; conversely, if the response speed of neuron 4 is higher than that of neuron 2, then only neuron 4 competes successfully and generates an output.

[0004] The Hebbian learning rule is applicable to the weight adjustment of neural networks. The content of this rule is as follows: The front and rear neurons are connected by a synapse, and the synapse has a weight. When both the front and rear neurons are active, the weight increases; when the front neuron is inactive and the rear neuron is active, the weight decreases; when the rear neuron is inactive, the weight remains unchanged regardless of whether the front neuron is active or not.

[0005] Traditional computers adopt the von Neumann architecture with separate memory and computing units. The frequent data transmission between its storage and computing units leads to high latency and high power consumption, and the current semiconductor process is gradually approaching the physical limit, resulting in a slowdown in the growth rate of computer performance. Therefore, neural networks implemented based on computer software are restricted. The neural network hardware circuit that simulates the biological brain can achieve in-memory computing, perform efficient information processing and adaptive learning, and has advantages such as low power consumption, high parallelism, and real-time processing, breaking through the von Neumann bottleneck problem.

[0006] Memristors are currently ideal devices for simulating biological brains to construct neural network circuits. The resistance value of a memristor is plastic and changes with the applied electric field; when the direction of the applied electric field is opposite, the resistance value of the memristor changes in the opposite way. Memristors also have characteristics such as nanoscale size, low power consumption, and compatibility with CMOS transistors, and can be applied to large-scale integrated circuits. Therefore, neural network circuits based on memristors have broad application prospects in improving computer performance and promoting the development of artificial intelligence, etc.

[0007] Competitive learning mechanisms have been widely applied in fields such as data classification, pattern recognition, and feature compression. However, most current related research uses computer software to construct neural networks, and rarely uses hardware circuits to construct neural networks. Implementing a competitive learning neural network in hardware through memristors can improve computational efficiency and reduce energy consumption at the same time.

[0008] Based on the plasticity of the resistance value of memristors, the present invention proposes a memristive neural network circuit based on a competitive learning mechanism. Different from previous research that realizes a competitive learning neural network through software algorithms, the present invention realizes a competitive learning neural network through a memristive hardware circuit and applies it to data classification, providing a certain reference for the hardware implementation of memristive neural network circuits. Summary of the Invention

[0009] The present invention proposes a memristive neural network circuit based on a competitive learning mechanism. A neural network circuit is constructed using the plasticity of the resistance value of memristors to simulate the competitive learning mechanism in neurons, and the circuit is used for data classification.

[0010] The present invention is realized through the following technical solutions: A memristive neural network circuit based on a competitive learning mechanism, which includes a forward calculation module and a reverse adjustment module. Among them, the forward calculation module is composed of a memristive crossbar array module and a leaky integrate-and-fire module, and the reverse adjustment module is composed of a weight adjustment module, as Figure 2 shown.

[0011] After receiving the input signal, the memristive crossbar array module outputs current to the leaky integrate-and-fire module. The memristive crossbar array module is composed of eight memristors M a1 -M a4 and M b1 -M b4 constitute. The memristors are arranged in four rows and two columns. Four input signals V in1 -V in4 are respectively connected to the memristors in four rows. The memristors in the same row receive the same input signal. After receiving the input signal, the memristors generate current. The end current of each column of memristors is the sum of the currents of the four memristors in that column. The resistance values of each memristor are different, so the end currents of each column are different. The first column of memristors and the leaky integrate-and-fire module 1 constitute neuron 1, and the second column of memristors and the leaky integrate-and-fire module 2 constitute neuron 2.

[0012] The leakage integration and firing module includes Module 1 and Module 2. The two modules correspond to two competing neurons, which have the same circuit structure. They receive the output current of the memristive crossbar array module and then generate output signals V O1 and V O2 . The leakage integration and firing module is composed of NMOS transistors N1 - N6, voltage - controlled switches S1, S2, resistors R1 - R12, capacitors C1, C2, operational amplifiers A1 - A4, voltage comparators COMP1, COMP2 and voltage sources. For Module 1, V f and V f1 come from the weight adjustment module and do not participate in the forward calculation process. In the forward calculation, V f and V f1 are 0. Therefore, NMOS transistors N1 and N2 are turned off, and the 5V voltage source is applied to the positive control terminal of the voltage - controlled switch S1 through the resistor R1, making the voltage - controlled switch S1 conduct. The end - of - column current of the first column of the memristive crossbar array module acts on the amplifier circuit composed of operational amplifiers A1 and A2 through the voltage - controlled switch S1, and then a voltage is generated at the output terminal of the operational amplifier A2. Therefore, an integrated voltage is generated on the capacitor C1. Similarly, for Module 2, an integrated voltage is generated on the capacitor C2. The output of the voltage comparator COMP1 is connected to the gate of the NMOS transistor N6 in Module 2, and the output of the voltage comparator COMP2 is connected to the gate of the NMOS transistor N3 in Module 1. If the integrated voltage of the capacitor C1 reaches the threshold voltage V th faster than the integrated voltage of the capacitor C2, then the voltage comparator COMP1 first outputs a high level. Therefore, Module 1 generates a high - level output signal V O1 and the NMOS transistor N6 conducts. Then, the integrated voltage of the capacitor C2 is discharged to the ground through the NMOS transistor N6, and the voltage comparator COMP2 can only output a low level, that is, the output signal V O2 of Module 2 is inhibited to a low level by Module 1. This is the process in which Module 1 wins the competition and generates the output signal V O1 , simulating the mechanism of lateral inhibition and competitive activation of neurons. Similarly, if the integrated voltage of the capacitor C2 reaches the threshold voltage V th faster than the integrated voltage of the capacitor C1, then the voltage comparator COMP2 first outputs a high level. Therefore, Module 2 wins the competition and generates the output signal V O2 , and the output signal V O1 of Module 1 is inhibited to a low level by Module 2.

[0013] The weight adjustment module includes Module 1 and Module 2. The circuit structures of the two modules are the same. They receive the output signals of the leakage integration and discharge module and then generate adjustment signals. The weight adjustment module consists of monostable flip-flops 74121A - 74121F, resistors R13 - R24, capacitors C3 - C8, voltage-controlled switches S3 - S6, summers SUM1 - SUM3, a voltage source, and an absolute value module ABS. In weight adjustment module 1, monostable flip-flop 74121A receives the output signal V O1 , and it is triggered at the rising edge of V O1 and generates a delay signal V Q1 with a pulse width of t1 = 0.7∙R13∙C3. Monostable flip-flop 74121B receives V Q1 , and it is triggered at the falling edge of V Q1 , and through voltage-controlled switch S3, it generates a delay signal V Q2 with an amplitude of 6V and a pulse width of t2 = 0.7∙R14∙C4. Monostable flip-flop 74121C receives V Q2 , and it is triggered at the falling edge of V Q2 , and through voltage-controlled switch S4, it generates a delay signal V Q3 with an amplitude of -6V and a pulse width of t3 = 0.7∙R15∙C5. V Q2 and V Q3 generate an adjustment signal V f1 after passing through adder SUM1. Similarly, weight adjustment module 2 generates an adjustment signal V f2 . V f1 and V f2 generate a signal V f after passing through adder SUM3 and absolute value module ABS. Signal V f is shared by the leakage integration and discharge modules 1 and 2. If the leakage integration and discharge module 1 wins, then the weight adjustment module 1 will generate an output signal V f1 while the weight adjustment module 2 has no output signal V f2 . V f causes the NMOS transistors N1, N2, N4, and N5 in the leakage integration and discharge module to conduct, and then the voltage-controlled switches S1 and S2 are turned off. Therefore, the leakage integration and discharge modules 1 and 2 stop receiving input signals from the memristor crossbar array module. NMOS transistors N2 and N5 provide discharge channels for capacitors C1 and C2. The adjustment signal V f1It is applied to the negative end of the memristors in the first column, so the voltage across the memristors changes. The reciprocal of the memristor resistance represents the weight. When the voltage exceeds the positive threshold of the memristor, the memristor resistance decreases, that is, the weight increases; when the voltage exceeds the negative threshold of the memristor, the memristor resistance increases, that is, the weight decreases. There is no adjustment signal at the negative end of the memristors in the second column, so the memristors do not change, that is, the weights remain unchanged. Similarly, if the leakage integration and discharge module 2 wins, the weight adjustment module 2 will generate an output signal V f2 while the weight adjustment module 1 has no output signal V f1 , so only the resistance values of the memristors in the second column change. When the resistance values of all memristors reach a steady state, that is, the resistance values reach the maximum or minimum values, it indicates that the memristive neural network circuit has completed learning. Description of the Drawings

[0014] Figure 1 is the schematic diagram of the winner-takes-all algorithm.

[0015] Figure 2 is the memristive neural network circuit based on the competitive learning mechanism.

[0016] Figure 3 is the external shape diagram of two kinds of iris flowers.

[0017] Figure 4 is the data distribution diagram of two kinds of iris flowers.

[0018] Figure 5 is the initial resistance value diagram of the memristor.

[0019] Figure 6 is the input signal simulation diagram.

[0020] Figure 7 is the simulation diagram of the capacitor voltage and the output signal.

[0021] Figure 8 is the voltage simulation diagram of the memristors in the second column.

[0022] Figure 9 is the resistance value change diagram of the memristors in the second column.

[0023] Figure 10 is the resistance value diagram of the memristor after training is completed.

[0024] Figure 11 is the simulation diagram of the capacitor voltage and the output signal after inputting the data of Iris setosa.

[0025] Figure 12 is the simulation diagram of the capacitor voltage and the output signal after inputting the data of Iris virginica. Detailed Implementation Manner

[0026] To make the technical solutions, objectives, and advantages of the present invention clearer and more explicit, the present invention will be further described in detail below with reference to the accompanying drawings.

[0027] As Figure 2 shown, the present invention provides a memristive neural network circuit based on a competitive learning mechanism, which includes a forward calculation module and a reverse adjustment module. Among them, the forward calculation module is composed of a memristive crossbar array module and a leaky integrate-and-fire module, and the reverse adjustment module is composed of a weight adjustment module. After the circuit is trained, it can be used for data classification.

[0028] As Figure 2 shown, the memristive crossbar array module is composed of memristors M a1 -M a4 and M b1 -M b4 The positive terminals of memristors M a1 and M b1 are connected in parallel and then connected to the input signal V in1 at node 1. The positive terminals of memristors M a2 and M b2 are connected in parallel and then connected to the input signal V in2 at node 2. The positive terminals of memristors M a3 and M b3 are connected in parallel and then connected to the input signal V in3 at node 3. The positive terminals of memristors M a4 and M b4 are connected in parallel and then connected to the input signal V in4 at node 4. The negative terminals of memristors M a1 -M a4 are connected in parallel and then connected to the input terminal of the voltage-controlled switch S1 at node 5. The negative terminals of memristors M b1 -M b4 are connected in parallel and then connected to the input terminal of the voltage-controlled switch S2 at node 6. The adjustment signal V f1 is connected to node 5, and the adjustment signal V f2 is connected to node 6.

[0029] As Figure 2 shown, the leaky integrate-and-fire module is composed of NMOS transistors N1-N6, voltage-controlled switches S1 and S2, resistors R1-R12, capacitors C1 and C2, operational amplifiers A1-A4, voltage comparators COMP1, COMP2, and voltage sources. The source of NMOS transistor N1 is grounded, the gate of NMOS transistor N1 is connected to the signal V f , one end of resistor R1 and the positive control terminal of voltage-controlled switch S1 are connected in parallel to node 7 and connected to the drain of NMOS transistor N1, the other end of resistor R1 is connected to the positive terminal of the 5V voltage source, the negative terminal of the 5V voltage source is grounded, and the negative control terminal of voltage-controlled switch S1 is grounded. Memristor Ma1 -M a4 The negative terminals of -M are connected in parallel and then connected to the input terminal of voltage-controlled switch S1 at node 5. The output terminal of voltage-controlled switch S1 and one end of resistor R2 are connected in parallel at node 8 and connected to the inverting input terminal of operational amplifier A1. The non-inverting input terminal of operational amplifier A1 is grounded. The other end of resistor R2 and one end of resistor R3 are connected in parallel at node 9 and connected to the output terminal of operational amplifier A1. The other end of resistor R3 and one end of resistor R4 are connected in parallel at node 10 and connected to the inverting input terminal of operational amplifier A2. The non-inverting input terminal of operational amplifier A2 is grounded. The other end of resistor R4, one end of resistor R5, and the drain of NMOS transistor N2 are connected in parallel to the output terminal of operational amplifier A2 at node 11. The source of NMOS transistor N2 is grounded, and the gate of NMOS transistor N2 is connected to signal V f . The source of NMOS transistor N3 is grounded, and the gate of NMOS transistor N3 and one end of resistor R12 are connected at node 20; the other end of resistor R5, the drain of NMOS transistor N3, and one end of capacitor C1 are connected in parallel to the non-inverting input terminal of voltage comparator COMP1 at node 12; the inverting input terminal of voltage comparator COMP1 is connected to voltage source V th . The positive power supply pin of voltage comparator COMP1 is connected to a 6V voltage source, the negative power supply pin of voltage comparator COMP1 is grounded, one end of resistor R6 and the gate of NMOS transistor N6 are connected in parallel to the output terminal of voltage comparator COMP1 at node 13, and the output terminal of voltage comparator COMP1 outputs signal V O1 . The source of NMOS transistor N4 is grounded, the gate of NMOS transistor N4 is connected to signal V f . One end of resistor R7 and the positive control terminal of voltage-controlled switch S2 are connected in parallel at node 14 and connected to the drain of NMOS transistor N4. The other end of resistor R7 is connected to the positive terminal of a 5V voltage source, the negative terminal of the 5V voltage source is grounded, and the negative control terminal of voltage-controlled switch S2 is grounded. Memristor M b1 -M b4The negative terminals are connected in parallel and then connected to the input terminal of the voltage-controlled switch S2 at node 6. The output terminal of the voltage-controlled switch S2 and one end of the resistor R8 are connected in parallel to node 15 and connected to the inverting input terminal of the operational amplifier A3. The non-inverting input terminal of the operational amplifier A3 is grounded. The other end of the resistor R8 and one end of the resistor R9 are connected in parallel to node 16 and connected to the output terminal of the operational amplifier A1. The other end of the resistor R9 and one end of the resistor R10 are connected in parallel to node 17 and connected to the inverting input terminal of the operational amplifier A4. The non-inverting input terminal of the operational amplifier A4 is grounded. The other end of the resistor R10, one end of the resistor R11, and the drain of the NMOS transistor N5 are connected in parallel to the output terminal of the operational amplifier A4 at node 18. The source of the NMOS transistor N5 is grounded, and the gate of the NMOS transistor N5 is connected to the signal V f connected. The source of the NMOS transistor N6 is grounded, and the gate of the NMOS transistor N6 and one end of the resistor R6 are connected to node 13; the other end of the resistor R11, the drain of the NMOS transistor N6, and one end of the capacitor C2 are connected in parallel to the non-inverting input terminal of the voltage comparator COMP2 at node 19. The inverting input terminal of the voltage comparator COMP2 is connected to the voltage source V th connected. The positive power supply pin of the voltage comparator COMP2 is connected to a 6V voltage source, the negative power supply pin of the voltage comparator COMP2 is grounded, one end of the resistor R12 and the gate of the NMOS transistor N3 are connected in parallel to the output terminal of the voltage comparator COMP2 at node 20, and the output terminal of the voltage comparator COMP2 outputs the signal V O2 .

[0030] As Figure 2 shown, the weight adjustment module consists of monostable flip-flops 74121A - 74121F, resistors R13 - R24, capacitors C3 - C8, voltage-controlled switches S3 - S6, summers SUM1 - SUM3, voltage sources, and an absolute value module ABS. The signal V O1 is connected to the B pin of the monostable flip-flop 74121A. The A1 and A2 pins of 74121A are grounded. The V cc pin of 74121A and one end of the resistor R13 are connected in parallel to the positive terminal of the 5V voltage source at node 21. The negative terminal of the 5V voltage source is grounded. The other end of the resistor R13 and one end of the capacitor C3 are connected in parallel to the R ext / C ext pin of 74121A at node 22. The other end of the capacitor C3 is connected to the C extThe pins are connected. The Q pin of 74121A and one end of resistor R16 are connected to the A1 and A2 pins of 74121B in parallel at node 23, and the other end of resistor R16 is grounded. The B pin of 74121B is connected to the positive terminal of the 5V voltage source, the negative terminal of the 5V voltage source is grounded, and the V cc pin of 74121B and one end of resistor R14 are connected to the positive terminal of the 5V voltage source in parallel at node 24, the negative terminal of the 5V voltage source is grounded, and the other end of resistor R14 and one end of capacitor C4 are connected to the R ext / C ext pin of 74121B at node 25, and the other end of capacitor C4 is connected to the C ext pin of 74121B. The Q pin of 74121B is connected to the positive control terminal of voltage-controlled switch S3, the negative control terminal of voltage-controlled switch S3 is grounded, the input terminal of voltage-controlled switch S3 is connected to the positive terminal of the 6V voltage source, the negative terminal of the 6V voltage source is grounded, and the output terminal of voltage-controlled switch S3 and one end of resistor R17 are connected to port 2 of summing amplifier SUM1 in parallel at node 26, and the other end of resistor R17 is grounded. The A1 and A2 pins of 74121C are connected to node 26, the B pin of 74121C is connected to the positive terminal of the 5V voltage source, the negative terminal of the 5V voltage source is grounded, and the V cc pin of 74121C and one end of resistor R15 are connected to the positive terminal of the 5V voltage source in parallel at node 27, the negative terminal of the 5V voltage source is grounded, and the other end of resistor R15 and one end of capacitor C5 are connected to the R ext / C ext pin of 74121C at node 28, and the other end of capacitor C5 is connected to the C ext pin of 74121C. The Q pin of 74121C is connected to the positive control terminal of voltage-controlled switch S4, the negative control terminal of voltage-controlled switch S4 is grounded, the input terminal of voltage-controlled switch S4 is connected to the positive terminal of the -6V voltage source, the negative terminal of the -6V voltage source is grounded, and the output terminal of voltage-controlled switch S4 and one end of resistor R18 are connected to port 1 of summing amplifier SUM1 in parallel at node 29, and the other end of resistor R18 is grounded. The 3 port of summing amplifier SUM1 outputs signal V f1 . Signal V O2 is connected to the B pin of monostable flip-flop 74121D. The A1 and A2 pins of 74121D are grounded. The V cc pin of 74121D and one end of resistor R19 are connected to the positive terminal of the 5V voltage source in parallel at node 30, the negative terminal of the 5V voltage source is grounded, and the other end of resistor R19 and one end of capacitor C6 are connected to the R ext / C ext pin of 74121D at node 31, and the other end of capacitor C6 is connected to the Cext The pins are connected. The Q pin of 74121D and one end of resistor R22 are connected to the A1 and A2 pins of 74121E in parallel at node 32, and the other end of resistor R22 is grounded. The B pin of 74121E is connected to the positive terminal of the 5V voltage source, the negative terminal of the 5V voltage source is grounded, and the V cc pin of 74121E and one end of resistor R20 are connected to the positive terminal of the 5V voltage source in parallel at node 33, the negative terminal of the 5V voltage source is grounded, and the other end of resistor R20 and one end of capacitor C7 are connected to the R ext / C ext pin of 74121E in parallel at node 34, and the other end of capacitor C7 is connected to the C ext pin of 74121E. The Q pin of 74121E is connected to the positive control terminal of voltage-controlled switch S5, the negative control terminal of voltage-controlled switch S5 is grounded, the input terminal of voltage-controlled switch S5 is connected to the positive terminal of the 6V voltage source, the negative terminal of the 6V voltage source is grounded, and the output terminal of voltage-controlled switch S5 and one end of resistor R23 are connected to port 2 of summer SUM2 in parallel at node 35, and the other end of resistor R23 is grounded. The A1 and A2 pins of 74121F are connected to node 35, the B pin of 74121F is connected to the positive terminal of the 5V voltage source, the negative terminal of the 5V voltage source is grounded, and the V cc pin of 74121F and one end of resistor R21 are connected to the positive terminal of the 5V voltage source in parallel at node 36, the negative terminal of the 5V voltage source is grounded, and the other end of resistor R21 and one end of capacitor C8 are connected to the R ext / C ext pin of 74121F in parallel at node 37, and the other end of capacitor C8 is connected to the C ext pin of 74121F. The Q pin of 74121F is connected to the positive control terminal of voltage-controlled switch S6, the negative control terminal of voltage-controlled switch S6 is grounded, the input terminal of voltage-controlled switch S6 is connected to the positive terminal of the -6V voltage source, the negative terminal of the -6V voltage source is grounded, and the output terminal of voltage-controlled switch S6 and one end of resistor R24 are connected to port 1 of summer SUM2 in parallel at node 38, the other end of resistor R24 is grounded, and port 3 of summer SUM2 outputs signal V f2 . Signal V f1 and V f2 are respectively connected to port 1 and port 2 of summer SUM3, port 3 of SUM3 and the input terminal of absolute value module ABS are connected, and the output terminal of ABS outputs signal V f .

[0031] The proposed memristive neural network circuit is used for the classification of two kinds of iris flowers (Iris setosa and Iris virginica). The appearances of Iris setosa and Iris virginica are respectively as Figure 3 (a) andFigure 3 (b) shows the data distributions of the two types of flowers (petal length, petal width, sepal length, and sepal width), as Figure 4 shown, with 50 sets of data for each. Compared with Iris virginica, Iris setosa has smaller petal length, petal width, and sepal length, while its sepal width is larger. The initial resistances of eight memristors are randomly set, and the resistances of each memristor are as Figure 5 shown. 30 sets of data are taken from each of the two types of irises for training the memristive neural network circuit. Taking one training as an example, the data of a Iris virginica flower: petal length is 4.8 cm, petal width is 1.8 cm, sepal length is 6 cm, and sepal width is 3 cm; the size data is input into the circuit in the form of voltage signals. V in1 (t = 20 ms, V = 4.8 V) represents the petal length, V in2 (t = 20 ms, V = 1.8 V) represents the petal width, V in3 (t = 20 ms, V = 6 V) represents the sepal length, V in4 (t = 20 ms, V = 3 V) represents the sepal width, and the input signal is as Figure 6 shown. Figure 7 shows the voltages of capacitors C1 and C2 and the output signals V O1 and V O2 of the two neurons. As the voltage signal is input, the charge accumulation rate on capacitor C1 is less than that on capacitor C2. At 10.4 ms, the integrated voltage of capacitor C2 first reaches the threshold voltage V th , and then neuron 2 outputs a high-level signal V O2 . The integrated voltage of capacitor C1 is discharged to ground, and V C1 instantly drops to 0 V, and the output signal V O1 of neuron 1 is 0 V. Neuron 2 wins, and the memristors corresponding to neuron 2 include M b1 , M b2 , M b3 , and M b4 start receiving the feedback voltage signal from the weight adjustment module at 17 ms. After 17 ms, the voltage of each memristor is equal to the difference between its input signal and the feedback voltage signal, Figure 8 shows the voltages on each memristor. Since neuron 1 does not output due to losing the competition, its weight adjustment module does not generate an adjustment signal. After receiving the adjustment signal generated by the weight adjustment module, the resistance values of the memristors of neuron 2 change, as Figure 9 shown. The voltages of M b1 , M b2 , and M b3 exceed their positive threshold voltages, and their resistance values decrease. The voltage of M b4When the voltage exceeds its negative threshold, its resistance increases. The above process is the entire learning process of the memristive neural network circuit based on the competitive learning mechanism for a set of input signals. Each time a set of voltage signals is input, only one neuron wins and only the weight of the winning neuron can be changed.

[0032] The circuit uses whether the weight characteristics of the memristor after training are consistent with the data characteristics of the input signal as the classification basis. After 1000 times of training, the resistance value of the memristor reaches a steady state and the circuit completes learning. The resistance values of the memristors are as Figure 10 shown. For memristors M a1 , M a2 and M a3 , they reach the maximum value, and for memristor M a4 , it reaches the minimum value, indicating that the weights of the first three memristors reach the minimum and the weight of the fourth memristor reaches the maximum. The first three memristors respectively receive input signals of petal length, petal width, and sepal length, and the fourth memristor receives the input signal of sepal width. Compared with Iris virginica, the data characteristics of Iris setosa are that its petal length, petal width, and sepal length are smaller, while its sepal width is larger. Therefore, the weight characteristics of neuron 1 are consistent with the data characteristics of Iris setosa, that is, neuron 1 corresponds to Iris setosa. Similarly, the weight characteristics of neuron 2 are consistent with the data characteristics of Iris virginica, that is, neuron 2 corresponds to Iris virginica. After training, the circuit can be used for classification. Each time it receives an input, only one neuron wins. The output signal of neuron 1 indicates that the input is classified as Iris setosa, and the output signal of neuron 2 indicates that the input is classified as Iris virginica. For example, input the data of an Iris setosa (petal length 1.4 cm, petal width 0.2 cm, sepal length 5.5 cm, sepal width 4.2 cm) and an Iris virginica (petal length 6.7 cm, petal width 2.2 cm, sepal length 7 cm, sepal width 3.8 cm) into the circuit respectively. Figure 11 Corresponding to the input of Iris setosa, the integrated voltage V C1 of capacitor C1 exceeds the threshold voltage V C2 faster than the integrated voltage V th of capacitor C2. Neuron 1 wins and outputs a high level V O1 , and the signal V O2 is 0, indicating that the circuit successfully classifies the input as Iris setosa. Figure 12 Corresponding to the input of Iris virginica, the integrated voltage V C2 of capacitor C2 exceeds the threshold voltage V C1 faster than the integrated voltage V th of capacitor C1. Neuron 2 wins and outputs a high level V O2 , and V O1Is 0, indicating that the circuit has successfully classified the input into Iris virginica. After testing with 40 sets of data, one set of data was misclassified. A Iris setosa with petal length of 1.3 cm, petal width of 0.3 cm, sepal length of 4.5 cm, and sepal width of 2.3 cm was misclassified as Iris virginica. The classification accuracy reached 97.5% (39 / 40), indicating that the memristive neural network circuit has a high classification accuracy.

Claims

1. A memristive neural network circuit based on a competitive learning mechanism, characterized in that, It includes a forward calculation module and a reverse adjustment module; among them, the forward calculation module is composed of a memristive crossbar array module and a leakage integration and discharge module, and the reverse adjustment module is composed of a weight adjustment module; the forward calculation module realizes lateral inhibition and competitive activation between two neurons through the winner-takes-all algorithm. For each input, only one neuron competes successfully and then generates an output signal; the reverse adjustment module adjusts the neuron weights through the Hebbian learning rule to achieve self-learning. It receives the output signal of the forward calculation module and then generates an adjustment signal to the forward calculation module to adjust the weights of the winning neurons.

2. The memristive neural network circuit based on a competitive learning mechanism according to claim 1, wherein After receiving the input signal, the memristive crossbar array module outputs current to the leakage integration and discharge module; the memristive crossbar array module consists of eight memristors M a1 -M a4 and M b1 -M b4 ; the positive terminals of the memristors M a1 and M b1 are connected in parallel and then connected to the input signal V in1 at node 1, the positive terminals of the memristors M a2 and M b2 are connected in parallel and then connected to the input signal V in2 at node 2, the positive terminals of the memristors M a3 and M b3 are connected in parallel and then connected to the input signal V in3 at node 3, the positive terminals of the memristors M a4 and M b4 are connected in parallel and then connected to the input signal V in4 at node 4, the negative terminals of the memristors M a1 -M a4 are connected in parallel and then connected to the input terminal of the voltage-controlled switch S1 at node 5, the negative terminals of the memristors M b1 -M b4 are connected in parallel and then connected to the input terminal of the voltage-controlled switch S2 at node 6; the adjustment signal V f1 is connected to node 5, and the adjustment signal V f2 is connected to node 6.

3. The memristive neural network circuit based on a competitive learning mechanism according to claim 1, wherein The leakage integration and discharge module receives the output current of the memristor crossbar array module and then generates output signals V O1 and V O2 ; The leakage integration and discharge module consists of NMOS transistors N1 - N6, voltage - controlled switches S1 and S2, resistors R1 - R12, capacitors C1 and C2, operational amplifiers A1 - A4, voltage comparators COMP1, COMP2, and voltage sources; The source of NMOS transistor N1 is grounded, the gate of NMOS transistor N1 is connected to signal V f connected, one end of resistor R1 and the positive control terminal of voltage - controlled switch S1 are connected in parallel to node 7 and connected to the drain of NMOS transistor N1, the other end of resistor R1 is connected to the positive terminal of the 5V voltage source, the negative terminal of the 5V voltage source is grounded, and the negative control terminal of voltage - controlled switch S1 is grounded; The negative terminals of memristors M a1 -M a4 are connected in parallel and then connected to the input terminal of voltage - controlled switch S1 at node 5, the output terminal of voltage - controlled switch S1 and one end of resistor R2 are connected in parallel to node 8 and connected to the inverting input terminal of operational amplifier A1, the non - inverting input terminal of operational amplifier A1 is grounded, the other end of resistor R2 and one end of resistor R3 are connected in parallel to node 9 and connected to the output terminal of operational amplifier A1; The other end of resistor R3 and one end of resistor R4 are connected in parallel to node 10 and connected to the inverting input terminal of operational amplifier A2, the non - inverting input terminal of operational amplifier A2 is grounded; The other end of resistor R4, one end of resistor R5, and the drain of NMOS transistor N2 are connected in parallel to the output terminal of operational amplifier A2 at node 11; The source of NMOS transistor N2 is grounded, and the gate of NMOS transistor N2 is connected to signal V f connected; The source of NMOS transistor N3 is grounded, the gate of NMOS transistor N3 and one end of resistor R12 are connected to node 20; The other end of resistor R5, the drain of NMOS transistor N3, and one end of capacitor C1 are connected in parallel to the non - inverting input terminal of voltage comparator COMP1 at node 12; The inverting input terminal of voltage comparator COMP1 is connected to voltage source V th connected, the positive power supply pin of voltage comparator COMP1 is connected to the 6V voltage source, the negative power supply pin of voltage comparator COMP1 is grounded, one end of resistor R6 and the gate of NMOS transistor N6 are connected in parallel to the output terminal of voltage comparator COMP1 at node 13, and the output terminal of voltage comparator COMP1 outputs signal V O1 ; The source of NMOS transistor N4 is grounded, the gate of NMOS transistor N4 is connected to signal V f connected, one end of resistor R7 and the positive control terminal of voltage - controlled switch S2 are connected in parallel to node 14 and connected to the drain of NMOS transistor N4, the other end of resistor R7 is connected to the positive terminal of the 5V voltage source, the negative terminal of the 5V voltage source is grounded, and the negative control terminal of voltage - controlled switch S2 is grounded; The memristor M b1 -M b4 The negative terminals of -M are connected in parallel and then connected to the input terminal of the voltage-controlled switch S2 at node 6. The output terminal of the voltage-controlled switch S2 and one end of the resistor R8 are connected in parallel at node 15 and connected to the inverting input terminal of the operational amplifier A3. The non-inverting input terminal of the operational amplifier A3 is grounded. The other end of the resistor R8 and one end of the resistor R9 are connected in parallel at node 16 and connected to the output terminal of the operational amplifier A1. The other end of the resistor R9 and one end of the resistor R10 are connected in parallel at node 17 and connected to the inverting input terminal of the operational amplifier A4. The non-inverting input terminal of the operational amplifier A4 is grounded. The other end of the resistor R10, one end of the resistor R11, and the drain of the NMOS transistor N5 are connected in parallel to the output terminal of the operational amplifier A4 at node 18. The source of the NMOS transistor N5 is grounded, and the gate of the NMOS transistor N5 is connected to the signal V f connected. The source of the NMOS transistor N6 is grounded, and the gate of the NMOS transistor N6 and one end of the resistor R6 are connected at node 13. The other end of the resistor R11, the drain of the NMOS transistor N6, and one end of the capacitor C2 are connected in parallel to the non-inverting input terminal of the voltage comparator COMP2 at node 19. The inverting input terminal of the voltage comparator COMP2 is connected to the voltage source V th connected. The positive power supply pin of the voltage comparator COMP2 is connected to a 6V voltage source, the negative power supply pin of the voltage comparator COMP2 is grounded. One end of the resistor R12 and the gate of the NMOS transistor N3 are connected in parallel to the output terminal of the voltage comparator COMP2 at node 20. The output terminal of the voltage comparator COMP2 outputs the signal V O2 .

4. A memristive neural network circuit based on a competitive learning mechanism according to claim 1, characterized in that, The weight adjustment module receives the leakage integral and the output signal of the discharge module, and then generates an adjustment signal; the weight adjustment module consists of monostable flip - flops 74121A - 74121F, resistors R13 - R24, capacitors C3 - C8, voltage - controlled switches S3 - S6, summers SUM1 - SUM3, a voltage source, and an absolute - value module ABS; the signal V O1 is connected to the B pin of the monostable flip - flop 74121A. The A1 and A2 pins of 74121A are grounded. The V cc pin and one end of the resistor R13 are connected in parallel to the positive terminal of the 5V voltage source at node 21. The negative terminal of the 5V voltage source is grounded. The other end of the resistor R13 and one end of the capacitor C3 are connected in parallel to the R ext / C ext pin of 74121A at node 22. The other end of the capacitor C3 is connected to the C ext pin of 74121A. The Q pin of 74121A and one end of the resistor R16 are connected in parallel to the A1 and A2 pins of 74121B at node 23. The other end of the resistor R16 is grounded. The B pin of 74121B is connected to the positive terminal of the 5V voltage source. The negative terminal of the 5V voltage source is grounded. The V cc pin and one end of the resistor R14 are connected in parallel to the positive terminal of the 5V voltage source at node 24. The negative terminal of the 5V voltage source is grounded. The other end of the resistor R14 and one end of the capacitor C4 are connected in parallel to the R ext / C ext pin of 74121B at node 25. The other end of the capacitor C4 is connected to the C ext pin of 74121B. The Q pin of 74121B is connected to the positive control terminal of the voltage - controlled switch S3. The negative control terminal of the voltage - controlled switch S3 is grounded. The input terminal of the voltage - controlled switch S3 is connected to the positive terminal of the 6V voltage source. The negative terminal of the 6V voltage source is grounded. The output terminal of the voltage - controlled switch S3 and one end of the resistor R17 are connected in parallel to the 2 - port of the summer SUM1 at node 26. The other end of the resistor R17 is grounded. The A1 and A2 pins of 74121C are connected to node 26. The B pin of 74121C is connected to the positive terminal of the 5V voltage source. The negative terminal of the 5V voltage source is grounded. The V cc pin and one end of the resistor R15 are connected in parallel to the positive terminal of the 5V voltage source at node 27. The negative terminal of the 5V voltage source is grounded. The other end of the resistor R15 and one end of the capacitor C5 are connected in parallel to the R ext / C ext pin of 74121C at node 28. The other end of the capacitor C5 is connected to the C ext The pins are connected. The Q pin of 74121C is connected to the positive control terminal of the voltage-controlled switch S4. The negative control terminal of the voltage-controlled switch S4 is grounded. The input terminal of the voltage-controlled switch S4 is connected to the positive terminal of the -6V voltage source. The negative terminal of the -6V voltage source is grounded. The output terminal of the voltage-controlled switch S4 and one end of the resistor R18 are connected to the 1 port of the summer SUM1 in parallel at node 29. The other end of the resistor R18 is grounded. The 3 port of the summer SUM1 outputs the signal V f1 ; The signal V O2 is connected to the B pin of the monostable flip-flop 74121D. The A1 and A2 pins of 74121D are grounded. The V cc pin of 74121D and one end of the resistor R19 are connected to the positive terminal of the 5V voltage source in parallel at node 30. The negative terminal of the 5V voltage source is grounded. The other end of the resistor R19 and one end of the capacitor C6 are connected to the R ext / C ext pin of 74121D in parallel at node 31. The other end of the capacitor C6 is connected to the C ext pin of 74121D. The Q pin of 74121D and one end of the resistor R22 are connected to the A1 and A2 pins of 74121E in parallel at node 32. The other end of the resistor R22 is grounded; The B pin of 74121E is connected to the positive terminal of the 5V voltage source. The negative terminal of the 5V voltage source is grounded. The V cc pin of 74121E and one end of the resistor R20 are connected to the positive terminal of the 5V voltage source in parallel at node 33. The negative terminal of the 5V voltage source is grounded. The other end of the resistor R20 and one end of the capacitor C7 are connected to the R ext / C ext pin of 74121E in parallel at node 34. The other end of the capacitor C7 is connected to the C ext pin of 74121E. The Q pin of 74121E is connected to the positive control terminal of the voltage-controlled switch S5. The negative control terminal of the voltage-controlled switch S5 is grounded. The input terminal of the voltage-controlled switch S5 is connected to the positive terminal of the 6V voltage source. The negative terminal of the 6V voltage source is grounded. The output terminal of the voltage-controlled switch S5 and one end of the resistor R23 are connected to the 2 port of the summer SUM2 in parallel at node 35. The other end of the resistor R23 is grounded; The A1 and A2 pins of 74121F are connected to node 35. The B pin of 74121F is connected to the positive terminal of the 5V voltage source. The negative terminal of the 5V voltage source is grounded. The V cc pin of 74121F and one end of the resistor R21 are connected to the positive terminal of the 5V voltage source in parallel at node 36. The negative terminal of the 5V voltage source is grounded. The other end of the resistor R21 and one end of the capacitor C8 are connected to the R ext / C ext pin of 74121F in parallel at node 37. The other end of the capacitor C8 is connected to the C ext The pins are connected. The Q pin of 74121F is connected to the positive control terminal of the voltage-controlled switch S6. The negative control terminal of the voltage-controlled switch S6 is grounded. The input terminal of the voltage-controlled switch S6 is connected to the positive terminal of the -6V voltage source. The negative terminal of the -6V voltage source is grounded. The output terminal of the voltage-controlled switch S6 and one end of the resistor R24 are connected to the 1 port of the summer SUM2 in parallel at node 38. The other end of the resistor R24 is grounded. The 3 port of the summer SUM2 outputs the signal V f2 ; The signal V f1 and V f2 are respectively connected to the 1 port and the 2 port of the summer SUM3. The 3 port of SUM3 is connected to the input terminal of the absolute value module ABS. The output terminal of ABS outputs the signal V f .

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