Semiconductor memory device

Abstract

The invention discloses a semiconductor memory device. The semiconductor memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a memory cell array formed in a memory region and including bit lines and word lines, and a plurality of upper metal pads. The second semiconductor structure is arranged below the first semiconductor structure; and a plurality of lower metal pads respectively bonded to the plurality of upper metal pads, peripheral circuits disposed under the memory region, and a voltage generator disposed under the memory region and providing an internal voltage to one or more of the peripheral circuits. The plurality of upper metal pads are electrically connected to the bit line or the word line, and the plurality of lower metal pads are electrically connected to terminals of the peripheral circuit.

Description

Technical Field

[0001] Embodiments of the present disclosure described herein relate to semiconductor devices, and more particularly, to semiconductor memory devices. Background Art

[0002] A semiconductor memory may be a volatile memory that loses data stored therein when power supplied to the memory is cut off, or a non-volatile memory that retains data when power supplied to the memory is cut off. Volatile memories include static random access memories (SRAMs) and dynamic random access memories (DRAMs). Non-volatile memories include flash memories, phase change RAMs (PRAMs), magnetic RAMs (MRAMs), resistive RAMs (RRAMs), and ferroelectric RAMs (FRAMs).

[0003] A DRAM device includes memory cells connected to word lines and bit lines. Through the bit lines, the DRAM device stores data in the memory cells or reads data stored in the memory cells. Through the bit lines and word lines, a peripheral circuit may store data in the memory cells or may read the stored data. A voltage generator converts an external voltage (supplied externally to the DRAM) into an internal voltage used by the circuits of the DRAM. For example, the voltage generator may supply a converted constant voltage to the peripheral circuit. However, when the power consumption of the peripheral circuit is large, the characteristics of the internal voltage output by the voltage generator may become worse. Summary of the Invention

[0004] Embodiments of the present disclosure provide a semiconductor memory device in which a peripheral circuit is stably supplied with an internal voltage and its integration degree is improved.

[0005] According to an embodiment, a semiconductor memory device includes: a first semiconductor structure including a first semiconductor substrate, a memory cell array, and a plurality of upper metal pads, the memory cell array being formed in a memory region of the first semiconductor substrate and including bit lines and word lines; and a second semiconductor structure disposed under the first semiconductor structure and including a second semiconductor substrate, a plurality of lower metal pads respectively bonded to the plurality of upper metal pads, a peripheral circuit disposed under the memory region, and a voltage generator disposed on a lower side of the memory region to supply an internal voltage to the peripheral circuit, wherein the bit lines and the word lines are electrically connected to corresponding ones of the plurality of upper metal pads, and wherein some or all of the plurality of lower metal pads are electrically connected to terminals of the peripheral circuit.

[0006] According to an embodiment, a semiconductor memory device includes: a first semiconductor structure including a first semiconductor substrate, a plurality of sub-memory cell arrays arranged in a two-dimensional manner, and a plurality of upper metal pads; and a second semiconductor structure disposed below the first semiconductor structure, wherein the second semiconductor structure includes a second semiconductor substrate, a plurality of lower metal pads, a plurality of peripheral circuits, and a plurality of voltage generators, the plurality of lower metal pads being bonded to the plurality of upper metal pads, the plurality of peripheral circuits being respectively disposed below corresponding ones of the plurality of sub-memory cell arrays and electrically connected to the corresponding ones of the plurality of sub-memory cell arrays, and the plurality of voltage generators being all disposed below corresponding ones of the plurality of sub-memory cell arrays to supply an internal voltage to a corresponding peripheral circuit.

[0007] According to an embodiment, a semiconductor memory device includes: a first semiconductor substrate; a memory cell array formed in a memory region of the first semiconductor substrate and including a plurality of word lines and a plurality of bit lines; a plurality of upper metal pads formed in the memory region and arranged in a two-dimensional array; one or more first metal layers electrically connecting a first end of the plurality of word lines or a first end of the plurality of bit lines to a corresponding one of the plurality of upper metal pads; a second semiconductor substrate disposed below the first semiconductor substrate; a first bit line sense amplifier formed in a region of the second semiconductor substrate below the memory cell array and configured to read and amplify a voltage of a corresponding one of the plurality of bit lines; a second bit line sense amplifier formed in a region of the second semiconductor substrate below the memory cell array and configured to read and amplify a voltage of a corresponding one of the plurality of bit lines; a sub-word line driver configured to apply a voltage to a corresponding one of the plurality of word lines; a voltage generator formed in a first region of the second semiconductor substrate below the memory cell array and configured to supply an internal voltage to at least one of the first bit line sense amplifier, the second bit line sense amplifier, and the sub-word line driver; a plurality of lower metal pads arranged in a two-dimensional array; and one or more second metal layers electrically connecting the first bit line sense amplifier, the second bit line sense amplifier, and the sub-word line driver to a corresponding one of the plurality of lower metal pads, wherein the plurality of upper metal pads and the plurality of lower metal pads are bonded together. Description of the Drawings

[0008] The above and other objects and features of the present disclosure will become apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0009] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Figure 2 is a perspective view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 3 is an illustration along Figure 2 a view of a vertical cross-section taken along lines A-A' and B-B'.

[0012] Figure 4 is a diagram illustrating an example of a second semiconductor structure according to an embodiment of the present disclosure.

[0013] Figure 5 is a diagram illustrating the surface of a second semiconductor structure according to an embodiment of the present disclosure.

[0014] Figure 6A and Figure 6B is a diagram illustrating the routing of signals in a first semiconductor structure according to an embodiment of the present disclosure.

[0015] Figure 7 is a diagram illustrating a memory cell array of a first semiconductor structure according to an embodiment of the present disclosure.

[0016] Figure 8 is a diagram illustrating a connection structure of a vertical cross-section along a first direction according to an embodiment of the present disclosure.

[0017] Figure 9 is a diagram illustrating a connection structure of a vertical cross-section along a second direction according to an embodiment of the present disclosure.

[0018] Figure 10A and Figure 10B is a diagram illustrating the placement of a memory cell array and a peripheral circuit according to an embodiment of the present disclosure.

[0019] Figure 11 is a diagram depicting an integrated circuit device.

[0020] Figure 12 is an illustration of Figure 11 a pad array of an integrated circuit device.

[0021] Figure 13 is an illustration along Figure 12 a view of a vertical cross-section of an integrated circuit device taken along line A-A'.

[0022] Figure 14 is a view showing a vertical cross-section of an integrated circuit device taken along line B-B' Figure 12 as shown. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the present disclosure will be described in detail and clearly so that those of ordinary skill in the art can easily implement the present disclosure.

[0024] Hereinafter, embodiments in exemplary embodiments will be described with reference to the accompanying drawings. For example, as can be seen in the drawings, items described herein in the singular may be provided in the plural. Thus, unless the context indicates otherwise, the description of a single item provided in the plural should be understood to apply to the remaining plurality of items.

[0025] Figure 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present disclosure. Referring to Figure 1 , the semiconductor memory device 100 may include a memory cell array 110, a peripheral circuit 120, a voltage generator 130, and a control logic circuit 140. Like all semiconductor devices disclosed herein, the semiconductor memory device 100 may be a semiconductor chip. Such a semiconductor chip may be a semiconductor device singly cut (e.g., diced from a wafer) that may be formed from a single substrate (e.g., a bulk silicon substrate, a bulk germanium substrate, silicon-on-insulator (SOI), etc.) or from a combination of a plurality of component wafers each having a corresponding substrate.

[0026] The semiconductor memory device 100 may be a dynamic random access memory (DRAM), a double data rate 4 (DDR4) synchronous DRAM (SDRAM), a low power DDR4 (LPDDR4) SDRAM, an LPDDR5 SDRAM, a graphics double data rate 5 (GDDR5) SDRAM, a GDDR6 SDRAM, and / or a high bandwidth memory (HBM), such as HBM2, HBM2E, and / or HBM3, but the present invention is not limited thereto.

[0027] The memory cell array 110 may include a plurality of word lines WL, a plurality of bit lines BL, and memory cells MC connected to the word lines WL and the bit lines BL. Each memory cell MC may include a select transistor and a storage capacitor. The select transistor may be connected between the storage capacitor and the bit line BL and may operate in response to the voltage of the word line WL. The storage capacitor may be connected to the select transistor and may store data according to the operation of the select transistor and the level of the bit line BL. A plurality of memory cells MC may be grouped into sub-memory cell arrays.

[0028] The peripheral circuit 120 may include a plurality of circuits for operations of the semiconductor memory device 100, such as operations of writing, reading, and managing data associated with the memory cells MC. For example, the peripheral circuit 120 may include a row decoder, a column decoder, an input / output circuit, etc. The row decoder may be connected to the memory cell array 110 through a plurality of word lines WL. The row decoder may decode a row address provided from an external device (a device external to the semiconductor memory device 100, such as a memory controller), and may control the voltages of the plurality of word lines WL based on the decoding result. The column decoder may be connected to the memory cell array 110 through a plurality of bit lines BL. The column decoder may decode a column address provided from an external device (e.g., a memory controller), and may control the plurality of bit lines BL based on the decoding result. The input / output circuit may send data to an external device (e.g., a memory controller), or may receive data from an external device. The input / output circuit may provide the data received from the external device to a sense amplifier and / or a write driver, or may provide the data received from the sense amplifier and / or the write driver to an external device.

[0029] The peripheral circuit 120 may further include a bit line sense amplifier and a sub-word line driver. The bit line sense amplifier may be electrically connected to the bit lines BL of the memory cell array 110, and may read and amplify the voltages of the bit lines BL (e.g., the voltage difference between the bit lines BL and complementary bit lines). The sub-word line driver may be electrically connected to the word lines WL of the memory cell array 110, and may apply a word line driving voltage to the connected word lines WL. As used herein, components described as "electrically connected" are configured such that an electrical signal can be transmitted from one component to another (however, such an electrical signal may attenuate in strength as it is transmitted, and may be selectively transmitted). In addition, components that are "directly electrically connected" form a common electrical node through an electrical connection made by one or more conductors (such as, for example, wires, pads, internal wires, via paths, etc.). Thus, components that are directly electrically connected do not include components that are electrically connected through active elements (such as transistors or diodes).

[0030] The voltage generator 130 may convert an external voltage VEXT input thereto into an internal voltage VINT to be used by the peripheral circuit 120. For example, the voltage generator 130 may generate an internal voltage to be used by at least one of a row decoder, a column decoder, an input / output circuit, a bit line sense amplifier, or a sub-word line driver. The internal voltage VINT corresponds to a constant (e.g., non-fluctuating) voltage used in the operation of the peripheral circuit 120. The voltage generator 130 may generate one or more internal voltages to be used by the peripheral circuit 120. For example, when the peripheral circuit 120 operates, a plurality of internal (constant) voltages may be generated by the voltage generator and provided to the peripheral circuit 120 for its use. In this case, the voltage generator 130 may convert the external voltage VEXT into a plurality of internal voltages, and the levels of such internal voltages may be different from each other. The plurality of internally converted voltages may be respectively provided to the corresponding circuits included in the peripheral circuit 120. Each circuit of the peripheral circuit 120 may operate based on the control signals provided thereto and one or more of the provided internal voltages.

[0031] The external voltage VEXT supplied to the voltage generator 130 may be provided by a device external to the semiconductor memory device 100. Accordingly, the voltage generator 130 may have one or more electrical connections (e.g., wires or interconnections formed by a patterned metal layer and / or vias) to one or more chip pads (terminals of the semiconductor memory device 100), which in turn may be connected to an external device to receive the external voltage VEXT. Additionally, several external voltages VEXT (of the same or different voltage levels) may be provided in a manner from the external device to the voltage generator 130 for the voltage generator 130 to use to generate one or more internal voltages.

[0032] The control logic circuit 140 may control the operation of the semiconductor memory device 100. For example, the control logic circuit 140 may generate one or more control signals CS such that the semiconductor memory device 100 performs a write operation or a read operation. The control logic circuit 140 may include a command decoder that decodes a command CMD and an address ADDR received from an external device (e.g., a memory controller) and a mode setting register for setting an operating mode of the semiconductor memory device 100. In response to the control signal CS, the peripheral circuit 120 may store data in the memory cell array 110 or may read data from the memory cell array 110.

[0033] The semiconductor memory device 100 may have a cell-on-periphery (CoP) structure in which some or all of the peripheral circuits 120 are disposed below the memory cell array 110 (or in a region on the lower side of the memory cell array 110). Since the CoP structure is applied to the semiconductor memory device 100, the storage capacity of the semiconductor memory device 100 can be increased and the space utilization can be improved.

[0034] When a relatively large amount of power consumption occurs in the peripheral circuit 120, the level of the internal voltage may temporarily drop (e.g., a transient voltage drop). Such a transient voltage drop in the internal voltage can cause a reduction in the operation reliability and performance of the semiconductor memory device 100. However, by forming the semiconductor memory device 100 having the CoP structure, the voltage generator 130 can be disposed relatively close to the peripheral circuit 120, and thus, the supply path of the internal voltage to the peripheral circuit 120 can be made relatively short. For example, the peripheral circuit 120 and the voltage generator 130 may be disposed below the memory region to be adjacent to each other. According to the above configuration / structure, the voltage generator 130 can stably supply the internal voltage to the peripheral circuit 120 and can improve the integration degree of the semiconductor memory device 100.

[0035] Figure 2 is a perspective view illustrating a semiconductor memory device according to an embodiment of the present disclosure. Refer to Figure 2 , the semiconductor memory device 100 may include a first semiconductor structure SEMS1 and a second semiconductor structure SEMS2.

[0036] The first semiconductor structure SEMS1 may include a memory region MA. A memory cell array including a plurality of bit lines and a plurality of word lines may be formed in the memory region MA. The bit lines and word lines included in the memory cell array may be electrically connected to corresponding upper metal pads (not shown).

[0037] The second semiconductor structure SEMS2 may be disposed below (or on the lower side of) the first semiconductor structure SEMS1. The second semiconductor structure SEMS2 may include an unused region UNA and a peripheral circuit region PCA. As will be understood, the unused region UNA may include circuits for operating the semiconductor memory device, and the unused region UNA may correspond to a corresponding region not used in a conventional semiconductor memory device. The unused region UNA and the peripheral circuit region PCA correspond to a region on the lower side of the memory region MA (hereinafter, referred to as the "lower side region"). Peripheral circuits may be disposed in the peripheral circuit region PCA. For example, a bit line sense amplifier and a sub-word line driver may be disposed in the peripheral circuit region PCA. The peripheral circuits disposed in the peripheral circuit region PCA may be electrically connected to lower metal pads (not shown). For example, the bit line sense amplifier and the sub-word line driver may be electrically connected to corresponding lower metal pads.

[0038] The lower region may correspond to a region projected vertically downward from a specific region included in a first plane. Assume that the first plane includes a first region, the first plane is parallel to a second plane, and the second plane includes a second region. The second region being located in the lower region of the first region means that the second region is located in the region projected vertically downward from the first region.

[0039] The upper metal pads of the first semiconductor structure SEMS1 and the lower metal pads of the second semiconductor structure SEMS2 may be arranged in the form of a matrix array including a plurality of rows and a plurality of columns. The first semiconductor structure SEMS1 and the second semiconductor structure SEMS2 may be joined together by joining the upper metal pads to the lower metal pads.

[0040] As the pitch from the upper metal pad(s) to the lower metal pad(s) decreases, or as the number of memory cells per word line and the number of memory cells per bit line on the memory cell array increase, there may be redundant upper metal pads and lower metal pads. That is, there may be upper metal pads not connected to any of the bit lines and word lines. Similarly, there may be lower metal pads not connected to the peripheral circuit. The unused area UNA may be an area where upper metal pads and lower metal pads not connected to the bit lines, word lines, and peripheral circuit are provided.

[0041] In the present disclosure, the first direction D1 is expressed as a direction associated with the upper side (e.g., extending upward, away from the upper side and perpendicular to the upper side), and the direction opposite to the first direction D1 is expressed as a direction associated with the lower side. However, in the present disclosure, the upper / lower expressions "upper side" and "lower side" are provided only for describing the relative positions of components, and the present invention is not limited thereto. For example, the second semiconductor structure SEMS2 may be provided above (or on the upper side of) the first semiconductor structure SEMS1.

[0042] Figure 1The voltage generator 130 can be disposed in the unused area UNA included in the second semiconductor structure SEMS2. In some examples, the voltage generator 130 can be the only circuit in the unused area UNA. An external voltage can be applied to the voltage generator 130 disposed in the unused area UNA, and the voltage generator 130 can convert the external voltage into an internal voltage to be used by the peripheral circuits. The internal voltage generated by the voltage generator 130 is supplied to the peripheral circuits disposed in the peripheral circuit area PCA. The peripheral circuits 120 can operate by using the internal voltage generated by the voltage generator 130. For example, the peripheral circuits 120 can drive the word lines or bit lines included in the memory cell array in accordance with the received control signal(s) and internal voltage(s). The peripheral circuits 120 can drive the word lines or bit lines of the memory cell array to write data received from the outside into the memory cells or read data stored in the memory cells. Driving the word lines can constitute applying an appropriate voltage to the word lines such that the selection transistors of the memory cells connected to the word lines (e.g., having a gate connected to or formed by the word lines) are turned on. Driving the bit lines can constitute applying an appropriate voltage to the bit lines to supply appropriate data to the accessed memory cells connected to the bit lines, or can constitute precharging the bit lines.

[0043] Since the voltage generator and the peripheral circuits included in the second semiconductor structure are disposed below the memory cell array, the horizontal area of the semiconductor memory device can be reduced, and the integration degree can be improved in terms of the horizontal dimension. In addition, since the voltage generator and the peripheral circuits are disposed relatively close to each other (or are respectively disposed in relatively close areas), the supply path of the internal voltage from the voltage generator to the peripheral circuits can be reduced, and the supply of the internal voltage can be improved. Accordingly, the internal voltage can be stably provided.

[0044] Figure 3 is a view showing a vertical cross section taken along Figure 2 lines A-A' and B-B'. Referring to Figure 3 , the memory cell array 110 can be disposed in the memory area MA of the first semiconductor structure SEMS1.

[0045] The first semiconductor structure SEMS1 may include a first semiconductor substrate 210, a memory cell array 110, and a plurality of upper metal pads UMP. The memory cell array 110 may include word lines, bit lines, and memory cells formed at intersections of the word lines and the bit lines. The memory cell array 110 may be formed in the first semiconductor substrate 210 and / or on the first semiconductor substrate 210. The first semiconductor substrate 210 may be a bulk semiconductor substrate formed of a crystalline semiconductor layer or including a crystalline semiconductor layer (e.g., a bulk silicon substrate, a bulk germanium substrate, SOI, etc.). The plurality of upper metal pads UMP may be formed at the surface of the first semiconductor structure SEMS1. Some of the upper metal pads UMP and the memory cell array 110 may be electrically connected by a first metal line ML1. The first metal line ML1 may be formed in at least one metal layer. For example, the metal line ML1 may be formed by connecting metal patterns formed of different metal layers with one or more conductive vias.

[0046] The plurality of upper metal pads UMP may include unused upper metal pads UMP_UN and connected upper metal pads UMP_CAL. The connected upper metal pads UMP_CAL may be electrically connected to components of the memory cell array 110. For example, the connected upper metal pads UMP_CAL may be connected to the memory cell array 110 by the first metal line ML1. As an example, each connected upper metal pad UMP_CAL may be connected to a corresponding word line and / or a corresponding bit line included in the memory cell array 110 by a corresponding first metal line ML1.

[0047] The unused upper metal pads UMP_UN are metal pads corresponding to isolated metal pads and not electrically connected to any of the word lines and bit lines. Each unused upper metal pad UMP_UN may form all or part of a corresponding electrically floating electrical node.

[0048] The second semiconductor structure SEMS2 is disposed below (or on the lower side of) the first semiconductor structure SEMS1. The second semiconductor structure SEMS2 may include a second semiconductor substrate 220, a peripheral circuit 120, a voltage generator 130, and a plurality of lower metal pads LMP. The second semiconductor substrate 220 may be a bulk semiconductor substrate formed of or including a crystalline semiconductor layer (e.g., a bulk silicon substrate, a bulk germanium substrate, SOI, etc.). The unused area UNA and the peripheral circuit area PCA may be located in the second semiconductor structure SEMS2. The unused area UNA and the peripheral circuit area PCA correspond to the lower side area of the memory area MA. The peripheral circuit 120 may be disposed in the peripheral circuit area PCA of the second semiconductor structure SEMS2. The peripheral circuit 120 may include circuits necessary for operating the memory cell array 110, such as bit line sense amplifiers and sub-word line drivers. The peripheral circuit 120 may be formed on the second semiconductor substrate 220 and / or in the second semiconductor substrate 220. The plurality of lower metal pads LMP may be formed on the surface of the second semiconductor structure SEMS2. Some of the lower metal pads LMP and the peripheral circuit 120 may be electrically connected by a second metal line ML2. The second metal line ML2 may be formed in at least one metal layer. Each of the first semiconductor substrate 210 and the second semiconductor substrate 220 may be a bulk semiconductor substrate (e.g., an initial semiconductor substrate that forms the wafer in the final wafer product, such as a bulk semiconductor substrate (e.g., crystalline silicon), a silicon-on-insulator (SOI) substrate, etc.).

[0049] The plurality of lower metal pads LMP may include unused lower metal pads LMP_UN and connected lower metal pads LMP_PC. The unused lower metal pads LMP_UN are the lower metal pads disposed in the unused area UNA, while the connected upper metal pads LMP_PC are the lower metal pads disposed in the peripheral circuit area PCA. The connected lower metal pads LMP_PC may be electrically connected to the peripheral circuit 120. For example, the connected lower metal pads LMP_PC may be connected to the peripheral circuit 120 by the second metal line ML2. As an example, the connected lower metal pads LMP_PC may be connected to one of the bit line sense amplifiers or sub-word line drivers included in the peripheral circuit 120 by the second metal line ML2.

[0050] The unused lower metal pad LMP_UN is a metal pad corresponding to an isolated metal pad and electrically disconnected from the peripheral circuit 120. Each unused lower metal pad UMP_UN can form all or part of an electrically floating corresponding electrical node. The unused lower metal pad LMP_UN can be a dummy pad. A voltage generator can be disposed under the unused lower metal pad LMP_UN. In some examples, a group of unused lower metal pads LMP_UN can be confined to a first region of the lower metal pads LMP_PC that are not connected, and the voltage generator 130 can be formed within the boundary of the first region with respect to a top view (i.e., formed within the occupied area of the first region). This first region can correspond to the unused region UNA described herein (e.g., form all or part of it).

[0051] The lower metal pad LMP and the upper metal pad UMP can have the same size and the same arrangement (e.g., have a one-to-one correspondence with respect to a top view). The lower metal pad LMP and the upper metal pad UMP can include, for example, copper (Cu), aluminum (Al), nickel (Ni), cobalt (Co), tungsten (W), titanium (Ti), tin (Sn), or an alloy thereof.

[0052] The semiconductor memory device 100 can have a structure in which the metal pads of the first semiconductor structure SEMS1 and the second semiconductor structure SEMS2 are joined together. The upper metal pad UMP of the first semiconductor structure SEMS1 and the lower metal pad LMP of the second semiconductor structure SEMS2 can be electrically connected and physically connected to each other by joining. That is, the lower metal pad LMP and the upper metal pad UMP can be in contact with each other. The peripheral circuit 120 and the memory cell array 110 can be electrically connected by the joining of the lower metal pad LMP and the upper metal pad UMP. By controlling the word line and the bit line via the second metal line ML2, the connected lower metal pad LMP_PC, the connected upper metal pad UMP_CAL, and the first metal line ML1, the peripheral circuit 120 can write data into the memory cells or can read the data stored in the memory cells.

[0053] The unused lower metal pad LMP_UN may be disposed in the unused area UNA of the second semiconductor structure SEMS2, and the unused upper metal pad UMP_UN may be disposed in the area corresponding to the unused area UNA in the memory area MA of the first semiconductor structure SEMS1. The voltage generator 130 may be disposed in the unused area UNA of the second semiconductor structure SEMS2. The voltage generator 130 may receive an external voltage VEXT and may convert the external voltage VEXT into an internal voltage VINT to be used by the peripheral circuit 120. The internal voltage VINT as a preset constant voltage may include a plurality of voltage levels. The voltage generator 130 may supply the internal voltage VINT to the peripheral circuit 120. Depending on the purpose of the internal voltage VINT, the internal voltage VINT generated by the voltage generator 130 may include a plurality of voltage levels. That is, the voltage generator 130 may supply the internal voltage VINT including one or more voltage levels to the peripheral circuit 120.

[0054] The voltage generator 130 may be disposed in the unused area UNA adjacent to the peripheral circuit area PCA in the lower area of the memory area MA, and may supply the internal voltage VINT at a short distance from the peripheral circuit 120. When the power consumption associated with the internal voltage instantaneously increases due to the operation of the peripheral circuit 120, a transient voltage drop of the internal voltage may occur. The transient voltage drop becomes an obstacle to the operation of the peripheral circuit 120. Assuming that the voltage generator 130 is disposed relatively far from the peripheral circuit 120, it is relatively difficult to supply the internal voltage to the peripheral circuit 120 when a transient voltage drop occurs. This may result in a relatively large voltage drop. Therefore, the relatively large voltage drop due to the transient voltage drop may make it difficult to ensure the normal operation of the peripheral circuit 120.

[0055] In the semiconductor memory device 100 according to the present disclosure, the voltage generator 130 may be disposed at a position relatively close to the peripheral circuit 120. The voltage generator 130 may easily supply voltage to the peripheral circuit 120 and may improve the transient voltage drop due to the power consumption of the peripheral circuit 120. Therefore, the operation performance of the peripheral circuit 120 may be improved.

[0056] Figure 4 is a diagram illustrating an example of a second semiconductor structure according to an embodiment of the present disclosure. Refer to Figure 4 , the second semiconductor structure SEMS2 may include an unused area UNA and a peripheral circuit area PCA.

[0057] The unused area UNA and the peripheral circuit area PCA of the second semiconductor structure SEMS2 may correspond to the lower area of the memory area MA of the first semiconductor structure SEMS1. The peripheral circuit area PCA may be set to include three sides of the lower area of the memory area MA, and the unused area UNA may be located in the remaining area other than the peripheral circuit area PCA and may be set to be surrounded by the peripheral circuit area PCA. In this case, the unused area UNA may be set such that three sides of the unused area UNA are adjacent to the peripheral circuit area PCA.

[0058] The first peripheral circuit PC1 may be provided on the first side portion of the peripheral circuit area PCA close to the first side of the peripheral circuit area PCA. The second peripheral circuit PC2 may be provided on the second side portion of the peripheral circuit area PCA close to the second side opposite to the first side. The third peripheral circuit PC3 may be provided between the first side portion and the second side portion of the peripheral circuit area PCA. The first peripheral circuit PC1 may include a first bit line sense amplifier BLSA1, and the second peripheral circuit PC2 may include a second bit line sense amplifier BLSA2. The first bit line sense amplifier BLSA1 may be connected to half of the bit lines included in the memory cell array, and the second bit line sense amplifier BLSA2 may be connected to the other half of the bit lines. The first bit line sense amplifier BLSA1 and the second bit line sense amplifier BLSA2 may control the bit lines of the memory cell array and may read and amplify the voltage levels of the bit lines. The third peripheral circuit PC3 may include a sub-word line driver SWD. The sub-word line driver SWD may be connected to the word lines included in the memory cell array and may apply a word line driving voltage to each word line.

[0059] The voltage generator 130 may be disposed in the unused area UNA. One or more external voltages VEXT are applied to the voltage generator 130. The external voltage VEXT, which is a voltage input from the outside of the semiconductor memory device 100, may be a positive voltage, a negative voltage, or an external ground voltage. The voltage generator 130 may convert the (one or more) external voltages VEXT into a first internal voltage VINT1 to be used by the first peripheral circuit PC1, a second internal voltage VINT2 to be used by the second peripheral circuit PC2, and a third internal voltage VINT3 to be used by the third peripheral circuit PC3. The voltage generator 130 may supply the first internal voltage VINT1 to the first peripheral circuit PC1, may supply the second internal voltage VINT2 to the second peripheral circuit PC2, and may supply the third internal voltage VINT3 to the third peripheral circuit PC3. Each of the first internal voltage VINT1 to the third internal voltage VINT3 may include at least one voltage level. The voltage levels respectively included in the first internal voltage VINT1 to the third internal voltage VINT3 are used in the operations of the first peripheral circuit PC1 to the third peripheral circuit PC3.

[0060] Figure 5 is a diagram showing the surface of a second semiconductor structure according to an embodiment of the present disclosure. Refer to Figure 5 , the second semiconductor structure SEMS2 may include a first peripheral circuit area PCA1, a second peripheral circuit area PCA2, a third peripheral circuit area PCA3, and an unused area UNA.

[0061] A plurality of lower metal pads LMP may be disposed on the surface of the second semiconductor structure SEMS2 in the form of a matrix array including a plurality of rows and a plurality of columns of the lower metal pads LMP. Figure 5 An example shows a plurality of lower metal pads LMP in the form of a matrix array having 8 rows and 8 columns, but in this matrix array, the number of rows and columns may be more or less.

[0062] The lower metal pads LMP disposed at the surface of the first peripheral circuit area PCA1 of the second semiconductor structure SEMS2 may be electrically connected to the first peripheral circuit PC1. For example, the first peripheral circuit area PCA1 may be an area including the lower metal pads LMP of the first row and the second row belonging to the matrix array of the lower metal pads LMP. The lower metal pads LMP of the first peripheral circuit area PCA1 correspond to the first peripheral circuit pads PCP1. The first peripheral circuit pads PCP1 may be electrically connected to the first peripheral circuit PC1.

[0063] The lower metal pad LMP disposed on the surface of the second peripheral circuit area PCA2 of the second semiconductor structure SEMS2 can be electrically connected to the second peripheral circuit PC2. For example, the second peripheral circuit area PCA2 can be an area of the lower metal pad LMP including the seventh and eighth rows of the matrix array to which the lower metal pad LMP belongs. The lower metal pad LMP of the second peripheral circuit area PCA2 corresponds to the second peripheral circuit pad PCP2. The second peripheral circuit pad PCP2 can be electrically connected to the second peripheral circuit PC2.

[0064] The lower metal pad LMP disposed on the surface of the third peripheral circuit area PCA3 of the second semiconductor structure SEMS2 can be electrically connected to the third peripheral circuit PC3. For example, the third peripheral circuit area PCA3 can be an area of the lower metal pad LMP including the lower metal pads LMP disposed in the common area defined by the third to sixth rows and the fifth to eighth columns of the matrix array of the lower metal pads LMP. The lower metal pad LMP of the third peripheral circuit area PCA3 corresponds to the third peripheral circuit pad PCP3. The third peripheral circuit pad PCP3 can be electrically connected to the third peripheral circuit PC3.

[0065] The first peripheral circuit PC1 can be a first bit line sense amplifier, the second peripheral circuit PC2 can be a second bit line sense amplifier, and the third peripheral circuit PC3 can be a sub-word line driver. The first peripheral circuit area PCA1 to the third peripheral circuit area PCA3 can correspond to Figure 4 the peripheral circuit area PCA.

[0066] The lower metal pad LMP disposed on the surface of the unused area UNA of the second semiconductor structure SEMS2 corresponds to the isolated lower metal pad ILP. For example, the unused area UNA can be an area of the lower metal pad LMP including the lower metal pads LMP disposed in the common area defined by the third to sixth rows and the first to fourth columns of the matrix array of the lower metal pads LMP. The isolated lower metal pad ILP disposed on the surface of the unused area UNA can be not connected to the first peripheral circuit PC1 to the third peripheral circuit PC3 of the second semiconductor structure SEMS2, nor can it be connected to any other circuit of the second semiconductor structure SEMS2. Each isolated lower metal pad ILP can form all or part of the corresponding electrically floating electrical node.

[0067] As described above, the voltage generator can be disposed in the unused area UNA of the second semiconductor structure SEMS2 (e.g., within the occupied area of the unused area UNA of the second semiconductor structure SEMS2). The voltage generator can supply one or more internal voltages of one or more voltage levels to each of the first peripheral circuit PC1 to the third peripheral circuit PC3.

[0068] Figure 6A and Figure 6B is a diagram illustrating the routing of signals in a first semiconductor structure SEMS1 according to an embodiment of the present disclosure. Referring to Figure 6A , in a memory region MA, a plurality of upper metal pads UMP may be disposed on the surface of the first semiconductor structure SEMS1 in the form of a matrix array including a plurality of rows and a plurality of columns. The placement of the plurality of upper metal pads UMP may be the same as that of Figure 5 a plurality of lower metal pads LMP.

[0069] The upper metal pads UMP connected to bit lines may be disposed on the surface of the first semiconductor structure SEMS1 corresponding to a first peripheral circuit region PCA1. For example, the upper metal pads UMP belonging to the first row and the second row of the matrix array of the upper metal pads UMP may be bit line pads BLP1 connected to some bit lines. Figure 4 a first peripheral circuit PC1 may be connected to a bit line BL through a first peripheral circuit pad PCP1 disposed on the surface of the second semiconductor structure SEMS2 corresponding to the first peripheral circuit region PCA1 and a bit line pad BLP1 disposed on the surface of the first semiconductor structure SEMS1 corresponding to the first peripheral circuit region PCA1.

[0070] The upper metal pads UMP connected to the remaining bit lines may be disposed on the surface of the first semiconductor structure SEMS1 corresponding to a second peripheral circuit region PCA2. For example, the upper metal pads UMP belonging to the seventh row and the eighth row of the matrix array of the upper metal pads UMP may be bit line pads BLP2 connected to the remaining bit lines BL. Figure 4 a second peripheral circuit PC2 may be connected to a bit line BL through a second peripheral circuit pad PCP2 disposed on the surface of the second semiconductor structure SEMS2 corresponding to the second peripheral circuit region PCA2 and a bit line pad BLP2 disposed on the surface of the first semiconductor structure SEMS1 corresponding to the second peripheral circuit region PCA2.

[0071] Some of the bit lines BL may be connected to the first peripheral circuit PC1, and other bit lines BL may be connected to the second peripheral circuit PC2. As described above, each of the first peripheral circuit PC1 and the second peripheral circuit PC2 may include a bit line sense amplifier.

[0072] Isolated upper metal pads IUP may be disposed on the surface of the first semiconductor structure SEMS1 corresponding to an unused region UNA. For example, the unused region UNA may be a region including upper metal pads UMP disposed in a common region defined by the third to sixth rows and the first to fourth columns of the matrix array of the upper metal pads UMP. The isolated upper metal pads IUP disposed in the unused region UNA may not be connected to bit lines and word lines.

[0073] Reference Figure 6B , the first semiconductor structure SEMS1 may include a first bit line connection area BCA1, a second bit line connection area BCA2, and a word line connection area WCA.

[0074] The first bit line connection area BCA1 is placed outside the first side of the memory area MA. The second bit line connection area BCA2 is placed outside the second side of the memory area MA opposite to the first side. The word line connection area WCA is placed outside the third side adjacent to the first side and the second side.

[0075] A plurality of bit line contacts BC are formed in the first bit line connection area BCA1. The bit line pad BLP1 corresponding to the first peripheral circuit area PCA1 is electrically connected to the corresponding bit line contact BC in the bit line contacts BC through a respective first metal line ML1. Thus, some of the first metal lines ML1 can be electrically connected to the bit line pad BLP1 and can be electrically connected to some of the bit lines through the bit line contacts BC in the first bit line connection area BCA1.

[0076] A plurality of bit line contacts BC are formed in the second bit line connection area BCA2. The bit line pad BLP2 corresponding to the second peripheral circuit area PCA2 is electrically connected to the corresponding bit line contact BC in the bit line contacts BC through a respective first metal line ML1. Thus, other first metal lines among the first metal lines ML1 can be electrically connected to the bit line pad BLP2 and can be electrically connected to some of the bit lines through the bit line contacts BC in the second bit line connection area BCA2.

[0077] A plurality of word line contacts WC are formed in the word line connection area WCA. The word line pad WLP corresponding to the third peripheral circuit area PCA3 is electrically connected to the corresponding word line contact WC in the word line contacts WC through a respective first metal line ML1. That is, other first metal lines among the first metal lines ML1 can be electrically connected to the word line pad WLP and can be electrically connected to the word lines through the word line contacts WC in the word line connection area WCA.

[0078] The bit line contacts BC formed in the first bit line connection area BCA1 are connected to some of the bit lines BL of the memory cell array, and the bit line contacts BC formed in the second bit line connection area BCA2 are connected to other bit lines of the bit lines BL of the memory cell array. The word lines formed in the word line connection area WCA can be connected to some or all of the word lines of the memory cell array.

[0079] The first metal line ML1 may be formed in one or more metal layers (e.g., the portions thereof connected through conductive vias) included in the first semiconductor structure SEMS1.

[0080] Figure 7 FIG. is a diagram illustrating a memory cell array 110 of a first semiconductor structure SEMS1 according to an embodiment of the present disclosure. Referring to Figure 7 , a plurality of bit lines BL and a plurality of word lines WL may be disposed in a memory region MA. In the memory region MA, the plurality of bit lines BL may be regularly arranged and spaced apart by a first pitch. The plurality of word lines WL may be regularly arranged and spaced apart by a second pitch (which may be the same as or different from the first pitch).

[0081] A plurality of memory cells (not shown) may be disposed at intersections of the plurality of word lines WL and the plurality of bit lines BL.

[0082] Bit line contacts BC associated with some of the plurality of bit lines BL are formed in a first bit line connection region BCA1, and bit line contacts BC associated with other bit lines of the plurality of bit lines BL are formed in a second bit line connection region BCA2. The bit line contacts BC may be formed only outside the memory region MA, such as arranged along adjacent opposite boundaries of the memory region MA (e.g., the upper and lower boundaries of the memory region MA as Figure 7 shown). Along a specific boundary of the memory region MA, the bit line contacts BC may be arranged in a single line or in a number of adjacent lines (e.g., extending in the D2 direction). Word line contacts WC associated with the plurality of word lines WL are formed in a word line connection region WCA. The word line contacts WC may be formed only outside the memory region MA, such as arranged in a single line or in a number of adjacent lines (extending in the D3 direction) along the boundary of the memory region MA. In Figure 7 , the word line contacts WC are shown as being arranged only on one boundary of the memory region MA, but they may also be arranged along the opposite boundaries of the memory region MA in a similar arrangement (i.e., the word line contacts WC may be arranged along the two boundaries extending in the D3 direction in Figure 7 ).

[0083] Figure 4 A first peripheral circuit PC1 included in a second semiconductor structure SEMS2 of Figure 5 is connected to a lower metal pad LMP disposed in a first peripheral circuit region PCA1 of Figure 6A . The lower metal pad LMP is bonded to an upper metal pad UMP of Figure 6BThe upper metal pad UMP corresponding to the first peripheral circuit area PCA1 is electrically connected to some of the multiple bit lines BL through the first metal line ML1 and the bit line contact BC of the first bit line connection area BCA1. The first peripheral circuit PC1 can operate based on one or more control signals and the first internal voltage VINT1 provided by the voltage generator 130, and can control some of the multiple bit lines BL (e.g., selectively supply voltage thereto) during the access to the memory cells.

[0084] Figure 4 The second peripheral circuit PC2 included in the second semiconductor structure SEMS2 is connected to the lower metal pad LMP provided in Figure 5 the second peripheral circuit area PCA2. The lower metal pad LMP is bonded to Figure 6A the upper metal pad UMP for electrical and physical connection. The upper metal pad UMP corresponding to the second peripheral circuit area PCA2 is electrically connected to the other bit lines of the multiple bit lines BL through the first metal line ML1 and the bit line contact BC of the second bit line connection area BCA2. Figure 6B The second peripheral circuit PC2 can operate based on one or more control signals and the second internal voltage VINT2 provided by the voltage generator 130, and can control the other bit lines of the multiple bit lines BL (e.g., selectively supply voltage thereto) during the access to the memory cells.

[0085] Figure 4 The third peripheral circuit PC3 included in the second semiconductor structure SEMS2 is connected to the lower metal pad LMP provided in Figure 5 the third peripheral circuit area PCA3. The lower metal pad LMP is bonded to Figure 6A the upper metal pad UMP for electrical and physical connection. The upper metal pad UMP corresponding to the third peripheral circuit area PCA3 is electrically connected to the multiple word lines WL through the first metal line ML1 and the word line contact WC of the word line connection area WCA. Figure 6B The third peripheral circuit PC3 can operate based on one or more control signals and the third internal voltage VINT3 provided by the voltage generator 130, and can control the multiple word lines WL (e.g., selectively supply voltage thereto) to provide access to the memory cells.

[0086] In some examples, some of the multiple word lines WL disposed in the memory region MA may be electrically connected to the third peripheral circuit PC3. Other word lines among the multiple word lines WL may be electrically connected to a fourth peripheral circuit (i.e., another sub-word line driver) disposed in another region (which may or may not be disposed below the memory region MA), and may be accessed through the operation of the fourth peripheral circuit. Some of the multiple word lines WL may be odd-numbered word lines WL, while other word lines among the multiple word lines WL may be even-numbered word lines WL. The third peripheral circuit PC3 may be an odd-numbered word line driver connected to the odd-numbered word lines WL, and the fourth peripheral circuit may be an even-numbered word line driver connected to the even-numbered word lines WL.

[0087] Figure 8 is a diagram showing a connection structure of a vertical cross-section along a first direction according to an embodiment of the present disclosure. Refer to Figure 8 , the voltage generator 130 may supply a first internal voltage VINT1 to the first bit line sense amplifier BLSA1. The voltage generator 130 may supply a second internal voltage VINT2 to the second bit line sense amplifier BLSA2.

[0088] The first bit line sense amplifier BLSA1 is disposed in the first peripheral circuit region PCA1 of the second semiconductor structure SEM2. The first bit line sense amplifier BLSA1 is electrically connected to the first peripheral circuit pad PCP1 among the lower metal pads through at least one metal layer included in the second semiconductor structure SEM2. The first peripheral circuit pad PCP1 is bonded to the bit line pad BLP1 of the first semiconductor structure SEM1. That is, the first peripheral circuit pad PCP1 and the bit line pad BLP1 are electrically connected and physically connected. The bit line pad BLP1 is electrically connected to the bit line contact BC1 formed in the first bit line connection region BCA1 through a metal wire formed in at least one metal layer included in the first semiconductor structure SEM1. The bit line contact BC1 provides access to the bit line BL1 disposed in the memory region MA. The first bit line sense amplifier BLSA1 may control the bit line BL1 based on the control signal CS1 and the first internal voltage VINT1, and may read and amplify the voltage of the bit line BL1.

[0089] The second bit line sense amplifier BLSA2 is disposed in the second peripheral circuit area PCA2 of the second semiconductor structure SEM2. The second bit line sense amplifier BLSA2 is electrically connected to the second peripheral circuit pad PCP2 among the plurality of lower metal pads through at least one metal layer included in the second semiconductor structure SEM2. The second peripheral circuit pad PCP2 is bonded to the bit line pad BLP2 of the first semiconductor structure SEM1. That is, the second peripheral circuit pad PCP2 and the bit line pad BLP2 are electrically and physically connected. The bit line pad BLP2 is electrically connected to the bit line contact BC2 formed in the second bit line connection area BCA2 through a metal wire formed in at least one metal layer included in the first semiconductor structure SEM1. The bit line contact BC2 provides access to the bit line BL2 disposed in the memory area MA. The second bit line sense amplifier BLSA2 can control the bit line BL2 based on the control signal CS2 and the second internal voltage VINT2, and can read and amplify the voltage of the bit line BL2. The bit line BL2 can be disposed in the same plane as the bit line BL1.

[0090] The voltage generator 130 is disposed in the unused area UNA of the second semiconductor structure SEM2. The voltage generator 130 can convert the external voltage VEXT received from the outside of the semiconductor memory device 100 into the first internal voltage VINT1 and the second internal voltage VINT2. The voltage generator 130 can supply the first internal voltage VINT1 to the first bit line sense amplifier BLSA1, and can supply the second internal voltage VINT2 to the second bit line sense amplifier BLSA2.

[0091] A first peripheral circuit area PCA1, a second peripheral circuit area PCA2, and an unused area UNA are located in a lower area of a memory area MA. The unused area UNA is adjacent to the first peripheral circuit area PCA1 and the second peripheral circuit area PCA2. A voltage generator 130 may be disposed in the unused area UNA, may supply a first internal voltage VINT1 to a first bit line sense amplifier BLSA1 disposed in the first peripheral circuit area PCA1 adjacent to the unused area UNA, and may supply a second internal voltage VINT2 to a second bit line sense amplifier BLSA2 disposed in the second peripheral circuit area PCA2 adjacent to the unused area UNA. The voltage generator 130 may supply the internal voltages VINT1 and VINT2 to the first bit line sense amplifier BLSA1 and the second bit line sense amplifier BLSA2, respectively, at relatively close positions. In this case, compared with a case where the internal voltages VINT1 and VINT2 are supplied to the first bit line sense amplifier BLSA1 and the second bit line sense amplifier BLSA2 from positions outside the memory area MA, respectively, the voltage generator 130 may supply power to the first bit line sense amplifier BLSA1 and the second bit line sense amplifier BLSA2 more stably, and thus, transient voltage drops may be improved. That is, even if the first bit line sense amplifier BLSA1 and the second bit line sense amplifier BLSA2 instantaneously consume a large amount of power, the voltages supplied to the first bit line sense amplifier BLSA1 and the second bit line sense amplifier BLSA2 may be stably maintained.

[0092] In addition, the voltage generator 130 may supply the first internal voltage VINT1 to the first bit line sense amplifier BLSA1. Similarly, the voltage generator 130 may supply the second internal voltage VINT2 to the second bit line sense amplifier BLSA2.

[0093] Figure 9 FIG. is a diagram illustrating a connection structure of a vertical cross section along a second direction according to an embodiment of the present disclosure. Refer to Figure 9 , the voltage generator 130 may supply a third internal voltage VINT3 to a sub-word line driver SWD.

[0094] The sub-word line driver SWD is disposed in a third peripheral circuit area PCA3 of the second semiconductor structure SEM S2. The sub-word line driver SWD is electrically connected to a third peripheral circuit pad PCP3 among a plurality of lower metal pads through at least one metal layer included in the second semiconductor structure SEM S2. The third peripheral circuit pad PCP3 is bonded to a word line pad WLP of the first semiconductor structure SEM S1. That is, the third peripheral circuit pad PCP3 and the word line pad WLP are electrically and physically connected. The word line pad WLP is electrically connected to a word line contact WC formed in a word line connection area WCA through a metal wire formed in at least one metal layer included in the first semiconductor structure SEM S1. The word line contact WC provides access to a word line WL disposed in a memory area MA. The sub-word line driver SWD may drive the word line WL based on a control signal CS3 and a third internal voltage VINT3.

[0095] The third peripheral circuit area PCA3 and an unused area UNA are located in a portion of the second semiconductor structure SEM S2 under the memory area MA of the first semiconductor structure SEM S1. The unused area UNA is adjacent to the third peripheral circuit area PCA3. A voltage generator 130 may be disposed in the unused area UNA and may provide a third internal voltage VINT3 including one or more voltage levels to the sub-word line driver SWD disposed in the third peripheral circuit area PCA3 adjacent to the unused area UNA. The voltage generator 130 may provide the third internal voltage VINT3 to the sub-word line driver SWD at a relatively close position. In this case, compared with the case of supplying the third internal voltage VINT3 to the sub-word line driver SWD from the outside of the memory area MA, the voltage generator 130 may stably supply power to the sub-word line driver SWD, and thus, transient voltage drops may be improved. That is, even if the sub-word line driver SWD instantaneously uses a large amount of power, the voltage supplied to the sub-word line driver SWD may be stably maintained.

[0096] Figure 10A and Figure 10B is a diagram illustrating the placement of a memory cell array and peripheral circuits according to an embodiment of the present disclosure. Refer to Figure 10A, the memory cell array 110 may include a plurality of sub-memory cell arrays SMAa, SMAb, …, SMAh. In some examples, each of the sub-memory cell arrays SMAa, SMAb, …, SMAh may be the same as the memory cell array MA described herein for the first semiconductor structure SEMS1 (however, they may be formed on a single semiconductor substrate 210 and / or formed in a single semiconductor substrate 210 (e.g., sharing a single semiconductor substrate 210)). In some examples, the peripheral circuits and voltage generators formed under each of the sub-memory cell arrays SMAa, SMAb, …, SMAh may be the same as those described herein for the second semiconductor structure SEMS2 (e.g., the same as the voltage generator 130 and the peripheral circuits 120, PC1, PC2, PC3) (however, they may be formed on a single semiconductor substrate 220 and / or formed in a single semiconductor substrate 220 (e.g., sharing a single semiconductor substrate 220)).

[0097] In each of the plurality of sub-memory cell arrays SMAa to SMAh, a plurality of word lines may be arranged along the second direction D2, and a plurality of bit lines may be arranged along the third direction D3. Each of the plurality of sub-memory cell arrays SMAa to SMAh may include memory cells formed at intersections of the plurality of word lines and the plurality of bit lines.

[0098] The plurality of sub-memory cell arrays SMAa to SMAh may be arranged in the form of a matrix array. For example, the plurality of sub-memory cell arrays SMAa to SMAh may be arranged in two rows and four columns. As an embodiment, the plurality of sub-memory cell arrays SMAa to SMAd may be arranged in the first row, and the plurality of sub-memory cell arrays SMAe to SMAh may be arranged in the second row.

[0099] The word line connection regions WCA1, WCA2, …, WCA5 may be located in the middle regions of the sub-memory cell arrays SMAa to SMAd belonging to the first row and in the outer regions of the sub-memory cell arrays SMAa to SMAd belonging to the first row. For example, the first word line connection region WCA1 may be located in the outer region on one side of the sub-memory cell array SMAa, and the fifth word line connection region WCA5 may be located in the outer region on one side of the sub-memory cell array SMAd on the side opposite to the sub-memory cell array SMAa. The second word line connection region WCA2, the third word line connection region WCA3, and the fourth word line connection region WCA4 may be located in the middle regions of the sub-memory cell arrays SMAa to SMAd belonging to the first row.

[0100] Similar to the sub - memory cell arrays SMAa to SMAd belonging to the first row, the word - line connection regions WCA6, WCA7, …, WCA10 can be located in the middle region of the sub - memory cell arrays SMAe to SMAh belonging to the second row and in the outer region of the sub - memory cell arrays SMAe to SMAh belonging to the second row.

[0101] The sub - memory cell array SMAa and the sub - memory cell array SMAe can be located in the first column. The first bit - line connection region BCA1 can be located outside one side of the sub - memory cell array SMAa. The fifth bit - line connection region BCA5 can be located in the middle region between the sub - memory cell array SMAa and the sub - memory cell array SMAe. The ninth bit - line connection region BCA9 can be located outside one side of the sub - memory cell array SMAe on the side away from the sub - memory cell array SMAa. Similar to the first column, the bit - line connection regions BCA2, BCA3, BCA4, BCA6, BCA7, BCA8, BCA10, BCA11, and BCA12 can be located in the second to fourth columns.

[0102] The word - line contacts of some of the word - lines set in the sub - memory cell array SMAa can be formed in the first word - line connection region WCA1. The word - line contacts of other word - lines set in the sub - memory cell array SMAa can be formed in the second word - line connection region WCA2. For example, the word - line contacts of the even - numbered word - lines set in the sub - memory cell array SMAa can be formed in the first word - line connection region WCA1, and the word - line contacts of the odd - numbered word - lines set in the sub - memory cell array SMAa can be formed in the second word - line connection region WCA2. The even - numbered word - lines and the odd - numbered word - lines can be alternately set in the sub - memory cell array SMAa.

[0103] The word - line contacts formed in the second word - line connection region WCA2 can provide access to the word - lines set in the sub - memory cell array SMAb and to the word - lines set in the sub - memory cell array SMAa. For example, the odd - numbered word - lines among the word - lines set in the sub - memory cell array SMAb can be connected to the word - line contacts of the second word - line connection region WCA2. That is, the odd - numbered word - lines set in the sub - memory cell array SMAa and the odd - numbered word - lines set in the sub - memory cell array SMAb can share the word - line contacts formed in the second word - line connection region WCA2. Similar to the above description, the even - numbered word - lines set in the sub - memory cell array SMAb and the even - numbered word - lines set in the sub - memory cell array SMAc can share the word - line contacts formed in the third word - line connection region WCA3.

[0104] Bit line contacts for some of the bit lines provided in the sub memory cell array SMAa may be formed in the first bit line connection region BCA1. Bit line contacts for other bit lines provided in the sub memory cell array SMAa may be formed in the fifth bit line connection region BCA5. Bit line contacts for some of the bit lines provided in the sub memory cell array SAMe may be formed in the fifth bit line connection region BCA5, and bit line contacts for other bit lines provided in the sub memory cell array SMAe may be formed in the ninth bit line connection region BCA9.

[0105] Reference Figure 10B , a peripheral circuit and a voltage generator may be provided below each of the plurality of sub memory cell arrays SMAa to SMAh. The peripheral circuit may include a first bit line sense amplifier, a second bit line sense amplifier, and a sub word line driver. The (one or more) external voltage VEXT may be applied to the voltage generators VGa, VGb, …, VGh. Each of the voltage generators VGa, VGb, …, VGh may convert the (one or more) external voltage VEXT into one or more internal voltages to be used by the peripheral circuit. Each of the voltage generators VGa, VGb, …, VGh may supply the internal voltage having one or more voltage levels to the peripheral circuit.

[0106] For example, the voltage generator VGa may supply the internal voltage having one or more voltage levels to each of the first bit line sense amplifier BLSAa1, the second bit line sense amplifier BLSAa2, and the sub word line driver SWDa. As in the above description, each of the voltage generators VGb to VGh may similarly supply the internal voltage having one or more voltage levels to the peripheral circuit adjacent thereto.

[0107] The first bit line sense amplifier BLSAa1 may be connected to some of the bit lines provided in the sub memory cell array SMAa through metal lines, metal pads, and bit line contacts formed in the first bit line connection region BCA1. The first bit line sense amplifier BLSAa1 may control some of the bit lines provided in the sub memory cell array SMAa based on the (one or more) control signals and the internal voltage supplied from the voltage generator VGa.

[0108] The second bit line sense amplifier BLSAa2 may be connected to other bit lines of the bit lines provided in the sub memory cell array SMAa through metal lines, metal pads, and bit line contacts formed in the fifth bit line connection region BCA5. The second bit line sense amplifier BLSAa2 may control other bit lines of the bit lines provided in the sub memory cell array SMAa based on the (one or more) control signals and the internal voltage supplied from the voltage generator VGa.

[0109] The sub-word line driver SWDa can be connected to odd word lines among the word lines provided in the sub memory cell array SMAa through metal lines, metal pads, and word line contacts formed in the second word line connection region WCA2. The sub-word line driver SWDa can drive the odd word lines provided in the sub memory cell array SMAa based on (one or more) control signals and an internal voltage provided from the voltage generator VGa. In this case, the sub-word line driver SWDa can further drive the odd word lines provided in the sub memory cell array SMAb that share the word line contacts with the odd word lines provided in the sub memory cell array SMAa.

[0110] The sub-word line driver SWDb can be connected to even word lines provided in the sub memory cell arrays SMAb and SMAc through metal lines, metal pads, and word line contacts formed in the third word line connection region WCA3. The sub-word line driver SWDb can drive the even word lines provided in the sub memory cell arrays SMAb and SMAc based on (one or more) control signals and an internal voltage provided from the voltage generator VGb.

[0111] The voltage generators VGa to VGh are respectively provided in the lower regions of the sub memory cell arrays SMAa to SMAh. Each of the voltage generators VGa to VGh can provide an internal voltage to adjacent peripheral circuits as described herein with respect to the voltage generator VGa and 130. Since each of the voltage generators VGa to VGh provides an internal voltage to adjacent peripheral circuits, the influence of transient voltage drops between the peripheral circuits can be reduced, and the internal voltage used by the peripheral circuits can be stably maintained.

[0112] Figure 10A and Figure 10B The sub memory cell arrays SMAa to SMAh and the peripheral circuits of can be in the shape of a matrix having two rows and four columns, but this is an example. The number of rows of the sub memory cell arrays constituting the memory cell array 110 can be more or less.

[0113] Figure 11 is a diagram showing details of an integrated circuit device that can be embodied by the semiconductor memory device described herein. Referring to Figure 11 , the integrated circuit device can include a memory cell array structure MAS and a core-peripheral circuit structure CPS. The integrated circuit device can be a semiconductor chip formed in a chip-on-periphery (CoP) structure.

[0114] A memory cell array structure MAS may be formed on a first substrate SB1 (e.g., a semiconductor substrate). The memory cell array structure MAS may include a data storage structure DSS and a signal routing structure SRS. The data storage structure DSS may include a plurality of memory cells, a plurality of bit lines, and a plurality of word lines, each memory cell including a capacitor "C" and a cell transistor TR (e.g., a DRAM cell). The signal routing structure SRS may include a plurality of upper metal pads UMP and a plurality of metal lines ML. The plurality of metal lines ML electrically connect the plurality of upper metal pads UMP and components of the data storage structure DSS. For example, the plurality of metal lines ML may electrically connect some of the plurality of upper metal pads UMP and the bit lines. Additionally, the plurality of metal lines ML may electrically connect some of the plurality of upper metal pads UMP and the word lines.

[0115] A core - peripheral circuit structure CPS may be formed on a second substrate SB2. The core - peripheral circuit structure CPS may include a transistor layer TRL. Various elements including a plurality of transistors for controlling or driving the bit lines and word lines included in the data storage structure DSS may be provided in the transistor layer TRL. Some of the plurality of elements provided in the transistor layer TRL may be included in a bit line sense amplifier. Other elements of the plurality of elements provided in the transistor layer TRL may be included in a sub - word line driver. Other elements of the plurality of elements provided in the transistor layer TRL may be included in a voltage generator.

[0116] A plurality of lower metal pads LMP may be provided at the surface of the core - peripheral circuit structure CPS. Some or all of the plurality of lower metal pads LMP may be electrically connected to a plurality of peripheral circuits provided in the transistor layer TRL through a plurality of metal lines ML.

[0117] The plurality of upper metal pads UMP and the plurality of lower metal pads LMP may be provided in the same matrix array form and provide electrical connections for each component included in the memory cell array structure MAS and each component included in the core - peripheral circuit structure CPS. The plurality of upper metal pads UMP and the plurality of lower metal pads LMP may constitute a pad array PDA.

[0118] In addition, an unused area may be located below a part of a memory area where a plurality of word lines and a plurality of bit lines are provided. The upper metal pads UMP corresponding to the unused area may not be connected to the bit lines and word lines. The lower metal pads LMP corresponding to the unused area may not be connected to the bit line sense amplifier and the sub - word line driver. A voltage generator may be provided in an area of the transistor layer TRL corresponding to the unused area. The voltage generator may supply an internal voltage to an adjacent bit line sense amplifier or an adjacent sub - word line driver.

[0119] One or more plugs PG provide an electrical connection between the core-peripheral circuit structure CPS and devices external to the integrated circuit device. Command signals, address signals, data signals, and external power can be input to the core-peripheral circuit structure CPS through one or more plugs PG.

[0120] In the integrated circuit device, since the memory cell array structure MAS and the core-peripheral circuit structure CPS are vertically arranged, the area on the plane can be reduced compared to the case where the memory cell array and the peripheral circuit are arranged on one plane.

[0121] Figure 12 is a diagram showing Figure 11 the array of pads of the integrated circuit device. Referring to Figure 12 , the pad array PDA may include a plurality of bit line pads BL_PADs and a plurality of word line pads WL_PADs. The pad array PDA corresponds to Figure 11 the plurality of upper metal pads UMP shown. Figure 11 The lower metal pads LMP of

[0122] can be arranged to have the same layout as the upper metal pads UMP. A plurality of bit line pads BL_PADs may be arranged in a first peripheral region of the plane and a second peripheral region of the plane opposite to the first peripheral region. The plurality of bit line pads BL_PADs can be electrically connected to the bit line connection region BLB through one or more metal layers. Signals received through the plurality of bit line pads BL_PADs arranged in the first peripheral region can be routed to the bit line connection region BLBa outside the first peripheral region, and signals received through the plurality of bit line pads BL_PADs arranged in the second peripheral region can be routed to the bit line connection region BLBb outside the second peripheral region.

[0123] The bit line connection regions BLBa and BLBb can provide an electrical connection between the plurality of bit line pads BL_PADs and the bit lines included in the memory cell array (e.g., as described elsewhere herein). The word line connection region WLB can provide an electrical connection between the plurality of word line pads WL_PADs and the word lines included in the memory cell array (e.g., as described elsewhere herein).

[0124] Figure 13 is a diagram showing a vertical cross-section of the integrated circuit device taken along Figure 12 line A-A'. Referring to Figure 13 , the bit line sense amplifier provided in the transistor layer TRL can be electrically connected to the bit line BL.

[0125] For clarity, some components (e.g., adjacent metal pads) are not shown, and repetitive descriptions may be omitted.

[0126] The data storage structure DSS may include a plurality of capacitors "C", cell transistors TR, and a plurality of bit lines BL. The signal routing structure SRS is an example of the metal lines ML described herein and may include portions of a plurality of metal layers LM0 to LM3 and an upper metal pad UMP0. The routing shown may be simplified, and other patterns may be formed in the metal layers to form the routing structure / metal lines ML.

[0127] The bit line sense amplifier circuit disposed in the transistor layer TRL may be connected to the lower metal pad LMP0 through metal layers M0, M1, M2, M3, M4, and M5 (which form another example of the metal lines ML described herein). The lower metal pad LMP0 may be bonded to the upper metal pad UMP0. That is, the lower metal pad LMP0 may be physically and electrically connected to the upper metal pad UMP0. The upper metal pad UMP0 may be electrically connected to portions of a plurality of metal layers LM3, LM2, LM1, and LM0. The metal layer LM0 may be electrically connected to the bit line BL through a metal contact MC0. The metal contact MC0 may be formed in Figure 12 the bit line connection region BLB. The potential change of the bit line BL caused by the capacitor "C" and the cell transistor TR is transmitted to the transistor layer TRL through a plurality of metal lines formed by portions of LM0 to LM3, the upper metal pad UMP0, the lower metal pad LMP0, and portions of a plurality of metal layers M0 to M5. The bit line sense amplifier disposed in the transistor layer TRL may read and amplify the data stored in the capacitor "C" by amplifying the potential difference between the potential of the bit line BL and the potential of a complementary bit line (a complementary bit line (not shown) to which the bit line sense amplifier is also connected in a similar manner).

[0128] Figure 14 is a diagram showing a vertical cross-section of an integrated circuit device taken along Figure 12 the line B-B'. Referring to Figure 14 , the sub-word line driver disposed in the transistor layer TRL may be electrically connected to the word line WL.

[0129] Certain components (e.g., adjacent metal pads) are not shown for clarity, and repetitive descriptions may be omitted.

[0130] The data storage structure DSS may include a plurality of capacitors "C", cell transistors TR, a plurality of bit lines BL, and a plurality of word lines WL. The signal routing structure SRS is an example of the metal line ML described herein and may include portions of a plurality of metal layers LM0 to LM3 and an upper metal pad UMP1. A sub-word line driver disposed in the transistor layer TRL may be connected to a lower metal pad LMP1 through metal layers M0, M1, M2, M3, M4, and M5 (forming another example of the metal line ML described herein). The lower metal pad LMP1 may be bonded to the upper metal pad UMP1. That is, the lower metal pad LMP1 may be physically and electrically connected to the upper metal pad UMP1. The upper metal pad UMP1 may be electrically connected to portions of a plurality of metal layers LM3, LM2, LM1, and LM0. The metal layer LM0 may be electrically connected to the word line WL through a metal contact MC0. The metal contact MC0 may be formed in Figure 12 the word line connection region WLB. The word line driving voltage output from the sub-word line driver is applied to the word line WL through portions of a plurality of metal layers M0 to M5, the lower metal pad LMP1, the upper metal pad UMP1, portions of a plurality of metal layers LM0 to LM3, and the metal contact MC0. The cell transistor TR may be switched by the word line driving voltage applied to the word line WL, and thus, the bit line BL and the capacitor "C" are connected.

[0131] As described above, a semiconductor memory device according to an embodiment of the present disclosure may include a voltage generator that is disposed in a region below the memory cell array and supplies an internal voltage to an adjacent peripheral circuit. Since the voltage generator provides the internal voltage to the peripheral circuit in a relatively close position, transient voltage drops caused when the power consumption of the peripheral circuit instantaneously increases can be improved.

[0132] In a semiconductor memory device according to an embodiment of the present disclosure, a memory cell array is disposed in a memory region of a first semiconductor substrate, and a peripheral circuit and a voltage generator are disposed in a second semiconductor substrate bonded to the first semiconductor substrate through a metal pad. The peripheral circuit and the voltage generator are disposed below (or on the lower side) the memory region adjacent to each other. Therefore, the voltage generator can stably supply voltage to the peripheral circuit, and the integration degree of the semiconductor memory device can be improved.

[0133] Although the present invention has been described with reference to embodiments of the present invention, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A first semiconductor structure, the first semiconductor structure including a first semiconductor substrate, a memory cell array, and a plurality of upper metal pads, the memory cell array being formed in a memory region of the first semiconductor substrate and including bit lines and word lines; And A second semiconductor structure, the second semiconductor structure being disposed below the first semiconductor structure and including a second semiconductor substrate, a plurality of lower metal pads respectively bonded to the plurality of upper metal pads, a peripheral circuit disposed below the memory region, and a voltage generator disposed on a lower side of the memory region to supply an internal voltage to the peripheral circuit, Wherein the bit lines and the word lines are electrically connected to corresponding ones of the plurality of upper metal pads, and Wherein some or all of the plurality of lower metal pads are electrically connected to terminals of the peripheral circuit.

2. The semiconductor memory device according to claim 1, Among them, The plurality of lower metal pads include a first lower metal pad electrically connected to the peripheral circuit and a second lower metal pad serving as a dummy pad, and Wherein the voltage generator is disposed below the second lower metal pad.

3. The semiconductor memory device according to claim 1, wherein, The peripheral circuit includes a first bit line sense amplifier, a second bit line sense amplifier, and a sub-word line driver.

4. The semiconductor memory device according to claim 3, wherein, The first bit line sense amplifier is disposed in a first peripheral region below a first side of the memory cell array, the second bit line sense amplifier is disposed in a second peripheral region below a second side of the memory cell array opposite to the first side of the memory cell array, and the sub-word line driver is disposed in a third peripheral region below a third side of the memory cell array located between the first peripheral region and the second peripheral region.

5. The semiconductor memory device according to claim 4, wherein, The voltage generator supplies the internal voltage to at least one of the first bit line sense amplifier, the second bit line sense amplifier, and the sub-word line driver.

6. The semiconductor memory device according to claim 1, wherein The first semiconductor structure further includes a first bit line connection region, a second bit line connection region, and a word line connection region.

7. The semiconductor memory device according to claim 6, wherein, The first bit line connection region is located outside a first side of the memory cell array and is positioned along the first side, the second bit line connection region is located outside a second side of the memory cell array opposite to the first side of the memory cell array and is positioned along the second side, and the word line connection region is located outside a third side of the memory cell array extending between the first side and the second side and is positioned along the third side.

8. The semiconductor memory device according to claim 7, wherein, The first semiconductor structure further includes a first metal line and a bit line contact, the first metal line being connected to a corresponding one of the plurality of upper metal pads, and the bit line contact electrically connecting a corresponding bit line among the bit lines and the first metal line in the first bit line connection region.

9. The semiconductor memory device according to claim 8, wherein, The first semiconductor structure further includes a second metal line and a word line contact, the second metal line being connected to a corresponding one of the plurality of upper metal pads, and the word line contact electrically connecting a corresponding word line among the word lines and the second metal line in the word line connection region.

10. A semiconductor memory device, the semiconductor memory device comprising: A first semiconductor structure, the first semiconductor structure including a first semiconductor substrate, a plurality of sub - memory cell arrays arranged in a two - dimensional manner, and a plurality of upper metal pads; And A second semiconductor structure, the second semiconductor structure disposed below the first semiconductor structure, Wherein, the second semiconductor structure includes a second semiconductor substrate, a plurality of lower metal pads, a plurality of peripheral circuits, and a plurality of voltage generators, the plurality of lower metal pads are bonded to the plurality of upper metal pads, the plurality of peripheral circuits are respectively disposed below the corresponding sub - memory cell arrays among the plurality of sub - memory cell arrays and are electrically connected to the corresponding sub - memory cell arrays among the plurality of sub - memory cell arrays, and the plurality of voltage generators are all disposed below the corresponding sub - memory cell arrays among the plurality of sub - memory cell arrays to provide an internal voltage to the corresponding peripheral circuits.

11. The semiconductor memory device according to claim 10, wherein, Each of the plurality of peripheral circuits includes a first bit - line sense amplifier, a second bit - line sense amplifier, and a sub - word - line driver.

12. The semiconductor memory device according to claim 11, wherein, The first bit - line sense amplifier corresponding to the first sub - memory cell array among the plurality of sub - memory cell arrays is disposed in a first peripheral region below the first side of the first sub - memory cell array, the second bit - line sense amplifier corresponding to the first sub - memory cell array is disposed in a second peripheral region below the second side of the first sub - memory cell array facing the first side of the first sub - memory cell array, and the sub - word - line driver is disposed below the third side of the first sub - memory cell array located between the first peripheral region and the second peripheral region.

13. The semiconductor memory device according to claim 12, wherein, The first voltage generator among the plurality of voltage generators is disposed below the first sub - memory cell array in a first region, the first region being adjacent to the first bit - line sense amplifier on the first side of the first region, the second bit - line sense amplifier on the second side of the first region, and the sub - word - line driver on the third side of the first region.

14. The semiconductor memory device according to claim 12, Among them, The first sub - memory cell array includes a plurality of odd - numbered bit - lines interleaved with a plurality of even - numbered bit - lines, Wherein, the plurality of sub - memory cell arrays further includes a second sub - memory cell array adjacent to the first sub - memory cell array in the row direction and including a plurality of odd - numbered bit - lines interleaved with a plurality of even - numbered bit - lines, and Wherein, a first sub - word - line driver drives the odd - numbered bit - lines of the first sub - memory cell array and the odd - numbered bit - lines of the second sub - memory cell array.

15. The semiconductor memory device according to claim 14, Among them, The plurality of sub - memory cell arrays further includes a third sub - memory cell array adjacent to the second sub - memory cell array in the row direction and including a plurality of odd - numbered bit - lines interleaved with a plurality of even - numbered bit - lines, and Wherein, a second sub - word - line driver is disposed below the second sub - memory cell array to drive the even - numbered bit - lines of the second sub - memory cell array and the even - numbered bit - lines of the third sub - memory cell array.

16. The semiconductor memory device according to claim 12, wherein, The first semiconductor structure further includes a first bit line connection region extending in a column direction and positioned along a first side of the first sub - memory cell array, and a second bit line connection region extending in the column direction and positioned along a second side of the first sub - memory cell array, where the second side of the first sub - memory cell array is opposite to the first side of the first sub - memory cell array.

17. The semiconductor memory device according to claim 16, Among them, The first bit line sense amplifier is electrically connected to a corresponding bit line metal contact formed in the first bit line connection region, and wherein the second bit line sense amplifier is electrically connected to a corresponding bit line metal contact formed in the second bit line connection region.

18. A semiconductor memory device, the semiconductor memory device comprising: A first semiconductor substrate; A memory cell array formed in a memory region of the first semiconductor substrate and including a plurality of word lines and a plurality of bit lines; A plurality of upper metal pads formed in the memory region and arranged in a two - dimensional array; One or more first metal layers that electrically connect a first end of the plurality of word lines or a first end of the plurality of bit lines to a corresponding upper metal pad among the plurality of upper metal pads; A second semiconductor substrate disposed under the first semiconductor substrate; A first bit line sense amplifier formed in a region of the second semiconductor substrate under the memory cell array and configured to read and amplify a voltage of a corresponding bit line among the plurality of bit lines; A second bit line sense amplifier formed in a region of the second semiconductor substrate under the memory cell array and configured to read and amplify a voltage of a corresponding bit line among the plurality of bit lines; A sub - word line driver configured to apply a voltage to a corresponding word line among the plurality of word lines; A voltage generator formed in a first region of the second semiconductor substrate under the memory cell array and configured to provide an internal voltage to at least one of the first bit line sense amplifier, the second bit line sense amplifier, and the sub - word line driver; A plurality of lower metal pads arranged in a two - dimensional array; And One or more second metal layers that electrically connect the first bit line sense amplifier, the second bit line sense amplifier, and the sub - word line driver to corresponding lower metal pads among the plurality of lower metal pads, and wherein the plurality of upper metal pads and the plurality of lower metal pads are bonded together.

19. The semiconductor memory device according to claim 18, wherein, The first bit line sense amplifier is disposed in a first peripheral region below a first side of the memory cell array, the second bit line sense amplifier is disposed in a second peripheral region below a second side of the memory cell array opposite to the first side of the memory cell array, and the sub-word line driver is disposed in a third peripheral circuit region between the first peripheral region and the second peripheral region.

20. The semiconductor memory device according to claim 19, wherein, The first region is adjacent to each of the first peripheral region, the second peripheral region, and the third peripheral circuit region.

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