Sensitive amplification circuit and memory

Abstract

The application discloses a sensitive amplification circuit and a memory. The sensitive amplification circuit is applied to the memory. The sensitive amplification circuit comprises a sensitive amplification module, target bit lines and complementary bit lines are connected to the sensitive amplification module respectively, and the sensitive amplification module has a first circuit and a second circuit. In a pre-charging stage, the voltages on the target bit lines and the complementary bit lines are pulled to a reference voltage. In an activation stage, the target bit lines transfer storage charges stored in corresponding selected storage units. In a sensing stage, the sensitive amplification module is used for, through the first circuit and the second circuit, respectively accessing corresponding power supply voltages, performing sensitive amplification processing on a target bit line voltage on the target bit line from which the storage charges are transferred. A sensitive voltage control module is connected to the first circuit and the second circuit respectively. The sensitive voltage control module is used for, in a writing stage after the sensing stage, stopping the first circuit and the second circuit from respectively accessing the corresponding power supply voltages. Based on the above mode, the writing success rate of the memory can be improved.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to sensitive amplifier circuits and memories. Background Art

[0002] In the prior art, the writing process of a memory device (such as DRAM (Dynamic Random Access Memory)) works by first forcing the voltage on the corresponding target bit line to 0 or 1 via a strong power supply in a sensitive amplifier circuit to write data to the memory cell. Then, when the data stored in the memory cell needs to be rewritten, the voltage on the target bit line is rewritten to change its state from 0 to 1, or from 1 to 0, thereby rewriting the data in the memory cell.

[0003] The drawback of the prior art is that, since the 0 or 1 on the target bit line is set based on a strong power supply, a large driving capability is required to change the state of the target bit line in the sensitive amplifier circuit when performing the above-mentioned data rewriting. In addition, a relatively sufficient write time is required to achieve the data rewriting. If the driving capability is insufficient or the write time is insufficient, the above-mentioned data rewriting may easily fail. That is, the write success rate of the existing memory is low. Summary of the Invention

[0004] The main technical problem solved by this application is how to improve the writing success rate of the memory.

[0005] In order to solve the above technical problems, the first technical solution adopted in the present application is: a sensitive amplifier circuit, applied to a memory, the sensitive amplifier circuit comprising: a sensitive amplifier module, respectively connected to a target bit line and a complementary bit line, and having a first circuit and a second circuit; in a pre-charging phase, the voltages on the target bit line and the complementary bit line are both pulled to a reference voltage; in an activation phase, the target bit line transfers the storage charge stored in the corresponding selected memory cell; in a sensing phase, the sensitive amplifier module is used to, respectively access the corresponding power supply voltage through the first circuit and the second circuit, and perform sensitive amplification processing on the target bit line voltage on the target bit line that has transferred the storage charge; a sensitive voltage control module, respectively connected to the first circuit and the second circuit, and the sensitive voltage control module is used to, in a write phase after the sensing phase, stop accessing the corresponding power supply voltage through the first circuit and the second circuit, respectively.

[0006] The sensitive voltage control module is used to float the first line and the second line respectively in a writing phase after the sensing phase, so as to stop accessing the corresponding power supply voltage.

[0007] Among them, the sensitive voltage control module includes: a first switch unit, the first end of the first switch unit is used to receive a first power supply voltage, the second end of the first switch unit is connected to the first circuit, and the control end of the first switch unit is used to receive a first control signal; the first power supply voltage is greater than the reference voltage; a second switch unit, the first end of the second switch unit is used to receive a second power supply voltage, the second end of the second switch unit is connected to the second circuit, and the control end of the second switch unit is used to receive a second control signal; the second power supply voltage is less than the reference voltage; the first control signal and the second control signal are used to turn on the corresponding switch unit in the sensing phase and disconnect the corresponding switch unit in the writing phase.

[0008] Among them, the sensitive voltage control module also includes: a third switch unit, the first end of the third switch unit is connected to the first circuit, the second end of the third switch unit is connected to the second circuit, and the control end of the third switch unit is used to receive a third control signal; the third control signal is used to disconnect the corresponding switch unit in the sensing phase and turn on the corresponding switch unit in the writing phase.

[0009] The conduction time of the third switch unit in the writing phase is less than or equal to the total time of the writing phase.

[0010] Among them, the third switch unit includes: a first sub-switch, the first end of the first sub-switch is connected to the first circuit; a second sub-switch, the second end of the first sub-switch is connected to the first end of the second sub-switch, and the second end of the second sub-switch is connected to the second circuit, the control end of the first sub-switch and the control end of the second sub-switch are used to receive a third control signal, and the third control signal is used to disconnect the corresponding sub-switch in the sensing phase and turn on the corresponding sub-switch in the writing phase.

[0011] The first supply voltage is twice or more than twice the reference voltage, and / or the second supply voltage is the ground voltage.

[0012] Among them, the sensitive amplifier circuit also includes: a column selection module, the first end of the column selection module is connected to the target bit line, the second end of the column selection module is connected to the target input and output line, and the column selection module is used to be turned on during the write phase to perform a write operation on the storage unit corresponding to the target bit line through the target input and output line.

[0013] Among them, the sensitive amplifier circuit also includes: an initialization module, the initialization module is respectively connected to the target bit line, the complementary bit line and the reference voltage line, the reference voltage line is used to provide a reference voltage, and the initialization module is used to turn on the target bit line, the complementary bit line and the reference voltage line during the pre-charging stage to pull the voltages on the target bit line and the complementary bit line to the reference voltage.

[0014] In order to solve the above technical problems, the second technical solution adopted in this application is: a memory including the above sensitive amplifier circuit.

[0015] The beneficial effects of the present application are as follows: different from the prior art, in the technical solution of the present application, a sensitive amplifier circuit is applied to a memory, and the sensitive amplifier circuit includes: a sensitive amplifier module, which is respectively connected to a target bit line and a complementary bit line and has a first circuit and a second circuit; in a pre-charging phase, the voltages on the target bit line and the complementary bit line are both pulled to a reference voltage; in an activation phase, the target bit line transfers the storage charge stored in the corresponding selected memory cell; in a sensing phase, the sensitive amplifier module is used to respectively access the corresponding power supply voltage through the first circuit and the second circuit, and perform sensitive amplification processing on the target bit line voltage on the target bit line that has transferred the storage charge; a sensitive voltage control module, which is respectively connected to the first circuit and the second circuit, and is used to stop respectively accessing the corresponding power supply voltage through the first circuit and the second circuit in a write phase after the sensing phase. Based on the above method, after the sensing stage in which the target bit line voltage on the target bit line is sensitively amplified based on the power supply voltage, that is, in the write stage, the power supply voltage is stopped from being connected through the first line and the second line. At this time, if data needs to be rewritten for the storage unit corresponding to the target bit clue in the write stage, since the target bit line is no longer connected to the power supply voltage, the target bit line voltage on the target bit line can be changed while providing a voltage with a lower absolute amplitude and a shorter data rewriting time. That is, the strength of the driving capability of the voltage required to provide when rewriting the data is reduced, and the necessary time of the write stage when rewriting the data is also reduced, thereby reducing the possibility of data rewriting failure in the memory during the write stage and improving the write success rate of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 It is a structural diagram of an embodiment of the memory of the present application;

[0018] Figure 2 This is a structural diagram of an embodiment of the sensitive amplification module of the present application;

[0019] Figure 3 is a schematic diagram of an embodiment of the sensitive amplification process of the present application;

[0020] Figure 4 This is a waveform diagram of the conventional technology of this application;

[0021] Figure 5This is a structural diagram of an embodiment of the sensitive voltage control module of the present application;

[0022] Figure 6 It is a waveform diagram of the sensitive amplifier circuit of the present application;

[0023] Figure 7 It is a structural diagram of an embodiment of the memory of the present application.

[0024] Figure numerals: 10, sensitive amplifier circuit; 11, sensitive amplifier module; 12, sensitive voltage control module; 121, first switch unit; 122, second switch unit; 123, third switch unit; 1231, first sub-switch; 1232, second sub-switch; 20, storage unit; 30, memory. DETAILED DESCRIPTION

[0025] The present application will be further described in detail below in conjunction with the accompanying drawings and examples. It is particularly noted that the following examples are only intended to illustrate the present application and are not intended to limit the scope of the present application. Similarly, the following examples are only some examples of the present application and not all examples. All other examples obtained by those of ordinary skill in the art without creative work are intended to fall within the scope of protection of this application.

[0026] References to "embodiments" herein mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0027] In the description of this application, it should be noted that, unless otherwise specified or limited, the terms "installed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they can mean fixed connection, detachable connection, or integral connection; mechanical connection or electrical connection; direct connection or connection through an intermediate medium. Those skilled in the art will be able to understand the specific meanings of the above terms in this application in specific circumstances.

[0028] This application proposes a sensitive amplifier circuit, which is applied to a memory. Figure 1 , Figure 1 Schematic diagram of the structure of an embodiment of the memory of the present application. Figure 1 As shown, the sensitive amplifier circuit includes a sensitive amplifier module 11 and a sensitive voltage control module 12 .

[0029] The sense amplifier module 11 is connected to the target bit line and the complementary bit line respectively, and has a first circuit and a second circuit.

[0030] In the precharge phase, the voltages on the target bit line and the complementary bit line are both pulled to the reference voltage. In the activation phase, the target bit line transfers the stored charge stored in the corresponding selected memory cell 20. In the sensing phase, the sensitive amplifier module 11 is used to connect the corresponding supply voltage through the first line and the second line respectively, and perform sensitive amplification processing on the target bit line voltage on the target bit line after the stored charge is transferred.

[0031] The sensitive voltage control module 12 is connected to the first line and the second line respectively. The sensitive voltage control module 12 is used to stop accessing the corresponding power supply voltage through the first line and the second line respectively in a writing phase after the sensing phase.

[0032] For example, see Figure 2 , Figure 2 This is a schematic structural diagram of an embodiment of the sensitive amplification module of the present application. Figure 1 and Figure 2 As shown, WL is the word line, BL is the target bit line, BL# is the complementary bit line, PCS is the first line, NCS is the second line, the first line can be used to receive the power supply voltage provided by the high-voltage strong power supply, and the second line can be used to receive the power supply voltage provided by the low-voltage strong power supply.

[0033] See also Figure 3 , Figure 3 This is a schematic diagram of an embodiment of the sensitive amplification process of the present application. Figure 3 As shown, in the pre-charging stage, the voltages on the target bit line BL and the complementary bit line BL# can be pulled to the reference voltage Vref, i.e., Vcc / 2, through the corresponding initialization module. The amplitude of the power supply voltage provided by the high-voltage strong power supply is Vcc, and the amplitude of the power supply voltage provided by the low-voltage strong power supply is GND, i.e., the ground voltage.

[0034] In the activation phase, the corresponding memory cell 20 may be selected through the word line WL so that the capacitor of the corresponding memory cell 20 is connected to the target bit line BL, thereby transferring the stored charge in the capacitor of the memory cell 20 to the target bit line.

[0035] During the sensing phase, the first line PCS can be connected to the power supply voltage provided by a high-voltage power supply, and the second line NCS can be connected to the power supply voltage provided by a low-voltage power supply. The sensitive amplifier module 11 can perform sensitive amplification processing on the target bit line voltage on the target bit line BL based on the power supply voltages respectively provided by the two strong power supplies received, so as to increase the target bit line voltage of the target bit line with a relatively high voltage after the storage voltage is transferred, or reduce the target bit line voltage of the target bit line with a relatively low voltage after the storage voltage is transferred, so as to improve the recognizability of the target bit line voltage. In this case, the sensitive amplifier module 11 can be controlled by providing a first sensitive amplification control signal SOT and a second sensitive amplification control signal OCT to achieve the above-mentioned sensitive amplification processing.

[0036] In the write phase, the power supply voltage provided by the corresponding strong power supply through the first line PCS and the second line NCS can be stopped. At the same time, the line between the target input-output line LIO and the target bit line BL is turned on through the column selection signal YST provided by the corresponding column selection module, and the line between the complementary input-output line LIO# and the complementary bit line BL# is turned on. The corresponding high-voltage or low-voltage signal is input through the target input-output line LIO, so that the target bit line voltage on the target bit line BL is the same as the voltage of the signal output by the target input-output line LIO, and then the signal is output through the target bit line BL. The data is written to the capacitor of the memory cell 20. Since the power supply voltage provided by the corresponding high-voltage power source is no longer connected to the first and second lines PCS and NCS, when the voltage difference between the target voltage signal and the signal output by the target input / output line LIO is large, that is, when the data of the memory cell 20 needs to be rewritten (e.g., from 0 to 1, or from 1 to 0), the target bit line voltage can be changed more quickly than in conventional techniques that maintain the power supply voltage, while maintaining the same driving capability of the target input / output line BL. This allows for faster data rewriting of the memory cell 20. During the write phase, the power supply voltage provided by the corresponding high-voltage power source can be stopped from being connected to the first and second lines PCS and NCS, for example, by disconnecting the first and second lines PCS and NCS. During other phases outside the write phase, the power supply voltage provided by the corresponding high-voltage power source can be restored to the first and second lines PCS and NCS, for example, by turning on the first and second lines PCS and NCS, to restore the sensitive amplifier circuit's ability to sensitively amplify the voltage on the target input / output line BL based on the power supply voltage.

[0037] It should be noted here that, see Figure 4 , Figure 4 It is a waveform diagram of the conventional technology of this application, such as Figure 4As shown, in the conventional technology, since the corresponding power supply voltages are respectively connected through the first line PCS and the second line NCS during the write phase, when the driving capability of the target input / output line BL is the same and the column selection time length (the period length during which the column selection signal YST is at a high level) provided by the column selection signal YST is the same, the speed of change of the target bit line voltage is relatively slower, which easily leads to the following phenomenon: Figure 4 In the situation shown, the voltage of the target bit line BL has not completed the voltage change before the column selection signal YST returns to a low level, then the target bit line voltage will be restored to the original voltage under the action of the sensitive amplifier module 11, that is, the data rewrite fails, resulting in a low write success rate of the memory in the traditional technology.

[0038] Through the technical solution of the present application, the data rewriting rate can be increased when the driving capability of the target input and output lines BL is the same, thereby reducing the possibility of data rewriting failure in the above-mentioned traditional technology and improving the writing success rate of the memory.

[0039] Furthermore, when the data rewriting rate is relatively fast, the data writing efficiency can be improved by reducing the column strobe time, thereby enhancing the performance of the memory.

[0040] Different from the prior art, in the technical solution of the present application, a sensitive amplifier circuit is applied to a memory, and the sensitive amplifier circuit includes: a sensitive amplifier module, which is respectively connected to a target bit line and a complementary bit line and has a first circuit and a second circuit; in a pre-charging phase, the voltages on the target bit line and the complementary bit line are both pulled to a reference voltage; in an activation phase, the target bit line transfers the stored charge stored in the corresponding selected memory cell; in a sensing phase, the sensitive amplifier module is used to respectively access the corresponding power supply voltage through the first circuit and the second circuit, and perform sensitive amplification processing on the target bit line voltage on the target bit line that has transferred the stored charge; a sensitive voltage control module, which is respectively connected to the first circuit and the second circuit, and is used to stop respectively accessing the corresponding power supply voltage through the first circuit and the second circuit in a write phase after the sensing phase. Based on the above method, after the sensing stage in which the target bit line voltage on the target bit line is sensitively amplified based on the power supply voltage, that is, in the write stage, the supply voltage is stopped from being connected through the first line and the second line. At this time, if data needs to be rewritten for the storage cell corresponding to the target bit line in the write stage, since the target bit line is not connected to the power supply voltage in the write stage, the target bit line voltage on the target bit line can be changed while providing a voltage with a lower absolute amplitude and a shorter data rewriting time. That is, the strength of the driving capability of the voltage required to provide when rewriting data is reduced, and the necessary time of the write stage when rewriting data is also reduced, thereby reducing the possibility of data rewriting failure in the memory during the write stage and improving the write success rate of the memory.

[0041] In one embodiment, the sensitive voltage control module 12 is configured to float the first line and the second line respectively in a writing phase after the sensing phase, so as to stop receiving the corresponding supply voltage.

[0042] For example, Figure 2 As shown, during the write phase, by disconnecting the line between the first line PCS and the corresponding strong power supply providing high voltage, and by disconnecting the line between the second line NCS and the corresponding strong power supply providing low voltage, the line connected to the corresponding power supply voltage is physically disconnected, thereby increasing the data rewriting rate during the write phase and improving the write success rate of the memory.

[0043] In one embodiment, see Figure 5 , Figure 5 This is a structural diagram of an embodiment of the sensitive voltage control module of the present application. Figure 5 As shown, the sensitive voltage control module 12 includes a first switch unit 121 and a second switch unit 122 .

[0044] The first terminal of the first switch unit 121 is used to receive a first power supply voltage, the second terminal of the first switch unit 121 is connected to the first line, and the control terminal of the first switch unit 121 is used to receive a first control signal.

[0045] The first end of the second switch unit 122 is used to receive a second power supply voltage, the second end of the second switch unit 122 is connected to the second line, and the control end of the second switch unit 122 is used to receive a second control signal.

[0046] The first control signal and the second control signal are used to turn on the corresponding switch unit in the sensing phase and to turn off the corresponding switch unit in the writing phase.

[0047] For example, Figure 5 As shown, PCSOCT is the first control signal, NCSOCT is the second control signal, Vref is the reference voltage, the first supply voltage is twice the reference voltage Vref, and the second supply voltage is the ground voltage GND. The first control signal PCSOCT can be used to control the first switch unit 121 to stop connecting the first supply voltage to the first line PCS during the write phase, and the second control signal NCSOCT can also be used to control the second switch unit 122 to stop connecting the second supply voltage to the second line NCS during the write phase.

[0048] See also Figure 6 , Figure 6 This is a waveform diagram of the sensitive amplifier circuit of the present application, such as Figure 6 As shown, when the column selection signal YST is at a high level, a corresponding signal can be input to the target bit line BL through the target input / output line LIO to rewrite the data. At the same time, the first switch unit 121 can be turned off by the first control signal PCSOCT to stop connecting the first power supply voltage to the first line PCS, and the second switch unit 122 can be turned off by the second control signal NCSOCT to stop connecting the second power supply voltage to the second line NCS, so that the target bit line voltage on the target bit line BL can be changed quickly, thereby improving the data rewriting rate and thereby improving the write success rate of the memory.

[0049] Based on the above manner, by setting the switch unit, stable control of whether the first circuit and the second circuit are connected to the corresponding power supply voltage can be achieved, thereby improving the reliability of the sensitive amplifier circuit.

[0050] In addition, the above voltage setting is only an example, and the first supply voltage may also be any voltage that is twice or more than twice the reference voltage Vref, and / or the second supply voltage may be the ground voltage.

[0051] Alternatively, as Figure 5As shown, the sensitive voltage control module 12 further includes a third switch unit 123 .

[0052] A first end of the third switch unit 123 is connected to the first circuit, a second end of the third switch unit 123 is connected to the second circuit, and a control end of the third switch unit 123 is used to receive a third control signal.

[0053] The third control signal is used to turn off the corresponding switch unit in the sensing phase and turn on the corresponding switch unit in the writing phase.

[0054] Exemplarily, EQT is the third control signal.

[0055] During at least part of the write phase, the first line PCS and the second line NCS can be turned on by the third control signal EQT so that the voltages on the first line PCS and the second line NCS tend to be the same, thereby further improving the rate of subsequent data rewriting and further improving the write success rate of the memory.

[0056] Furthermore, the conduction time duration of the third switch unit 123 in the writing phase is less than or equal to the total time duration of the writing phase.

[0057] For example, based on the above approach, the possibility of a decrease in the data rewriting rate due to a long conduction period of the first line PCS and the second line NCS can be reduced, thereby improving the reliability of the sensitive amplifier circuit.

[0058] Furthermore, if Figure 5 As shown, the third switch unit 123 includes a first sub-switch 1231 and a second sub-switch 1232 .

[0059] A first end of the first sub-switch 1231 is connected to the first line.

[0060] The second end of the first sub-switch 1231 is connected to the first end of the second sub-switch 1232, and the second end of the second sub-switch 1232 is connected to the second line. The control end of the first sub-switch 1231 and the control end of the second sub-switch 1232 are used to receive a third control signal, and the third control signal is used to disconnect the corresponding sub-switch in the sensing phase and turn on the corresponding sub-switch in the writing phase.

[0061] Exemplarily, based on the above method, when at least one of the first sub-switch 1231 and the second sub-switch 1232 can still operate normally, at least the first line PCS and the second line NCS can be restored to the disconnected state. The failure of the third switch unit 123 to be turned on does not affect the normal operation of the memory. However, if the third switch unit 123 cannot be disconnected, the memory may not operate normally. Therefore, the possibility of the memory not being able to operate due to a failure of the third switch unit 123 can be reduced, thereby improving the reliability of the memory.

[0062] In one embodiment, the sensitive amplifier circuit may further include the column selection module described in the previous embodiment, wherein the first end of the column selection module is connected to the target bit line, and the second end of the column selection module is connected to the target input / output line. The column selection module is configured to be turned on during the write phase to perform a write operation on the storage cell 20 corresponding to the target bit line through the target input / output line.

[0063] In one embodiment, the sensitive amplifier circuit may further include the initialization module described in the above embodiment, the initialization module is respectively connected to the target bit line, the complementary bit line and the reference voltage line, the reference voltage line is used to provide a reference voltage, and the initialization module is used to turn on the target bit line, the complementary bit line and the reference voltage line during the pre-charging stage to pull the voltages on the target bit line and the complementary bit line to the reference voltage.

[0064] This application also provides a memory, see Figure 7 , Figure 7 Schematic diagram of the structure of an embodiment of the memory of the present application. Figure 7 As shown, the memory 30 includes a sensitive amplifier circuit 10. The sensitive amplifier circuit 10 may be any of the sensitive amplifier circuits described in the foregoing embodiments, which will not be described in detail here.

[0065] Exemplarily, the memory 30 may further include a storage unit 20. The storage unit 20 may be any of the storage units described in the foregoing embodiments, which will not be described in detail here.

[0066] Different from the prior art, in the technical solution of the present application, a sensitive amplifier circuit is applied to a memory, and the sensitive amplifier circuit includes: a sensitive amplifier module, which is respectively connected to a target bit line and a complementary bit line and has a first circuit and a second circuit; in a pre-charging phase, the voltages on the target bit line and the complementary bit line are both pulled to a reference voltage; in an activation phase, the target bit line transfers the stored charge stored in the corresponding selected memory cell; in a sensing phase, the sensitive amplifier module is used to respectively access the corresponding power supply voltage through the first circuit and the second circuit, and perform sensitive amplification processing on the target bit line voltage on the target bit line that has transferred the stored charge; a sensitive voltage control module, which is respectively connected to the first circuit and the second circuit, and is used to stop respectively accessing the corresponding power supply voltage through the first circuit and the second circuit in a write phase after the sensing phase. Based on the above method, after the sensing stage in which the target bit line voltage on the target bit line is sensitively amplified based on the power supply voltage, that is, in the write stage, the power supply voltage is stopped from being connected through the first line and the second line. At this time, if data needs to be rewritten for the storage unit corresponding to the target bit clue in the write stage, since the target bit line is no longer connected to the power supply voltage, the target bit line voltage on the target bit line can be changed while providing a voltage with a lower absolute amplitude and a shorter data rewriting time. That is, the strength of the driving capability of the voltage required to provide when rewriting the data is reduced, and the necessary time of the write stage when rewriting the data is also reduced, thereby reducing the possibility of data rewriting failure in the memory during the write stage and improving the write success rate of the memory.

[0067] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0068] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0069] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0070] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (which can be a personal computer, server, network device, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic devices), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and a portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0071] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A sensitive amplifier circuit, characterized in that: Applied to a memory, the sensitive amplifier circuit comprises: a sensitive amplifier module, connected to a target bit line and a complementary bit line, respectively, and having a first circuit and a second circuit; Wherein, in the pre-charging stage, the voltages on the target bit line and the complementary bit line are both pulled to a reference voltage; In the activation phase, the target bit line transfers the stored charge stored in the corresponding selected memory cell; In the sensing phase, the sensitive amplification module is used to connect corresponding power supply voltages through the first line and the second line respectively, and perform sensitive amplification processing on the target bit line voltage on the target bit line to which the stored charge has been transferred; a sensitive voltage control module, connected to the first line and the second line respectively, and configured to, in a writing phase following the sensing phase, stop accessing corresponding power supply voltages through the first line and the second line respectively; The sensitive voltage control module includes: a third switch unit, a first end of the third switch unit is connected to the first line, a second end of the third switch unit is connected to the second line, and a control end of the third switch unit is used to receive a third control signal; The third control signal is used to turn off the corresponding switch unit in the sensing phase and turn on the corresponding switch unit in the writing phase.

2. The sensitive amplifier circuit according to claim 1, characterized in that: The sensitive voltage control module is configured to float the first line and the second line respectively in a writing phase after the sensing phase, so as to stop accessing the corresponding power supply voltage.

3. The sensitive amplifier circuit according to claim 1 or 2, characterized in that: The sensitive voltage control module further includes: a first switch unit, wherein a first end of the first switch unit is used to receive a first power supply voltage, a second end of the first switch unit is connected to the first line, and a control end of the first switch unit is used to receive a first control signal; Wherein, the first supply voltage is greater than the reference voltage; a second switch unit, wherein a first end of the second switch unit is used to receive a second supply voltage, a second end of the second switch unit is connected to the second line, and a control end of the second switch unit is used to receive a second control signal; Wherein, the second supply voltage is lower than the reference voltage; The first control signal and the second control signal are used to turn on the corresponding switch unit in the sensing phase and to turn off the corresponding switch unit in the writing phase.

4. The sensitive amplifier circuit according to claim 1, wherein: The conduction time length of the third switch unit in the writing phase is less than or equal to the total time length of the writing phase.

5. The sensitive amplifier circuit according to claim 1, characterized in that: The third switch unit includes: a first sub-switch, wherein a first end of the first sub-switch is connected to the first line; The second sub-switch, the second end of the first sub-switch is connected to the first end of the second sub-switch, the second end of the second sub-switch is connected to the second line, the control end of the first sub-switch and the control end of the second sub-switch are used to receive the third control signal, and the third control signal is used to disconnect the corresponding sub-switch in the sensing phase and turn on the corresponding sub-switch in the writing phase.

6. The sensitive amplifier circuit according to claim 3, characterized in that: The first supply voltage is twice or more than twice the reference voltage, and / or the second supply voltage is a ground voltage.

7. The sensitive amplifier circuit according to claim 1 or 2, characterized in that: The sensitive amplifier circuit also includes: a column enable module, a first end of the column enable module is connected to the target bit line, and a second end of the column enable module is connected to the target input / output line. The column enable module is configured to be turned on during the write phase to perform a write operation on the storage cell corresponding to the target bit line through the target input / output line.

8. The sensitive amplifier circuit according to claim 1 or 2, characterized in that: The sensitive amplifier circuit also includes: an initialization module, which is respectively connected to the target bit line, the complementary bit line and the reference voltage line, the reference voltage line is used to provide the reference voltage, and the initialization module is used to turn on the target bit line, the complementary bit line and the reference voltage line during the pre-charging stage to pull the voltages on the target bit line and the complementary bit line to the reference voltage.

9. A memory, characterized in that: The sensitive amplifier circuit comprises the sensitive amplifier circuit according to any one of claims 1 to 8.

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