Flash memory testing method
By writing "0" and writing "1" operations on the memory cell array combined with erasing and reading operations, the memory cells in the entire column where the abnormal floating gate is located are filtered out, which solves the memory cell leakage problem caused by process environment defects and improves the reliability of flash memory.
Patent Information
- Application Number
- CN202510397046.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2025-07-18
AI Technical Summary
In the prior art, the memory cell leakage problem caused by abnormal floating gate morphology caused by process environment defects leads to the failure of the entire column of memory cells during the use of end users. It is difficult for the prior art to effectively screen out defective memory cells in the yield testing stage.
By writing "0" to the memory cell array, and then writing "1" operations several times under the background of all memory bits being "0", combined with erasing and reading operations, the memory cells in the entire column where the abnormal floating gate is located are filtered to ensure that defective chips are eliminated during the yield test phase.
Improve the reliability of flash memory, avoid failure caused by defective storage units during end users, and ensure that storage units are timely screened before leaving the factory.
Smart Images
Figure CN120340577A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a method for testing a flash memory. Background Art
[0002] As an integrated circuit storage device, a flash memory is widely used in electronic products such as portable computers, mobile phones, digital music players, etc. because it has the function of electrically erasable and writable storage of information and the stored information will not be lost after power-off.
[0003] As Figure 1 shown, in the process of a split-gate flash memory, due to process environment defects, some memory cells will have abnormal morphologies. The memory structure on the left side of the trench 030 includes a first floating gate 011 and a first word line 012, and the memory structure on the right side of the trench 030 includes a second floating gate 021 and a second word line 022. The first floating gate 011 has a normal morphology, with a sharp corner at the position facing the first word line 012, and there is a gap between the first floating gate 011 and the first word line 012. A bit line is formed in the trench 030. The second floating gate 021 (inside the yellow ellipse) has an abnormal morphology. The position of the second floating gate 021 facing the second word line 022 does not form the sharp corner shape that should be there, Figure 1 and an extra part also grows at the left position of the second floating gate 021 inside the yellow ellipse in
[0004] Normally, such defective memory cells will be screened out by the punch-through crosstalk test item during the yield test and repaired, and can be shipped and used normally. Although the defective memory cells are repaired during the yield test, other rows in the memory array still share the bit line with the defective memory cells and are not completely separated. Although shipped as normal samples to the terminal market, due to the different sizes and shapes of the defects, during the continuous use of the end users, the bit line of the defective memory cell leaks electricity due to this defect, resulting in the failure of the entire column of memory cells during the write "1" operation, and then becoming a terminal failure event. Summary of the Invention
[0005] The purpose of the present invention is to provide a method for testing a flash memory, by first writing "0", and then performing several write "1" operations in the background that all storage bits of the memory cell are "0", so as to obtain a voltage difference between the bit line and the floating gate that is much larger than that in the write "1" operation mode of the end user; making defective memory cells be exposed and eliminated as early as possible. Screening out defective chips at the yield test stage, not flowing to end users, improving the reliability of the flash memory, and avoiding the failure of the flash memory during the use of end users.
[0006] The present invention provides a method for testing a flash memory, including:
[0007] Step S1: Provide a flash memory, the flash memory includes a memory cell array, the memory cell array includes a plurality of memory cells arranged in a matrix, and the memory cells are split-gate flash memory cells; each of the memory cells includes a floating gate and a bit line; the memory cells in each column share the bit line;
[0008] Step S2: Perform a write "0" operation on the memory cells of the memory cell array;
[0009] Step S3: Perform a plurality of write "1" operations under the background that the storage bits of the memory cells of the memory cell array are all "0";
[0010] Step S4: Erase the memory cells of the memory cell array, and perform a read operation on the erased memory cells;
[0011] Step S5: Perform a write "1" operation under the background that the storage bits of the memory cells of the memory cell array are all "1" to screen for floating gate defects of the erased memory cells. The write "1" operation of the memory cells in the entire column where the abnormal floating gate is located fails, so as to screen out the memory cells in the entire column where the abnormal floating gate is located.
[0012] Further, in step S2, the voltage application conditions for the write "0" operation include: the source region voltage V S is 8.2V, the bit line voltage V B is 0.7V, and the word line voltage V W is 1.6V.
[0013] Further, in step S3, the voltage application conditions for the write "1" operation include: the source region voltage V S is 8.2V, the bit line voltage V B is 2.5V, and the word line voltage V W is 1.6V.
[0014] Further, in step S4, the read operation on the erased memory cells specifically includes: judging whether the erased state reaches the state where the storage bit is "1" according to the read current; if the state where the storage bit is "1" is reached, the erasure is successful and step S5 is performed; if the state where the storage bit is "1" is not reached, the erasure fails and is excluded.
[0015] Further, after step S5 performs a write "1" operation on the flash memory, it further includes: performing a read operation on the memory cells after the write "1" operation, and judging whether the storage bit maintains the "1" state according to the read current; if the storage bit maintains the "1" state, the write "1" operation is successful; if the storage bit is in the "0" state, the write "1" operation fails and is excluded.
[0016] Further, in step S5, the voltage conditions for writing "1" in the context where all storage bits are "1" include: the source region voltage V S ranging from 8.0 V to 8.4 V; the bit line voltage V B ranging from 2.3 V to 2.7 V; the word line voltage V W ranging from 1.4 V to 1.8 V.
[0017] Further, after step S1 and before step S2, it further includes:
[0018] First test: perform short - circuit, open - circuit, and leakage tests; if the first test is qualified, it proceeds to the second test; if the first test is unqualified, it is rejected.
[0019] Further, the second test includes: perform static power consumption and dynamic power consumption tests; if the second test is qualified, it proceeds to step S2; if the second test is unqualified, it is rejected.
[0020] Further, the end - user performs a write "1" operation based on the erased state of the storage unit in the flash memory, with the bit line voltage being 2.5 V and the floating gate voltage ranging from 2.5 V to 3.2 V;
[0021] In step S2, a write "0" operation is performed on the storage cell array, and electrons of the corresponding storage cell enter the floating gate from the substrate channel, obtaining a floating gate voltage range of - 0.7 V to - 0.5 V, and the bit line voltage is 2.5 V.
[0022] Further, one split - gate flash memory cell includes two storage structures that share a common source region and are symmetrically distributed; the storage structure includes a drain region and the source region located in the substrate, the drain region is connected to the bit line, a floating gate and a word line are formed on the substrate between the source region and the drain region, a floating gate tip is formed on one side of the floating gate close to the word line, and a tunneling oxide layer is formed between the floating gate and the word line.
[0023] Compared with the prior art, the present invention has the following beneficial effects:
[0024] The present invention provides a method for testing a flash memory. In step S2, a write "0" operation is performed on the memory cell array, and electrons of the corresponding memory cells enter the floating gate from the substrate channel, and the floating gate obtains the lowest floating gate voltage. In step S3, a write "1" operation is performed under the background that all the stored bits of the memory cells in the memory cell array are "0". By first writing "0" and then performing a number of write "1" operations under the background that all the stored bits of the memory cells are "0", the voltage difference between the bit line and the floating gate in the write "1" operation mode of the end user can be obtained far greater; so that defective memory cells can be exposed and eliminated as early as possible. Erase and read operations are performed on the memory cells of the memory cell array; a write "1" operation is performed under the background that all the stored bits of the memory cells in the memory cell array are "1" to screen for floating gate defects of the erased memory cells. The write "1" operation fails for the memory cells in the entire column where the abnormal floating gate is located, so as to screen out the memory cells in the entire column where the abnormal floating gate is located. Defective chips are screened out in the yield test stage and do not flow to end users, improving the reliability of the flash memory and avoiding the failure of the flash memory during end user use. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 FIG. is a schematic diagram of a split-gate flash memory.
[0026] Figure 2 FIG. is a schematic flow chart of a method for testing a flash memory according to an embodiment of the present invention.
[0027] Figure 3 FIG. is a schematic diagram of a flash memory according to an embodiment of the present invention.
[0028] Figure 4 FIG. is a schematic diagram of the principle of a flash memory according to an embodiment of the present invention.
[0029] Among them, the reference numerals are as follows:
[0030] 011 - First floating gate; 012 - First word line; 030 - Trench; 021 - Second floating gate; 022 - Second word line;
[0031] 11 - Floating gate; 12 - Word line; 13 - Bit line; 14 - Source region; 15 - Drain region; A - Memory cell; B - Memory cell with abnormal floating gate. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0032] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.
[0033] For ease of description, some embodiments of the present application may use spatial relative terms such as "above", "below", "top", "bottom", etc. to describe the relationship between one element or component and another (or other) element or component as shown in the respective drawings of the embodiments. It should be understood that, in addition to the orientations described in the drawings, spatial relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawing is flipped, an element or component described as "below" or "beneath" other elements or components will subsequently be positioned "above" or "over" the other elements or components. The terms "first", "second", etc. in the following text are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms may be replaced where appropriate.
[0034] Embodiments of the present invention provide a method for testing a flash memory, as Figure 2 shown, including:
[0035] Step S1: Provide a flash memory. The flash memory includes a memory cell array. The memory cell array includes a plurality of memory cells arranged in a matrix. The memory cells are split-gate flash memory cells; each memory cell includes a floating gate and a bit line; the memory cells in each column share the bit line;
[0036] Step S2: Perform a write "0" operation on the memory cells of the memory cell array;
[0037] Step S3: Perform a plurality of write "1" operations in the background where all the stored bits of the memory cells of the memory cell array are "0";
[0038] Step S4: Erase the memory cells of the memory cell array and perform a read operation on the erased memory cells;
[0039] Step S5: Perform a write "1" operation in the background where all the stored bits of the memory cells of the memory cell array are "1" to screen for floating gate defects in the erased memory cells. The write "1" operation fails for the memory cells in the entire column where the abnormal floating gate is located, thereby screening out the memory cells in the entire column where the abnormal floating gate is located.
[0040] The following will Figure 3 and Figure 4 detail each step of the method for testing the flash memory according to the embodiments of the present invention.
[0041] Step S1: As Figure 3 and Figure 4As shown, a flash memory is provided. The flash memory includes a memory cell array, and the memory cell array includes a plurality of memory cells A arranged in a matrix. The memory cells are split-gate flash memory cells; each memory cell includes a floating gate 11 and a bit line 13; the memory cells in each column share the bit line 13. A plurality of split-gate flash memory cells are formed side by side on a semiconductor substrate. The material of the semiconductor substrate can be silicon, germanium, silicon germanium, silicon carbide, etc., or can also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or can also be other materials, such as group III-V compounds such as gallium arsenide.
[0042] In this embodiment, a split-gate flash memory cell includes two memory structures that share a source region 14 and are symmetrically distributed. Each split-gate flash memory cell includes a drain region 15 (connected to the bit line 13), a source region 14 formed in the semiconductor substrate, and a source line (not shown) formed on the semiconductor substrate and connected to the source region 14. The source line is located above the source region 14. A word line 12 is formed between the source region 14 and the drain region 15. Two word lines 12 of the same split-gate flash memory cell are formed on both sides of the corresponding source line. A floating gate oxide layer, a floating gate 11, and sidewalls are formed on the semiconductor substrate between the source line and the word line 12. A tunneling oxide layer is formed between the floating gate 11 and the word line 12. The materials of the floating gate 11, the word line 12, and the source line can all be polysilicon. A floating gate tip is formed on one side of the floating gate 11 close to the word line 12. The left memory structure and the right memory structure are symmetrically distributed and share the source line. In this embodiment, the source region 14 and the drain region 15 are both N-type doped, for example.
[0043] Next, a first test is performed: short circuit, open circuit, and leakage test; if the first test is qualified, it proceeds to the second test; if the first test is unqualified, it is rejected.
[0044] Next, a second test is performed: static power consumption and dynamic power consumption test; if the second test is qualified, it proceeds to the erasing step; if the second test is unqualified, it is rejected.
[0045] Step S2: Perform a write "0" operation on the memory cell array. The memory cell array includes a plurality of memory cells A arranged in a matrix. By applying a programming voltage to the memory cells, electrons of the corresponding memory cells enter the floating gate 11 from the substrate channel to complete programming. After programming, the stored bit of the memory cell is in the "0" state. Programming is also called the write "0" operation. The write "0" operation changes the stored bit from the "1" state to the "0" state. After this step, all the memory cells A in the memory cell array of the flash memory are set to "0".
[0046] When programming the split-gate flash memory cell, the word line 12 serves as the control gate, a high voltage is applied to the source region 14, a voltage that can turn on the channel is applied to the word line 12, and a constant current is injected through the drain region 15. Also, the source region 14 is at a high potential. Under the action of the high potential, on the one hand, hot electrons are generated in the channel, and on the other hand, the high potential is coupled to the floating gate 11, and the floating gate 11 generates a coupling voltage. Under the action of the coupling voltage, electrons are injected from the channel into the floating gate 11, thereby realizing programming, and programming is also called the write "0" operation. Exemplarily, the voltage application conditions for the write "0" operation include: the source region voltage V S is 8.2V, the bit line voltage V B is 0.7V, and the word line voltage V W is 1.6V.
[0047] Step S3: Perform a number of write "1" operations against the background that all the storage bits of the storage cells in the storage cell array are "0"; perform a number of write "1" operations on the flash memory. The write "1" operation is to apply a voltage to the storage cell to inhibit the operation of the storage cell, so that the storage cell does not meet the programming conditions and also does not meet the erasure conditions. The storage cell is neither programmed nor erased, and maintains its original storage state, keeping the electrons in the floating gate 11 stationary, that is, maintaining the storage bits of the storage cells in the storage cell array of the flash memory to be always in the "0" state. In this step, perform a number of write "1" operations to simulate multiple write "1" operations. By first writing "0" and then performing the write "1" operation against the background that all the storage bits of the storage cell are "0", the voltage difference between the bit line and the floating gate in the write "1" operation mode of the end user can be obtained far greater, so that the storage cells with leakage defects can be exposed and eliminated as early as possible. Exemplarily, the voltage application conditions for the write "1" operation include: the source region voltage V S is 8.2V, the bit line voltage V B is 2.5V, and the word line voltage V W is 1.6V.
[0048] Step S4: Erase the storage cells of the storage cell array; when erasing the split-gate flash memory cell, a high voltage is applied to the word line 12. The tip of the floating gate reduces the channel voltage of the tunneling effect through the principle of tip discharge, enabling electrons to pass through the tunneling oxide layer from the tip of the floating gate 11 into the word line 12. After the storage cell is erased, the storage bit of the storage cell is in the "1" state; that is, all the storage cells of the flash memory are erased and set to "1".
[0049] Perform a read operation on the erased storage cell; during the read operation, a voltage is applied to the bit line 13, the source region voltage V S is 0V, and an opening voltage is applied to the word line 12. Determine whether the storage bit reaches the "1" state after erasure according to the read current; if the storage bit reaches the "1" state, the erasure is successful and the floating gate defect screening is performed; if the storage bit does not reach the "1" state, the erasure fails and the cell is excluded.
[0050] Step S5: A write "1" operation is performed under the background that all the storage bits of the storage cells in the storage cell array are "1" to screen for floating gate defects in the erased storage cells. The write "1" operation fails for the storage cells in the entire column where the abnormal floating gate is located, thereby screening out the storage cells in the entire column where the abnormal floating gate is located. This step simulates the write "1" operation of the end user and performs a write "1" operation check. The voltage conditions for the write "1" operation under the background that all the storage bits are "1" include: the source region voltage V S in the range of: 8.0V to 8.4V; the bit line voltage V B in the range of: 2.3V to 2.7V; the word line voltage V W in the range of: 1.4V to 1.8V.
[0051] The write "1" operation fails for the storage cells in the entire column where the abnormal floating gate is located, thereby screening out the storage cells in the entire column where the abnormal floating gate is located. Figure 4 Shows the storage cell B with a floating gate abnormality. For the storage cell B with a floating gate abnormality, for example, the position of the floating gate facing the word line does not form the sharp corner shape that should be there, and there is an extra part growing on the side of the floating gate close to the word line. When the storage cell with a floating gate defect (abnormality) is first used, the voltage difference between the source region voltage V S and the bit line voltage V B is less than the channel opening voltage, and the electrons of the corresponding storage cell will not enter the floating gate 11 from the substrate, and the storage bit of the storage cell has always been in the "1" state. During continuous use, this defect causes the bit line 13 where the storage cell is located to leak electricity, resulting in the suppression voltage, that is, the bit line voltage V B being pulled down. Correspondingly, electrons will enter their respective floating gates 11 from the substrate for all the storage cells in the entire column on this bit line, and then all the storage cells in the entire column are programmed to be written as "0", that is, the storage bits of all the storage cells in the entire column change from the "1" state to the "0" state. Therefore, for a storage cell with a floating gate defect, there is a leakage between the bit line 13 and the floating gate during use, resulting in the failure of the write "1" operation during subsequent use and inability to be used normally.
[0052] The end user performs a write "1" operation based on the erased state of the storage cells in the flash memory. The bit line voltage V B is usually 2.5V. Before improvement, the floating gate voltage V F1 is 2.5V to 3.2V; the bit line voltage V B and the floating gate voltage V F1 have a small voltage difference, and the difference between V B and V F1 is in the range of 0V to -0.7V.
[0053] The present invention provides a method for testing a flash memory. After the improvement of the present invention, in step S2, a write "0" operation is performed on the memory cell array, and electrons of the corresponding memory cells enter the floating gate 11 from the substrate channel, and the floating gate 11 obtains the lowest floating gate voltage V F2 , V F2 is about -0.7V. In step S3, a write "1" operation is performed under the background that all the stored bits of the memory cells in the memory cell array are "0". The bit line voltage V B is still 2.5V. The floating gate voltage V F2 of the improved present invention is about -0.7V; the bit line voltage V B and the floating gate voltage V F2 have a significantly increased voltage difference, about 3.2V. By first writing "0" and then performing several write "1" operations under the background that all the stored bits of the memory cells are "0", the present invention obtains a voltage difference between the bit line and the floating gate that is much larger than that in the write "1" operation mode of the end user, so that defective memory cells can be exposed and removed as early as possible. Erase and read operations are performed on the memory cells of the memory cell array; a write "1" operation is performed under the background that all the stored bits of the memory cells in the memory cell array are "1" to screen for floating gate defects of the erased memory cells. The write "1" operation of the memory cells in the entire column where the abnormal floating gate is located fails, so as to screen out the memory cells in the entire column where the abnormal floating gate is located. Defective chips are screened out in the yield test stage and do not flow to end users, improving the reliability of the flash memory and avoiding the failure of the flash memory during end user use.
[0054] In the present specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the description in the method part.
[0055] The above description is only a description of the preferred embodiments of the present invention, and does not limit any scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and decorations made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention all belong to the protection scope of the technical solution of the present invention.
Claims
1. A test method for a flash memory, characterized in that, Including: Step S1: Provide a flash memory, the flash memory includes a memory cell array, the memory cell array includes a plurality of memory cells arranged in a matrix, and the memory cells are split-gate flash memory cells; each of the memory cells includes a floating gate and a bit line; the memory cells in each column share the bit line; Step S2: Perform a write "0" operation on the memory cells of the memory cell array; Step S3: Perform a plurality of write "1" operations in the background where the stored bits of the memory cells of the memory cell array are all "0"; Step S4: Erase the memory cells of the memory cell array, and perform a read operation on the erased memory cells; Step S5: Perform a write "1" operation in the background where the stored bits of the memory cells of the memory cell array are all "1" to screen for floating gate defects of the erased memory cells. The write "1" operation of the memory cells in the entire column where the abnormal floating gate is located fails, thereby screening out the memory cells in the entire column where the abnormal floating gate is located.
2. The test method for a flash memory according to claim 1, wherein In step S2, the voltage conditions for the "write 0" operation include: the source region voltage V S is 8.2V, the bit line voltage V B is 0.7V, and the word line voltage V W is 1.6V.
3. The test method for a flash memory according to claim 1, wherein In step S3, the voltage conditions for writing the "1" operation include: the source region voltage V S is 8.2V, the bit line voltage V B is 2.5V, and the word line voltage V W is 1.6V.
4. The test method for a flash memory according to claim 1, wherein In step S4, the read operation on the erased memory cells specifically includes: judging whether the erased state reaches the state where the stored bit is "1" according to the read current; if the state where the stored bit is "1" is reached, the erasure is successful and proceed to step S5; if the state where the stored bit is "1" is not reached, the erasure fails and is rejected.
5. The test method for a flash memory according to claim 1, wherein After step S5 performs a write "1" operation on the flash memory, it further includes: performing a read operation on the memory cells after the write "1" operation, and judging whether the stored bit maintains the "1" state according to the read current; if the stored bit maintains the "1" state, the write "1" operation is successful; if the stored bit is in the "0" state, the write "1" operation fails and is rejected.
6. The test method for a flash memory according to claim 1, wherein In step S5, the voltage conditions for writing "1" under the background that all storage bits are "1" include: the source region voltage V S ranges from 8.0 V to 8.4 V; the bit line voltage V B ranges from 2.3 V to 2.7 V; the word line voltage V W ranges from 1.4 V to 1.8 V.
7. The test method for a flash memory according to claim 1, wherein After step S1 and before step S2, it further includes: The first test: Perform short-circuit, open-circuit, and leakage tests; if the first test is qualified, proceed to the second test; if the first test is unqualified, reject it.
8. The test method for a flash memory according to claim 7, wherein The second test includes: performing static power consumption and dynamic power consumption tests; if the second test is qualified, proceed to step S2; if the second test is unqualified, reject it.
9. The test method for a flash memory according to claim 1, wherein The end user performs a write "1" operation based on the state of the memory cells of the flash memory after erasure, the bit line voltage is 2.5V, and the floating gate voltage is 2.5V to 3.2V; In step S2, a write "0" operation is performed on the memory cell array. Correspondingly, electrons of the memory cell enter the floating gate from the substrate channel, and the obtained floating gate voltage range is: -0.7V to -0.5V, and the bit line voltage is 2.5V.
10. The test method for a flash memory according to claim 1, wherein One of the split-gate flash memory cells includes two memory structures that share a common source region and are symmetrically distributed; the memory structure includes a drain region and the source region located in the substrate, the drain region is connected to the bit line, a floating gate and a word line are formed on the substrate between the source region and the drain region, a floating gate tip is formed on one side of the floating gate close to the word line, and a tunneling oxide layer is formed between the floating gate and the word line.