Method and device for obtaining and displaying invalid address information

Abstract

The invention discloses a failure address information obtaining and displaying method and device, address test information of a tested object is obtained, the address test information is obtained by performing a failure address test on the tested object, and address information included in the address test information is three-dimensional address information; based on an information dimension used for indicating a memory block to which the address belongs in the three-dimensional address information, performing two-dimensional quantization processing on the address test information to obtain a two-dimensional unit view corresponding to at least one memory block included in the tested object, the two-dimensional unit view being used for indicating a failure address test result of the memory block; and displaying the two-dimensional unit view corresponding to each memory block, thereby improving the acquisition and display efficiency of the failure address information.

Description

Technical Field

[0001] The present disclosure relates to chip testing technology, and in particular to a method and apparatus for obtaining and displaying failure address information. Background Art

[0002] Chip testing is used to verify whether a chip can correctly implement the designed logical functions. Chip testing includes testing the storage addresses in the internal space of the chip to detect whether there are failure address bits in the storage space.

[0003] In the related art, after obtaining the failure address test information of the chip, the failure address test information is compressed and displayed on a single graph. This method requires data compression, and the efficiency of obtaining and displaying the failure address information is relatively low. Summary of the Invention

[0004] Embodiments of the present disclosure provide a method and apparatus for obtaining and displaying failure address information to solve the above technical problems to a certain extent.

[0005] In one aspect of the embodiments of the present disclosure, a method for obtaining and displaying failure address information is provided, including:

[0006] Obtaining address test information of a test object, where the address test information is obtained by performing a failure address test on the test object, and the address information included in the address test information is three-dimensional address information;

[0007] Based on the information dimension for indicating the memory block to which the address belongs in the three-dimensional address information, performing two-dimensional quantization processing on the address test information to obtain at least one two-dimensional unit view corresponding to the memory block included in the test object, where the two-dimensional unit view is used to indicate the failure address test result of the memory block;

[0008] Displaying the two-dimensional unit views corresponding to each of the memory blocks.

[0009] In another aspect of the embodiments of the present disclosure, an apparatus for obtaining and displaying failure address information is provided, including:

[0010] An information acquisition module, configured to obtain address test information of a test object, where the address test information is obtained by performing a failure address test on the test object, and the address information included in the address test information is three-dimensional address information;

[0011] A two-dimensional processing module, configured to perform two-dimensional quantization processing on the address test information based on the information dimension for indicating the memory block to which the address belongs in the three-dimensional address information, to obtain at least one two-dimensional unit view corresponding to the memory block included in the test object, where the two-dimensional unit view is used to indicate the failure address test result of the memory block;

[0012] A view display module, configured to display two-dimensional unit views corresponding to each of the memory blocks.

[0013] Another aspect of the embodiments of the present disclosure provides an electronic device, including:

[0014] A memory, configured to store a computer program;

[0015] A processor, configured to execute the computer program stored in the memory, and when the computer program is executed, implement the method for obtaining and displaying failure address information according to any one of the above embodiments of the present disclosure.

[0016] Another aspect of the embodiments of the present disclosure provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, implement the method for obtaining and displaying failure address information according to any one of the above embodiments of the present disclosure.

[0017] Another aspect of the embodiments of the present disclosure provides a computer program product, including a computer program, and when the computer program is executed by a processor, implement the method for obtaining and displaying failure address information according to any one of the above embodiments of the present disclosure.

[0018] In the embodiments of the present disclosure, for the address test information of the object under test, based on the information dimension for indicating the memory block to which the address belongs in the included three-dimensional address information, two-dimensional quantization processing is performed on the address test information to obtain and display at least one two-dimensional unit view corresponding to the memory blocks included in the object under test. The two-dimensional unit view can indicate the failure address test result of the memory block. According to the two-dimensional unit views of each memory block, the failure address information of the object under test can be obtained. By performing two-dimensional quantization processing on the address test information based on the information dimension for indicating the memory block to which the address belongs, the failure address information corresponding to the whole object under test can be displayed based on the failure address information corresponding to this information dimension, without compressing the data, which can improve the efficiency of obtaining and displaying failure address information.

[0019] Next, through the drawings and embodiments, the technical solutions of the present disclosure will be further described in detail. Description of the Drawings

[0020] The drawings forming a part of the specification depict the embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure.

[0021] Referring to the drawings, the present disclosure can be more clearly understood according to the following detailed description, where:

[0022] Figure 1 It is a flowchart of the method for obtaining and displaying failure address information provided for an exemplary embodiment of the present disclosure;

[0023] Figure 2Schematic diagram of tiled display of two-dimensional cell views corresponding to each memory block provided by an exemplary embodiment of the present disclosure;

[0024] Figure 3 Schematic diagram of an interface for displaying two-dimensional cell views corresponding to each memory block provided by an exemplary embodiment of the present disclosure;

[0025] Figure 4 Schematic diagram of an interface for displaying a target address information view provided by an exemplary embodiment of the present disclosure;

[0026] Figure 5 Flowchart of a method for obtaining and displaying failure address information provided by another exemplary embodiment of the present disclosure;

[0027] Figure 6 Schematic structural diagram of a device for obtaining and displaying failure address information provided by an exemplary embodiment of the present disclosure;

[0028] Figure 7 Schematic structural diagram of an electronic device provided by an exemplary embodiment of the present disclosure. Detailed implementation manners

[0029] Now, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that: Unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure.

[0030] Those skilled in the art can understand that terms such as "first", "second", etc. in the embodiments of the present disclosure are only used to distinguish different steps, devices, or modules, etc., and neither represent any specific technical meaning nor indicate an inevitable logical order between them.

[0031] It should also be understood that in the embodiments of the present disclosure, "a plurality" may refer to two or more, and "at least one" may refer to one, two, or more.

[0032] It should also be understood that for any component, data, or structure mentioned in the embodiments of the present disclosure, unless clearly defined or given a contrary indication in the context, it is generally understood to be one or more.

[0033] In addition, the term "and / or" in the present disclosure is merely a description of the association relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in the present disclosure generally represents an "or" relationship between the associated objects before and after.

[0034] It should also be understood that the descriptions of the various embodiments in the present disclosure emphasize the differences between the various embodiments, and their similarities or similarities can be referred to each other. For the sake of brevity, they will not be described one by one.

[0035] At the same time, it should be understood that, for the sake of convenience of description, the dimensions of the various parts shown in the drawings are not drawn in actual proportional relationship.

[0036] The following description of at least one exemplary embodiment is actually only illustrative and in no way limits the present disclosure, its application or use.

[0037] Techniques, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods, and devices should be regarded as part of the specification.

[0038] It should be noted that like reference numerals and letters indicate like items in the following figures, and thus, once an item is defined in one figure, it does not need to be further discussed in subsequent figures.

[0039] The embodiments of the present disclosure can be applied to electronic devices such as terminal devices, computer systems, servers, etc., which can operate together with many other general or special computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments, and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, servers, etc. include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, small computer systems, large computer systems, and distributed cloud computing technology environments including any of the above systems, and so on.

[0040] Terminal devices, computer systems, servers and other electronic devices can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Generally, program modules can include routines, programs, object programs, components, logics, data structures, etc., which perform specific tasks or implement specific abstract data types. The computer system / server can be implemented in a distributed cloud computing environment, where tasks are executed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can be located on local or remote computing system storage media including storage devices.

[0041] In the embodiments of the present disclosure, a method for obtaining and displaying failure address information is provided, which can perform two-dimensional quantization processing on the address test information of the object under test to obtain a two-dimensional unit view corresponding to the memory block included in the object under test, and the failure address information of the object under test can be previewed through the two-dimensional unit views of the respective memory blocks.

[0042] The method for obtaining and displaying failure address information provided by the embodiments of the present disclosure can be used in the host computer of a test device. Optionally, the host computer can be the above-mentioned electronic device. A device for obtaining and displaying failure address information is provided in the host computer. Optionally, the method provided in this embodiment can be specifically used for the device for obtaining and displaying failure address information in the host computer. The test device can be used to perform semiconductor tests on a device under test (DUT). Among them, the DUT can include wafers, chips, etc. In the present disclosure, the device under test is also referred to as the object under test. In a possible implementation manner, the test device can perform a failure address test on the object under test to obtain failure address information (Fail Bit Information, FBI), and the host computer can obtain and display it. In the embodiments of the present disclosure, the failure address information is also referred to as address test information.

[0043] Figure 1 The flowchart of the method for obtaining and displaying failure address information provided by an exemplary embodiment of the present disclosure is for the host computer as described above. As Figure 1 shown, the method of this embodiment includes steps 110-130:

[0044] Step 110, obtain the address test information of the object under test, and the address test information is obtained by performing a failure address test on the object under test.

[0045] The address information included in the address test information is three-dimensional address information.

[0046] The address test information is the information obtained by performing a failure address test on the object under test. Specifically, the address test information is the information obtained after testing the storage unit of the object under test based on a preset test vector (Pattern) for failure address testing, which includes the pass (Pass) and / or fail (Fail) information of the storage unit. Optionally, it can include the Pass and / or Fail information corresponding to each three-dimensional address included in the storage unit.

[0047] In a possible implementation manner, a selection item for selecting an object is provided in the user interaction interface. When a selection operation on the object under test is received, the address test information of the object under test can be obtained.

[0048] Optionally, the address test information can be stored in a preset memory space, such as the failure address storage space (FailMemory). Optionally, the address test information can be stored in a preset memory space of the lower computer of the test device. The lower computer of the test device is used to execute the test process of the failure address test, obtain the address test information, and store the address test information.

[0049] In a possible implementation, address test information of an object under test can be obtained from a lower computer.

[0050] Step 120: Based on the information dimension in the three-dimensional address information that indicates the memory block to which the address belongs, perform two-dimensional quantization processing on the address test information to obtain a two-dimensional unit view corresponding to at least one memory block included in the object under test.

[0051] The two-dimensional unit view is used to indicate the failure address test result of the memory block.

[0052] The three-dimensional address information includes information on three dimensions (x, y, z) where the address is located. Among them, the first dimension x is used to indicate the row information corresponding to the three-dimensional address (indicating the row where the address is located), the second dimension y is used to indicate the column information corresponding to the three-dimensional address (indicating the column where the address is located), and the third dimension z is used to indicate the memory block information corresponding to the three-dimensional address (indicating the memory block to which the address belongs). The memory block is obtained by dividing the storage units of the object under test. Optionally, an object under test includes multiple memory blocks.

[0053] In the embodiments of the present disclosure, based on the information dimension in the three-dimensional address information that indicates the memory block to which the address belongs, that is, the third dimension, perform two-dimensional quantization processing on the address test information. During the two-dimensional quantization processing, taking the memory block indicated by the third dimension as a whole, generate a two-dimensional unit view representing the overall test result of the memory block. That is, for a memory block, according to the overall test result corresponding to the memory block, generate a two-dimensional unit view corresponding to the overall memory block. This two-dimensional unit view can be used to indicate the failure address test result corresponding to the overall memory block. Optionally, the two-dimensional unit view of the memory block can be used to indicate whether the memory block contains a failure address bit (i.e., a three-dimensional address with a test result of Fail).

[0054] In a possible implementation, the overall test result of the memory block can be determined according to the test results of each three-dimensional address corresponding to the same memory block, and a two-dimensional unit view corresponding to the memory block can be generated according to the overall test result of the memory block, where the third dimension z information of each three-dimensional address corresponding to the same memory block is the same.

[0055] Step 130: Display the two-dimensional unit views corresponding to each memory block.

[0056] Through two-dimensional quantization processing, two-dimensional unit views corresponding to at least one memory block included in the object under test can be generated, and the generated two-dimensional unit views can be displayed on the user interaction interface. In a possible implementation, for a memory block, the memory block identifier corresponding to the memory block and the two-dimensional unit view are displayed in the user interaction interface, and the memory block identifier is used to uniquely indicate the memory block.

[0057] Optionally, the two-dimensional unit views corresponding to each memory block can be randomly arranged and displayed on the user interface, or they can also be arranged and displayed in sequence according to a preset rule on the user interface. Exemplarily, as Figure 2 shown, which shows a schematic diagram of the arranged display of two-dimensional unit views provided by an exemplary embodiment of the present disclosure. Among them, the two-dimensional unit views corresponding to memory blocks 0, 1, 2... are tiled and displayed in sequence.

[0058] The two-dimensional unit view of the memory block can be used to indicate the failure address test result of the entire memory block. By displaying the two-dimensional unit views corresponding to each memory block, the user can preview the overall failure address information of each memory block of the object under test through each two-dimensional unit view, so as to know the failure address information of the object under test. In this process, two-dimensional quantization processing can be directly performed according to the address test information obtained by the test, without data compression, which helps to improve the acquisition and display efficiency of the failure address information.

[0059] In the embodiments of the present disclosure, for the address test information of the object under test, two-dimensional quantization processing can be performed on the address test information based on the information dimension in the included three-dimensional address information that is used to indicate the memory block to which the address belongs, to obtain and display at least one two-dimensional unit view corresponding to the memory blocks included in the object under test. The two-dimensional unit view can indicate the failure address test result of the memory block. According to the two-dimensional unit views of each memory block, the failure address information of the object under test can be obtained. Performing two-dimensional quantization processing on the address test information based on the information dimension used to indicate the memory block to which the address belongs can display the failure address information corresponding to the entire object under test based on the failure address information corresponding to this information dimension, without data compression, which can improve the acquisition and display efficiency of the failure address information.

[0060] When obtaining the address test information of the object under test, the address test information of the object under test can be read from the lower computer of the test device. In a possible implementation manner, it can be obtained from the failure address storage space of the lower computer for storing the address test information. After the lower computer performs a failure address test on the object under test, the address test information is stored in the failure address storage space.

[0061] In another possible implementation manner, it can also be obtained from the test board of the lower computer in real time. During the test process of the object under test, the address test information of the already tested address is read from the test board, and the test board is used to perform a failure address test on the object under test. Optionally, the address test information obtained by real-time testing can be obtained from the storage space of the test board, and the two-dimensional unit views of each memory block are generated and displayed according to the real-time read address test information.

[0062] Optionally, a refresh control for refreshing the two-dimensional cell view is displayed in the user interaction interface. In response to an interaction operation on the refresh control, that is, in response to a view refresh operation, updated test information can be obtained from the test board. The updated test information includes address test information that has been tested and not read yet, that is, the updated test information includes the address test information newly tested by the test board after the most recent data reading. After reading the updated test information, the two-dimensional cell views of the displayed memory blocks can be updated according to the updated test information.

[0063] In the embodiments of the present disclosure, the address test information can be read online in real time. When an abnormality is found during the test, the user can view the failed address information in real time, which helps to quickly locate the abnormal problem in the debugging stage and improve the efficiency of discovering and solving abnormal problems.

[0064] In a possible implementation manner, the two-dimensional quantization processing process of step 120 further includes the following steps 1201-1202:

[0065] Step 1201: Based on the block address test information corresponding to each of at least one memory block, determine the test result of each memory block. The block address test information includes the address test information of the three-dimensional address belonging to the memory block.

[0066] In a possible implementation manner, taking the memory block dimension as a unit, the block address test information corresponding to each memory block can be obtained respectively. One block address test information includes the address test information corresponding to the three-dimensional addresses (i.e., the three-dimensional addresses included in the memory block) belonging to the memory block. In the lower computer, the block address test information corresponding to each memory block can be stored respectively taking the memory block dimension as a unit for the upper computer to read, which can improve the acquisition and display efficiency of the failed address information.

[0067] In another possible implementation manner, after obtaining the address test information of the object under test, according to the third dimension information corresponding to each three-dimensional address in the address test information, the block address test information corresponding to the different memory blocks included therein can be determined.

[0068] For a memory block, after obtaining the corresponding block address test information, the test result corresponding to the memory block can be determined according to the block address test information. The test result can be used to indicate whether the memory block as a whole passes the test. In a possible implementation manner, when the number of failed address bits included in the memory block is less than the preset number threshold, it is determined that the memory block as a whole passes the test, that is, the test result of the memory block is Pass. When the number of failed address bits included in the memory block is not less than the preset number threshold, it is determined that the memory block as a whole fails the test, and the test result of the memory block is Fail.

[0069] In another possible implementation, when there are invalid address bits in the three-dimensional addresses included in the memory block, it is determined that the memory block fails the test; when there are no invalid address bits in the three-dimensional addresses included in the memory block, it is determined that the memory block passes the test.

[0070] Step 1202: Generate a two-dimensional cell view of the memory block based on the test results of each memory block, where different test results correspond to different types of two-dimensional views.

[0071] According to the test results of each memory block, corresponding two-dimensional cell views can be generated. Optionally, the test results include passing the test and failing the test, and passing the test and failing the test respectively correspond to different types of two-dimensional views.

[0072] That is, the test results corresponding to each memory block are displayed through different types of two-dimensional views, and the test result of a memory block can be determined through the two-dimensional cell view of the memory block. Optionally, different types of two-dimensional views can be two-dimensional views with different display forms. Exemplarily, different display forms can correspond to at least one of different two-dimensional shapes, different colors, and different patterns.

[0073] In the embodiments of the present disclosure, according to the test results of each three-dimensional address included in the memory block, the overall test result of the memory block is determined, and according to the overall test result of the memory block, a two-dimensional cell view corresponding to the memory block is generated, implementing a two-dimensional quantization process based on the dimension of the memory block, enabling the user to determine the overall test result of the memory block based on the two-dimensional cell view, and thus, based on the overall test results of each memory block, obtaining the overall test result of the object under test, which helps to improve the acquisition and display efficiency of invalid address information.

[0074] In an exemplary embodiment, the test result can be used to indicate whether there are invalid address bits in the memory block. In the process of generating a two-dimensional cell view corresponding to the memory block according to the test result, for the target memory block (which can be any memory block) in at least one memory block, in response to the target memory block having invalid address bits, a first two-dimensional view is generated as the two-dimensional cell view of the target memory block, and the first two-dimensional view is used to indicate that the target memory block has invalid address bits; in response to the target memory block having no invalid address bits, a second two-dimensional view is generated as the two-dimensional cell view of the target memory block, and the second two-dimensional view has a different display form from the first two-dimensional view, and the second two-dimensional view is used to indicate that the target memory block has no invalid address bits.

[0075] That is, different types of two-dimensional views may include a first two-dimensional view and a second two-dimensional view, and the first two-dimensional view and the second two-dimensional view may be preset views with different display forms. In a possible implementation manner, when there is an address with a test result of Fail in the three-dimensional addresses included in the target memory block, it is determined that there is a failed address bit in the target memory block, and the preset first two-dimensional view may be used as the two-dimensional unit view of the target memory block. When there is no address with a test result of Fail in the three-dimensional addresses included in the target memory block, it is determined that there is no failed address bit in the target memory block, and the preset second two-dimensional view may be used as the second unit view of the target memory block.

[0076] Exemplarily, as Figure 3 shown, it shows a schematic diagram of an interface displaying two-dimensional unit views of each memory block provided by an exemplary embodiment of the present disclosure. Among them, there are failed address bits in memory blocks 0-8, corresponding to the first two-dimensional view 301 (corresponding to the dark gray squares in the figure), and there are no failed address bits in memory blocks 9-62, corresponding to the second two-dimensional view 302 (corresponding to the light gray squares in the figure).

[0077] In the embodiments of the present disclosure, when there is a failed address bit in a memory block, its test result is displayed in the first two-dimensional view. When there is no failed address bit in a memory block, its test result is displayed in the second two-dimensional view, enabling the user to determine the memory blocks with failed address bits through the displayed first two-dimensional view and the memory blocks without failed address bits through the displayed second two-dimensional view. Without data compression, the user can quickly know whether there are failed address bits in each memory block, improving the acquisition efficiency of failed address information.

[0078] In a possible implementation manner, after displaying the two-dimensional unit views of each memory block, the user may need to highlight the two-dimensional unit views of a certain type of memory block (such as the two-dimensional unit views corresponding to memory blocks that fail the test). An update control for updating the view display form may be provided in the user interface to enable the user to update the displayed two-dimensional unit views.

[0079] Optionally, in response to a display update operation on the first two-dimensional view, update the display form of the first two-dimensional view, and the updated display form of the first two-dimensional view is different from the current display form of the second two-dimensional view. Optionally, in response to a display update operation on the second two-dimensional view, update the display form of the second two-dimensional view, and the updated display form of the second two-dimensional view is different from the current display form of the first two-dimensional view.

[0080] Optionally, a first update control for updating the first two-dimensional view may be displayed in the user interface. In response to receiving an interaction operation on the first update control, it is determined that a display update operation on the first two-dimensional view is received, and the display form of the first two-dimensional view can be updated.

[0081] In a possible implementation, in response to an interaction operation on a first update control, selection items corresponding to different types of display forms can be displayed. In response to receiving a selection operation on a first selection item, the display form of the first two-dimensional view can be updated to the first display form corresponding to the first selection item. For example, color selection items for selecting different colors, shape selection items corresponding to different shapes, pattern selection items corresponding to different patterns, etc. can be displayed.

[0082] Taking the display of color selection items corresponding to different colors as an example, in response to receiving a selection operation on a first color, the display color of the first two-dimensional view can be updated to the first color. Exemplarily, the first color can be red. Combining Figure 3 with the example, the first two-dimensional view displayed therein can be updated from dark gray to red.

[0083] It should be noted that the display form of the updated first two-dimensional view needs to be different from the display form of the currently displayed second two-dimensional view to distinguish different test results. The currently displayed second two-dimensional view can be the second two-dimensional view displayed after the most recent update. In a possible implementation, the selection items displayed do not include the selection item corresponding to the display form of the currently displayed second two-dimensional view, or the selection item corresponding to the display form of the second two-dimensional view cannot be selected. Schematically, combining the above example, the color of the currently displayed second two-dimensional view is light gray, and the light gray selection item is not included in the color selection items.

[0084] Optionally, a second update control for updating the second two-dimensional view is displayed in the user interface. In response to receiving an interaction operation on the second update control, it is determined that a display update operation on the second two-dimensional view is received, and the display form of the second two-dimensional view can be updated.

[0085] In response to an interaction operation on the second update control, selection items corresponding to different types of display forms can be displayed. In response to receiving a selection operation on a second selection item, the display form of the second two-dimensional view can be updated to the second display form corresponding to the second selection item.

[0086] For example, color selection items corresponding to different colors can be displayed. In response to receiving a selection operation on a second color, the display color of the second two-dimensional view can be updated to the second color. Exemplarily, the second color can be green. Combining Figure 3 with the example, Figure 3 the second two-dimensional view in

[0087] The display form of the updated second two-dimensional view needs to be different from the display form of the currently displayed first two-dimensional view. In one possible implementation, the display options do not include the option corresponding to the display form of the currently displayed first two-dimensional view, or the option corresponding to the display form of the first two-dimensional view cannot be selected. The currently displayed first two-dimensional view is the first two-dimensional view displayed after the most recent update. Combining the above example, after updating the first two-dimensional view from dark gray to red, the currently displayed first two-dimensional view is the red first two-dimensional view, and the color selection options in the display do not include the red option.

[0088] In the embodiments of the present disclosure, after displaying the two-dimensional unit view corresponding to the memory block, the user can update the display form of the different two-dimensional unit views corresponding to different test results to highlight the view to be viewed, so that the user can intuitively obtain the failure address information of each memory block.

[0089] In one possible implementation, in addition to displaying the two-dimensional unit views corresponding to each memory block, list information obtained by statistically analyzing the failure address bits can also be displayed. After performing two-dimensional quantization processing on the address test information, the overview data list information corresponding to at least one memory block can be displayed, and the overview data list information includes the number of failure address bits corresponding to each memory block.

[0090] The number of failure address bits corresponding to a memory block is the total number of failure address bits included in the memory block. Optionally, the overview data list information includes the number of failure address bits of each memory block with failure address bits, that is, the memory blocks without failure address bits do not need to be counted in the overview data list information. In one possible implementation, the number of failure address bits of a memory block can be determined according to the block address test information corresponding to the memory block.

[0091] Optionally, the overview data list information can be synchronously displayed with the two-dimensional unit views of each memory block in the same view window of the user interaction interface, or can be displayed in different view windows, and the user can switch between the window for displaying the two-dimensional unit view and the window for displaying the overview data list information.

[0092] In one possible implementation, the overview data list information includes the number of failure address bits of the memory block corresponding to the currently displayed two-dimensional unit view. That is, the overview data list information can be updated with the currently displayed two-dimensional unit view. When a new first two-dimensional view (i.e., a two-dimensional unit view corresponding to a newly added memory block with failure address bits) is added to the currently displayed two-dimensional unit view, the number of failure address bits of the memory block corresponding to the newly added first two-dimensional view can be added to the overview data list information.

[0093] Exemplarily, such as Figure 3As shown, the overview data list information 303 is synchronously displayed in the same view window of the user interaction interface as the two-dimensional unit view of the memory block. The overview data list information 303 includes the number of failed address bits (FailedCells) corresponding to memory blocks 0-8 with failed address bits respectively.

[0094] In the embodiments of the present disclosure, when displaying the two-dimensional unit view, the number of failed address bits of each memory block can be synchronously displayed, so that the user can intuitively obtain the total number of failed address bits existing in each memory block, improving the intuitiveness and efficiency of information acquisition.

[0095] The two-dimensional unit view is used to indicate the overall test result of the memory block. In a possible implementation manner, the two-dimensional unit view can also be expanded to display the detailed address test information corresponding to the memory block.

[0096] After displaying the two-dimensional unit views corresponding to each memory block, in response to a preset expansion operation on the target two-dimensional unit view, a target address information view corresponding to the target two-dimensional unit view is displayed. The target address information view is used to indicate the failed address test results corresponding to each three-dimensional address included in the memory block corresponding to the target two-dimensional unit view.

[0097] Optionally, the preset expansion operation can be a preset interaction operation on the target two-dimensional unit view, such as a click operation, a long press operation, etc. The target two-dimensional unit view can be any currently displayed two-dimensional unit view. The following embodiments will be described by taking the two-dimensional unit view corresponding to the target memory block as an example.

[0098] After receiving the preset expansion operation on the target two-dimensional unit view, the corresponding target address information view can be displayed in the user interaction interface. The target address information view includes the failed address test results corresponding to each three-dimensional address included in the target memory block. Optionally, the target address information view can be a two-dimensional matrix bitmap.

[0099] Optionally, the target address information view can include a thumbnail information view and a detailed information view. The thumbnail information view displays the test results of each three-dimensional address in the overall address range included in the target memory block, and the detailed information view displays the test results of the three-dimensional addresses in the local address range included in the target memory block.

[0100] In a possible implementation, a thumbnail of target address information is displayed in a first area of the user interaction interface. Different areas in the thumbnail of the target address information correspond to different address ranges of memory blocks. The thumbnail of the target address information may be the above-mentioned thumbnail information view. In the thumbnail of the target address information, invalid address bits and non-invalid address bits are displayed in different display states. Exemplarily, the invalid address bits and non-invalid address bits correspond to different colors, so as to indicate the address range where invalid address bits specifically exist through the thumbnail of the target address information.

[0101] Optionally, the detailed information view may correspond to a local address range in the thumbnail information view. In a possible implementation, in response to a selection operation on a target area in the thumbnail of the target address information, an expansion view of the target address information corresponding to the target area is displayed in a second area of the user interaction interface. The expansion view of the target address information includes test result information of each three-dimensional address in the target address range corresponding to the target area.

[0102] The expansion view of the target address information is the detailed information view. Optionally, the expansion view of the target address information includes a plurality of matrix units, and different matrix units correspond to different three-dimensional addresses (the rows and / or columns of different three-dimensional addresses are different, but the memory block information they belong to is the same).

[0103] In a possible implementation, the display state of each matrix unit in the expansion view of the target address information may be determined according to the address test result of the corresponding three-dimensional address. The display state of the three-dimensional address with a test result of Pass is different from the display state of the test result of Fail. Exemplarily, different test results may be indicated by matrix units of different colors. Optionally, when different colors are used to indicate different test results, the same test result is indicated by the same color in the expansion view of the target address information and the two-dimensional unit view of the memory block. Exemplarily, the color of the matrix unit corresponding to the three-dimensional address with a test result of Pass in the expansion view of the target address information is the same as the color of the above-mentioned second two-dimensional view, and the color of the matrix unit corresponding to the three-dimensional address with a test result of Fail is the same as the color of the above-mentioned first two-dimensional view. Optionally, when the same test result is indicated by the same color in the expansion view of the target address information and the two-dimensional unit view of the memory block, when the color corresponding to the first two-dimensional view is updated, the color of the matrix unit corresponding to the three-dimensional address with a test result of Fail is synchronously updated to the same color, and when the color corresponding to the second two-dimensional view is updated, the color of the matrix unit corresponding to the three-dimensional address with a test result of Pass is synchronously updated to the same color.

[0104] In a possible implementation, the thumbnail of the target address information can be synchronously displayed with the expanded view of the target address information in the user interaction interface. The thumbnail of the target address information is displayed in the first area of the user interaction interface, and the expanded view of the target address information is displayed in the second area, where the area of the first area is smaller than the area of the second area.

[0105] Optionally, each three-dimensional address shown in the expanded view of the target address information belongs to the local address range corresponding to the target area, that is, the expanded view of the target address information corresponds to the selected target area in the thumbnail of the target address information, and the expanded view of the target address information is generated based on the address test information of the local address range corresponding to the target area. In response to an update operation on the target area in the thumbnail of the target address information, the expanded view of the target address information displayed in the second area can be updated based on the address test information of the local address range corresponding to the updated target area.

[0106] Optionally, the update operation on the target area in the thumbnail of the target address information can be a box selection operation on the local matrix area in the thumbnail of the target address information, and the box-selected local matrix area can be determined as the target area. The expanded view of the target address information displayed in the second area is a two-dimensional matrix bitmap obtained by magnifying the box-selected local matrix area in the thumbnail of the target address information.

[0107] Schematically, as Figure 4 shown, a thumbnail 401 of the target address information is displayed in the first area, and an expanded view 402 of the target address information is displayed in the second area, where the expanded view 402 of the target address information corresponds to the selected target area 403 in the thumbnail 401 of the target address information. The expanded three-dimensional address information belongs to the local address range corresponding to the target area 403. The dark gray matrix cells in the expanded view 402 of the target address information correspond to invalid address bits, and the light gray matrix cells correspond to non-invalid address bits.

[0108] In a possible implementation, when a marking operation on a matrix cell in the expanded view of the target address information is received, the three-dimensional address information corresponding to the marked matrix cell can be displayed, enabling the user to obtain the specific three-dimensional address information of the invalid address bit by marking the matrix cell corresponding to the invalid address bit.

[0109] In a possible implementation, the user can adjust and update the expanded view of the target address information through interaction operations on the expanded view of the target address information. Optionally, the interaction operations include the above-mentioned marking operation, and can also include zoom-in operation, zoom-out operation, dragging operation, etc. Among them, the zoom-in operation can be used to magnify a local area, the zoom-out operation can be used to reduce a local area, and the dragging operation can be used to drag the view displayed in the current interface.

[0110] Schematically, as Figure 4As shown, after receiving a marking operation on the target matrix cell 404 (the white cell), its corresponding three-dimensional address information can be displayed: (x: 15, y: 11, z: 6), indicating the three-dimensional address of the 15th row and 11th column in memory block 6 corresponding to the target matrix cell.

[0111] In the embodiments of the present disclosure, for the two-dimensional cell view of the memory block, detailed address test information can be expanded and displayed, enabling the user to view the specific failed address bits in the memory block through the corresponding address information view. The approximate address range where the failed address bits are located can be determined through the thumbnail of the target address information, and the specific three-dimensional address information of the failed address bits can be determined through the expanded view of the target address information, allowing the user to obtain detailed failed address information and improving the information acquisition efficiency.

[0112] In a possible implementation, for the selected target two-dimensional cell view, the detailed address list information of the memory block corresponding to the target two-dimensional cell view can be displayed, and the detailed address list information includes the detailed three-dimensional address information corresponding to the failed address bits.

[0113] The detailed list address information includes the failed address bits and their corresponding detailed three-dimensional address information. Optionally, the detailed list address information can be synchronously displayed with the target address information view of the corresponding memory block in the same view window of the user interface, or can be displayed in different view windows, and the user can switch between the window for displaying the target address information view and the window for displaying the detailed list address information.

[0114] In a possible implementation, the detailed list address information includes each failed address bit existing in the memory block corresponding to the target two-dimensional cell view and the three-dimensional address information (x, y, z) of each failed address bit. In another possible implementation, the detailed list address information includes each failed address bit existing in the local address range (the local address range corresponding to the target area) corresponding to the expanded view of the target address information and the three-dimensional address information (x, y, z) of each failed address bit.

[0115] Exemplarily, as Figure 4 shown, the detailed list address information 405 is synchronously displayed with the target address information view in the same view window of the user interface, and the detailed list address information 405 includes the three-dimensional address information corresponding to multiple failed address bits (numbered 1, 2, 3,...) respectively.

[0116] In the embodiments of the present disclosure, when displaying the detailed address information view of a memory block, the detailed list address information of the memory block can be synchronously displayed, so that the user can intuitively obtain the three-dimensional address information corresponding to the failed address bits existing in the memory block, improving the intuitiveness of information acquisition and the information acquisition efficiency.

[0117] In a possible implementation, as Figure 5 shown, the method for obtaining and displaying failure address information includes the following steps:

[0118] Step 510, the host computer sends a test item execution instruction to the slave computer.

[0119] Among them, the test item execution instruction includes test item related information for failure address testing.

[0120] Step 520, the test board of the slave computer tests the object under test based on the test item to obtain address test information.

[0121] Step 530, the host computer reads the address test information from the slave computer.

[0122] Optionally, it can be read from the test item data execution result file of the slave computer, or it can be read from the hardware storage of the test board.

[0123] Step 540, perform two-dimensional quantization processing on the address test information to obtain two-dimensional unit views corresponding to each memory block.

[0124] Step 550, display each two-dimensional unit view.

[0125] Step 560, in response to a preset expansion operation on the target two-dimensional unit view, display the corresponding target address information view.

[0126] Among them, the implementation manners of steps 510-560 can refer to the above embodiments and will not be elaborated here.

[0127] As Figure 6 shown, it shows a schematic structural diagram of a device for obtaining and displaying failure address information provided by an exemplary embodiment of the present disclosure. The device includes:

[0128] An information acquisition module 610, configured to acquire address test information of the object under test, where the address test information is obtained by performing a failure address test on the object under test, and the address information included in the address test information is three-dimensional address information;

[0129] A two-dimensional processing module 620, configured to perform two-dimensional quantization processing on the address test information based on the information dimension for indicating the memory block to which the address belongs in the three-dimensional address information, to obtain two-dimensional unit views corresponding to at least one memory block included in the object under test, and the two-dimensional unit views are used to indicate the failure address test results of the memory blocks;

[0130] A view display module 630, configured to display the two-dimensional unit views corresponding to each of the memory blocks.

[0131] In an exemplary embodiment, the two-dimensional processing module 620 is further configured to:

[0132] Based on the block address test information corresponding to each of the at least one memory block, determine the test results of each memory block, where the block address test information includes the address test information of the three-dimensional address belonging to the memory block;

[0133] Based on the test results of each memory block, generate a two-dimensional unit view of the memory block, where different test results correspond to different types of two-dimensional views.

[0134] In an exemplary embodiment, the two-dimensional processing module 620 is further configured to:

[0135] In response to the existence of a failed address bit in the target memory block, generate a first two-dimensional view as the two-dimensional unit view of the target memory block, where the first two-dimensional view is used to indicate the existence of the failed address bit in the target memory block, and the target memory block is any one of the at least one memory block;

[0136] In response to the non-existence of the failed address bit in the target memory block, generate a second two-dimensional view as the two-dimensional unit view of the target memory block, where the display form of the second two-dimensional view is different from that of the first two-dimensional view, and the second two-dimensional view is used to indicate the non-existence of the failed address bit in the target memory block.

[0137] In an exemplary embodiment, the device further includes:

[0138] A view update module, configured to update the display form of the first two-dimensional view in response to a display update operation on the first two-dimensional view, where the display form of the updated first two-dimensional view is different from that of the currently displayed second two-dimensional view;

[0139] The view update module is further configured to update the display form of the second two-dimensional view in response to a display update operation on the second two-dimensional view, where the display form of the updated second two-dimensional view is different from that of the currently displayed first two-dimensional view.

[0140] In an exemplary embodiment, the device further includes:

[0141] A list display module, configured to display the overview data list information corresponding to the at least one memory block, where the overview data list information includes the number of failed address bits corresponding to each memory block.

[0142] In an exemplary embodiment, the view display module 630 is further configured to:

[0143] In response to a preset expansion operation on a target two-dimensional unit view, a target address information view corresponding to the target two-dimensional unit view is displayed, where the target address information view is used to indicate the failure address test results corresponding to each three-dimensional address included in the memory block corresponding to the target two-dimensional unit view.

[0144] In an exemplary embodiment, the view display module 630 is further configured to:

[0145] Display a target address information thumbnail in a first area of the user interface, where different areas in the target address information thumbnail correspond to different address ranges of the memory block;

[0146] In response to a selection operation on a target area in the target address information thumbnail, display a target address information expansion view corresponding to the target area in a second area of the user interface, where the target address information expansion view includes test result information of each three-dimensional address in the target address range corresponding to the target area.

[0147] In an exemplary embodiment, the list display module is further configured to:

[0148] Display detailed address list information of the memory block corresponding to the target two-dimensional unit view, where the detailed address list information includes detailed three-dimensional address information corresponding to the failure address bits.

[0149] In an exemplary embodiment, the information acquisition module 610 is further configured to:

[0150] During the testing process of the object under test, read the address test information of the tested addresses from the test board, where the test board is used to perform failure address testing on the object under test;

[0151] In response to a view refresh operation, obtain updated test information from the test board, where the updated test information includes address test information that has been tested and not read.

[0152] The failure address information acquisition and display device in the embodiments of the present disclosure corresponds to the embodiments of the above-mentioned failure address information acquisition and display method of the present disclosure, and the relevant content can be referred to each other, which will not be elaborated here. The beneficial technical effects corresponding to the failure address information acquisition and display device in the embodiments of the present disclosure can be seen in the corresponding beneficial technical effects in the above-mentioned corresponding exemplary method part, which will not be elaborated here.

[0153] In addition, the embodiments of the present disclosure further provide an electronic device, including:

[0154] A memory for storing a computer program;

[0155] A processor for executing a computer program stored in the memory, and when the computer program is executed, implementing the method for obtaining and displaying failure address information according to any one of the above embodiments of the present disclosure.

[0156] Figure 7 FIG. is a schematic structural diagram of an electronic device provided by an exemplary embodiment of the present disclosure. As Figure 7 shown, the electronic device includes one or more processors and a memory.

[0157] The processor may be a central processing unit (CPU) or other forms of processing units with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0158] The memory may store one or more computer program products. The memory may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory, etc. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program products may be stored on the computer-readable storage media, and the processor may run the computer program products to implement the method for obtaining and displaying failure address information according to various embodiments of the present disclosure described above and / or other desired functions.

[0159] In one example, the electronic device may further include: an input device and an output device, and these components are interconnected through a bus system and / or other forms of connection mechanisms (not shown).

[0160] In addition, the input device may further include, for example, a keyboard, a mouse, and the like.

[0161] The output device may output various information to the outside, including the determined distance information, direction information, etc. The output device may include, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0162] Of course, for simplicity, Figure 7 only some of the components related to the present disclosure in the electronic device are shown in, and components such as buses, input / output interfaces, etc. are omitted. In addition, according to specific application scenarios, the electronic device may further include any other appropriate components.

[0163] In addition to the above methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions that, when run by a processor, cause the processor to execute the steps in the method for obtaining and displaying failure address information according to various embodiments of the present disclosure described in the above part of this specification.

[0164] The computer program product may be written in any combination of one or more programming languages for programming code to perform the operations of the embodiments of the present disclosure. The programming languages include object-oriented programming languages such as Java, C++, etc., and also include conventional procedural programming languages such as the "C" language or similar programming languages. The programming code may be executed entirely on the user's computing device, partially on the user's device, executed as a stand-alone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0165] Furthermore, an embodiment of the present disclosure may also be a computer-readable storage medium, on which computer program instructions are stored that, when run by a processor, cause the processor to execute the steps in the method for obtaining and displaying failure address information according to various embodiments of the present disclosure described in the above part of this specification.

[0166] The computer-readable storage medium may adopt any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0167] The basic principles of the present disclosure have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, benefits, effects, etc. mentioned in the present disclosure are only examples and not limitations. It cannot be considered that these advantages, benefits, effects, etc. are essential for each embodiment of the present disclosure. In addition, the above specific details are only for illustrative purposes and for ease of understanding, and are not limitations. The above details do not limit the present disclosure to necessarily adopt the above specific details for implementation.

[0168] In this specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. For system embodiments, since they basically correspond to method embodiments, the description is relatively simple. For related parts, reference can be made to the partial description of method embodiments.

[0169] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any way. Words such as "including", "comprising", "having", etc. are open-ended terms, meaning "including but not limited to", and can be used interchangeably with each other. The word "or" and "and" used herein refer to the word "and / or", and can be used interchangeably with each other unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to", and can be used interchangeably with each other.

[0170] The methods and apparatuses of this disclosure can be implemented in many ways. For example, the methods and apparatuses of this disclosure can be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of the steps for the methods is only for illustration. The steps of the methods of this disclosure are not limited to the specific order described above, unless otherwise specifically stated. In addition, in some embodiments, this disclosure can also be implemented as a program recorded in a recording medium, and these programs include machine-readable instructions for implementing the methods according to this disclosure. Therefore, this disclosure also covers the recording medium storing the programs for executing the methods according to this disclosure.

[0171] It should also be noted that in the apparatuses, equipment, and methods of this disclosure, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be regarded as equivalent solutions of this disclosure.

[0172] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects are very obvious to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

[0173] The foregoing description has been presented for purposes of illustration and description. In addition, this description is not intended to limit embodiments of the present disclosure to the form disclosed herein. Although several example aspects and embodiments have been discussed above, those skilled in the art will recognize some of their variations, modifications, alterations, additions, and subcombinations.

Claims

1. A method for obtaining and displaying invalid address information, characterized in that The method includes: Obtaining address test information of the object under test, where the address test information is obtained by performing a failed address test on the object under test, and the address information included in the address test information is three-dimensional address information; Based on the information dimension for indicating the memory block to which the address belongs in the three-dimensional address information, performing two-dimensional quantization processing on the address test information to obtain a two-dimensional unit view corresponding to at least one memory block included in the object under test, where the two-dimensional unit view is used to indicate the failed address test result of the memory block; Displaying the two-dimensional unit views corresponding to each of the memory blocks.

2. The method according to claim 1, characterized in that The performing two-dimensional quantization processing on the address test information based on the information dimension for indicating the memory block to which the address belongs in the three-dimensional address information to obtain a two-dimensional unit view corresponding to at least one memory block included in the object under test includes: Based on the block address test information corresponding to each of the at least one memory block, determining the test result of each of the memory blocks, where the block address test information includes the address test information of the three-dimensional address belonging to the memory block; Based on the test results of each of the memory blocks, generating a two-dimensional unit view of the memory block, where different test results correspond to different types of two-dimensional views.

3. The method according to claim 2, wherein The generating a two-dimensional unit view of the memory block based on the test results of each of the memory blocks includes: In response to the existence of a failed address bit in the target memory block, generating a first two-dimensional view as the two-dimensional unit view of the target memory block, where the first two-dimensional view is used to indicate the existence of the failed address bit in the target memory block, and the target memory block is any one of the at least one memory block; In response to the non-existence of the failed address bit in the target memory block, generating a second two-dimensional view as the two-dimensional unit view of the target memory block, where the display form of the second two-dimensional view is different from that of the first two-dimensional view, and the second two-dimensional view is used to indicate the non-existence of the failed address bit in the target memory block.

4. The method according to claim 3, wherein After displaying the two-dimensional unit views corresponding to each of the memory blocks, the method further includes: In response to a display update operation on the first two-dimensional view, updating the display form of the first two-dimensional view, and the display form of the updated first two-dimensional view is different from that of the currently displayed second two-dimensional view; In response to a display update operation on the second two-dimensional view, updating the display form of the second two-dimensional view, and the display form of the updated second two-dimensional view is different from that of the currently displayed first two-dimensional view.

5. The method according to any one of claims 1 to 4, characterized in that After performing two-dimensional quantization processing on the address test information, the method further includes: Displaying overview data list information corresponding to the at least one memory block, where the overview data list information includes the number of failed address bits corresponding to each of the memory blocks.

6. The method according to any one of claims 1 to 4, characterized in that After displaying the two-dimensional unit views corresponding to each of the memory blocks, the method further includes: In response to a preset expansion operation on the target two-dimensional unit view, displaying a target address information view corresponding to the target two-dimensional unit view, where the target address information view is used to indicate the failed address test results corresponding to each three-dimensional address included in the memory block corresponding to the target two-dimensional unit view.

7. The method according to claim 6, wherein The target address information view corresponding to the display of the target two-dimensional unit view includes: Displaying a thumbnail of target address information in a first area of the user interface, where different areas in the thumbnail of target address information correspond to different address ranges of memory blocks; In response to a selection operation on a target area in the thumbnail of target address information, displaying an expanded view of the target address information corresponding to the target area in a second area of the user interface, where the expanded view of the target address information includes test result information of each three-dimensional address in the target address range corresponding to the target area.

8. The method according to claim 6, wherein After displaying the target address information view corresponding to the target two-dimensional unit view, the method further includes: Displaying detailed address list information of the memory block corresponding to the target two-dimensional unit view, where the detailed address list information includes detailed three-dimensional address information corresponding to the failed address bits.

9. The method according to any one of claims 1 to 4, characterized in that The obtaining of the address test information of the object under test includes: During the testing of the object under test, reading the address test information of the tested addresses from a test board, where the test board is used to perform a failed address test on the object under test; In response to a view refresh operation, obtaining updated test information from the test board, where the updated test information includes address test information that has been tested and not read.

10. An acquisition and display device for invalid address information, characterized in that, The apparatus includes: An information acquisition module, configured to acquire address test information of an object under test, where the address test information is obtained by performing a failed address test on the object under test, and the address information included in the address test information is three-dimensional address information; A two-dimensional processing module, configured to perform two-dimensional quantization processing on the address test information based on the information dimension for indicating the memory block to which the address belongs in the three-dimensional address information, to obtain at least one two-dimensional unit view corresponding to the memory blocks included in the object under test, where the two-dimensional unit view is used to indicate the failed address test result of the memory block; A view display module, configured to display the two-dimensional unit views corresponding to the respective memory blocks.

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