Etching method of semiconductor structure, semiconductor structure and semiconductor device

Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to an etching method of a semiconductor structure, the semiconductor structure and a semiconductor device. The method comprises the steps of providing an initial semiconductor structure; the initial semiconductor structure comprises a substrate structure and a patterned hard mask which are stacked; forming a first protective layer on the surface of the patterned hard mask, subsequently, circularly etching the initial semiconductor structure based on plasmas under a first power parameter, a second power parameter and a third power parameter in sequence until a preset etching depth is reached, and removing the hard mask to obtain a semiconductor structure; the radio frequency power in the first power parameter, the second power parameter and the third power parameter is sequentially reduced, and the bias power is sequentially increased; and the plasma can react with the material of the first protection layer under the first power parameter to generate a second protection layer. Therefore, the etching precision can be improved, and the bridging defect is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly relates to an etching method for a semiconductor structure, a semiconductor structure, and a semiconductor device. Background Art

[0002] With the continuous iteration of the miniaturization of semiconductor devices, the requirements for related etching processes are also getting higher and higher. The etching processes in general semiconductor structures include wet etching and dry etching. Since wet etching has poor controllability and low etching accuracy, dry etching is usually used for structures with higher etching accuracy requirements. Dry etching is a technology for etching thin films with plasma. Specifically, plasma etching technology is a method of etching the surface of a material with high-energy particles or molecular beams. By generating plasma in a low-pressure gas environment, the ions in the plasma are used to bombard the surface of the material, causing chemical reactions or physical processes on the surface of the material to achieve etching of the material surface. Plasma etching technology has the advantages of high precision, high selectivity, and high uniformity, and can achieve micro-nano scale processing.

[0003] However, currently, a continuous plasma etching method is often used to etch a substrate, that is, the substrate is etched based on a preset fixed radio frequency power and a fixed bias power, so that the plasma generated in the etching reaction chamber bombards the surface of the substrate, and then the substrate is continuously etched. However, the above etching method still has problems such as low etching accuracy of the line edge profile and bridging. Summary of the Invention

[0004] To solve the above technical problems, on the one hand, the present application discloses an etching method for a semiconductor structure, which includes:

[0005] Providing an initial semiconductor structure; the initial semiconductor structure includes a stacked substrate structure and a patterned hard mask;

[0006] Forming a first protective layer on the surface of the patterned hard mask;

[0007] Circularly etching the initial semiconductor structure with plasma based on a first power parameter, a second power parameter, and a third power parameter in sequence to obtain a semiconductor structure; the radio frequency power in the first power parameter, the second power parameter, and the third power parameter decreases in sequence, and the bias power increases in sequence; and the plasma can react with the material of the first protective layer under the first power parameter to generate a second protective layer.

[0008] In an exemplary embodiment, before circularly etching the initial semiconductor structure with plasma based on a first power parameter, a second power parameter, and a third power parameter in sequence to obtain a semiconductor structure, the method further includes:

[0009] Etch the initial semiconductor structure based on a fourth power parameter; the bias power in the fourth power parameter is zero.

[0010] In an exemplary embodiment, the RF power in the fourth power parameter is 100 - 300 watts.

[0011] In an exemplary embodiment, the second power parameter is twice the third power parameter;

[0012] The RF power in the first power parameter is ten times the RF power in the third power parameter.

[0013] In an exemplary embodiment, forming a first protective layer on the surface of the patterned hard mask includes:

[0014] Bombard the silicon source of the upper electrode plate with plasma generated based on a fifth power parameter to form a first protective layer on the surface of the patterned hard mask; the bias power in the fifth power parameter is zero, and the RF power in the fifth power parameter is less than the RF power in the first power parameter.

[0015] In an exemplary embodiment, the RF power in the fifth power parameter is 50 - 200 watts;

[0016] The pulse time corresponding to the fifth power parameter is less than the pulse times corresponding to other power parameters; the other power parameters include the first power parameter, the second power parameter, and the third power parameter.

[0017] In an exemplary embodiment, the RF power in the first power parameter is 100 - 300 watts, and the bias power is 30 - 50 watts.

[0018] In an exemplary embodiment, the RF power in the second power parameter is 50 - 150 watts, and the bias power is 60 - 100 watts.

[0019] In an exemplary embodiment, the RF power in the third power parameter is 10 - 30 watts, and the bias power is 110 - 300 watts.

[0020] In an exemplary embodiment, the material of the first protective layer includes silicon;

[0021] The plasma includes CxFy, where x and y are determined by the material of the substrate structure to be etched;

[0022] The material of the second protective layer includes carbon.

[0023] On the other hand, the present application discloses a semiconductor structure, which is obtained by etching with the above-described etching method.

[0024] On the other hand, the present application discloses a semiconductor device, which includes the above-described semiconductor structure.

[0025] The etching method of the semiconductor structure provided by the embodiments of the present application first provides an initial semiconductor structure; the initial semiconductor structure includes a stacked substrate structure and a patterned hard mask; a first protective layer is formed on the surface of the patterned hard mask, so as to protect the hard mask. Subsequently, the initial semiconductor structure is etched cyclically based on the plasmas under the first power parameter, the second power parameter, and the third power parameter until a preset etching depth is reached, and the hard mask is removed to obtain a semiconductor structure; the radio frequency powers in the first power parameter, the second power parameter, and the third power parameter decrease in sequence, and the bias powers increase in sequence; and the plasma can react with the material of the first protective layer under the first power parameter to generate a second protective layer. Thereby, the etching accuracy can be improved and bridging defects can be reduced. Description of the Drawings

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0027] Figure 1 is a schematic structural diagram of a semiconductor etching device provided by an embodiment of the present application;

[0028] Figure 2 is a schematic structural diagram of a fin field-effect transistor;

[0029] Figure 3 is a three-dimensional structural schematic diagram of a semiconductor structure before etching in the prior art;

[0030] Figure 4 is a side view of a semiconductor structure before etching in the prior art;

[0031] Figure 5 is a three-dimensional structural schematic diagram of a semiconductor structure after etching in the prior art;

[0032] Figure 6 is a side view of a semiconductor structure after etching in the prior art;

[0033] Figure 7 is a three-dimensional structural schematic diagram of another semiconductor structure after etching in the prior art;

[0034] Figure 8 is a top partial enlarged view of an existing etched semiconductor structure;

[0035] Figure 9 is a side partial enlarged view of an existing etched semiconductor structure;

[0036] Figure 10 is a top partial enlarged view of another existing etched semiconductor structure;

[0037] Figure 11 is a schematic flow chart of an etching method for a semiconductor structure provided by an embodiment of the present application;

[0038] Figure 12 is a schematic structural diagram of an initial semiconductor structure provided by an embodiment of the present application;

[0039] Figure 13 is a schematic structural diagram of a structure formed in a fifth power parameter stage provided by an embodiment of the present application;

[0040] Figure 14 is a schematic structural diagram of a structure formed in a first power parameter stage provided by an embodiment of the present application;

[0041] Figure 15 is a schematic etching window diagram under a second power parameter provided by an embodiment of the present application;

[0042] Figure 16 is a reaction mechanism in a second power parameter stage provided by an embodiment of the present application;

[0043] Figure 17 is a schematic etching window diagram under a third power parameter provided by an embodiment of the present application;

[0044] Figure 18 is a schematic structural diagram of a structure formed during the execution of a third power parameter stage provided by an embodiment of the present application;

[0045] Figure 19 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present application;

[0046] Figure 20 is a side partial enlarged view of a semiconductor structure provided by an embodiment of the present application.

[0047] Figure 21 is a schematic diagram showing the changes in radio frequency power and bias power in each etching stage provided by an embodiment of the present application.

[0048] The following is a supplementary description of the drawings:

[0049] 1 - Initial semiconductor structure; 101 - Substrate structure; 1011 - Support substrate; 1012 - Layer to be etched; 2 - Hard mask; 3 - First protective layer; 4 - Second protective layer; 5 - Etching reaction chamber; 6 - Upper electrode plate; 7 - Carrying platform; 8 - Insulating layer; 9 - Gate; 10 - Source; 11 - Drain. Detailed implementation manners

[0050] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0051] For the purposes of the following detailed description, it should be understood that the present invention may take various alternative variations and step sequences, unless expressly specified to the contrary. Further, except in any operating examples, or otherwise indicated, all numbers expressing, for example, quantities of ingredients in the specification and claims are to be understood as being modified in all instances by the term "about". Accordingly, unless indicated to the contrary, the numerical parameters set forth in the following specification and attached claims are approximations that may vary depending upon the desired properties sought to be obtained by the present invention. At the very least, and not as an attempt to limit the application of the doctrine of equivalents to the scope of the claims, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques.

[0052] When a numerical range is disclosed herein, the above range is considered continuous and includes the minimum and maximum values of the range, as well as every value therebetween. Further, when the range is an integer, every integer between the minimum and maximum values of the range is included. Additionally, when multiple ranges are provided to describe features or characteristics, the ranges may be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all sub-ranges subsumed therein. For example, the specified range from "1 to 10" should be considered to include any and all sub-ranges between the minimum value 1 and the maximum value 10. Exemplary sub-ranges of the range 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0053] Please refer to Figure 1, which shows a structural schematic diagram of a semiconductor etching device provided by an embodiment of the present application. The semiconductor etching device includes an etching reaction chamber 5, a carrier table 7, a controller, a gas supply device, etc. An initial semiconductor structure 1 to be etched is placed on the carrier table 7. The carrier table 7 (which can serve as a lower electrode plate) is electrically connected to the controller. An upper electrode plate 6 is provided at the top of the semiconductor etching device, and the upper electrode plate 6 is electrically connected to the controller. The gas supply device passes gas into the etching reaction chamber 5 through the top of the semiconductor etching device. The controller is connected to a radio frequency power source and a bias power source. Among them, the radio frequency power source and the bias power source are used to generate pulses of radio frequency power and pulses of bias power respectively, and supply them to the etching reaction chamber 5 to cause the generated plasma gas to bombard and react with the initial semiconductor structure 1. Optionally, the semiconductor etching device further includes an exhaust device for exhausting the excess gas in the etching reaction chamber 5 and the residues formed by the etching reaction.

[0054] In the embodiments of the present disclosure, the above-mentioned controller can control the opening and closing of the radio frequency power source and the bias power source, as well as control the magnitude and pulse time of the radio frequency power generated by the radio frequency power source and the magnitude and pulse time of the bias power generated by the bias power source.

[0055] In the embodiments of the present disclosure, the controller can specifically be an electronic device or an independent control unit. Optionally, the electronic device can be a terminal, such as a desktop computer, a laptop computer, etc. Among them, the terminal can include one or more processors (the processor can include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA), a memory for storing data, and a transmission device for communication functions. In addition, it can further include: a display, an input / output interface (I / O interface), a universal serial bus (USB) port (which can be included as one of the ports of the I / O interface), a network interface, a power supply, and / or a camera. Those of ordinary skill in the art can understand.

[0056] The memory can be used to store software programs and modules of application software, such as the program instructions / data storage device corresponding to the control method of the semiconductor etching device in the embodiments of the present application (specifically, it can include the control of the operating parameters of the radio frequency power source, bias power source, upper electrode plate 6, gas supply device, exhaust device, etc.). The processor executes various functional applications and data processing by running the software programs and modules stored in the memory, that is, to implement the above-mentioned control method of a semiconductor etching device. The memory can include a high-speed random access memory, and can also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memories. In some instances, the memory can further include a memory remotely set relative to the processor, and these remote memories can be connected to the terminal through a network. Examples of the above-mentioned network include but are not limited to the Internet, enterprise intranet, local area network, mobile communication network, and their combinations.

[0057] The transmission device is used to receive or send data via a network. In one instance, the transmission device includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station and thus can communicate with the Internet. In one embodiment, the transmission device can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0058] The display can be, for example, a touch-screen liquid crystal display (LCD), which enables the user to interact with the user interface of the terminal (or mobile device).

[0059] The embodiments of the present application also provide a computer-readable storage medium. The storage medium can be disposed in the above-mentioned terminal to store at least one instruction or at least one segment of program related to implementing the control method of the semiconductor etching device in the method embodiments. The at least one instruction or the at least one segment of program is loaded and executed by the processor to implement the control method of the semiconductor etching device provided in the above method embodiments. Optionally, the above storage medium can be located in at least one of multiple network servers in a computer network. Optionally, the above storage medium can include but is not limited to: USB flash drive, read-only memory (ROM), random access memory (RAM), mobile hard disk, magnetic disk, or optical disc, etc., various media that can store program codes.

[0060] Currently, with the development of Complementary Metal Oxide Semiconductor (CMOS) devices, after the etching accuracy reaches the 20-nanometer node, CMOS devices gradually change from a planar structure to a 3D structure. For example, a new type of CMOS device, the FinField-Effect Transistor (FinFET), please refer to Figure 2 , which shows a schematic structural diagram of a fin field-effect transistor. A FinFET usually includes a support substrate 1011, an insulating layer 8 located on the support substrate 1011, a gate 9 located on the insulating layer 8, and a source 10 and a drain 11 are also provided on both sides of the gate 9. Its feature is that the channel region is a fin-shaped semiconductor wrapped by the gate 9. The length of the fin along the source-drain direction is the channel length; the structure wrapped by the gate 9 enhances the control ability of the gate, provides better electrical control for the channel, thereby reducing the leakage current and suppressing the short-channel effect.

[0061] Generally, FinFET devices can be divided into two categories, bulk silicon FinFET devices and SOI FinFET devices. According to different specific application requirements, other high-performance devices will be derived from the above two devices, such as structures with lower power consumption: annular gate FinFET devices, Π-shaped gate FinFET devices, and Ω-shaped gate FinFET devices, etc. Generally, the front-end process of FinFET adopts a three-dimensional structure, and the difficulty of its process is to form the shape of the Fin. Optionally, plasma etching technology can be used to etch a semiconductor structure (as Figures 3 - 4 shown, the semiconductor structure may include a support substrate 1011, an etching layer 1012 to be etched, and a patterned hard mask 2 layer stacked from bottom to top). Under continuous etching conditions, after the etching of the etching layer 1012 to be etched is completed, a structure as shown in Figure 5 or Figure 6 is formed. Then, the hard mask 2 is removed. At this time, based on the patterned etching layer 1012 to be etched, the support substrate 1011 (such as a silicon layer) can be etched to a certain depth, and the target semiconductor structure as shown in Figure 7 can be obtained. After the etching layer 1012 to be etched is removed subsequently, the Fin is formed. Of course, according to needs, the self-aligned double patterning (SADP) technology can also be used to form the Fin. Specifically, an auxiliary layer (such as silicon nitride) can be formed on the substrate silicon first, and then a gate-like structure is formed by etching in sequence, a sidewall structure of the gate 9 is formed by etching, the auxiliary layer is removed to form the hard mask 2, and then the Fin can be formed by continuing the etching. In the formation of the Fin, due to the very poor depth loading effect and pattern roughness in the hard mask etching of the Fin, the depth will be different when forming the Fin, and the pattern roughness will be very poor (asFigure 8 As shown, the line profile accuracy of the hard mask 2 is poor, which will affect the subsequent processes and the electrical performance of the final device, and may even form a bridge connection that causes the device to fail (such as Figures 9 - 10 the area marked by the dashed box in

[0062] Therefore, hard mask etching is a key factor in determining Fin formation.

[0063] However, currently, continuous etching is used for the hard mask of Fin. This etching method results in insufficient hard mask protection and non-straight profiles, leading to problems such as depth loading effects and poor pattern roughness. As the etching node progresses, the width dimension of Fin becomes smaller and smaller. Thus, the width dimension of the Fin hard mask needs to be smaller and smaller, and the dense areas become denser, resulting in more bridge connection defects and roughness problems. Figure 9 As shown

[0064] In the prior art, to reduce by-products during plasma etching, the common method is to adjust the composition of the processing gas. For example, reducing the content of polymer-rich gas in the gas or increasing the content of oxygen in the processing gas to reduce the carbon-fluorine ratio (C / F) in the processing gas, thereby reducing the formation of non-volatile by-products. However, reducing the content of polymer-rich gas or oxygen will result in poor selectivity of the etching gas for the mask layer, causing the etched via hole size to be enlarged. Therefore, the effect of maintaining the via hole size uniformity by adjusting the etching gas composition is poor, and the formed via hole size is inaccurate.

[0065] It can be understood that the etching method provided by the embodiments of the present application is not limited to the etching of Fins, but can also be the etching of other structures of other semiconductor devices, as long as the etching substrate can adopt a dry etching method. However, for the convenience of understanding the solution of the present application, the etching of Fins will still be used as a specific example for elaboration below.

[0066] In view of this, please refer to Figure 11 , the present application provides an etching method for a semiconductor structure, which includes:

[0067] S1101: Provide an initial semiconductor structure 1; the initial semiconductor structure 1 includes a stacked substrate structure 101 and a patterned hard mask 2.

[0068] In the embodiments of the present disclosure, the initial semiconductor structure 1 may be a structure as Figure 12 shown. Optionally, the substrate structure 101 includes a stacked support substrate 1011 and an etching target layer 1012. Optionally, the material of the substrate may include, but is not limited to, silicon. The etching target layer 1012 includes, but is not limited to, single-layer structures such as silicon oxide and silicon nitride, or may be a multi-layer structure of multiple materials. As Figure 12 shown, the etching target layer 1012 may include a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer arranged in sequence from bottom to top. Optionally, the material of the hard mask 2 includes, but is not limited to, silicon nitride. Optionally, the etching target layer 1012 may also contain the material of the support substrate 1011, that is to say, the etching target layer 1012 may include a part of the substrate area. The area of the substrate not included in the etching target layer 1012 is called the support substrate 1011. During the actual etching process, a part of the substrate area will be etched.

[0069] In the embodiments of the present disclosure, the preparation process of the initial semiconductor structure 1 may include: providing a support substrate 1011 (specifically, a silicon wafer), forming an etching target layer 1012 on the support substrate 1011 by a deposition process, then forming a mask material layer on the etching target layer 1012 by a substrate process, and then patterning the mask material layer to form a structure as Figure 12The initial semiconductor structure 1 shown. Optionally, the specific method of patterning the mask material layer can be a dry etching method. Specifically, a patterned hard mask 2 can be formed by using self-aligned double imaging technology. For example, an auxiliary layer is formed on the surface of the mask material layer, and then a gate-like structure 9 is formed. The width of the gate-like structure is equal to the width between the lines of the subsequent patterned hard mask 2. A silicon dioxide layer is deposited on the surface of the gate-like structure as a mask. By controlling the thickness of the silicon dioxide layer, the width of the hard mask 2 can be controlled. Then, a dry etching process is used to form the sidewall structure of the gate 9. Next, the auxiliary layer is removed, and the hard mask 2 material layer is etched to remove the silicon dioxide layer to obtain the patterned hard mask 2. Other dry etching methods can also be specifically used, which are not limited here. The specific etching part can also be a wet etching method. The lithography process can also use a photoresist as a mask. Specifically, a photoresist can be coated on the hard mask 2 material layer, and then the process steps of exposure - development - wet etching are performed to obtain the patterned hard mask 2.

[0070] S1103: Form a first protective layer 3 on the surface of the patterned hard mask 2.

[0071] In an exemplary embodiment, step S1103 may specifically include: bombarding the silicon source of the upper electrode plate 6 with plasma generated based on the fifth power parameter to form a first protective layer 3 on the surface of the patterned hard mask 2, obtaining the structure as Figure 13 described. The bias power in the fifth power parameter is zero, and the radio frequency power in the fifth power parameter is less than the radio frequency power in the following first power parameter.

[0072] In the embodiments of the present disclosure, by controlling the magnitude of the radio frequency power generated by the radio frequency power source, the energy of the plasma gas bombarding the substrate can be controlled, and the bias power can control the direction of plasma bombardment. Turning on the bias power source can make the plasma gas move towards the support substrate 1011 of the initial semiconductor structure 1, thereby realizing the etching of a through hole with a preset depth of the layer to be etched 1012.

[0073] In the embodiments of the present disclosure, the plasma includes CxFy, where x and y are determined by the material of the substrate structure 101 to be etched. In the case where the bias power source is not turned on, that is, the bias power is zero, and the upper electrode plate 6 is turned on, the generated plasma gas CxFy will bombard the silicon source of the upper electrode plate 6, thereby forming a uniform and dense first protective layer 3 (i.e., a silicon layer) on the surface of the patterned hard mask 2, obtaining the structure as Figure 13In the structure shown, the first protective layer 3 can protect the patterned hard mask 2, preventing the etching of the hard mask 2 during the subsequent etching of the layer to be etched 1012, thereby reducing the etching effect. Optionally, exemplary embodiments of CxFy may include CF2, C2F2, C3F4, etc.

[0074] In an exemplary embodiment, the RF power in the fifth power parameter is 50 to 200 watts. In an exemplary embodiment, the RF power in the fifth power parameter may be 50 watts, 60 watts, 70 watts, 80 watts, 90 watts, 100 watts, 110 watts, 120 watts, 130 watts, 140 watts, 150 watts, 160 watts, 170 watts, 180 watts, 190 watts, 200 watts, etc. The pulse time corresponding to the fifth power parameter is less than the pulse times corresponding to the other power parameters; the other power parameters include the first power parameter, the second power parameter, and the third power parameter. Optionally, the pulse time corresponding to the fifth power parameter is 20 to 40 seconds. In an exemplary embodiment, the pulse time corresponding to the fifth power parameter may be 20 seconds, 23 seconds, 25 seconds, 27 seconds, 29 seconds, 31 seconds, 33 seconds, 35 seconds, 37 seconds, 39 seconds, 40 seconds, etc.

[0075] In an exemplary embodiment, before sequentially etching the initial semiconductor structure 1 with the plasmas based on the first power parameter, the second power parameter, and the third power parameter to obtain a semiconductor structure, the method further includes: etching the initial semiconductor structure 1 based on a fourth power parameter; the bias power in the fourth power parameter is zero. This allows the generated CxFy plasma gas to slowly contact the first protective layer 3, ensuring that the first protective layer 3 has fully contacted the plasma gas in the subsequent etching step, thereby improving the subsequent etching reaction effect.

[0076] In an exemplary embodiment, the RF power in the fourth power parameter is 100 to 300 watts. In an exemplary embodiment, the RF power in the fourth power parameter may be 100 watts, 130 watts, 150 watts, 170 watts, 190 watts, 210 watts, 230 watts, 250 watts, 270 watts, 290 watts, 300 watts, etc. Optionally, the pulse time corresponding to the fourth power parameter is less than the pulse time corresponding to the fifth power parameter. Specifically, the pulse time corresponding to the fifth power parameter may be greater than 8 times the pulse time corresponding to the fourth power parameter. Optionally, the pulse time corresponding to the fourth power parameter is 1.5 to 5 seconds. In an exemplary embodiment, the pulse time corresponding to the fourth power parameter may be 1.5 seconds, 1.7 seconds, 1.9 seconds, 2.1 seconds, 2.3 seconds, 2.5 seconds, 2.7 seconds, 2.9 seconds, 3.1 seconds, 3.3 seconds, 3.5 seconds, 3.7 seconds, 3.9 seconds, 4.1 seconds, 4.3 seconds, 4.5 seconds, 4.7 seconds, 5 seconds, etc.

[0077] S1105: Sequentially perform cyclic etching on the initial semiconductor structure 1 based on the plasma under the first power parameter, the second power parameter, and the third power parameter to obtain a semiconductor structure; the radio frequency power in the first power parameter, the second power parameter, and the third power parameter decreases in sequence, and the bias power increases in sequence; and the plasma can react with the material of the first protective layer 3 under the first power parameter to generate a second protective layer 4.

[0078] In the embodiments of the present disclosure, by etching the initial semiconductor based on the plasma under the first power parameter, the plasma under the first power parameter reacts with the material of the first protective layer 3 to generate a second protective layer 4. Continuing the above example, when the first protective layer 3 is a silicon layer, the plasma generated under the first power parameter is CxFy. At this time, since both the bias power source and the radio frequency power source are turned on, the generated plasma can be promoted to bombard the hard mask 2. The plasma CxFy will react with the first protective layer 3, and the specific reaction equation is: Si + CxFy -> SiF4↑ + Cx. The reaction products are carbon and SiF4 gas. Among them, the SiF4 gas will volatilize and can be discharged through the exhaust channel of the semiconductor etching device, so that no additional by-products are generated, and it will not affect the bombardment etching of the subsequent plasma on the layer to be etched 1012, improving the etching efficiency and effect. The carbon generated in this stage will cover the surface of the hard mask 2 as the second protective layer 4 to protect the hard mask 2, obtaining the structure as Figure 14 shown. Optionally, the radio frequency power in the first power parameter can be equal to the radio frequency power parameter in the fourth power parameter, and the radio frequency power in the first power parameter is 100 - 300 watts. In an exemplary embodiment, the radio frequency power in the first power parameter can be 100 watts, 130 watts, 150 watts, 170 watts, 190 watts, 210 watts, 230 watts, 250 watts, 270 watts, 290 watts, 300 watts, etc. The bias power in the first power parameter is 30 - 50 watts. In an exemplary embodiment, the bias power in the first power parameter can be 30 watts, 33 watts, 35 watts, 37 watts, 39 watts, 41 watts, 43 watts, 45 watts, 47 watts, 49 watts, 50 watts, etc. Optionally, the pulse time corresponding to the first power parameter can be equal to the pulse time corresponding to the fourth power parameter, and their relationship can also be less than or equal to, which can be specifically set according to needs and is not limited here. Optionally, the pulse time corresponding to the first power parameter is 1.5 - 5 seconds. In an exemplary embodiment, the pulse time corresponding to the first power parameter can be 1.5 seconds, 1.7 seconds, 1.9 seconds, 2.1 seconds, 2.3 seconds, 2.5 seconds, 2.9 seconds, 3.1 seconds, 3.3 seconds, 3.5 seconds, 3.7 seconds, 3.9 seconds, 4.1 seconds, 4.3 seconds, 4.5 seconds, 4.9 seconds, 5 seconds, etc.

[0079] Next, continue to etch the initial semiconductor structure 1 based on the plasma under the second power parameter. At this time, since both the bias power source and the RF power source are turned on, the generated plasma can be promoted to bombard the hard mask 2. At this time, the RF power in the second power parameter is less than the RF power in the first power parameter. Specifically, the RF power in the second power parameter can be half of the RF power in the first power parameter. Compared with the first power parameter stage, fewer ions / electrons / free radicals are dissociated in the second power parameter stage.

[0080] As can be seen from the following formula (1), when the number of ions T i is small, the ion angular distribution (θ) is small, and the number of ions is positively correlated with the RF power. Therefore, the smaller the RF power, the smaller the ion angular distribution (θ):

[0081]

[0082] And increasing the bias power V in the second power parameter bias , such that the bias power in the second power parameter is greater than the bias power in the first power parameter, will also make the ion angular distribution (θ) small. Please refer to Figure 15 , which shows a schematic diagram of an etching window under the second power parameter provided by an embodiment of the present application. The RF power in the second power parameter is 50 - 150 watts. In an exemplary embodiment, the RF power in the second power parameter can be 50 watts, 60 watts, 70 watts, 80 watts, 90 watts, 95 watts, 100 watts, 110 watts, 120 watts, 130 watts, 140 watts, 150 watts, etc. The bias power in the second power parameter is 60 - 100 watts. In an exemplary embodiment, the bias power in the second power parameter can be 60 watts, 65 watts, 70 watts, 75 watts, 80 watts, 85 watts, 90 watts, 95 watts, 100 watts, etc. Optionally, the pulse time corresponding to the second power parameter is 1.5 - 3 seconds. In an exemplary embodiment, the pulse time corresponding to the second power parameter can be 1.5 seconds, 1.7 seconds, 1.9 seconds, 2.1 seconds, 2.3 seconds, 2.5 seconds, 2.7 seconds, 2.9 seconds, 3 seconds, etc.

[0083] The second power parameter stage is a process of making the second protective layer 4 more dense. Please refer to Figure 16 , by breaking the C - F bonds and having more C - C bonds, the second protective layer 4 becomes more dense, which provides a good hard mask for subsequent etching and finally achieves a good effect of pattern roughness.

[0084] Subsequently, continue to etch the initial semiconductor structure 1 based on the plasma under the third power parameter. At this time, both the bias power source and the RF power source are turned on. The RF power in the third power parameter is less than the RF power in the second power parameter. Specifically, the RF power in the third power parameter can be 1 / 5 of the RF power in the second power parameter. Compared with the second power parameter stage, fewer ions / electrons / free radicals are dissociated in the third power parameter stage.

[0085] Increase the bias power V in the third power parameter bias , so that the bias power in the third power parameter is greater than the bias power in the second power parameter. Based on the above formula (1), it can be known that the ion angular distribution (θ) will be smaller. Please refer to Figure 17 , which shows a schematic diagram of an etching window under the third power parameter provided by an embodiment of the present application. The RF power in the third power parameter is 10 - 30 watts. In an exemplary embodiment, the RF power in the third power parameter can be 10 watts, 13 watts, 15 watts, 17 watts, 19 watts, 21 watts, 23 watts, 25 watts, 27 watts, 29 watts, 30 watts, etc. The bias power in the third power parameter is 110 - 300 watts. In an exemplary embodiment, the bias power in the first power parameter can be 110 watts, 120 watts, 130 watts, 140 watts, 150 watts, 160 watts, 170 watts, 180 watts, 190 watts, 200 watts, 210 watts, 220 watts, 230 watts, 240 watts, 250 watts, 260 watts, 270 watts, 280 watts, 290 watts, 300 watts, etc. Optionally, the pulse time corresponding to the third power parameter is 1.5 - 5 seconds. In an exemplary embodiment, the pulse time corresponding to the second power parameter can be 1.5 seconds, 1.7 seconds, 1.9 seconds, 2.1 seconds, 2.3 seconds, 2.5 seconds, 2.7 seconds, 2.9 seconds, 3.1 seconds, 3.3 seconds, 3.5 seconds, 3.7 seconds, 3.9 seconds, 4.1 seconds, 4.3 seconds, 4.5 seconds, 4.7 seconds, 4.9 seconds, 5 seconds, etc.

[0086] In the third power parameter stage, due to the smaller RF power and higher bias power, ions can be transported to the bottom of the etching, making the bottom of the first oxide layer more vertical (such as Figure 18 the structure shown), leaving a large window for the etching of the silicon nitride layer. The load depth effect can be improved from 35A to 7A, an improvement of about 80%, thus reducing the generation of bridging defects in subsequent processes.

[0087] By sequentially cycling the etching of the initial semiconductor in the above first power parameter stage, second power parameter stage, and third power parameter stage until the etching of the layer to be etched 1012 is completed, and then removing the hard mask 2, a semiconductor structure as shown in Figure 19 can be obtained. Please compare Figure 9 andFigure 20 It can be seen that after etching is completed by using the etching method of the embodiment of the present application, the bridging phenomenon between adjacent lines can be greatly improved, and the line profile is also straighter.

[0088] In the embodiment of the present disclosure, in the etching preparation stage, please refer to Figure 21, the magnitude of the power value at each stage is represented by the height of the gray column. Based on the set fifth power parameter, specifically, in the fifth power parameter stage, the controller can turn on the radio frequency power source, turn off the bias control source, and turn on the upper electrode plate 6. The generated plasma will bombard the silicon source of the upper electrode plate 6, thereby forming a uniform and dense first protective layer 3 (i.e., silicon layer) on the surface of the patterned hard mask 2. The pulse time corresponding to this stage can be set to be less than the pulse times corresponding to other power parameters; the other power parameters include the fourth power parameter, the first power parameter, the second power parameter, and the third power parameter. The radio frequency power in the fifth power parameter is 50-200 watts. Next, in the fourth power parameter stage, the controller can continue to keep the radio frequency power source on and the bias control source off. The radio frequency power in the fourth power parameter is greater than the radio frequency power in the fifth power parameter. Specifically, the radio frequency power in the fourth power parameter can be 100-300 watts, and the bias power is zero, so that the generated CxFy plasma gas slowly contacts the first protective layer 3, ensuring that the first protective layer 3 has fully contacted the plasma gas in the subsequent etching step, improving the reaction effect. In the subsequent first power parameter stage, the controller can turn on the radio frequency power source and the bias control source. The radio frequency power in the first power parameter is 10 times the radio frequency power in the third power parameter. The radio frequency power in the first power parameter stage can be equal to the radio frequency power parameter in the fourth power parameter. That is to say, in the first power parameter stage, only the radio frequency power in the fourth power parameter stage needs to be continued, and only the bias power source needs to be turned on. The bias power in the first power parameter can be set to 30-50 watts. When the first protective layer 3 is a silicon layer, the plasma generated under the first power parameter is CxFy. At this time, since both the bias power source and the radio frequency power source are turned on, the generated plasma can be promoted to bombard the hard mask 2. The plasma CxFy will react with the first protective layer 3, and the reaction products are carbon and SiF4 gas. Among them, the SiF4 gas volatilizes and can be discharged through the exhaust channel of the semiconductor etching device, so that no additional by-products are generated and it will not affect the subsequent bombardment etching of the layer to be etched 1012 by the plasma, improving the etching efficiency and effect. In the second power parameter stage, the controller can turn on the radio frequency power source and the bias control source. The radio frequency power in the second power parameter is less than the radio frequency power in the first power parameter. Specifically, the radio frequency power in the second power parameter can be half of the radio frequency power in the first power parameter. Compared with the first power parameter stage, fewer ions / electrons / free radicals are dissociated in the second power parameter stage. The bias power in the second power parameter is increased, resulting in a small ion angular distribution (θ). By breaking the C-F bond and having more C-C bonds, the second protective layer 4 becomes denser, providing a good hard mask for the subsequent etching and finally achieving a good effect of pattern roughness.Next, it is the etching process for the etching layer 1012. The radio frequency power in the third power parameter is less than the radio frequency power in the second power parameter. Specifically, the radio frequency power in the third power parameter can be 1 / 5 of the radio frequency power in the second power parameter. Compared with the second power parameter stage, fewer ions / electrons / free radicals are dissociated in the third power parameter stage. The bias power in the third power parameter is higher, that is, the bias power in the third power parameter stage is greater than the bias power in the second power parameter stage. Ions can be transported to the bottom of the etching, making the bottom of the first oxide layer more vertical, leaving a large window for the etching of the silicon nitride layer. The load depth effect can be improved from 35 Å to 7 Å, an improvement of about 80%, thereby reducing the generation of bridging defects in subsequent processes. Subsequently, the fourth power parameter stage, the first power parameter stage, the second power parameter stage, and the third power parameter stage can be cyclically executed successively as needed until the etching of the etching layer 1012 is completed, and then the hard mask 2 is removed.

[0089] Compared with the prior art in which continuous plasma etching is performed on silicon oxide using a plasma gas of CxFy or oxygen and continuous plasma etching is performed on silicon nitride using CHxFy or oxygen, this novel pulsed etching with multiple stages in the embodiment of the present application uses a method of carbon layer protection for the hard mask. Carbon has a higher selectivity ratio for etching silicon oxide and can well protect the line profile. The roughness transferred to the Fin is increased by at least about 15%.

[0090] It can be understood that during the actual pulsed etching process, the amount of gas entering the etching reaction chamber 5 can be adaptively adjusted as needed, which is not limited herein. The power of each stage in the specific etching process can be adaptively adjusted, and any concept that can achieve the final effect of each stage described above belongs to the protection scope of this solution.

[0091] In the embodiments of the present disclosure, specifically according to needs, to further improve the etching effect, during the etching process, it can also be to sequentially and cyclically execute the fifth power parameter stage, the fourth power parameter stage, the first power parameter stage, the second power parameter stage, and the third power parameter stage until the etching of the layer to be etched 1012 is completed, and then the hard mask 2 is removed. That is, based on the set fifth power parameter, specifically, in the fifth power parameter stage, the radio frequency power source can be turned on based on the controller, the bias control source is turned off, and the upper electrode plate 6 is turned on. The generated plasma will bombard the silicon source of the upper electrode plate 6, thereby forming a uniform and dense first protective layer 3 (i.e., a silicon layer) on the surface of the patterned hard mask 2. The pulse time corresponding to this stage can be set to be less than the pulse times corresponding to other power parameters; the other power parameters include the fourth power parameter, the first power parameter, the second power parameter, and the third power parameter. The radio frequency power in the fifth power parameter is 50 to 200 watts. Next, in the fourth power parameter stage, the radio frequency power source can be continuously turned on based on the controller, the bias control source is turned off. The radio frequency power in the fourth power parameter is greater than the radio frequency power in the fifth power parameter. Specifically, the radio frequency power in the fourth power parameter can be 100 to 300 watts, and the bias power is zero, so that the generated CxFy plasma gas slowly contacts the first protective layer 3, making the first protective layer 3 fully contact with the plasma gas in the subsequent etching steps and improving the reaction effect. In the subsequent first power parameter stage, the radio frequency power source and the bias control source can be turned on based on the controller. The radio frequency power in the first power parameter stage can be equal to the radio frequency power parameter in the fourth power parameter. The bias power in the first power parameter can be set to 30 to 50 watts. When the first protective layer 3 is a silicon layer, the plasma generated under the first power parameter is CxFy. At this time, since both the bias power source and the radio frequency power source are turned on, the generated plasma can be promoted to bombard the hard mask 2. The plasma CxFy will react with the first protective layer 3, and the reaction products are carbon and SiF4 gas. Among them, the SiF4 gas volatilizes and can be specifically discharged through the exhaust channel of the semiconductor etching device, so that no additional by-products are generated and it will not affect the bombardment etching of the subsequent plasma on the layer to be etched 1012, improving the etching efficiency and effect. In the second power parameter stage, the radio frequency power source and the bias control source can be turned on based on the controller. The radio frequency power in the second power parameter is less than the radio frequency power in the first power parameter. Specifically, the radio frequency power in the second power parameter can be half of the radio frequency power in the first power parameter. Compared with the first power parameter stage, fewer ions / electrons / free radicals are dissociated in the second power parameter stage. The bias power in the second power parameter is increased, making the ion angular distribution (θ) small. By breaking the C-F bond and having more C-C bonds, the second protective layer 4 becomes denser, which provides a good hard mask for the subsequent etching and finally achieves a good effect of pattern roughness.Next is the etching process for the etching layer 1012. The radio frequency power in the third power parameter is less than that in the second power parameter. Compared with the second power parameter stage, fewer ions / electrons / free radicals are dissociated in the third power parameter stage. The bias power of the third power parameter is higher, that is, the bias power in the third power parameter stage is greater than that in the second power parameter stage. Ions can be transported to the bottom of the etching, making the bottom of the first oxide layer more vertical, leaving a large window for the etching of the silicon nitride layer, thereby reducing the generation of bridging defects in subsequent processes. Subsequently, the fifth power parameter stage, the fourth power parameter stage, the first power parameter stage, the second power parameter stage, and the third power parameter stage can be executed. If the preset etching depth is not reached, the fifth power parameter stage, the fourth power parameter stage, the first power parameter stage, the second power parameter stage, and the third power parameter stage can continue to be executed in sequence until the etching of the etching layer 1012 is completed, and then the hard mask 2 is removed.

[0092] An embodiment of the present application provides a semiconductor structure, which is etched by the above etching method, such as Figure 19 the structure shown. Since the method for preparing the semiconductor structure is to first provide an initial semiconductor structure 1; the initial semiconductor structure 1 includes a stacked substrate structure 101 and a patterned hard mask 2; a first protective layer 3 is formed on the surface of the patterned hard mask 2, so as to protect the hard mask 2. Subsequently, the initial semiconductor structure 1 is circularly etched based on the plasma under the first power parameter, the second power parameter, and the third power parameter in sequence until the preset etching depth is reached, and the hard mask 2 is removed to obtain the semiconductor structure; the radio frequency power in the first power parameter, the second power parameter, and the third power parameter decreases in sequence, and the bias power increases in sequence; and the plasma can react with the material of the first protective layer 3 under the first power parameter to generate a second protective layer 4. Thereby, the etching accuracy can be improved and bridging defects can be reduced. Therefore, the prepared semiconductor structure has similar advantages.

[0093] An embodiment of the present application provides a semiconductor device, and the semiconductor device includes the above-mentioned semiconductor structure. Since the above-mentioned semiconductor device includes the above-mentioned semiconductor structure, the method for preparing the semiconductor structure is to first provide an initial semiconductor structure 1; the initial semiconductor structure 1 includes a stacked substrate structure 101 and a patterned hard mask 2; a first protective layer 3 is formed on the surface of the patterned hard mask 2, so as to protect the hard mask 2. Subsequently, the initial semiconductor structure 1 is circularly etched based on the plasma under the first power parameter, the second power parameter, and the third power parameter in sequence until a preset etching depth is reached, and the hard mask 2 is removed to obtain a semiconductor structure; the radio frequency power among the first power parameter, the second power parameter, and the third power parameter decreases in sequence, and the bias power increases in sequence; and the plasma can react with the material of the first protective layer 3 under the first power parameter to generate a second protective layer 4. Thereby, the etching accuracy can be improved and bridging defects can be reduced. Therefore, the prepared semiconductor device has similar advantages.

[0094] It should be noted that: the above sequence of embodiments of the present application is only for description and does not represent the superiority or inferiority of the embodiments. And the above specific embodiments of this specification have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be executed in a different order from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0095] Each embodiment in this specification is described in a progressive manner, and the same or similar parts among the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiments.

[0096] Those of ordinary skill in the art can understand that all or part of the steps for implementing the above embodiments can be completed by hardware, or can be completed by a program instructing relevant hardware. The program can be stored in a computer-readable storage medium, and the above-mentioned storage medium can be a read-only memory, a disk, an optical disc, etc.

[0097] The above are only optional embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An etching method for a semiconductor structure, characterized in that, Comprising: Providing an initial semiconductor structure; The initial semiconductor structure includes a stacked substrate structure and a patterned hard mask; Forming a first protective layer on the surface of the patterned hard mask; Sequentially performing cyclic etching on the initial semiconductor structure based on plasmas under a first power parameter, a second power parameter, and a third power parameter to obtain a semiconductor structure; the radio frequency power in the first power parameter, the second power parameter, and the third power parameter decreases in sequence, and the bias power increases in sequence; and the plasma can react with the material of the first protective layer under the first power parameter to generate a second protective layer.

2. The etching method according to claim 1, characterized in that Before the step of sequentially performing cyclic etching on the initial semiconductor structure based on plasmas under a first power parameter, a second power parameter, and a third power parameter to obtain a semiconductor structure, the method further includes: Etching the initial semiconductor structure based on a fourth power parameter; the bias power in the fourth power parameter is zero.

3. The etching method according to claim 2, wherein The radio frequency power in the fourth power parameter is 100 - 300 watts.

4. The etching method according to claim 1, wherein The second power parameter is twice the third power parameter; The radio frequency power in the first power parameter is ten times the radio frequency power in the third power parameter.

5. The etching method according to claim 1, wherein The step of forming a first protective layer on the surface of the patterned hard mask includes: Bombarding the silicon source of the upper electrode plate with a plasma generated based on a fifth power parameter to form a first protective layer on the surface of the patterned hard mask; the bias power in the fifth power parameter is zero, and the radio frequency power in the fifth power parameter is less than the radio frequency power in the first power parameter.

6. The etching method according to claim 5, wherein The radio frequency power in the fifth power parameter is 50 - 200 watts; The pulse time corresponding to the fifth power parameter is less than the pulse times corresponding to other power parameters; the other power parameters include the first power parameter, the second power parameter, and the third power parameter.

7. The etching method according to claim 1, wherein The radio frequency power in the first power parameter is 100 - 300 watts, and the bias power is 30 - 50 watts.

8. The etching method according to claim 1, characterized in that The radio frequency power in the second power parameter is 50 - 150 watts, and the bias power is 60 - 100 watts.

9. The etching method according to claim 1, wherein The radio frequency power in the third power parameter is 10 - 30 watts, and the bias power is 110 - 300 watts.

10. The etching method according to claim 1, characterized in that The material of the first protective layer includes silicon; The plasma includes CxFy, where x and y are determined by the material of the substrate structure to be etched; The material of the second protective layer includes carbon.

11. A semiconductor structure, characterized in that, Etched by the etching method according to any one of claims 1 - 10.

12. A semiconductor device, characterized in that, Including the semiconductor structure according to claim 11.

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