Preparation method of SOI wafer

Abstract

The invention provides a preparation method of an SOI wafer, and the method comprises the steps: sequentially carrying out a pre-annealing process and an annealing process on a bonded wafer through furnace tube equipment, so as to enable a part of thickness of a device substrate in the bonded wafer to be peeled off along an ion implantation layer, the temperature of the pre-annealing process is 250-300 DEG C, and the temperature of the annealing process is 400-500 DEG C. Therefore, in the stripping process of the device substrate, the temperature field distribution uniformity in the furnace tube equipment can be improved, so that the haze difference of the bonding wafers in the furnace tube equipment is improved, the haze uniformity between the bonding wafers in the furnace tube equipment is improved, the haze of the surfaces of the bonding wafers is reduced, and the yield of the device substrate is improved. And the difference value between the maximum value and the minimum value of the haze values of all the bonded wafers in the same batch is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly to a method for preparing an SOI wafer. Background Art

[0002] The application of SOI (Silicon on Insulator) technology in semiconductor devices has significant advantages, such as reducing parasitic capacitance, lowering power consumption, increasing operating speed, and enhancing radiation resistance. However, the performance of SOI devices is also affected by various factors. Among them, haze, as an optical property, can indirectly reflect the uniformity of the device surface state or internal structure. A higher haze will affect the optical and electrical properties of the device. For example, high haze may lead to enhanced light scattering, thereby affecting the optical coupling efficiency or signal transmission quality of the device; in addition, the change in haze may also be related to the reflectivity of the material surface, thus having an indirect impact on the overall performance of the device.

[0003] In the current process of preparing SOI wafers, after bonding the support substrate and the device substrate to form a bonded wafer, it is necessary to perform a peeling process on the device substrate in the bonded wafer. However, in the current peeling process, a batch operation mode is usually adopted, resulting in a wide range of haze distribution (5.0 ppm - 5.8 ppm) between the bonded wafers at different positions (slots) in the furnace tube equipment, which affects the haze uniformity between the bonded wafers, and the haze of the bonded wafers at some positions is relatively high, resulting in a relatively large difference (0.8 ppm) between the maximum haze value and the minimum haze value of the bonded wafers in the same furnace tube equipment. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for preparing an SOI wafer to improve the haze uniformity between the bonded wafers during the peeling process.

[0005] To achieve the above purpose, the present invention provides a method for preparing an SOI wafer, including:

[0006] Providing a device substrate, on the surface of which an insulating layer is formed;

[0007] Performing an ion implantation process on the device substrate to form an ion implantation layer in the device substrate;

[0008] Providing a support substrate;

[0009] Bonding the support substrate and the device substrate to form a bonded wafer, wherein the insulating layer is located between the device substrate and the support substrate;

[0010] The pre-annealing process and the annealing process are sequentially performed on the bonded wafer through a furnace tube device, so that the device substrate with a partial thickness in the bonded wafer is peeled off along the ion implantation layer. The temperature of the pre-annealing process is 250°C to 300°C, and the temperature of the annealing process is 400°C to 500°C.

[0011] Optionally, in the method for manufacturing the SOI wafer, when performing the pre-annealing process, the process temperature, gas flow rate, and process time of the pre-annealing process satisfy the following relational expression:

[0012] Z = 0.35*X + 0.5*Y - 80;

[0013] Wherein, Z represents the gas flow rate of the pre-annealing process; X represents the process temperature of the pre-annealing process; Y represents the process time of the pre-annealing process.

[0014] Optionally, in the method for manufacturing the SOI wafer, the process time of the pre-annealing process is 15 min to 35 min.

[0015] Optionally, in the method for manufacturing the SOI wafer, the gas used in the pre-annealing process includes argon and / or nitrogen.

[0016] Optionally, in the method for manufacturing the SOI wafer, the gas used in the annealing process includes argon and / or nitrogen.

[0017] Optionally, in the method for manufacturing the SOI wafer, the process time of the annealing process is 20 min to 60 min.

[0018] Optionally, in the method for manufacturing the SOI wafer, the gas flow rate of the annealing process is 20 L / min to 60 L / min.

[0019] Optionally, in the method for manufacturing the SOI wafer, when performing the annealing process, the heating rate is 2°C / min to 10°C / min.

[0020] Optionally, in the method for manufacturing the SOI wafer, after the peeling process of the bonded wafer, the method for manufacturing the SOI wafer further includes: thinning the bonded wafer.

[0021] In the method for preparing an SOI wafer provided by the present invention, a pre-annealing process and an annealing process are sequentially performed on the bonded wafer through a furnace tube device, so that a device substrate with a partial thickness in the bonded wafer is peeled off along an ion implantation layer. The temperature of the pre-annealing process is 250°C to 300°C, and the temperature of the annealing process is 400°C to 500°C. Thus, during the peeling process of the device substrate, the uniformity of the temperature field distribution in the furnace tube device can be improved, thereby improving the haze difference of the bonded wafers in the furnace tube device, and further improving the haze uniformity between the bonded wafers in the furnace tube device, and then reducing the haze on the surface of the bonded wafers, and reducing the difference between the maximum value and the minimum value of the haze values of all the bonded wafers in the same batch (i.e., all the bonded wafers that simultaneously perform the annealing process in the same furnace tube device). Description of the Drawings

[0022] Figure 1 is a schematic flow chart of the method for preparing an SOI wafer according to an embodiment of the present invention;

[0023] Figures 2 to 6 is a schematic structural diagram formed in the method for preparing an SOI wafer according to an embodiment of the present invention;

[0024] Figure 7 is a schematic diagram of the haze relationship of the bonded wafers in different embodiments in the method for preparing an SOI wafer according to an embodiment of the present invention;

[0025] Among them, the description of the reference numerals is as follows:

[0026] 100 - device substrate; 110 - insulating layer; 120 - ion implantation layer;

[0027] 200 - support substrate. Detailed Embodiments

[0028] The following further describes in detail the method for preparing an SOI wafer proposed by the present invention in conjunction with the drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0029] Figure 1 is a schematic flow chart of the method for preparing an SOI wafer according to an embodiment of the present invention. As Figure 1 shown, this embodiment provides a method for preparing an SOI wafer, including:

[0030] Step S1: Provide a device substrate, and an insulating layer is formed on the surface of the device substrate;

[0031] Step S2: Perform ion implantation on the device substrate to form an ion implantation layer in the device substrate;

[0032] Step S3: Provide a support substrate;

[0033] Step S4: Bond the support substrate and the device substrate to form a bonded wafer, where the insulating layer is located between the device substrate and the support substrate;

[0034] Step S5: Sequentially perform a pre-annealing process and an annealing process on the bonded wafer through a furnace tube equipment, so that a part of the thickness of the device substrate in the bonded wafer is peeled off along the ion implantation layer. The temperature of the pre-annealing process is 250°C to 300°C, and the temperature of the annealing process is 400°C to 500°C.

[0035] Figures 2 to 6 It is a schematic structural diagram formed in the method for preparing an SOI wafer provided by an embodiment of the present invention; hereinafter, it will be combined with the attached Figures 2 to 6 A more detailed description of the method for preparing the SOI wafer provided in this embodiment will be given.

[0036] First, as Figure 2 shown, perform Step S1 to provide a device substrate 100, and an insulating layer 110 is formed on the surface of the device substrate 100.

[0037] In this embodiment, the material of the device substrate 100 may be silicon, and the material of the insulating layer 110 is silicon oxide. In other specific embodiments, the material of the device substrate 100 may also be silicon germanium, germanium, or compound semiconductor, etc., and the material of the insulating layer 110 may be silicon nitride, silicon oxynitride, germanium silicon oxide, or other common insulating materials.

[0038] In this embodiment, the thickness of the insulating layer 110 may be 1500 Å to 2000 Å.

[0039] Next, as Figure 3 shown, perform Step S2 to perform an ion implantation process on the device substrate 100 to form an ion implantation layer 120 in the device substrate 100. Specifically, the ions implanted by the ion implantation process may be hydrogen ions, and the ion implantation layer 120 is used to peel off a part of the thickness of the device substrate 100 subsequently.

[0040] Exemplarily, when performing the ion implantation process on the device substrate 100, the implantation energy of the ion implantation process may be 60 keV, and the implantation dose may be 5.5E16 atom / cm 2 .

[0041] After that, as Figure 4As shown, step S3 is performed to provide a support substrate 200. The material of the support substrate 200 can be silicon, that is, the material of the support substrate 200 can be the same as that of the device substrate 100. In other embodiments, the material of the support substrate 200 can also be silicon germanium, germanium, or compound semiconductors, etc., as well as common substrate materials such as sapphire or silicon carbide.

[0042] Next, as Figure 5 shown, step S4 is performed to bond the support substrate 200 and the device substrate 100 to form a bonded wafer. Among them, the insulating layer 110 is located between the device substrate 100 and the support substrate 200, that is, the insulating layer 110 faces the support substrate 200.

[0043] Specifically, before bonding the support substrate 200 and the device substrate 100, the device substrate 100 and the support substrate 200 can be wet-cleaned first to remove particles on the surfaces of the device substrate 100 and the support substrate 200.

[0044] Then, the support substrate 200 and the device substrate 100 are bonded to form a bonded wafer. Among them, when bonding the support substrate 200 and the device substrate 100, an ordinary bonding process or a plasma-assisted bonding process can be used.

[0045] In addition, the surface of the support substrate 200 for bonding can also have an oxide layer, which together with the insulating layer 110 constitutes the buried oxide layer of the bonded wafer in the bonding step.

[0046] After that, as Figure 6 shown, step S5 is performed to perform a pre-annealing process and an annealing process on the bonded wafer in sequence through a furnace tube device, that is, the bonded wafer is peeled by combining the pre-annealing process and the annealing process, so that a part of the thickness of the device substrate 100 in the bonded wafer is peeled along the ion implantation layer 120. The temperature of the pre-annealing process is 250°C to 300°C, and the temperature of the annealing process is 400°C to 500°C. In this way, during the peeling process of the device substrate 100, the uniformity of the temperature field distribution in the furnace tube device can be improved, thereby improving the haze difference of the bonded wafers in the furnace tube device, and then improving the haze uniformity between the bonded wafers in the furnace tube device, and further reducing the haze on the surface of the bonded wafer. In this embodiment, when performing the pre-annealing process and the annealing process, multiple bonded wafers can be placed in the same furnace tube device, and the multiple bonded wafers are sequentially subjected to the pre-annealing process and the annealing process.

[0047] Specifically, when performing the pre-annealing process, the process temperature, gas flow rate, and process time of the pre-annealing process satisfy the following relationship:

[0048] Z = 0.35*X + 0.5*Y - 80;

[0049] Wherein, Z represents the gas flow rate of the pre-annealing process; X represents the process temperature of the pre-annealing process; Y represents the process time of the pre-annealing process.

[0050] In this way, during the execution of the pre-annealing process, the temperature uniformity inside the furnace tube equipment can be improved, thereby improving the haze difference of the bonded wafers inside the furnace tube equipment, and reducing the overall haze inside the furnace tube equipment.

[0051] In this embodiment, when the pre-annealing process is executed, the gas flow rate of the pre-annealing process is 25 L / min to 50 L / min, for example, 30 L / min, 40 L / min or 45 L / min.

[0052] It should be noted that if the gas flow rate is too large during the execution of the pre-annealing process, it will cause the enhancement of fluid momentum, thereby destroying the uniformity of the temperature field. Therefore, it is necessary to satisfy the above relationship, that is, when the temperature is relatively high and / or the process time is relatively long, the gas flow rate needs to be appropriately increased; when the temperature is relatively low and / or the process time is relatively short, the gas flow rate needs to be appropriately reduced to ensure the temperature field uniformity during the pre-annealing process, which is beneficial to improving the haze uniformity between the bonded wafers inside the furnace tube equipment.

[0053] In this embodiment, when the pre-annealing process is executed, multiple bonded wafers are simultaneously placed in the process chamber of the furnace tube equipment, and then the pre-annealing process is executed.

[0054] Preferably, the process time of the pre-annealing process is 15 min to 35 min, for example, 20 min.

[0055] In this embodiment, the gas used in the pre-annealing process includes argon (Ar) and / or nitrogen (N2).

[0056] After the pre-annealing process is executed, an annealing process is performed on the bonded wafers. Specifically, the temperature of the annealing process is 400 °C to 500 °C, that is, in the same furnace tube equipment, the temperature in the process chamber of the furnace tube equipment is raised to 400 °C to 500 °C, and the heating rate is 2 °C / min to 10 °C / min. In this way, the temperature difference between the bonded wafers caused by rapid heating can be avoided, and further the haze between the bonded wafers can be prevented from being affected.

[0057] Exemplarily, the gas used in the annealing process includes argon and / or nitrogen, and the gas flow rate of the annealing process can be greater than that of the pre-annealing process. Among them, the gas flow rate of the annealing process can be 20 L / min to 60 L / min, for example, 35 L / min, 40 L / min, 45 L / min or 50 L / min.

[0058] Exemplarily, the process time of the annealing process is 20 min to 60 min.

[0059] The following provides multiple embodiments to further illustrate the effects of the method for preparing an SOI wafer provided in this embodiment.

[0060] Table 1 Comparison table of haze in different embodiments

[0061]

[0062] It should be noted that the average haze value in Table 1 is the average haze value of the bonded wafers in the process chamber of the furnace equipment, that is, the average value of the haze values on the surfaces of all bonded wafers in a single process batch; the difference between the maximum and minimum haze values refers to the difference between the maximum and minimum haze values of all bonded wafers in the same batch in the process chamber of the furnace equipment.

[0063] Figure 7 It is a schematic diagram of the haze relationship of the bonded wafers in different embodiments in the method for preparing an SOI wafer provided by the embodiment of the present invention. Figure 7 The abscissa in represents the different position numbers (Slot ID) in the furnace equipment, Figure 7 and the ordinate is the haze.

[0064] Exemplarily, referring to Table 1 and combining with Figure 7 as shown, in the first embodiment, the temperature of the pre-annealing process of the bonded wafer is 300 °C, the time of the pre-annealing process is 30 min, the gas flow rate of the pre-annealing process is 40 L / min, the average haze value between all bonded wafers (wafer to wafer) in the furnace equipment is 4.80 ppm, and the difference between the maximum and minimum haze values of the bonded wafers in the furnace equipment is 0.4 ppm.

[0065] In the second embodiment, the pre-annealing temperature of the bonded wafer is 300 °C, the pre-annealing time is 30 min, the gas flow rate of the pre-annealing process is 10 L / min, the average haze value is 5.15 ppm, and the difference between the maximum and minimum haze values is 0.85 ppm.

[0066] In Example 3, the pre-annealing temperature of the bonded wafer is 300 °C, the pre-annealing time is 30 min, the flow rate of the pre-annealing process gas is 70 L / min, the average haze value is 5.10 ppm, and the difference between the maximum and minimum haze values is 0.80 ppm.

[0067] In Example 4, the pre-annealing temperature of the bonded wafer is 300 °C, the pre-annealing time is 30 min, the flow rate of the pre-annealing process gas is 40 L / min, the average haze value is 5.50 ppm, and the difference between the maximum and minimum haze values is 0.50 ppm.

[0068] In Example 5, the pre-annealing temperature of the bonded wafer is 400 °C, the pre-annealing time is 30 min, the flow rate of the pre-annealing process gas is 40 L / min, the average haze value is 5.42 ppm, and the difference between the maximum and minimum haze values is 0.48 ppm.

[0069] In Example 6, the pre-annealing temperature of the bonded wafer is 300 °C, the pre-annealing time is 60 min, the flow rate of the pre-annealing process gas is 40 L / min, the average haze value is 5.50 ppm, and the difference between the maximum and minimum haze values is 0.45 ppm.

[0070] In Example 7, the pre-annealing temperature of the bonded wafer is 0 °C, the pre-annealing time is 0 min, that is, the pre-annealing process is not performed, and only the pre-annealing process gas is introduced into the furnace tube equipment. The flow rate of the pre-annealing process gas is 40 L / min, the average haze value is 5.55 ppm, and the difference between the maximum and minimum haze values is 0.45 ppm.

[0071] Comparing the above Examples 1 to 7, it can be seen that by using the method for preparing an SOI wafer provided in this example (Example 1), the uniformity of the temperature field distribution in the furnace tube equipment can be improved, thereby improving the haze difference of the bonded wafers in the furnace tube equipment, thus improving the haze uniformity between the bonded wafers in the furnace tube equipment, and further reducing the haze on the surface of the bonded wafers, and reducing the difference between the maximum and minimum haze values of all the bonded wafers in the same batch. The difference between the maximum and minimum haze values of all the bonded wafers in the same batch can be reduced to 0.40 ppm.

[0072] In this example, after performing the annealing process, that is, after the device substrate 100 is peeled off, the method for preparing the SOI wafer further includes: thinning the bonded wafer to thin the device substrate 100 in the bonded wafer so that the thickness of the device substrate 100 is thinned to a preset thickness.

[0073] After that, a strengthening heat treatment is performed on the bonded wafer to strengthen the bonding surface between the device substrate 100 and the support substrate 200. Among them, the strengthening heat treatment can be performed in the same step as the pre-annealing process and the annealing process in the foregoing steps, that is, the strengthening heat treatment is performed in situ to simplify the process.

[0074] In summary, in the method for preparing an SOI wafer provided in the embodiment of the present invention, the pre-annealing process and the annealing process are sequentially performed on the bonded wafer through a furnace tube device, so that a part of the device substrate with a certain thickness in the bonded wafer is peeled off along the ion implantation layer. The temperature of the pre-annealing process is 250°C to 300°C, and the temperature of the annealing process is 400°C to 500°C. In this way, during the peeling process of the device substrate, the uniformity of the temperature field distribution in the furnace tube device can be improved, thereby improving the haze difference of the bonded wafers in the furnace tube device, and further improving the haze uniformity between the bonded wafers in the furnace tube device, and then reducing the haze on the surface of the bonded wafers, and reducing the difference between the maximum value and the minimum value of the haze values of all the bonded wafers in the same batch.

[0075] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art according to the above disclosure are within the scope of the claims.

[0076] In addition, it should also be recognized that although the present invention has been disclosed above in preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the above-disclosed technical content, or it can be modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belong to the scope of protection of the technical solution of the present invention.

Claims

1. A method for preparing an SOI wafer, characterized in that, Comprising: Providing a device substrate, on the surface of which an insulating layer is formed; Performing an ion implantation process on the device substrate to form an ion implantation layer in the device substrate; Providing a support substrate; Bonding the support substrate to the device substrate to form a bonded wafer, wherein the insulating layer is located between the device substrate and the support substrate; Sequentially performing a pre-annealing process and an annealing process on the bonded wafer through a furnace equipment, so that a part of the device substrate with a certain thickness in the bonded wafer peels off along the ion implantation layer, the temperature of the pre-annealing process is 250°C to 300°C, and the temperature of the annealing process is 400°C to 500°C.

2. The method for preparing an SOI wafer according to claim 1, characterized in that, When performing the pre-annealing process, the process temperature, gas flow rate and process time of the pre-annealing process satisfy the following relational expression: Z = 0.35*X + 0.5*Y - 80; Wherein, Z represents the gas flow rate of the pre-annealing process; X represents the process temperature of the pre-annealing process; Y represents the process time of the pre-annealing process.

3. The method for preparing an SOI wafer according to claim 2, characterized in that, The process time of the pre-annealing process is 15 min to 35 min.

4. The method for preparing an SOI wafer according to claim 2, wherein, The gas used in the pre-annealing process includes argon and / or nitrogen.

5. The method for preparing an SOI wafer according to claim 1, characterized in that, The gas used in the annealing process includes argon and / or nitrogen.

6. The method for preparing an SOI wafer according to claim 1, wherein, The process time of the annealing process is 20 min to 60 min.

7. The method for preparing an SOI wafer according to claim 1, characterized in that, The gas flow rate of the annealing process is 20 L / min to 60 L / min.

8. The method for preparing an SOI wafer according to claim 1, characterized in that, When performing the annealing process, the heating rate is 2°C / min to 10°C / min.

9. The method for preparing an SOI wafer according to claim 1, wherein, After performing the peeling process on the bonded wafer, the method for preparing the SOI wafer further includes: thinning the bonded wafer.

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