Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: providing a substrate on which a stacked structure is formed, the stacked structure comprising dielectric layers and a first sacrificial layer alternately stacked vertically from bottom to top; forming a plurality of through-holes penetrating the stacked structure; forming a second sacrificial layer covering the sidewalls of the through-holes, the second sacrificial layer comprising a plurality of sub-sacrificial layers stacked laterally; forming a conductive pillar structure filling the through-holes and covering the second sacrificial layer; removing all first sacrificial layers in the stacked structure to form a plurality of first trenches spaced apart in the longitudinal direction and surrounded by longitudinally adjacent dielectric layers; removing the exposed portion of the second sacrificial layer along each first trench to form a second trench exposing a portion of the sidewall of the conductive pillar structure, the second trench being connected to the first trench to form a third trench; forming a dielectric layer covering the side surfaces and bottom of the third trench; and forming a conductive plate structure filling the third trench and covering the dielectric layer. The present invention is advantageous in ensuring the operating performance of the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] The structure of 3D memory consists of multiple stacked conductive plates and dielectric layers, interspersed with numerous conductive pillars (pillars) that are wide at the top and narrow at the bottom. The surface where the plates and pillars meet is arranged in a top electrode-capacitor material-bottom electrode pattern. The top electrode connects to the upper conductor within the plate, while the bottom electrode connects to the lower conductor within the pillar. 3D memory utilizes a plate-last process, where the pillars are first formed, then wet-etched through trenches near the pillar matrix to the sacrificial material layers corresponding to the conductive plates. The sacrificial material layers are then removed, and the conductive plate material is then filled in to form the conductive plates. Summary of the Invention

[0003] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are beneficial to ensuring the working performance of the semiconductor structure.

[0004] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, on which a stacked structure is formed, the stacked structure comprising dielectric layers and first sacrificial layers alternately stacked from bottom to top in the longitudinal direction; forming a plurality of through holes penetrating the stacked structure; forming a second sacrificial layer covering the side walls of the through holes, the second sacrificial layer comprising a plurality of sub-sacrificial layers stacked in the transverse direction; forming a conductive pillar structure filling the through holes and covering the second sacrificial layer; removing all first sacrificial layers in the stacked structure to form a plurality of first trenches arranged at intervals in the longitudinal direction and surrounded by longitudinally adjacent dielectric layers; removing the exposed portion of the second sacrificial layer along each first trench to form a second trench exposing a portion of the side wall of the conductive pillar structure, the second trench being connected to the first trench to form a third trench; forming a dielectric layer covering each side surface and bottom surface of the third trench; and forming a conductive plate structure filling the third trench and covering the dielectric layer.

[0005] Correspondingly, an embodiment of the present invention also provides a semiconductor structure, including: a substrate; a conductive stack located on the substrate, the conductive stack including dielectric layers and conductive plate structures stacked alternately in sequence from bottom to top along the longitudinal direction; a plurality of conductive column structures, the conductive column structures passing through the conductive stack; a plurality of dielectric layers arranged at intervals along the longitudinal direction, the dielectric layers covering each surface of the corresponding conductive plate structures, and being located between the conductive plate structures and the conductive column structures; a plurality of second sacrificial layers arranged at intervals along the longitudinal direction, the second sacrificial layers covering part of the side walls of the conductive column structures, and being located between the corresponding dielectric layers and the conductive column structures, the second sacrificial layers including a plurality of sub-sacrificial layers stacked along the transverse direction.

[0006] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0007] In the formation method provided by the embodiment of the present invention, a second sacrificial layer covering the sidewall of the through hole is formed, and the second sacrificial layer includes a plurality of sub-sacrificial layers stacked in the transverse direction to form a conductive column structure filling the through hole and covering the second sacrificial layer, and all the first sacrificial layers in the stacked structure are removed to form a plurality of first grooves arranged in the longitudinal direction and spaced apart from each other and surrounded by longitudinally adjacent dielectric layers; in the embodiment of the present invention, the second sacrificial layer is composed of a plurality of stacked sub-sacrificial layers, and in the step of removing the exposed second sacrificial layer along the first groove, the plurality of sub-sacrificial layers are removed in sequence in the transverse direction, and when any sub-sacrificial layer is removed, the damage to the corresponding sub-sacrificial layer in the longitudinal direction depends on the thickness of the current sub-sacrificial layer, and the impact on other sub-sacrificial layers is small, so that after the plurality of sub-sacrificial layers are removed, the damage to each sub-sacrificial layer in the longitudinal direction is still kept small, so that after the exposed second sacrificial layer is removed along the first groove, the damage to the second sacrificial layer as a whole in the longitudinal direction is small. Compared with the solution in which the second sacrificial layer is a single film layer as a whole, when the second sacrificial layer is removed along the first groove, the damage to the second sacrificial layer in the longitudinal direction depends on the thickness of the entire second sacrificial layer, and the damage is relatively large. In this solution, the total thickness of the second sacrificial layer is divided into the thicknesses of multiple sub-sacrificial layers, so that the thickness of each sub-sacrificial layer is smaller, and the corresponding damage to the second sacrificial layer in the longitudinal direction is only based on the thickness of the sub-sacrificial layer, which is beneficial to reducing the damage to the second sacrificial layer in the longitudinal direction when the exposed second sacrificial layer is removed along the first groove, and is beneficial to increasing the size of the remaining second sacrificial layer between the longitudinally adjacent conductive plate structures. Correspondingly, it is beneficial to reduce the probability of peeling at the contact position between the dielectric layer and the second sacrificial layer when the exposed second sacrificial layer is removed along the first groove, and further beneficial to reducing the probability of leakage between the longitudinally adjacent conductive plate structures, thereby ensuring the working performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1 to 8 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0009] Figures 9 to 16 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention;

[0010] Figure 17 It is a structural schematic diagram corresponding to an embodiment of the semiconductor structure of the present invention. DETAILED DESCRIPTION

[0011] As can be seen from the background art, it is currently difficult to guarantee the working performance of semiconductor structures. The reasons why the working performance of semiconductor structures still needs to be guaranteed are now analyzed in conjunction with a semiconductor structure.

[0012] Figures 1 to 8The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0013] refer to Figure 1 A substrate 10 is provided, on which a stacked structure 20 is formed. The stacked structure 20 includes dielectric layers 21 and first sacrificial layers 22 alternately stacked longitudinally from bottom to top. A conductive block structure 11 is formed in the substrate 10, and the conductive block structure 11 is exposed on the top surface of the substrate 10; a plurality of through holes 23 are formed through the stacked structure 20, and the through holes 23 expose the conductive block structure 11.

[0014] refer to Figure 2 , forming a sacrificial material layer 31 covering the sidewall and bottom of the through hole 23 and the top of the stacked structure 20; and forming a protective material layer 32 covering the sacrificial material layer 31.

[0015] refer to Figure 3 , remove the sacrificial material layer 31 and the protective material layer 32 at the bottom of the through hole 23 and the top of the stacked structure 20, retain the sacrificial material layer 31 covering the side wall of the through hole 23 as the second sacrificial layer 33, and retain the protective material layer 32 covering the side wall of the through hole 23 as the protective layer 34.

[0016] refer to Figure 4 , remove the protective layer 34.

[0017] refer to Figure 5 , forming a conductive pillar structure 40 that fills the through hole 23 and covers the second sacrificial layer 33 .

[0018] After removing the protective layer 34 , the corner morphology of the second sacrificial layer 33 will be left at the bottom of the through hole 23 , and the size of the contact position between the bottom of the conductive column structure 40 and the conductive block structure 11 will be reduced, resulting in a larger contact resistance between the conductive column structure 40 and the conductive block structure 11 .

[0019] refer to Figure 6 , the first sacrificial layer 22 is removed, forming a first trench 51 surrounded by the longitudinally adjacent dielectric layers 21. It should be understood that the first sacrificial layer 22 is removed by a wet etching process, and before the wet etching process, at least one opening is formed through the stacked structure 20, allowing the etching solution to etch and remove the first sacrificial layer 22 through this opening.

[0020] refer to Figure 7 , Figure 7 (b) in the removal process Figure 7 (a) is a partial enlarged schematic diagram of the dotted box position. Figure 7 (c) in the figure is after removal Figure 7In (a), a partial enlarged schematic diagram of the dotted box position is shown, in which the exposed portion of the second sacrificial layer 33 is removed along the first trench 51 to form a second trench 52 exposing a portion of the sidewall of the conductive pillar structure 40 . The second trench 52 and the first trench 51 are connected to form a third trench 53 .

[0021] Typically, a wet etching process is used to remove the exposed portion of the second sacrificial layer 33 along the first trench 51, such as Figure 7 As shown in (b), if the thickness of the second sacrificial layer 33 is relatively thin, a pinhole will be formed in the second sacrificial layer 33. When removing the second sacrificial layer 33, the etching solution can easily enter through the pinhole and damage the conductive pillar structure 40. Figure 7 As shown in (c), due to the isotropy of the wet etching process, the loss (Loss) of the remaining second sacrificial layer 33 in the longitudinal direction is almost equal to twice the thickness of the second sacrificial layer 33, which easily leads to a smaller remaining size of the second sacrificial layer 33 in the longitudinal direction. After the conductive plate structure is subsequently formed in the third trench 53, leakage may easily occur between the conductive plate structures adjacent to each other in the longitudinal direction, thereby affecting the working performance of the semiconductor structure.

[0022] refer to Figure 8 , forming a dielectric layer 60 covering the side surfaces and bottom surface of the third trench 53 ; and forming a conductive plate structure 50 filling the third trench 53 and covering the dielectric layer 60 .

[0023] In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, on which a stacked structure is formed, the stacked structure including dielectric layers and first sacrificial layers alternately stacked from bottom to top in the longitudinal direction; forming a plurality of through holes penetrating the stacked structure; forming a second sacrificial layer covering the side walls of the through holes, the second sacrificial layer including a plurality of sub-sacrificial layers stacked in the transverse direction; forming a conductive pillar structure filling the through holes and covering the second sacrificial layer; removing all first sacrificial layers in the stacked structure to form a plurality of first trenches arranged at intervals in the longitudinal direction and surrounded by longitudinally adjacent dielectric layers; removing the exposed portion of the second sacrificial layer along each first trench to form a second trench exposing a portion of the side wall of the conductive pillar structure, the second trench being connected to the first trench to form a third trench; forming a dielectric layer covering each side surface and bottom surface of the third trench; and forming a conductive plate structure filling the third trench and covering the dielectric layer.

[0024] In the embodiment of the present invention, the second sacrificial layer is composed of a plurality of stacked sub-sacrificial layers. In the step of removing the exposed second sacrificial layer along the first groove, the plurality of sub-sacrificial layers are removed in sequence along the transverse direction. When any sub-sacrificial layer is removed, the damage to the corresponding sub-sacrificial layer along the longitudinal direction depends on the thickness of the current sub-sacrificial layer, and the impact on other sub-sacrificial layers is small, so that after the plurality of sub-sacrificial layers are removed, the damage to each sub-sacrificial layer along the longitudinal direction is still small. Therefore, after the exposed second sacrificial layer is removed along the first groove, the damage to the second sacrificial layer as a whole along the longitudinal direction is small. Compared with the solution in which the second sacrificial layer is a single film layer as a whole, when the second sacrificial layer is removed along the first groove, the damage to the second sacrificial layer along the longitudinal direction depends on the thickness of the entire second sacrificial layer. Thickness, the damage is large, while in this solution, the total thickness of the second sacrificial layer is divided into the thicknesses of multiple sub-sacrificial layers, so that the thickness of each sub-sacrificial layer is small, and the corresponding damage to the second sacrificial layer along the longitudinal direction is only based on the thickness of the sub-sacrificial layer, which is beneficial to reducing the damage to the second sacrificial layer along the longitudinal direction when the exposed second sacrificial layer is removed along the first groove, and is beneficial to increasing the size of the remaining second sacrificial layer between the longitudinally adjacent conductive plate structures. Correspondingly, it is beneficial to reduce the probability of peeling at the contact position between the dielectric layer and the second sacrificial layer when the exposed second sacrificial layer is removed along the first groove, and further helps to reduce the probability of leakage between the longitudinally adjacent conductive plate structures, thereby ensuring the working performance of the semiconductor structure.

[0025] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0026] Figures 9 to 16 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0027] refer to Figure 9 , providing a substrate 100, on which a laminated structure 200 is formed, the laminated structure 200 including a longitudinal direction (such as Figure 9 The dielectric layers 210 and the first sacrificial layers 220 are alternately stacked from bottom to top (as shown in the Z direction).

[0028] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure of the present invention.

[0029] In this embodiment, the substrate 100 is a semiconductor substrate. For example, the substrate 100 may include other semiconductor structures. The material of the film layer in contact with the substrate 100 and the stacked structure 200 includes silicon oxide or silicon nitride. As an example, in this embodiment, the material of the film layer in contact with the substrate 100 and the stacked structure 200 is silicon oxide.

[0030] The stacked structure 200 is used to subsequently form a conductive pillar structure and a conductive plate structure.

[0031] It should be noted that, in this embodiment, the bottom layer and the top layer of the stacked structure 200 are both dielectric layers 210 .

[0032] Specifically, the first sacrificial layer 220 is used to occupy a space for the subsequent formation of a conductive plate structure.

[0033] In this embodiment, the material of the first sacrificial layer 220 includes silicon nitride.

[0034] In this embodiment, the thickness of the first sacrificial layer 220 is 10 nm to 200 nm, which provides sufficient space for the subsequent formation of the conductive plate structure, while ensuring that the space occupied by the semiconductor structure is not too large, thereby improving the integration of the semiconductor structure.

[0035] The dielectric layer 210 is used to subsequently isolate longitudinally adjacent conductive plate structures.

[0036] In this embodiment, the material of the dielectric layer 210 includes silicon oxide.

[0037] Using silicon nitride to form the first sacrificial layer 220 and using silicon oxide to form the dielectric layer 210 is advantageous in that during the subsequent wet etching process to remove the first sacrificial layer 220 , the etching solution causes minimal or almost no damage to the dielectric layer 210 .

[0038] In this embodiment, the dielectric layer 210 has a thickness of 10 nm to 100 nm, so that the dielectric layer 210 has a better isolation effect and the space occupied by the semiconductor structure is not too large, thereby improving the integration of the semiconductor structure.

[0039] In this embodiment, in the step of providing the substrate 100 , a conductive block structure 110 is formed in the substrate 100 , and the conductive block structure 110 is exposed on the top surface of the substrate 100 .

[0040] The conductive block structure 110 is used for subsequent electrical connection with the conductive pillar structure.

[0041] refer to Figure 10 , forming a plurality of through holes 230 penetrating the stacked structure 200 .

[0042] The through hole 230 is used to provide a space for the subsequent formation of a conductive pillar structure.

[0043] Accordingly, in this embodiment, in the step of forming a through hole 230 penetrating the stacked structure 200 using a dry etching process, the through hole 230 exposes the conductive block structure 110, so that the conductive column structure subsequently formed in the through hole 230 contacts the conductive block structure 110 for electrical connection.

[0044] In this embodiment, through-hole 230 is used to form a conductive pillar structure. The opening size of through-hole 230 is between 10 nm and 80 nm. The smaller the size of through-hole 230, the more difficult the process of forming through-hole 230 becomes. However, the smaller the size of through-hole 230, the more conducive it is to achieving a higher integration density of the semiconductor structure. It should be understood that due to the limitations of existing photolithography equipment, the size of through-hole 230 cannot be further reduced. If a smaller conductive pillar structure is required, other methods must be used to further reduce the size of through-hole 230.

[0045] Combined with reference Figure 11 and Figure 12 , forming a second sacrificial layer 300 covering the sidewalls of the through hole 230, the second sacrificial layer 300 includes a Figure 12 A plurality of sacrificial sub-layers 330 are stacked (as shown in the X direction).

[0046] After the conductive column structure is subsequently formed in the through hole 230, when the first sacrificial layer 220 is removed, the second sacrificial layer 300 is used to protect the side wall of the conductive column structure. Moreover, in order to completely remove the first sacrificial layer 220, it is usually necessary to increase the excessive etching time, so that the second sacrificial layer 300 can better protect the conductive column structure during this etching process.

[0047] In this embodiment, the second sacrificial layer 300 includes a plurality of sub-sacrificial layers 330 stacked in a transverse direction. That is, the plurality of sub-sacrificial layers 330 are stacked and sequentially covered by the sidewalls of the through-hole 230 .

[0048] It should be noted that this embodiment is described by taking the second sacrificial layer 300 including two sub-sacrificial layers 330 stacked in the transverse direction as an example. In other embodiments, the number of sub-sacrificial layers in the second sacrificial layer is not limited.

[0049] In this embodiment, the second sacrificial layer 300 is composed of a plurality of stacked sub-sacrificial layers 330. In the subsequent step of removing the exposed second sacrificial layer 300 along the first groove, the plurality of sub-sacrificial layers 330 are removed in sequence along the transverse direction. When any sub-sacrificial layer 330 is removed, the damage to the corresponding sub-sacrificial layer 330 along the longitudinal direction depends on the thickness of the current sub-sacrificial layer 330, and the impact on other sub-sacrificial layers 330 is small. Therefore, after the plurality of sub-sacrificial layers 330 are removed, the damage to each sub-sacrificial layer 330 along the longitudinal direction is still small, so that after the exposed second sacrificial layer 300 is removed along the first groove, the second sacrificial layer 300 is removed. 00 has smaller damage in the longitudinal direction as a whole. Compared with the solution in which the second sacrificial layer is a single film layer as a whole, when the second sacrificial layer is removed along the first groove, the damage in the longitudinal direction of the second sacrificial layer depends on the thickness of the entire second sacrificial layer, and the damage is larger. In this solution, the total thickness of the second sacrificial layer 300 is divided into the thicknesses of multiple sub-sacrificial layers 330, so that the thickness of each sub-sacrificial layer 330 is smaller, and the corresponding damage in the longitudinal direction of the second sacrificial layer 300 is only based on the thickness of the sub-sacrificial layer 330, which is beneficial to reduce the damage in the longitudinal direction of the second sacrificial layer 300 when the exposed second sacrificial layer 300 is removed along the first groove.

[0050] In this embodiment, adjacent sub-sacrificial layers 330 are made of different materials.

[0051] The materials of adjacent sub-sacrificial layers 330 are different, so that when multiple sub-sacrificial layers 330 are subsequently removed, it is easy to form an etching selectivity ratio between adjacent sub-sacrificial layers 330. Therefore, when etching any sub-sacrificial layer 330, the damage to the adjacent sub-sacrificial layers 330 is small or almost no damage.

[0052] Specifically, in this embodiment, the materials of the multiple sacrificial sub-layers 330 are all different.

[0053] The materials of the multiple sub-sacrificial layers 330 are all different, so when any sub-sacrificial layer 330 is subsequently removed, the impact on all other sub-sacrificial layers 330 is relatively small, so that when any sub-sacrificial layer 330 is removed, the damage to all other sub-sacrificial layers 330 along the longitudinal direction is relatively small, so that after the multiple sub-sacrificial layers 330 are removed, the damage to each sub-sacrificial layer 330 along the longitudinal direction is still relatively small, thereby keeping the overall damage to the second sacrificial layer 300 along the longitudinal direction small or almost undamaged.

[0054] In this embodiment, the material of the sub-sacrificial layer 330 is selected from any one of silicon oxide, amorphous silicon, silicon nitride and titanium nitride.

[0055] The sub-sacrificial layers 330 formed of a material selected from silicon oxide, amorphous silicon, silicon nitride and titanium nitride are easy to form a large etching selectivity ratio with each other in the subsequent etching process, thereby reducing damage to other sub-sacrificial layers 330 when etching any sub-sacrificial layer 330.

[0056] In this embodiment, the thickness of each sub-sacrificial layer 330 is 1 nm to 25 nm.

[0057] The thickness of each sub-sacrificial layer 330 is 1 nm to 25 nm, which simplifies the formation process of each sub-sacrificial layer 330 and ensures the subsequent protection of the conductive pillar structure by the second sacrificial layer 300 composed of multiple sub-sacrificial layers 330.

[0058] Specifically, refer to Figure 11 The step of forming the second sacrificial layer 300 covering the sidewalls of the through hole 230 includes forming a plurality of sub-sacrificial material layers 310 stacked sequentially to cover the sidewalls and bottom of the through hole 230 and the top of the stacked structure 200 .

[0059] The sub-sacrificial material layer 310 is used to form a sub-sacrificial layer 330 .

[0060] In this embodiment, the sub-sacrificial material layer 310 is formed by an atomic layer deposition process or a furnace process.

[0061] The atomic layer deposition process or the furnace tube process can easily form stacked film layers, thereby easily forming a plurality of sub-sacrificial material layers 310 with good film quality.

[0062] Continue to refer Figure 11 Before subsequently removing the multiple sub-sacrificial material layers 310 at the bottom of the through hole 230 and the top of the stacked structure 200 , the method further includes: forming a protective material layer 320 covering the multiple sub-sacrificial material layers 310 .

[0063] The protective material layer 320 is used to form a protective layer later.

[0064] In this embodiment, the material of the protective material layer 320 includes silicon nitride.

[0065] In this embodiment, in the step of forming the protective material layer 320 covering the multiple sub-sacrificial material layers 310 , the thickness of the protective material layer 320 is less than or equal to the thickness of any sub-sacrificial material layer 310 , and the thickness of the protective material layer 320 is preferably 2 nm to 15 nm.

[0066] The subsequent protective material layer 320 forms a protective layer. After etching multiple sub-sacrificial layers 330, the protective layer will continue to be etched. When etching the protective layer, the damage to the protective layer in the longitudinal direction depends on the thickness of the protective layer. The thickness of the protective material layer 320 is less than or equal to the thickness of any layer of sub-sacrificial material layer 310, that is, the thickness of the protective layer is less than or equal to the thickness of any layer of sub-sacrificial material layer 310, then the damage to the protective layer in the longitudinal direction remains small, thereby ensuring that the overall damage along the longitudinal direction of the protective layer and the second sacrificial layer 300 remains small. Moreover, when etching the protective layer, the etched second sacrificial layer 300 is exposed to the etching environment, then the thickness of the protective layer is less than or equal to the thickness of any layer of sub-sacrificial material layer 310, so that the etching time of the protective layer is shorter, which is beneficial to reducing the damage of the second sacrificial layer 300 exposed to the etching environment.

[0067] refer to Figure 12 , remove the multiple sub-sacrificial material layers 310 at the bottom of the through hole 230 and the top of the stacked structure 200, and retain the multiple sub-sacrificial material layers 310 covering the sidewalls of the through hole 230 as multiple sub-sacrificial layers 330 to form the second sacrificial layer 300.

[0068] The multiple sub-sacrificial material layers 310 at the bottom of the through hole 230 and the top of the stacked structure 200 are removed to expose the conductive block structure 110 in preparation for the subsequent formation of the conductive pillar structure.

[0069] Continue to refer Figure 12 The step of removing the multiple sub-sacrificial material layers 310 at the bottom of the through hole 230 and the top of the stacked structure 200 also includes: removing the protective material layer 320 at the bottom of the through hole 230 and the top of the stacked structure 200, and retaining the protective material layer 320 of the multiple sub-sacrificial material layers 310 covering the side walls of the through hole 230 as a protective layer 340.

[0070] The protective layer 340 is used to protect the sub-sacrificial material layer 310 on the side wall of the through hole 230 during the process of removing the multiple sub-sacrificial material layers 310 at the bottom of the through hole 230 and the top of the stacked structure 200, so as to reduce damage to the sacrificial layer 330 on the side wall of the sub-through hole 230 and avoid the formation of pinhole defects (pin holes) in the side wall sacrificial layer 330. The protective layer 340 is also used to protect the conductive column structure together with the second sacrificial layer 300 when the first sacrificial layer 220 is subsequently removed.

[0071] refer to Figure 13 , forming a conductive pillar structure 400 that fills the through hole 230 and covers the second sacrificial layer 300 .

[0072] The conductive pillar structure 400 is used as a conductive pillar in a 3D memory.

[0073] Accordingly, in this embodiment, in the step of forming the conductive pillar structure 400 filling the through hole 230 and covering the second sacrificial layer 300 , the conductive pillar structure 400 is in contact with the conductive block structure 110 to be electrically connected.

[0074] Specifically, in this embodiment, the conductive column structure 400 includes a lower electrode covering the sidewalls and bottom of the through hole 230, and a lower conductive line filling the through hole 230 and covering the lower electrode. The lower electrode and the lower conductive line subsequently form a capacitor structure with the upper electrode and the upper conductive line.

[0075] It should be noted that, in this embodiment, the outer diameter of the conductive column structure 400 is regulated by controlling the thickness of the second sacrificial layer 300 and the protective layer 340. Thus, when the size of the through hole 230 reaches the limit of the device, the second sacrificial layer 300 and the protective layer 340 can be formed to occupy part of the space to achieve shrinkage, thereby forming a smaller conductive column structure 400.

[0076] It should also be noted that in this embodiment, the protective layer 340 covering the second sacrificial layer 300 is retained. Compared with the solution of removing the protective layer, this solution makes the bottom size and the top size of the conductive column structure 400 only a fixed difference in the process, and will not further reduce the bottom size of the conductive column structure 400 due to the morphology of the bottom corner of the second sacrificial layer 300. Then, while keeping the top size of the conductive column structure 400 unchanged, this embodiment can make the bottom size of the conductive column structure 400 larger while ensuring the working performance of the conductive column structure 400, which is beneficial to reduce the contact resistance between the conductive column structure 400 and the conductive block structure 110.

[0077] refer to Figure 14 , all the first sacrificial layers 220 in the stacked structure 200 are removed to form a plurality of first trenches 510 that are arranged at intervals in the longitudinal direction and surrounded by the longitudinally adjacent dielectric layers 210 .

[0078] The first trench 510 is used to provide a space for the subsequent formation of a conductive plate structure.

[0079] In this embodiment, a wet etching process is used to remove all of the first sacrificial layer 220 in the stacked structure 200. It should be understood that the wet etching process is used to remove the first sacrificial layer 220, and before the wet etching process, at least one opening is formed through the stacked structure 200, allowing the etching solution to etch and remove the first sacrificial layer 220 through this opening.

[0080] The wet etching process has the characteristic of isotropic etching, which is conducive to completely removing all the first sacrificial layers 220 . The wet etching process can easily achieve a large etching selectivity, thereby reducing damage to other film layers when removing the first sacrificial layer 220 .

[0081] It should be noted that, in the present embodiment, in the step of removing all the first sacrificial layers 220 in the stacked structure 200, the sidewalls of the conductive pillar structure 400 are covered with a plurality of sub-sacrificial layers 330 and a protective layer 340, and the pinhole gaps that may exist in each sub-sacrificial layer 330 and protective layer 340 are randomly distributed. The probability of the pinhole gaps in the plurality of sub-sacrificial layers 330 and protective layers 340 being aligned is low, which is beneficial to reducing the probability of the etching solution entering through the pinhole gaps and contacting the conductive pillar structure 400, reducing damage to the conductive pillar structure 400, and thereby ensuring the performance of the conductive pillar structure 400.

[0082] refer to Figure 15 , Figure 15 (b) in the Figure 15 In the partially enlarged schematic diagram at the position of the dotted box in (a), the exposed portion of the second sacrificial layer 300 is removed along each first trench 510 to form a second trench 520 exposing a portion of the sidewall of the conductive column structure 400. The second trench 520 is connected to the first trench 510 to form a third trench 530.

[0083] The second trench 520 is connected to the first trench 510 to form a third trench 530 , which is used to provide a spatial location for the subsequent formation of a conductive plate structure.

[0084] In this embodiment, in the step of removing the exposed second sacrificial layer 300 along the first groove 510, multiple sub-sacrificial layers 330 are removed in sequence along the horizontal direction. When any sub-sacrificial layer 330 is removed, the damage to the corresponding sub-sacrificial layer 330 along the longitudinal direction depends on the thickness of the current sub-sacrificial layer 330, and the impact on other sub-sacrificial layers 330 is relatively small, so that after the multiple sub-sacrificial layers 330 are removed, the damage to each sub-sacrificial layer 330 along the longitudinal direction is still relatively small, so that after the exposed second sacrificial layer 300 is removed along the first groove, the damage to the second sacrificial layer 300 as a whole along the longitudinal direction is relatively small. Compared with the solution in which the second sacrificial layer is a single film layer as a whole, when the second sacrificial layer is removed along the first groove, the damage to the second sacrificial layer along the longitudinal direction depends on the thickness of the entire second sacrificial layer, and the damage is relatively large. In this solution, the second sacrificial layer The total thickness of the layer 300 is divided into the thicknesses of multiple sub-sacrificial layers 330, so that the thickness of each sub-sacrificial layer 330 is relatively small. Accordingly, the damage to the second sacrificial layer 300 along the longitudinal direction is only based on the thickness of the sub-sacrificial layer 330, which is beneficial for reducing the damage to the second sacrificial layer 300 along the longitudinal direction when the exposed second sacrificial layer 300 is removed along the first groove, and is beneficial for increasing the size of the second sacrificial layer 300 remaining between the conductive plate structures longitudinally adjacent to the third groove 530 formed subsequently. Correspondingly, it is beneficial for reducing the probability of peeling at the contact position between the dielectric layer 210 and the second sacrificial layer 300 when the exposed second sacrificial layer 300 is removed along the first groove 510, and further beneficial for reducing the probability of leakage between the conductive plate structures adjacent to the longitudinal direction, thereby ensuring the working performance of the semiconductor structure.

[0085] It should be noted that Figure 15 The morphology of the second sacrificial layer 300 in (b) is not limited to Figure 15 At the dotted box position in (a), Figure 15 The longitudinal morphology of each second sacrificial layer 300 in (a) can be Figure 15 (b) in the.

[0086] In this embodiment, in the step of removing the exposed portion of the second sacrificial layer 300 along each first groove 510, each sub-sacrificial layer 330 has an etching selectivity ratio with other sub-sacrificial layers 330, so that when any sub-sacrificial layer 330 is removed, damage to other sub-sacrificial layers 330 is reduced.

[0087] As an example, in this embodiment, in the step of removing the exposed portion of the second sacrificial layer 300 along each first trench 510 , the etching selectivity is greater than or equal to 20.

[0088] In this embodiment, a wet etching process is used to remove the exposed portion of the second sacrificial layer 300 along each first trench 510 . The process includes: using the wet etching process to remove the exposed portion of each sub-sacrificial layer 330 layer by layer.

[0089] The wet etching process can easily achieve a large etching selectivity ratio, thereby reducing damage to other sub-sacrificial layers 330 when removing the exposed portions of each sub-sacrificial layer 330 in sequence.

[0090] In this embodiment, the step of removing the exposed second sacrificial layer 300 along the first trench 510 to form the second trench 520 exposing a portion of the sidewall of the conductive pillar structure 400 further includes: removing the exposed portion of the protection layer 340 along the first trench 510 .

[0091] The exposed portion of the protection layer 340 is removed along the first trench 510 to expose the sidewall of the conductive pillar structure 400 .

[0092] Accordingly, in this embodiment, after the exposed portions of the sub-sacrificial layers 330 are removed layer by layer using a wet etching process, the exposed portions of the protective layer 340 are further removed using a wet etching process.

[0093] refer to Figure 16 , Figure 16 (b) in the Figure 16 In (a), a partially enlarged schematic diagram of the dotted box position is shown, forming a dielectric layer 600 covering the side surfaces and bottom surface of the third trench 530; and forming a conductive plate structure 500 filling the third trench 530 and covering the dielectric layer 600.

[0094] The conductive plate structure 500 is used as a conductive plate in a 3D memory, and the dielectric layer 600 is used as a storage capacitor material in the memory.

[0095] In this embodiment, the conductive plate structure 500 includes an upper electrode covering the dielectric layer 600 and an upper conductive line filling the third trench 530 and covering the upper electrode. The upper electrode and the upper conductive line together with the dielectric layer, the lower electrode and the lower conductive line form a capacitor structure.

[0096] Specifically, the surface distribution of the conductive plate structure 500 and the conductive column structure 400 is upper electrode-storage capacitor material-lower electrode, that is, the capacitor layer. The upper electrode is connected to the upper wire in the conductive plate structure 500, and the lower electrode is connected to the lower wire in the conductive column structure 400.

[0097] It should be noted that Figure 16 The morphology of the surface where the conductive plate structure 500 and the conductive pillar structure 400 meet in (b) is not limited to Figure 16 At the dotted box position in (a), Figure 16 The morphology of the surface where each conductive plate structure 500 and the conductive column structure 400 are connected can be Figure 16 (b) in the.

[0098] Figure 17 It is a structural schematic diagram corresponding to an embodiment of the semiconductor structure of the present invention.

[0099] refer to Figure 17 , Figure 17 (b) in the Figure 17 In the partially enlarged schematic diagram of the dotted line frame in (a), the semiconductor structure includes: a substrate 100; a conductive stack 201 located on the substrate 100, and the conductive stack 201 includes a longitudinal direction (such as Figure 17 The dielectric layers 210 and the conductive plate structures 500 are alternately stacked from bottom to top (as shown in the Z direction); a plurality of conductive pillar structures 400, the conductive pillar structures 400 penetrate the conductive stack 201; a plurality of dielectric layers 600 arranged at intervals in the longitudinal direction, the dielectric layers 600 cover the respective surfaces of the corresponding conductive plate structures 500, and are located between the conductive plate structures 500 and the conductive pillar structures 400; a plurality of second sacrificial layers 300 arranged at intervals in the longitudinal direction, the second sacrificial layers 300 cover part of the sidewalls of the conductive pillar structures 400, and are located between the corresponding dielectric layers 210 and the conductive pillar structures 400, the second sacrificial layers 300 include a plurality of conductive pillar structures 400 arranged at intervals in the longitudinal direction, the second sacrificial layers 300 cover part of the sidewalls of the conductive pillar structures 400, and are located between the corresponding dielectric layers 210 and the conductive pillar structures 400, and ... Figure 17 A plurality of sacrificial sub-layers 330 are stacked (as shown in the X direction).

[0100] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure of the present invention.

[0101] In this embodiment, the substrate 100 is a semiconductor substrate. For example, the substrate 100 may include other semiconductor structures. The material of the film layer in contact with the substrate 100 and the stacked structure 200 includes silicon oxide or silicon nitride. As an example, in this embodiment, the material of the film layer in contact with the substrate 100 and the stacked structure 200 is silicon oxide.

[0102] The conductive stack 201 is used to form a plurality of conductive plate structures 500 spaced apart in the longitudinal direction.

[0103] The conductive plate structure 500 is used as a conductive plate in a 3D memory.

[0104] In this embodiment, the conductive plate structure 500 includes an upper electrode covering the dielectric layer 600 , and an upper conductive line filled between longitudinally adjacent dielectric layers 210 and covering the upper electrode.

[0105] The dielectric layer 210 is used to isolate longitudinally adjacent conductive plate structures 500 .

[0106] In this embodiment, the material of the dielectric layer 210 includes silicon oxide.

[0107] In this embodiment, the dielectric layer 210 has a thickness of 10 nm to 100 nm, so that the dielectric layer 210 has a better isolation effect and the space occupied by the semiconductor structure is not too large, thereby improving the integration of the semiconductor structure.

[0108] It should be noted that, in this embodiment, the bottommost layer and the topmost layer of the conductive stack 201 are both the dielectric layer 210 .

[0109] In this embodiment, a conductive block structure 110 is formed in the substrate 100 , and the conductive block structure 110 is exposed on the top surface of the substrate 100 .

[0110] The conductive block structure 110 is used to be electrically connected to the conductive pillar structure 400 .

[0111] The conductive pillar structure 400 is used as a conductive pillar in a 3D memory.

[0112] In this embodiment, the conductive pillar structure 400 includes a lower conductive line penetrating the conductive stack 201 and a lower electrode covering the sidewall and bottom of the lower conductive line. The lower electrode and the lower conductive line form a capacitor structure together with the dielectric layer, the upper electrode and the upper conductive line.

[0113] It should be noted that, in this embodiment, the outer diameter of the conductive column structure 400 is regulated by controlling the thickness of the second sacrificial layer 300 and the protective layer 340. Thus, when the size of the through hole used to form the conductive column structure 400 reaches the limit of the equipment, the second sacrificial layer 300 and the protective layer 340 can be formed to occupy part of the space to achieve shrinkage, thereby forming a smaller conductive column structure 400.

[0114] Accordingly, in this embodiment, the conductive pillar structure 400 penetrates the conductive stack 201 and contacts the conductive block structure 110 to be electrically connected.

[0115] The dielectric layer 600 is used as a storage capacitor material in the memory.

[0116] Specifically, the surface distribution of the conductive plate structure 500 and the conductive column structure 400 is upper electrode-storage capacitor material-lower electrode, that is, the capacitor layer. The upper electrode is connected to the upper wire in the conductive plate structure 500, and the lower electrode is connected to the lower wire in the conductive column structure 400.

[0117] In the semiconductor manufacturing process, a stacked structure in which a dielectric layer 210 and a first sacrificial layer are alternately stacked is first formed, and then a conductive pillar structure 400 is formed that penetrates the stacked structure. At this time, the second sacrificial layer covers the sidewalls of the conductive pillar structure 400. The first sacrificial layer is then removed to expose the second sacrificial layer 300. Subsequently, a portion of the second sacrificial layer 300 is removed, leaving the second sacrificial layer 300 between the dielectric layer 210 and the conductive pillar structure 400. Finally, a conductive plate structure 500 is formed at the original location of the first sacrificial layer. To this end, when the first sacrificial layer is removed, the second sacrificial layer 300 is used to protect the sidewalls of the conductive pillar structure 400. Moreover, in order to completely remove the first sacrificial layer, it is usually necessary to increase the etching time excessively, so that the second sacrificial layer 300 can better protect the conductive pillar structure 400 during this etching process.

[0118] In this embodiment, the second sacrificial layer 300 includes a plurality of sub-sacrificial layers 330 stacked in a transverse direction. That is, the plurality of sub-sacrificial layers 330 are sequentially covered and stacked by the sidewalls of the conductive pillar structure 400 .

[0119] It should be noted that this embodiment is described by taking the second sacrificial layer 300 including two sub-sacrificial layers 330 stacked in the transverse direction as an example. In other embodiments, the number of sub-sacrificial layers in the second sacrificial layer is not limited.

[0120] In this embodiment, the second sacrificial layer 300 is composed of a plurality of stacked sub-sacrificial layers 330. When the first sacrificial layer is removed to expose the second sacrificial layer 300, the plurality of sub-sacrificial layers 330 are removed in sequence along the transverse direction. When any sub-sacrificial layer 330 is removed, the damage to the corresponding sub-sacrificial layer 330 along the longitudinal direction depends on the thickness of the current sub-sacrificial layer 330, and the impact on other sub-sacrificial layers 330 is relatively small. Therefore, after the plurality of sub-sacrificial layers 330 are removed, the damage to each sub-sacrificial layer 330 along the longitudinal direction is still relatively small. Therefore, when the first sacrificial layer is removed to expose the second sacrificial layer 300, the damage to the second sacrificial layer 300 as a whole along the longitudinal direction is relatively small. Compared with the solution in which the second sacrificial layer as a whole is a single film layer, when the second sacrificial layer is removed, the damage to the second sacrificial layer along the longitudinal direction depends on the thickness of the entire second sacrificial layer. The damage is large, while in this solution, the total thickness of the second sacrificial layer 300 is divided into the thicknesses of multiple sub-sacrificial layers 330, so that the thickness of each sub-sacrificial layer 330 is small, and the damage of the corresponding second sacrificial layer 300 along the longitudinal direction is only based on the thickness of the sub-sacrificial layer 330, which is beneficial to reducing the damage of the second sacrificial layer 300 along the longitudinal direction when removing the exposed second sacrificial layer 300, and is beneficial to increasing the size of the remaining second sacrificial layer 300 between the longitudinally adjacent conductive plate structures 500. Correspondingly, it is beneficial to reduce the probability of peeling at the contact position between the dielectric layer 210 and the second sacrificial layer 300 when removing the exposed second sacrificial layer 300, and further beneficial to reducing the probability of leakage between the longitudinally adjacent conductive plate structures 500, thereby ensuring the working performance of the semiconductor structure.

[0121] It should be noted that, in this embodiment, when the first sacrificial layer is removed, the side walls of the conductive column structure 400 are covered with multiple sub-sacrificial layers 330 and protective layers 340. The pinhole gaps that may exist in each sub-sacrificial layer 330 and protective layer 340 are randomly distributed, and the probability of the pinhole gaps in the multiple sub-sacrificial layers 330 and protective layers 340 being aligned is low, which is beneficial to reducing the probability of the etching solution entering the conductive column structure 400 through the pinhole gaps and contacting the conductive column structure 400, reducing damage to the conductive column structure 400, and thereby ensuring the performance of the conductive column structure 400.

[0122] In this embodiment, adjacent sub-sacrificial layers 330 are made of different materials.

[0123] Adjacent sub-sacrificial layers 330 are made of different materials, so that when removing multiple sub-sacrificial layers 330 , it is easy to form an etching selectivity ratio between adjacent sub-sacrificial layers 330 , so when etching any sub-sacrificial layer 330 , the adjacent sub-sacrificial layers 330 are less damaged.

[0124] Specifically, in this embodiment, the materials of the multiple sacrificial sub-layers 330 are all different.

[0125] The materials of the multiple sub-sacrificial layers 330 are all different. Therefore, when any sub-sacrificial layer 330 is removed, the impact on all other sub-sacrificial layers 330 is relatively small. Therefore, when any sub-sacrificial layer 330 is removed, the damage to all other sub-sacrificial layers 330 along the longitudinal direction is relatively small. After the multiple sub-sacrificial layers 330 are removed, the damage to each sub-sacrificial layer 330 along the longitudinal direction is still relatively small, thereby keeping the overall damage to the second sacrificial layer 300 along the longitudinal direction relatively small.

[0126] In this embodiment, the material of the sub-sacrificial layer 330 is selected from any one of silicon oxide, amorphous silicon, silicon nitride and titanium nitride.

[0127] The sub-sacrificial layers 330 formed of a material selected from silicon oxide, amorphous silicon, silicon nitride and titanium nitride are easy to form a large etching selectivity ratio with each other in the subsequent etching process, thereby reducing damage to other sub-sacrificial layers 330 when etching any sub-sacrificial layer 330.

[0128] In this embodiment, the thickness of each sub-sacrificial layer 330 is 1 nm to 25 nm.

[0129] The thickness of each sub-sacrificial layer 330 is 1 nm to 25 nm, which makes the formation process of each sub-sacrificial layer 330 relatively simple, while ensuring the protection of the second sacrificial layer 300 composed of multiple sub-sacrificial layers 330 on the conductive pillar structure.

[0130] In this embodiment, a protection layer 340 is further formed between the second sacrificial layer 300 and the conductive pillar structure 400 .

[0131] The protection layer 340 is used to protect the sub-sacrificial layer 330 on the sidewall of the conductive pillar structure 400 during the process of patterning the second sacrificial layer 300 . The protection layer 340 is also used to protect the conductive pillar structure 400 together with the second sacrificial layer 300 when the first sacrificial layer is removed.

[0132] In this embodiment, the thickness of the protection layer 340 is less than or equal to the thickness of any sub-sacrificial layer 330 , and the thickness of the protection material layer 320 is preferably 2 nm to 15 nm.

[0133] In the semiconductor manufacturing process, after etching multiple sub-sacrificial layers 330, the protective layer 340 will continue to be etched. When etching the protective layer 340, the damage to the protective layer 340 in the longitudinal direction depends on the thickness of the protective layer 340. If the thickness of the protective layer 340 is less than or equal to the thickness of any layer of the sub-sacrificial layer 330, the damage to the protective layer 340 in the longitudinal direction remains small, thereby ensuring that the damage to the overall structure formed by the protective layer 340 and the second sacrificial layer 300 in the longitudinal direction remains small. Moreover, when etching the protective layer 340, the etched second sacrificial layer 300 is exposed to the etching environment, and the thickness of the protective layer is less than or equal to the thickness of any layer of the sub-sacrificial layer 330, so that the etching time of the protective layer 340 is shorter, which is beneficial to reducing the damage to the second sacrificial layer 300 exposed to the etching environment.

[0134] In this embodiment, the material of the protective material layer 320 includes silicon nitride.

[0135] It should be noted that, in this embodiment, the protective layer 340 covering the second sacrificial layer 300 is retained. Compared with the solution of removing the protective layer, this solution makes the bottom size and the top size of the conductive column structure 400 only a fixed difference in the process, and will not further reduce the bottom size of the conductive column structure 400 due to the morphology of the bottom corner of the second sacrificial layer 300. Therefore, while keeping the top size of the conductive column structure 400 unchanged, this embodiment can make the bottom size of the conductive column structure 400 larger while ensuring the working performance of the conductive column structure 400, which is beneficial to reduce the contact resistance between the conductive column structure 400 and the conductive block structure 110.

[0136] It should also be noted that Figure 17 The morphology of the surface where the conductive plate structure 500 and the conductive pillar structure 400 meet in (b) is not limited to Figure 17 At the dotted box position in (a), Figure 17 The morphology of the surface where each conductive plate structure 500 and the conductive column structure 400 are connected can be Figure 17 (b) in the.

[0137] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, on which a stacked structure is formed, the stacked structure comprising dielectric layers and first sacrificial layers alternately stacked from bottom to top along a longitudinal direction; forming a plurality of through holes penetrating the laminate structure; forming a second sacrificial layer covering the sidewall of the through hole, wherein the second sacrificial layer comprises a plurality of sub-sacrificial layers stacked in a transverse direction; forming a conductive pillar structure filling the through hole and covering the second sacrificial layer; removing all the first sacrificial layers in the stacked structure to form a plurality of first trenches surrounded by longitudinally adjacent dielectric layers and arranged at intervals in the longitudinal direction; removing the exposed portion of the second sacrificial layer along each of the first trenches to form a second trench exposing a portion of the sidewall of the conductive pillar structure, wherein the second trench is connected to the first trench to form a third trench; forming a dielectric layer covering the side surfaces and bottom surface of the third trench; A conductive plate structure is formed to fill the third trench and cover the dielectric layer.

2. The forming method according to claim 1, wherein: A wet etching process is used to remove all the first sacrificial layers in the stacked structure.

3. The forming method according to claim 1, wherein: A wet etching process is used to remove the exposed portion of the second sacrificial layer along each of the first trenches. The process includes: using the wet etching process to remove the exposed portion of each sub-sacrificial layer layer by layer.

4. The forming method according to claim 3, wherein: The adjacent sub-sacrificial layers are made of different materials.

5. The forming method according to claim 4, wherein: The material of the sub-sacrificial layer is selected from any one of silicon oxide, amorphous silicon, silicon nitride and titanium nitride.

6. The forming method according to claim 5, wherein: The thickness of each of the sub-sacrificial layers is 1 nm to 25 nm.

7. The forming method according to claim 1, wherein: The step of forming a second sacrificial layer covering the sidewalls of the through hole comprises: forming a plurality of sub-sacrificial material layers stacked in sequence and covering the sidewalls and bottom of the through hole and the top of the stacked structure; The multiple sub-sacrificial material layers at the bottom of the through hole and the top of the stacked structure are removed, and the multiple sub-sacrificial material layers covering the sidewalls of the through hole are retained as the multiple sub-sacrificial layers to constitute the second sacrificial layer.

8. The forming method according to claim 7, wherein: The sub-sacrificial material layer is formed by adopting an atomic layer deposition process or a furnace tube process.

9. The forming method according to claim 7, wherein: Before removing the plurality of sub-sacrificial material layers at the bottom of the through hole and the top of the stacked structure, the method further includes: forming a protective material layer covering the plurality of sub-sacrificial material layers; The step of removing the plurality of sub-sacrificial material layers at the bottom of the through hole and the top of the stacked structure further includes: removing the protective material layer at the bottom of the through hole and the top of the stacked structure, and retaining the protective material layer of the plurality of sub-sacrificial material layers covering the sidewalls of the through hole as a protective layer; The step of removing the exposed second sacrificial layer along the first trench to form a second trench exposing a portion of the sidewall of the conductive pillar structure further includes: removing the exposed portion of the protective layer along the first trench.

10. The forming method according to claim 1, wherein: In the step of providing the substrate, a conductive block structure is formed in the substrate, and the conductive block structure is exposed on the top surface of the substrate; In the step of forming a through hole penetrating the stacked structure, the through hole exposes the conductive block structure.

11. A semiconductor structure, characterized in that include: substrate; A conductive stack is located on the substrate, the conductive stack comprising dielectric layers and conductive plate structures alternately stacked in a longitudinal direction from bottom to top; a plurality of conductive pillar structures, wherein the conductive pillar structures penetrate the conductive stack; a plurality of dielectric layers arranged at intervals in the longitudinal direction, the dielectric layers covering respective surfaces of the corresponding conductive plate structures and being located between the conductive plate structures and the conductive pillar structures; A plurality of second sacrificial layers are arranged at intervals in the longitudinal direction, the second sacrificial layers cover part of the sidewalls of the conductive pillar structure and are located between the corresponding dielectric layer and the conductive pillar structure, and the second sacrificial layers include a plurality of sub-sacrificial layers stacked in the transverse direction.

12. The semiconductor structure according to claim 11, wherein The adjacent sub-sacrificial layers are made of different materials, and the material of the sub-sacrificial layers is selected from any one of silicon oxide, amorphous silicon, silicon nitride and titanium nitride.

13. The semiconductor structure according to claim 12, wherein: The thickness of each of the sub-sacrificial layers is 1 nm to 25 nm.

14. The semiconductor structure according to claim 11, wherein: A protective layer is further formed between the second sacrificial layer and the conductive pillar structure.

15. The semiconductor structure according to claim 11, wherein A conductive block structure is further formed in the substrate, and the conductive block structure is exposed on the top surface of the substrate; The conductive pillar structure penetrates the conductive stack and contacts and electrically connects to the conductive block structure.

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