Package substrate and manufacturing method thereof

Abstract

The invention provides a package substrate and a manufacturing method thereof. A layer-adding structure is formed on wiring layers on two opposite sides of a glass plate body, the glass plate body is used as a core layer, and the characteristics of high rigidity, low thermal expansion coefficient and the like of the glass plate body are utilized, so that the packaging substrate can be effectively prevented from being bent in a large-size specification process.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging process, and more particularly to a packaging substrate capable of improving product reliability and a manufacturing method thereof. Background Art

[0002] With the vigorous development of the electronics industry, electronic products tend to be thinner, lighter, shorter and smaller in form, and in terms of function, they are developed towards high performance, high functionality and high speed. Therefore, in order to meet the requirements of high integration and miniaturization of semiconductor devices, in the packaging process, packaging substrates with high density and fine pitch lines are often used.

[0003] The currently commonly used carrier is a resin-made packaging substrate on which double-sided circuit layers are fabricated. As Figure 1 shown, the existing packaging substrate 1 includes: a core layer 10 made of an organic material such as bismaleimide triazine (BT), and wiring layers 101 provided on opposite surfaces of the core layer 10. Conductive vias 100 electrically connecting the wiring layers 101 are provided in the core layer 10. An additional layer structure 12 is formed on one side of the core layer 10, which includes a dielectric layer 120 and a circuit layer 121 provided on the dielectric layer 120 and electrically connected to the wiring layer 101. A solder mask layer 15 is formed on the other side of the core layer 10 and on the additional layer structure 12.

[0004] However, in the existing packaging substrate 1, an organic board material is used as the core layer 10, and its characteristics such as low rigidity and high coefficient of thermal expansion (CTE) make the packaging substrate 1 prone to warping in the process of large-size specifications, resulting in poor product reliability.

[0005] Furthermore, the surface flatness of the core layer 10 of the organic board material is not good. Therefore, when performing a wiring process on it, the wiring layer 101 needs to have a certain line width / line pitch, which needs to be greater than 10 microns, resulting in the difficulty of the wiring layer 101 to meet the requirements of fine line specifications (line width / line pitch less than or equal to 5 microns), and making it difficult for the packaging substrate 1 to improve the functionality of the product.

[0006] Therefore, how to overcome the above-mentioned various problems of the existing technology has actually become an urgent issue to be solved at present. Summary of the Invention

[0007] The object of the present invention is to provide a packaging substrate and a manufacturing method thereof to solve at least one of the above problems.

[0008] In view of the various defects of the above-mentioned prior art, the present invention provides a packaging substrate, comprising: a glass plate body having two opposite surfaces and a plurality of conductive vias penetrating through the two opposite surfaces of the glass plate body; two wiring layers respectively formed on the two opposite surfaces of the glass plate body and electrically connected to the plurality of conductive vias; a first build-up structure disposed on one of the surfaces of the glass plate body and electrically connected to the wiring layer; and a second build-up structure disposed on the other surface of the glass plate body and electrically connected to the wiring layer.

[0009] The present invention also provides a method for manufacturing a packaging substrate, comprising: providing a plurality of glass plate bodies having two opposite surfaces and a plurality of conductive vias penetrating through the two opposite surfaces of the glass plate body, and two wiring layers electrically connected to the plurality of conductive vias are respectively formed on the two opposite surfaces of the glass plate body; bonding the glass plate bodies on opposite sides of a carrier; forming a first build-up structure electrically connected to the wiring layer on one of the surfaces of the glass plate body; removing the carrier; and forming a second build-up structure electrically connected to the wiring layer on the other opposite surface of the glass plate body.

[0010] In a specific embodiment of the packaging substrate and its manufacturing method of the present invention, the first build-up structure includes at least one insulating layer and a first circuit layer bonded to the insulating layer and electrically connected to the wiring layer.

[0011] In a specific embodiment of the packaging substrate and its manufacturing method of the present invention, the material for forming the insulating layer is selected from ABF film or prepreg (PP).

[0012] In a specific embodiment of the packaging substrate and its manufacturing method of the present invention, the second build-up structure has at least one dielectric layer and a second circuit layer bonded to the dielectric layer and electrically connected to the wiring layer.

[0013] In a specific embodiment of the packaging substrate and its manufacturing method of the present invention, the material for forming the dielectric layer is selected from polyimide (PI) or photosensitive polyimide (PSPI).

[0014] In a specific embodiment of the packaging substrate and its manufacturing method of the present invention, the coefficient of thermal expansion of the insulating layer is less than that of the dielectric layer.

[0015] In the foregoing packaging substrate and its manufacturing method, the second build-up structure adopts a process of a redistribution layer to directly form a metal layer under the bump on its surface.

[0016] In a specific embodiment of the packaging substrate and its manufacturing method of the present invention, the thickness of the second build-up structure is less than that of the first build-up structure.

[0017] In a specific embodiment of the packaging substrate and its manufacturing method of the present invention, the line width / line pitch of the second build-up structure is less than or equal to 5 microns.

[0018] As can be seen from the above, for the encapsulation substrate and its manufacturing method of the present invention, a glass plate body of a semiconductor sheet is mainly used as the core layer to utilize its characteristics such as high rigidity and low coefficient of thermal expansion (CTE), so that the encapsulation substrate can effectively prevent warping during the process of large-size specifications. Therefore, compared with the prior art, the present invention can greatly improve the product reliability.

[0019] Furthermore, the glass plate body of the semiconductor sheet has the characteristic of surface planarization. When performing a wiring process thereon, the line width / line pitch of the fine lines of the wiring layer can meet the requirement of being less than or equal to 5 micrometers. Therefore, compared with the prior art, the present invention is beneficial to improving the functionality of the product. Description of the Drawings

[0020] Figure 1 It is a schematic cross-sectional view of a conventional encapsulation substrate.

[0021] Figures 2A to 2E It is a schematic cross-sectional view of the manufacturing method of the encapsulation substrate of the present invention.

[0022] The reference numerals are as follows:

[0023] 1, 2 Encapsulation substrate

[0024] 10 Core layer

[0025] 100, 200 Conductive vias

[0026] 101, 201 Wiring layer

[0027] 12 Build-up structure

[0028] 120, 220 Dielectric layer

[0029] 121 Circuit layer

[0030] 15, 25 Solder mask layer

[0031] 20 Glass plate body

[0032] 21 First build-up structure

[0033] 210 Insulating layer

[0034] 211 First circuit layer

[0035] 22 Second build-up structure

[0036] 221 Second circuit layer

[0037] 23 Metal layer under bump

[0038] 250 Opening

[0039] 9 Carrier. Detailed implementation manners

[0040] The following describes the implementation manners of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0041] It should be noted that the structures, ratios, sizes, etc. shown in the attached drawings of this specification are only used to cooperate with the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they do not have technical essential meanings. Any modification of the structure, change of the proportional relationship or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope that can be covered by the technical content disclosed in the present invention. At the same time, the terms such as "upper" and "one" cited in this specification are only for the convenience of clear description and are not used to limit the scope for the implementation of the present invention. The change or adjustment of their relative relationships, without substantial change of the technical content, should also be regarded as the scope for the implementation of the present invention.

[0042] Figures 2A to 2E It is a schematic cross-sectional view of the manufacturing method of the encapsulation substrate 2 of the present invention.

[0043] As Figure 2A shown, a glass plate body 20 is provided. A wiring layer 201 is provided on two opposite surfaces thereof, and a plurality of conductive vias 200 electrically connecting the wiring layer 201 are formed in the glass plate body 20 and penetrate through two opposite surfaces of the glass plate body 20.

[0044] In this embodiment, the glass plate body 20 is made of quartz-based glass. It should be understood that quartz glass with higher purity and lower hydroxyl content can be used. Its glass transition temperature (abbreviation T g ) is higher, usually between 1180 and 1250 °C.

[0045] Furthermore, the glass plate body 20 has a planarized surface to facilitate the development of fine lines.

[0046] In addition, the glass plate body 20 not only has a low coefficient of thermal expansion (Coefficient of thermal expansion, abbreviated as CTE) to meet large-size requirements, but also has high rigidity to effectively improve the problem of warpage of the plate structure. In addition, the glass plate body 20 not only has the characteristic of low moisture absorption rate to increase the product reliability, but also the cost of the glass raw material is extremely cheap to reduce the product cost.

[0047] As Figure 2BAs shown, the glass plate body 20 is respectively combined on opposite sides of a carrier 9, such that the wiring layer 201 on one side of the glass plate body 20 is embedded in the carrier 9.

[0048] In this embodiment, the carrier 9 is a bonding material of a release film.

[0049] As Figure 2C shown, a first build-up structure 21 electrically connected to the wiring layer 201 is formed on one surface of the glass plate body 20.

[0050] In this embodiment, the first build-up structure 21 includes at least one insulating layer 210 and a first circuit layer 211 that is combined with the insulating layer 210 and electrically connected to the wiring layer 201. For example, the material forming the first circuit layer 211 is copper, and the material forming the insulating layer 210 is an ABF film (Ajinomoto build-up film), a prepreg (Prepreg, abbreviated as PP), or other dielectric materials.

[0051] As Figure 2D shown, the carrier 9 is removed by a peeling method.

[0052] As Figure 2E shown, a second build-up structure 22 electrically connected to the wiring layer 201 is formed on the other surface of the glass plate body 20.

[0053] In this embodiment, the second build-up structure 22 adopts a redistribution layer (RDL) process, which has at least one dielectric layer 220 and a second circuit layer 221 that is combined with the dielectric layer 220 and electrically connected to the wiring layer 201. For example, the material forming the second circuit layer 221 is copper, and the material forming the dielectric layer 220 is a dielectric material such as polyimide (Polyimide, abbreviated as PI), photosensitive polyimide (Photosensitive Polyimide, abbreviated as PSPI), etc.

[0054] Furthermore, a solder mask layer 25 can be formed on the first build-up structure 21, and the solder mask layer 25 has a plurality of openings 250 to expose a partial surface of the first circuit layer 211 to the plurality of openings 250.

[0055] In addition, the outermost dielectric layer 220 of the second build-up structure 22 can be used as a solder mask layer to directly fabricate an under bump metallurgy (UBM) 23 on the surface of the second circuit layer 221.

[0056] Therefore, the manufacturing method of the present invention mainly uses the glass plate body 20 as the core layer to utilize the characteristics of high rigidity and low coefficient of thermal expansion (CTE) of glass, so that the packaging substrate 2 can effectively prevent warping during the process of large-size specifications. Therefore, compared with the prior art, the present invention can greatly improve the product reliability.

[0057] Furthermore, the glass plate body 20 has the characteristic of surface planarization. When performing wiring processes thereon, the line width / line pitch of the fine lines of the RDL (such as the second wiring layer 221) can meet the requirement of being less than or equal to 5 microns (L / S≤5 / 5um). Therefore, compared with the prior art, the present invention is beneficial to improving the functionality of the product. It should be understood that any layer of the dielectric layer 220 is not limited to polyimide (PI) or photosensitive polyimide (PSPI).

[0058] In addition, the insulating layer 210 of the first build-up structure 21 is made of ABF film or prepreg (PP), and its CTE is less than that of the dielectric layer 220 (such as PSPI material), which is beneficial to improving the warping degree of the packaging substrate 2 and reducing the material cost.

[0059] In addition, using the glass plate body 20 as the core layer, conductive vias 200 with extremely small dimensions can be made to facilitate electrical conduction of the wiring layer 201 (ultra-fine line specification). Therefore, the present invention is suitable for overall wiring specifications from fine line level to thick line level.

[0060] The present invention also provides a packaging substrate 2, including: a glass plate body 20, two wiring layers 201, a first build-up structure 21, and a second build-up structure 22.

[0061] The glass plate body 20 is a semiconductor plate, and a plurality of conductive vias 200 penetrating through the opposite two surfaces of the glass plate body 20 are formed in the glass plate body 20.

[0062] The two wiring layers 201 are formed on the opposite two surfaces of the glass plate body 20 and are electrically connected to the plurality of conductive vias 200.

[0063] The first build-up structure 21 is disposed on one surface of the glass plate body 20 and is electrically connected to the wiring layer 201.

[0064] The second build-up structure 22 is disposed on the opposite other surface of the glass plate body 20 and is electrically connected to the wiring layer 201.

[0065] In one embodiment, the first build-up structure 21 includes at least one insulating layer 210 and a first wiring layer 211 that combines with the insulating layer 210 and is electrically connected to the wiring layer 201. In addition, in one embodiment, the material for forming the insulating layer is selected from ABF film or prepreg (PP).

[0066] In one embodiment, the second build-up structure 22 has at least one dielectric layer 220 and a second circuit layer 221 that bonds to the dielectric layer 220 and is electrically connected to the wiring layer 201. In addition, in one embodiment, the material for forming the dielectric layer is selected from polyimide (PI) or photosensitive polyimide (PSPI).

[0067] In addition, the thermal expansion coefficient of the insulating layer is less than that of the dielectric layer.

[0068] In one embodiment, the second build-up structure 22 is of the redistribution layer (RDL) type, and a under-bump metal layer 23 is directly formed on its surface. Therefore, generally, the thickness of the second build-up structure is less than that of the first build-up structure.

[0069] In summary, for the packaging substrate and its manufacturing method of the present invention, by using a glass plate body as the core layer, and taking advantage of the characteristics of high rigidity and low thermal expansion coefficient of glass, the packaging substrate can effectively prevent warping during the process of large-size specifications. Therefore, the present invention can greatly improve the product reliability.

[0070] Furthermore, the glass plate body has the characteristic of surface planarization. When performing a wiring process thereon, the line width / line pitch of the fine lines of the wiring layer can meet the requirement of being less than or equal to 5 microns. Therefore, the present invention is beneficial to improving the functionality of the product.

[0071] The above embodiments are used to illustrate the principles and effects of the present invention by way of example, rather than to limit the present invention. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the protection of the rights of the present invention shall be as listed in the claims.

Claims

1. An encapsulation substrate, characterized in that, Comprising: A glass plate body having two opposite surfaces and a plurality of conductive vias penetrating the two opposite surfaces of the glass plate body; Two wiring layers respectively formed on the two opposite surfaces of the glass plate body and electrically connected to the plurality of conductive vias; A first build-up structure disposed on one of the surfaces of the glass plate body and electrically connected to the wiring layer; And A second build-up structure disposed on the other opposite surface of the glass plate body and electrically connected to the wiring layer.

2. The encapsulated substrate according to claim 1, wherein The first build-up structure includes at least one insulating layer and a first circuit layer that binds to the insulating layer and is electrically connected to the wiring layer.

3. The encapsulated substrate according to claim 2, wherein The material forming the insulating layer is selected from an ABF film or a prepreg.

4. The encapsulation substrate according to claim 2, wherein, The second build-up structure has at least one dielectric layer and a second circuit layer that binds to the dielectric layer and is electrically connected to the wiring layer.

5. The encapsulated substrate according to claim 4, wherein The material forming the dielectric layer is selected from polyimide or photosensitive polyimide.

6. The encapsulated substrate according to claim 4, wherein The coefficient of thermal expansion of the insulating layer is less than that of the dielectric layer.

7. The encapsulated substrate according to claim 1, wherein The second build-up structure is of the RDL (Redistribution Layer) specification to directly form an under-bump metal layer on its surface.

8. The encapsulated substrate according to claim 7, wherein The thickness of the second build-up structure is less than that of the first build-up structure.

9. The encapsulation substrate according to claim 7, wherein, The line width / line pitch of the second build-up structure is less than or equal to 5 microns.

10. A manufacturing method of a packaging substrate, characterized in that, Comprising: Providing a plurality of glass plate bodies having two opposite surfaces and a plurality of conductive vias penetrating the two opposite surfaces of the glass plate body, and two wiring layers electrically connected to the plurality of conductive vias are respectively formed on the two opposite surfaces of the glass plate body; Bonding the glass plate bodies on opposite sides of a carrier; Forming a first build-up structure electrically connected to the wiring layer on one of the surfaces of the glass plate body; Removing the carrier; and Forming a second build-up structure electrically connected to the wiring layer on the other opposite surface of the glass plate body.

11. The manufacturing method of the encapsulation substrate according to claim 10, wherein, The first build-up structure includes at least one insulating layer and a first circuit layer that binds to the insulating layer and is electrically connected to the wiring layer.

12. The manufacturing method of the encapsulated substrate according to claim 11, wherein, The material forming the insulating layer is selected from an ABF film or a prepreg.

13. The manufacturing method of the encapsulated substrate according to claim 11, wherein, The second build-up structure has at least one dielectric layer and a second circuit layer that binds to the dielectric layer and is electrically connected to the wiring layer.

14. The method for manufacturing a packaged substrate according to claim 13, wherein, The material forming the dielectric layer is selected from polyimide or photosensitive polyimide.

15. The method for manufacturing a packaged substrate according to claim 13, wherein The coefficient of thermal expansion of the insulating layer is less than that of the dielectric layer.

16. The manufacturing method of the encapsulated substrate according to claim 10, wherein, The second build-up structure adopts the process of a redistribution layer to directly form an under-bump metal layer on its surface.

17. The manufacturing method of the encapsulated substrate according to claim 16, wherein, The thickness of the second build-up structure is less than that of the first build-up structure.

18. The manufacturing method of the encapsulated substrate according to claim 16, wherein, The line width / line pitch of the second build-up structure is less than or equal to 5 microns.

Images