Lead-bonded packaging chip and preparation method thereof

Abstract

The invention relates to the field of integrated circuit design and manufacturing in the electronic core industry, in particular to a lead bonding packaging chip and a preparation method thereof. The lead bonding packaging chip comprises a substrate, M substrate inductance pins are arranged on the substrate, and M is larger than or equal to 1; the bare chip is mounted on the substrate, N chip inductance bonding pads are arranged on the bare chip, and N is larger than or equal to 2; wherein the substrate inductance pins are electrically connected with the chip inductance bonding pads through second bonding wires, every two adjacent chip inductance bonding pads connected with different substrate inductance pins are electrically connected through an in-chip circuit of the bare chip, and the second bonding wires are electrically connected with the in-chip circuit to form a bonding wire inductor horizontally extending along the periphery of the bare chip. According to the invention, no extra process is added while the inductor with a relatively high quality factor is provided, and no extra area is occupied.

Description

Technical Field

[0001] The present invention relates to fields such as integrated circuit design and manufacturing in the electronic core industry, and particularly relates to a wire-bonded packaged chip and a preparation method thereof. Background Art

[0002] A voltage-controlled oscillator is a crucial module of a chip, which is directly related to performance indicators such as the operating frequency, phase noise, and power consumption of a frequency synthesizer. According to the calculation formula of the phase noise of a voltage-controlled oscillator, to achieve better phase noise, a higher quality factor (abbreviated as "Q value") is required. In an oscillator with an LC-tank structure, the quality factor of the inductor plays a leading role in the quality factor of the entire tank. In a rough calculation, the quality factor of the inductor can be approximated as the quality factor of the entire resonator. The quality factor of the inductor is determined by its own material shape and other characteristics.

[0003] The most commonly used structure for off-chip inductors is to solder the required inductor on the PCB outside the chip package. This type of inductor can achieve a relatively high quality factor. However, since it is completely off-chip and there is a certain distance from the chip, and there are multiple metal traces on the PCB in between, to obtain an accurate oscillator performance model, designers must model the inductor soldered on the PCB from the chip, including the solder joints and PCB traces in between. The various materials, connection, and routing methods in the path design package all pose great difficulties for accurate modeling, greatly increasing the design complexity and making the design process more difficult to control.

[0004] The most commonly used inductor in a system-on-chip is an on-chip inductor. It has good integration characteristics and the inductive reactance is relatively stable, but its quality factor is relatively low, and the limit value is less than 20. Summary of the Invention

[0005] I. Technical Problems to be Solved

[0006] The present invention is expected to at least partially solve one of the above technical problems.

[0007] II. Technical Solutions

[0008] The first aspect of the present invention provides a wire-bonded packaged chip. The wire-bonded packaged chip includes: a substrate, on which M substrate inductor pins are provided, M≥1; a bare chip, mounted on the substrate, on which N chip inductor pads are provided, N≥2; wherein, the substrate inductor pins and the chip inductor pads are electrically connected through second bonding wires, and two adjacent chip inductor pads connected to different substrate inductor pins are electrically connected through the on-chip circuit of the bare chip, and the second bonding wires and the on-chip circuit are electrically connected to form a bonding wire inductor that horizontally extends along the periphery of the bare chip.

[0009] In some embodiments of the present invention, S substrate signal pins are provided on a substrate, where S≥1; S chip signal pads are provided on a bare chip; the chip signal pads and the main substrate pads are electrically connected by first bonding wires; wherein, the distance L between the second bonding wire and the adjacent first bonding wire satisfies: L≥6r, where r is the wire radius of the first bonding wire and the second bonding wire.

[0010] In some embodiments of the present invention, for the m-th substrate inductance pin, it is electrically connected to the (2m - 1)-th chip inductance pad and the 2m-th chip inductance pad respectively through second bonding wires; except for the chip inductance pads located at both ends, for the 2m-th chip inductance pad, it is electrically connected to the m-th substrate inductance pin through a second bonding wire, and is electrically connected to the (2m + 1)-th chip inductance pad through an on-chip circuit of the bare chip; wherein, m = 1, 2, ……, M - 1.

[0011] In some embodiments of the present invention, N≥2M; the 1st chip inductance pad is connected to the 1st substrate inductance pin through a second bonding wire; the M-th substrate inductance pin is connected to the 2M-th chip inductance pad through a second bonding wire; there are U inductance segments between the 1st substrate inductance pin and the M-th substrate inductance pin, where U≥1; the inductance segment includes: the second bonding wire segment where the m-th substrate inductance pin is electrically connected to the 2m-th chip inductance pad; the on-chip circuit segment where the 2m-th chip inductance pad is electrically connected to the (2m + 1)-th chip inductance pad; the second bonding wire segment where the (2m + 1)-th chip inductance pad is electrically connected to the (m + 1)-th substrate inductance pin; wherein, m = 1, 2, ……, M - 1.

[0012] In some embodiments of the present invention, U≥4; the bare chip is rectangular, and there is at least 1 inductance segment on each of its peripheral sides.

[0013] In some embodiments of the present invention, the inductance value L of the bonding wire inductance bonding satisfies:

[0014]

[0015] wherein, l is the total length of all the second bonding wires in the bonding wire inductance, r is the wire radius of the second bonding wire, h is the arc height of the second bonding wire, and μ0 is the magnetic permeability of vacuum.

[0016] In some embodiments of the present invention, the packaged chip satisfies at least one of the following: 60μm≤h≤150μm; 10μm≤r≤100μm; 1mm≤l≤20mm.

[0017] In some embodiments of the present invention, S substrate signal pins are provided on a substrate, where S ≥ 1; S chip signal pads are provided on a bare chip; the chip signal pads are electrically connected to the main substrate pads through first bonding wires; wherein, the distance L between the second bonding wire and an adjacent first bonding wire satisfies: L ≥ 6r, where r is the wire radius of the first bonding wire and the second bonding wire.

[0018] In some embodiments of the present invention, the packaged chip satisfies: both the first bonding wire and the second bonding wire are gold wires.

[0019] In some embodiments of the present invention, the packaged chip satisfies: there is at least one substrate signal pin between adjacent substrate inductance pins.

[0020] In some embodiments of the present invention, the packaged chip satisfies: there is at least one chip signal pad between adjacent chip inductance pads.

[0021] In some embodiments of the present invention, the packaged chip satisfies: the first bonding wire and the second bonding wire are completed through the same wire bonding process.

[0022] In some embodiments of the present invention, the packaged chip satisfies: further comprising: a packaging shell, which is buckled on the outside of the bare chip and the first and second bonding wires and fixed on the substrate.

[0023] In some embodiments of the present invention, the packaged chip is a QFN package.

[0024] In some embodiments of the present invention, the substrate inductance pins are evenly arranged on the periphery of the substrate; the chip inductance pads are evenly arranged on the periphery of the bare chip.

[0025] In some embodiments of the present invention, the bonding wire inductance and the resonant capacitor formed inside the bare chip constitute an LC resonant circuit; the LC resonant circuit is part of a voltage-controlled oscillator in the packaged chip; the voltage-controlled oscillator is part of a frequency control circuit of the packaged chip; wherein, in the frequency control circuit, other parts except the bonding wire inductance are formed inside the bare chip.

[0026] In some embodiments of the present invention, the frequency control circuit includes: a frequency discriminator and phase detector, whose first input terminal and second input terminal are respectively connected to the reference voltage V of the frequency control circuit ref and the divided-frequency voltage V div, for comparing the frequency and phase differences of two signals and outputting a first control signal in digital form; a charge pump, whose input terminal is connected to the output terminal of the frequency discriminator and phase detector, for converting the first control signal output by the frequency discriminator and phase detector from digital form to analog form; a low-pass filter, connected between the output terminal of the charge pump and the ground voltage, for filtering out high-frequency noise and interference signals in the analog-form first control signal output by the charge pump; an automatic frequency control circuit, whose first end and second end are respectively connected to the frequency control circuit reference voltage V ref and the divider voltage V div , for using the two signals to find the operating frequency that the voltage-controlled oscillator needs to lock to and outputting a second control signal; a voltage-controlled oscillator, whose first input terminal and second input terminal respectively input the first control signal and the second control signal, for using the first and second control signals to control the output frequency of the LC resonance circuit to obtain a signal with the required frequency; a frequency divider by two, whose input terminal is connected to the output terminal of the voltage-controlled oscillator, for dividing the frequency of the signal output by the voltage-controlled oscillator by two; an N-frequency divider, whose input terminal is connected to the output terminal of the frequency divider by two, and whose output terminal is connected to the divider voltage V div , for performing N-frequency division on the signal output by the frequency divider by two and feeding back the signal after N-frequency division to the frequency discriminator and phase detector; a Delta-Sigma modulator, whose input terminal and output terminal are connected to the N-frequency divider, for adjusting the division coefficient of the N-frequency divider; wherein, the frequency discriminator and phase detector, the charge pump, the frequency divider by two, the N-frequency divider, and the Delta-Sigma modulator are all formed inside the bare chip.

[0027] In some embodiments of the present invention, it further includes: a power amplifier, whose input terminal is connected to the frequency divider by two, for amplifying the power of the signal output by the frequency divider by two; a mixer, whose input terminal is connected to the frequency divider by two, for mixing the signal output by the frequency divider by two to obtain new frequency components; wherein, the power amplifier and the mixer are both formed inside the bare chip.

[0028] The second aspect of the present invention provides a method for manufacturing a packaged chip. The method for manufacturing a packaged chip with wire bonding of the present invention is used to manufacture the packaged chip as above, including:

[0029] Step A, obtaining a substrate,

[0030] M substrate inductance pins and S substrate signal pins are arranged on the substrate, M≥1, S≥1;

[0031] Step B, obtaining a bare chip,

[0032] N chip inductance pads and S chip signal pads are arranged on the bare chip, wherein, two adjacent chip inductance pads preset to be connected to different substrate inductance pins are electrically connected through the in-chip circuit of the bare chip;

[0033] Step C: Mount the bare chip onto the substrate;

[0034] Step D: Perform the wire bonding process, including: performing the first wire bonding between the signal pins of the substrate and the signal pads of the chip; performing the second wire bonding between the inductance pins of the substrate and the inductance pads of the chip;

[0035] Among them, the second bonding wire electrically connecting the inductance pin of the substrate and the inductance pad of the chip is electrically connected through the in-chip circuit between the corresponding chip inductance pads, forming a bonding wire inductance extending horizontally along the periphery of the bare chip.

[0036] In some embodiments of the present invention, in the step of performing the second wire bonding between the inductance pin of the substrate and the inductance pad of the chip in Step D, at least one of the following is satisfied: 60μm ≤ h ≤ 150μm; 10μm ≤ r ≤ 100μm; 1mm ≤ l ≤ 20mm; where l is the length of all the second bonding wires in the bonding wire inductance, r is the wire radius of the second bonding wire, and h is the arc height of the second bonding wire.

[0037] In some embodiments of the present invention, in the step of obtaining the bare chip, a resonant capacitor is further formed in the bare chip; after performing Step D, the bonding wire inductance and the resonant capacitor form an LC resonant circuit; the LC resonant circuit constitutes a part of a voltage-controlled oscillator; the voltage-controlled oscillator is a part of a frequency control circuit; among them, in the frequency control circuit, all parts except the bonding wire inductance are formed inside the bare chip.

[0038] III. Beneficial Effects

[0039] As can be seen from the above technical solutions, the present invention has at least one of the following beneficial effects compared with the prior art:

[0040] (1) High integration

[0041] Space saving: The bonding wire can directly form an inductance structure inside the chip, eliminating the need for additional external inductance components, thus greatly saving the area and volume of the chip, making the chip design more compact, and being particularly suitable for microchips with strict size requirements.

[0042] System integration: Integrating the inductance inside the chip reduces the use of external components, improves the system integration, and reduces the assembly complexity and cost.

[0043] (2) Inductance performance optimization

[0044] Adjustability: The inductance value of the bonding wire inductor can be flexibly adjusted by changing parameters such as wire length, wire diameter, and arc height to meet the requirements of different frequency control circuit designs. This adjustability makes the chip design more flexible and can better optimize the performance of the frequency control circuit.

[0045] High Q value: The bonding wire inductor usually has a high Q value (quality factor), which means it has low losses in high-frequency applications, can improve the phase noise performance and frequency stability of the frequency control circuit, and thus enhance the performance of the entire system.

[0046] Furthermore, the bonding wire is basically made of pure gold wire, and the quality factor of the pure gold wire is as high as 50. Therefore, the bonding wire inductor has a very high quality factor, often reaching forty or fifty, which is much larger than that of on-chip inductors. This means it has low losses in high-frequency applications, can improve the phase noise performance and frequency stability of the frequency control circuit, and thus enhance the performance of the entire system.

[0047] (3) Manufacturing process compatibility

[0048] Mature process: The bonding wire technology is a mature semiconductor packaging process and is widely used in the field of chip manufacturing. Using it to form an inductor does not require the introduction of additional complex manufacturing processes or equipment, reducing production costs and process risks.

[0049] Easy to implement: The manufacturing process of the bonding wire inductor is relatively simple and can be completed by using existing bonding equipment and processes during the chip manufacturing process without complex microfabrication techniques, making it suitable for mass production.

[0050] (4) High reliability

[0051] Mechanical stability: The structure of the bonding wire inductor is relatively stable and is not easily affected by external mechanical stress, which can improve the reliability of the chip to a certain extent.

[0052] Environmental adaptability: The bonding wire inductor is inside the chip and is protected by the package, which can better resist interference from external environmental factors (such as humidity, temperature changes, etc.) and improve the working stability of the chip in harsh environments.

[0053] (5) Cost-effectiveness

[0054] Reduce material costs: The bonding wire inductor does not require the use of additional external inductor components, reducing material costs.

[0055] Simplify packaging: Since the inductor is integrated inside the chip, the need for pins and connecting wires during the packaging process is reduced, lowering the packaging cost and improving the packaging efficiency at the same time.

[0056] (6) Excellent high-frequency performance

[0057] Low parasitic effect: The parasitic capacitance and parasitic resistance of the bonding wire inductor are relatively small. Especially in high-frequency applications, it can effectively reduce signal loss and interference, and improve the high-frequency performance of the frequency control circuit.

[0058] Fast response: The high-frequency characteristics of the bonding wire inductor enable it to quickly respond to frequency changes in the frequency control circuit, improve the dynamic performance of the system, and are suitable for applications such as high-speed communication and high-performance computing.

[0059] (7) Design flexibility

[0060] Customization: The bonding wire inductor can be customized according to specific design requirements, including shape, size, and inductance value, etc., and can better meet the design requirements of the frequency control circuit under different application scenarios.

[0061] Easy to optimize: In the chip design stage, the parameters of the bonding wire inductor can be precisely adjusted through simulation and optimization tools to ensure that the performance of the frequency control circuit reaches the best state.

[0062] In summary, using the bonding wire as the inductor of the frequency control circuit can bring significant advantages in terms of integration, performance, cost, and reliability, and is particularly suitable for chip designs with strict requirements on size, performance, and cost.

[0063] (8) Arrangement method of the substrate inductor pins and the chip inductor pads

[0064] In the present invention, the substrate inductor pins are uniformly arranged on the periphery of the substrate, and the chip inductor pads are uniformly arranged on the periphery of the bare chip. Moreover, there is at least one chip signal pad between two adjacent chip inductor pads, and there is at least one substrate signal pin between two adjacent substrate inductor pins.

[0065] Such an arrangement is beneficial to extend the horizontal extension distance of the bonding wire inductor on the periphery of the bare chip, and at the same time reduces the parasitic effect. Especially in high-frequency applications, it reduces the magnitudes of the parasitic capacitance and parasitic resistance, effectively reduces signal loss and interference, and improves the high-frequency performance of the frequency control circuit. At the same time, it can quickly respond to frequency changes in the frequency control circuit, improve the dynamic performance of the system, and is suitable for applications such as high-speed communication and high-performance computing.

[0066] (9) The bonding wire inductor with horizontal extension has advantages compared with the inductor with vertical extension

[0067] In some existing technologies, a longitudinally extending spiral metal wire is formed around a bare chip to form an inductor. However, this kind of inductor requires two die and the metal wires (gold, copper or aluminum) are parallel to each other, and the bonding wires and the metal wires form a spiral path. On the one hand, this implementation method increases extra processes and has a higher cost; on the other hand, the design complexity is relatively high and it is difficult to control the design process.

[0068] In the present invention, the bonding leads do not need to be parallel, do not require die, do not need to form a spiral loop, and do not need to add extra processes, so the implementation cost is relatively low. On the other hand, according to the single-bonding-lead inductor formula in the present invention, it is only necessary to determine the material, length, radius, arc height, etc. of the bonding leads to obtain the inductor and quality factor (Q value) required by the frequency control circuit oscillator. This adjustability makes the chip design more flexible and can better optimize the performance of the frequency control circuit.

[0069] (10) The frequency control circuit corrects the frequency error caused by the bonding lead inductor

[0070] The processing of the bonding leads has errors compared with the chip processing, and its inductance value is also affected by the shape, length, thickness, etc. of the bonding leads. If the same method as the off-chip inductor factory consistency test is used to screen products with the same inductance value, the cost is relatively high.

[0071] In the present invention, through the frequency control circuit, the frequency of the LC resonant circuit composed of the bonding lead inductor and the resonant capacitor C can be quickly and accurately corrected and locked for use by the internal circuit of the bare chip, thus making up for the defect that the self-error of the bonding lead inductor cannot be screened through the product consistency test. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] Figure 1 It is a schematic structural diagram of a packaged chip with wire bonding according to an embodiment of the present invention.

[0073] Figure 2 is Figure 1 The circuit diagram of the frequency control circuit in the shown packaged chip.

[0074] Figure 3 It is a flowchart of a method for manufacturing a packaged chip according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0075] In the present invention, the inductance characteristics of the bonding wire itself are combined with the on-chip circuit specially designed inside the bare chip to form a bonding wire inductance that extends horizontally along the periphery of the bare chip. In a conventional package, the bonding wire is designed to be as short as possible to avoid introducing additional parasitics. However, in the present invention, the conventional bonding wire obviously cannot provide sufficient inductance. Therefore, in order to increase the inductance value, in the chip design of the present invention, in addition to the basic pad, a pad at a certain distance from the conventional pad is added, which is specifically used for bonding. The bonding is carried out in a way of back-and-forth jumper wires. Through the wiring between multiple pads, the length of the bonding wire is increased, so as to meet the inductance requirements in the design.

[0076] In order to make the purpose, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0077] The first aspect of the present invention provides a packaged chip with wire bonding. Figure 1 It is a schematic structural diagram of the packaged chip with wire bonding according to an embodiment of the present invention. As Figure 1 shown, the packaged chip with wire bonding in this embodiment includes:

[0078] A substrate 100, on which S substrate signal pins (such as Figure 1 the black substrate pins shown in the figure) and M substrate inductance pins (such as Figure 1 the yellow substrate pins shown in the figure) are provided, M≥1, S≥1;

[0079] A bare chip (die) 200, mounted on the substrate, on which S chip signal pads (such as Figure 1 the blue chip pads shown in the figure) and N chip inductance pads (such as Figure 1 the yellow chip pads shown in the figure) are provided, N≥2;

[0080] A first bonding wire (such as the blue wire shown in the figure), electrically connected between the substrate signal pin and the chip signal pad;

[0081] A second bonding wire (such as the yellow wire shown in the figure), electrically connected between the substrate inductance pin and the chip inductance pad;

[0082] A package housing (not shown in the figure), which is buckled on the outside of the bare chip and the first and second bonding wires and fixed on the substrate.

[0083] Among them, the first bonding wire leads out the signal of the chip signal pad to the substrate signal pin. Two adjacent chip inductance pads connected to different substrate inductance pins are electrically connected through the in-die circuit of the bare chip, and the second bonding wire is electrically connected to the in-die circuit to form a bonding wire inductance that horizontally extends along the periphery of the bare chip.

[0084] The following will detail each component of the packaged chip with wire bonding in this embodiment.

[0085] In this embodiment, both the substrate 100 and the bare chip 200 are square, but the present invention is not limited thereto. In other embodiments of the present invention, the substrate and the bare chip can also be in various shapes such as rectangular, circular, oval, etc., and the present invention can be implemented, and they are also within the protection scope of the present invention.

[0086] In this embodiment, the original functional circuit and S chip signal pads in the bare chip 200, and the S substrate signal pins on the substrate 100 are all structures of the original packaged chip, and will not be elaborated here in detail. The chip signal pad is connected to the corresponding substrate signal pin through the first bonding wire.

[0087] In this embodiment, based on the original bare chip and on the basis of the original chip signal pads, 16 chip inductance pads are additionally designed, and according to the designed inductance path, an in-die circuit is designed to electrically connect two adjacent chip inductance pads connected to different substrate inductance pins. Specifically, among the pads on the bare chip (die), pad_A to pad_P are designed to form a bonding wire inductance. Among them, pad_B is connected to pad_C, pad_D is connected to pad_E, pad_F is connected to pad_G, pad_H is connected to pad_I, pad_J is connected to pad_K, pad_L is connected to pad_M, and pad_N is connected to pad_O through the in-die circuit inside the bare chip respectively.

[0088] In this embodiment, based on the original substrate, 8 substrate inductance pins are additionally designed on the basis of the original substrate signal pins. Specifically, among the pins on the substrate 100, a total of 8 substrate inductance pins from pin_33 to pin_40 are designed to form a bonding wire inductance.

[0089] Please refer to Figure 1 , based on the angle of the substrate inductance pin, for the m-th substrate inductance pin, it is electrically connected to the (2m - 1)-th chip inductance pad and the 2m-th chip inductance pad respectively through the second bonding wire, where m = 1, 2, ……, M - 1.

[0090] For example, for the substrate inductance pin pin_33, it is connected to the chip inductance pads pad_A and pad_B through the second bonding wire respectively.

[0091] For another example, for the substrate inductor pin pin_35, it is respectively connected to the chip inductor pads pad_E and pad_F through the second bonding wires.

[0092] Since the bonding wire inductance needs to be connected to the frequency control circuit inside the bare chip, both its starting end and ending end should be located on the bare chip. Please refer to Figure 1 , based on the angles of the chip inductor pads, it can be divided into the following three cases:

[0093] (1) For the first chip inductor pad pad_A

[0094] The chip inductor pad pad_A serves as the starting end of the bonding wire inductance and is connected to the substrate inductor pin pin_33 through the second bonding wire.

[0095] (2) For the last chip inductor pad pad_L

[0096] The chip inductor pad pad_L serves as the terminating end of the inductance and is connected to the substrate inductor pin pin_38 through the second bonding wire.

[0097] (3) For the other chip inductor pads except the first chip inductor pad and the last chip inductor pad

[0098] For the 2m-th chip inductor pad, it is electrically connected to the m-th substrate inductor pin through the second bonding wire and is electrically connected to the (2m + 1)-th chip inductor pad through the on-chip circuit of the bare chip; m = 1, 2,..., M - 1.

[0099] For example, for the chip inductor pad pad_B, it is electrically connected to the substrate inductor pin pin_33 through the second bonding wire and is electrically connected to the chip inductor pad pad_C through the on-chip circuit of the bare chip.

[0100] For another example, for the chip inductor pad pad_H, it is electrically connected to the substrate inductor pin pin_36 through the second bonding wire and is electrically connected to the chip inductor pad pad_I through the on-chip circuit of the bare chip.

[0101] After the above connections, there are 5 inductance segments between the first substrate inductor pin and the M-th substrate inductor pin. For each inductance segment, it includes: the second bonding wire segment where the m-th substrate inductor pin is electrically connected to the 2m-th chip inductor pad; the on-chip circuit segment where the 2m-th chip inductor pad is electrically connected to the (2m + 1)-th chip inductor pad; the second bonding wire segment where the (2m + 1)-th chip inductor pad is electrically connected to the (m + 1)-th substrate inductor pin; where m = 1, 2,..., M - 1.

[0102] In this embodiment, there are 5 inductance segments, and there is at least 1 inductance segment on each side of the bare chip periphery. However, the present invention is not limited thereto. In other embodiments of the present invention, the number of inductance segments can be determined according to factors such as the required inductance value of the packaged chip, the size of the substrate and the bare chip. As long as there is one or more inductance segments, they are all within the protection scope of the present invention.

[0103] Please refer to Figure 1 , the substrate inductance pins are uniformly arranged on the periphery of the substrate, and the chip inductance pads are uniformly arranged on the periphery of the bare chip. Moreover, there is at least one chip signal pad between two adjacent chip inductance pads, and there is at least one substrate signal pin between two adjacent substrate inductance pins. With such an arrangement, it is beneficial to extend the horizontal extension distance of the bonding wire inductance on the periphery of the bare chip, while reducing the parasitic effect. Especially in high-frequency applications, the magnitudes of the parasitic capacitance and the parasitic resistance are reduced, effectively reducing the signal loss and interference, and improving the high-frequency performance of the frequency control circuit. At the same time, it can quickly respond to the frequency change in the frequency control circuit, improve the dynamic performance of the system, and is applicable to applications such as high-speed communication and high-performance computing.

[0104] In this embodiment, the chip package adopts QFN (Quad Flat No-leads Package), but the present invention is not limited thereto. In other embodiments of the present invention, other packaging methods can also be adopted, such as: DIP (Dual In-line Package), QFP (Plastic Quad Flat Package), PGA (Pin Grid Array Package), BGA (Ball Grid Array Package). The embodiments adopting these packaging methods are also within the protection scope of the present invention.

[0105] For the bonding wire inductance as Figure 1 shown, its inductance value L bonding satisfies:

[0106]

[0107] wherein, the unit of the inductance value L bonding is H, l is the total length of all the second bonding wires in the bonding wire inductance, and its unit is m; r is the lead radius of the second bonding wire, and the unit is m; h is the arc height of the second bonding wire, and the unit is m; μ0 is the magnetic permeability of vacuum, μ0 = 4π * 10 -7 H / m.

[0108] For the bonding wire inductance as Figure 1 shown, its quality factor (Q value) satisfies:

[0109]

[0110] wherein, R ACis the high-frequency AC resistance, which contains the influence of the skin effect and the proximity effect. ω is the angular frequency, and L bonding is the inductance value of the bonding wire inductance.

[0111] Please refer to Figure 1 , the chip signal pad and the main substrate pad are electrically connected through the first bonding wire. The distance L between the second bonding wire and the adjacent first bonding wire satisfies: L≥6r, where r is the wire radius of the first bonding wire and the second bonding wire. Such a setting can avoid the mutual inductance interference between different bonding wires.

[0112] In the present invention, for the bonding wire inductance as shown in Figure 1 , 60μm≤h≤150μm; 10μm≤r≤100μm; 1mm≤l≤20mm. In this embodiment, h = 100μm; r = 25μm; l = 5mm, and L = 6r.

[0113] In this embodiment, the first bonding wire and the second bonding wire are completed through the same wire bonding process; both the first bonding wire and the second bonding wire are gold wires.

[0114] It can be seen from the above description that in this embodiment, the inductor of the oscillator is realized through the inductance characteristics of the bonding wire itself. Using such a structure as the inductor of the voltage-controlled oscillator has the following advantages:

[0115] (1) It does not add additional processes and does not occupy additional area

[0116] The prior art CN115050539A provides a 3D inductor structure formed between at least two measurement Pad points by arranging the first metal layer and the second metal layer in a vertically staggered structure based on IPD technology. Among them, the first metal layer and the second metal layer need to be fabricated additionally, increasing the production cost.

[0117] In this embodiment, whether the chip is connected for external testing or to an external circuit, it is necessary to lead out the required ports through bonding wires. Using bonding wires as inductors does not add extra processes. Bonding wire technology is a mature semiconductor packaging process widely used in chip manufacturing. Using it to form inductors does not require introducing additional complex manufacturing processes or equipment, reducing production costs and process risks. The manufacturing process of bonding wire inductors is relatively simple and can be completed by using existing bonding equipment and processes during chip manufacturing without complex microfabrication techniques, making it suitable for mass production. Bonding wires can directly form an inductor structure inside the chip without additional external inductor components, thus greatly saving the area and volume of the chip, making the chip design more compact, and being particularly suitable for tiny chips with strict size requirements. Integrating the inductor inside the chip reduces the use of external components, improves the system integration level, and reduces assembly complexity and costs.

[0118] (2) Provide a relatively high quality factor

[0119] Bonding wires basically use pure gold wires, and the quality factor of pure gold wires is as high as 50. Therefore, bonding wire inductors have a very high quality factor, often reaching forty or fifty, which is much larger than that of on-chip inductors. This means that it has lower losses in high-frequency applications, can improve the phase noise performance and frequency stability of the frequency control circuit, and thus enhance the performance of the entire system.

[0120] (3) Cost and performance advantages of bonding wire inductors

[0121] Bonding wire inductors solve the problem of inductor on-chip integration. Bonding wire inductors do not require the use of additional external inductor components, reducing material costs and decreasing the chip volume and area.

[0122] The structure of bonding wire inductors is relatively stable and not easily affected by external mechanical stress, which can improve the reliability of the chip to a certain extent. Bonding wire inductors are inside the chip and are not only protected by the package, being able to better resist interference from external environmental factors (such as humidity, temperature changes, etc.), improving the working stability of the chip in harsh environments. Moreover, the parasitic capacitance and parasitic resistance of bonding wire inductors are relatively small, especially in high-frequency applications, which can effectively reduce signal loss and interference and improve the high-frequency performance of the frequency control circuit.

[0123] (4) Flexible adjustment of inductance value

[0124] The inductance value of bonding wire inductors can be flexibly adjusted by changing parameters such as wire length, wire diameter, and arc height to meet the requirements of different frequency control circuit designs. This adjustability makes the chip design more flexible and can better optimize the performance of the frequency control circuit.

[0125] (5) The inductance of the bond wire extending horizontally has an advantage compared to the inductance of the inductance extending vertically.

[0126] In some prior arts, a spiral metal wire extending vertically is formed around the bare chip to form an inductor. However, this inductor requires two dies and the metal wires (gold, copper or aluminum) are parallel to each other, and the bond wires and the metal wires form a spiral path. This implementation method increases additional processes and has a high cost on the one hand; on the other hand, the design complexity is high and the design process is difficult to control.

[0127] The bond wires of the present invention do not need to be parallel, do not require two dies, do not need to form a spiral loop, and do not need to add additional processes, so the implementation cost is low. On the other hand, according to the single bond wire inductance formula of the present invention, it is only necessary to determine the bond wire material, length, radius, arc height, etc. to obtain the inductance and quality factor (Q value) required by the frequency control circuit oscillator. This adjustability makes the chip design more flexible and can better optimize the performance of the frequency control circuit.

[0128] Those skilled in the art should understand that the above bond wire structure can realize inductance, but there are also problems. Since the inductance value of the bond wire inductance is determined by the bond wire alone, and there are errors in the processing of the bond wire compared to the chip processing, its inductance value is also affected by the shape, length, thickness, etc. of the bond wire. The off-chip inductor will undergo multiple tests during factory production and finally select products with consistent inductance. However, if the same method as the off-chip inductor factory consistency test is used to screen products with consistent inductance values for the bond wire inductance integrated with the chip package, the cost is high.

[0129] To overcome this problem, a special frequency control circuit needs to be designed for the bond wire inductance to output a more accurate frequency to meet the frequency requirements inside the packaged chip. In this embodiment, the bond wire inductance and the resonant capacitor formed inside the bare chip form an LC resonant circuit; the LC resonant circuit is a part of the voltage-controlled oscillator in the packaged chip; the voltage-controlled oscillator is a part of the frequency control circuit of the packaged chip; wherein, in the frequency control circuit, other parts except the bond wire inductance are formed inside the bare chip.

[0130] Figure 2 For Figure 1Circuit diagram of the frequency control circuit in the encapsulated chip shown. As shown in the figure, in the encapsulated chip of this embodiment, the frequency control circuit is used to lock the frequency of the voltage-controlled oscillator, which is equivalent to the function of a "phase-locked loop". The frequency control circuit includes: a phase frequency detector (Phase Frequency Detector, abbreviated as "PFD"); a charge pump (Charge Pump, abbreviated as "CP"); a low-pass filter (Low Pass Filter, abbreviated as "LPF"); a voltage-controlled oscillator (Voltage Controlled Oscillator, abbreviated as "VCO"); an automatic frequency control circuit (Automatic Frequency Control, abbreviated as "AFC"); a divide-by-two circuit (abbreviated as " / 2"); an N-divider (abbreviated as " / N") and other components. Except for the bonding wire inductance in the VCO, other parts of the frequency control circuit are formed inside the bare chip.

[0131] On the periphery of the frequency control circuit, the encapsulated chip also includes: a power amplifier (Power Amplifier, abbreviated as "PA"); a mixer and so on. And, the power amplifier PA and the mixer are both formed inside the bare chip.

[0132] The following will specifically describe each part related to the frequency control circuit.

[0133] In this embodiment, Vref is the reference voltage of the frequency control circuit.

[0134] In this embodiment, Vdiv is the voltage related to the divider. By adjusting Vdiv, the division ratio of the divider can be changed, thereby adjusting the frequency of the signal fed back to the PFD. This helps the frequency control circuit quickly lock to the frequency of the input reference signal Vref, and in the case of changes in the input signal frequency or the presence of interference, etc., the frequency control circuit can be kept in the locked state by appropriately adjusting Vdiv.

[0135] In this embodiment, the phase frequency detector PFD is a key component of the frequency control circuit. The first input terminal and the second input terminal of the PFD are respectively connected to the reference voltage Vref of the frequency control circuit and the divider voltage Vdiv, and are used to compare the frequency and phase differences of the two signals and output a first control signal in digital form.

[0136] In this embodiment, the charge pump CP is a key module connecting the phase frequency detector PFD and the loop filter. The input terminal of the CP is connected to the output terminal of the phase frequency detector, and is used to convert the first control signal output by the phase frequency detector from digital form to analog form to realize the adjustment of the frequency and phase of the voltage-controlled oscillator VCO.

[0137] In this embodiment, the low-pass filter LPF is an important part of the frequency control circuit, mainly used to filter out high-frequency noise and interference signals, smooth the signals output by the phase-frequency detector PFD and the charge pump CP, and provide a stable control voltage for the voltage-controlled oscillator VCO. Specifically, the LPF is connected between the output terminal of the charge pump and the ground voltage, and is used to filter out high-frequency noise and interference signals in the first control signal in analog form output by the charge pump.

[0138] In this embodiment, the core of the automatic frequency control AFC is to continuously compare the frequency of the input reference signal with the frequency of the signal output by the voltage-controlled oscillator VCO inside the frequency control circuit after frequency division. When a frequency deviation is detected between the two, the AFC circuit generates a control signal. This control signal is usually a voltage signal, which is applied to the VCO to change the oscillation frequency of the VCO, so that the frequency of the VCO output signal is adjusted in the direction of reducing the frequency deviation from the reference signal.

[0139] Specifically, the automatic frequency control circuit AFC looks up the operating frequency that the VCO needs to lock in the look-up table through two input signal frequency control circuit reference voltages Vref and the frequency divider voltage Vdiv, and realizes fast locking with the lowest number of look-up times, the highest look-up efficiency, and the lowest power consumption, and outputs the corresponding second control signal to the VCO, thereby realizing fast frequency locking.

[0140] In this embodiment, the voltage-controlled oscillator VCO is a key component that generates a periodic signal with a variable frequency. The first input terminal and the second input terminal respectively input a first control signal and a second control signal, which are used to control the output frequency of the LC resonant circuit by using the first and second control signals to obtain a signal with the required frequency.

[0141] The voltage-controlled oscillator VCO includes an LC resonant circuit. The inductor in the LC resonant circuit is the bonding wire inductor L formed by bonding wires outside the bare chip as described above. bonding . Bonding wire inductor: Together with the capacitor, it forms an LC resonant circuit. According to the formula The inductance value L and the capacitance value C together determine the basic range of the oscillation frequency of the VCO. The quality factor (Q value) represents the ratio of the energy stored in the inductor to the energy consumed. The higher the Q value, the smaller the energy loss of the inductor, and the better the performance of the VCO, such as reducing signal attenuation and phase noise.

[0142] In this embodiment, the frequency divider (abbreviated as " / 2") means that the frequency divider divides the frequency of the input signal by two. That is to say, the frequency of the output signal of the frequency divider is half of the frequency of the input signal. Specifically, the input terminal of the frequency divider is connected to the output terminal of the voltage-controlled oscillator, and is used to divide the frequency of the signal output by the voltage-controlled oscillator by two.

[0143] In this embodiment, in the N - divider (abbreviated as " / N"), "N" is a variable integer representing the division factor. This means that the divider divides the frequency of the input signal by N, and the resulting output signal frequency is 1 / N of the input signal frequency. Specifically, the input terminal of the N - divider is connected to the output terminal of the frequency divider by two, and its output terminal is connected to the divider voltage V div , which is used to perform N - division processing on the signal output by the frequency divider by two and feedback the signal after N - division processing to the frequency discriminator and phase discriminator.

[0144] In this embodiment, the Delta - Sigma modulator DSM is usually used in cooperation with the divider and is located in the feedback path of the frequency control circuit. A part of the signal generated by the VCO is used as the output signal, and the other part enters the divider. When DSM is adopted, it dynamically adjusts the division ratio of the divider. DSM outputs a series of discrete control signals according to the input signal and the internal modulation algorithm. These signals are used to change the division factor of the divider, so that the divider can achieve fractional division instead of fixed integer division. Specifically, the input terminal and the output terminal of the Delta - Sigma modulator are connected to the N - divider for adjusting the division factor of the N - divider.

[0145] In this embodiment, after the power amplifier PA receives the signal output by the frequency control circuit, if the signal needs to be used to drive a load or for long - distance transmission, its power may not be sufficient to meet the requirements. The main function of the power amplifier is to amplify the power of the signal output by the frequency control circuit, increase the amplitude and energy of the signal, so as to ensure that the signal can effectively drive the load, such as driving an antenna to transmit wireless signals. Specifically, the input terminal of the power amplifier is connected to the frequency divider by two for amplifying the power of the signal output by the frequency divider by two.

[0146] In this embodiment, the mixer Mixer is a device that can mix two or more signals with different frequencies to generate a signal containing new frequency components. Specifically, the input terminal of the mixer is connected to the frequency divider by two for performing mixing processing on the signal output by the frequency divider by two to obtain new frequency components.

[0147] Those skilled in the art should understand that although there is an error in the product consistency of the inductance value of the bonding wire inductance itself and the off - chip inductance when leaving the factory in this embodiment, through the above - mentioned frequency control circuit, the frequency of the LC resonant circuit composed of the bonding wire inductance and the resonant capacitor C can be quickly and accurately corrected and locked for use by the internal circuit of the bare chip, thus making up for the defect that the self - error of the bonding wire inductance cannot be screened through the product consistency test.

[0148] Based on the above - mentioned packaged chip, the second aspect of the present invention also provides a method for manufacturing a packaged chip.Figure 3 This is a flowchart of the method for manufacturing a packaged chip according to an embodiment of the present invention. As shown in the figure, the method for manufacturing a packaged chip in this embodiment includes:

[0149] Step A: Obtain a substrate,

[0150] There are M substrate inductance pins and S substrate signal pins provided on the substrate, where M≥1 and S≥1.

[0151] Step B: Obtain a bare chip,

[0152] There are N chip inductance pads and S chip signal pads provided on the bare chip. Among them, two adjacent chip inductance pads preset to be connected to different substrate inductance pins are electrically connected through the in-chip circuit of the bare chip. And, other parts of the frequency control circuit except the inductor are also provided in the bare chip.

[0153] Step C: Mount the bare chip onto the substrate;

[0154] Step D: Perform the wire bonding process, including: performing the first wire bonding between the substrate signal pins and the chip signal pads; performing the second wire bonding between the substrate inductance pins and the chip inductance pads;

[0155] Among them, the second bonding wire electrically connecting the substrate inductance pin and the chip inductance pad is electrically connected through the in-chip circuit between the corresponding chip inductance pads, forming an inductor that horizontally extends along the periphery of the bare chip.

[0156] Among them, in the step of performing the second wire bonding, the following are satisfied: 60μm≤h≤150μm; and / or, 10μm≤r≤100μm; and / or, 1mm≤l≤20mm, where l is the total length of all the second bonding wires in the inductor, r is the wire radius of the second bonding wire, and h is the arc height of the second bonding wire.

[0157] After performing the step D, the inductor and the resonant capacitor form an LC resonant circuit; the LC resonant circuit constitutes a part of a voltage-controlled oscillator; the voltage-controlled oscillator is a part of the frequency control circuit.

[0158] Those skilled in the art should understand that although the above first wire bonding and second wire bonding are described separately, in actual processes, the two are performed simultaneously. As long as the relevant programs are input into the wire bonder, the wire bonder can automatically complete them without manual intervention. In addition, the technical content and beneficial effects of this embodiment can also refer to the prior packaged chip embodiments, which will not be elaborated here.

[0159] So far, the various embodiments of the present invention have been introduced. Based on the above description, those skilled in the art should have a clear understanding of the present invention.

[0160] It should be noted that for some implementation manners, if they are not the key content of the present invention and are well-known to those of ordinary skill in the art, due to space limitations, they are not described in detail in the accompanying drawings of the specification or in the text. In this case, reference may be made to the relevant prior art for understanding.

[0161] For the numerical values and numerical ranges mentioned in the present invention, unless clearly indicated to the contrary, the numerical parameters in the specification and claims of the present invention may be approximate values and can be changed according to the content of the present invention. Specifically, all the numbers recorded in the specification and claims representing the contents of components, reaction conditions, etc. should be understood to be modified by the term "about" in all cases, and the meaning expressed is that it includes a change of ±10% of a specific quantity in some embodiments.

[0162] For the ordinal numbers used in the present invention, such as "first", "second", as well as Arabic numerals, letters, etc., which are used to modify the corresponding elements (or steps), their original intention is only to clearly distinguish one element (or step) with a certain name from another element (or step) with the same name, and does not mean that the element (or step) has any ordinal number, nor does it represent the order of one element (or step) and another element (or step).

[0163] Those skilled in the art should understand that in the claims and specification of the present invention, the word "comprising" does not exclude the existence of elements (or steps) not listed in the claims. The word "a" or "an" before an element (or step) does not exclude the existence of a plurality of such elements (or steps).

[0164] Moreover, the purpose of providing the above embodiments is only to make the present invention meet the legal requirements, and the present invention can be implemented in many different forms and should not be construed as limited to the embodiments described herein.

[0165] Similarly, it should be understood that in order to streamline the present invention, in the above description of the exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, the method of the present invention should not be construed as reflecting the intention that the claimed invention requires more features than those clearly recited in each claim. More precisely, as reflected in the claims, each aspect of the invention lies in less than all the features of the previous single embodiment. And, the embodiments can be mixed and used with each other or with other embodiments based on considerations of design and reliability, that is, the technical features in different embodiments can be freely combined to form more embodiments. Therefore, the claims following the specific implementation manners are hereby clearly incorporated into the specific implementation manners, where each claim itself is a separate embodiment of the present invention.

[0166] In the above specific embodiments, the objectives, technical means, and beneficial effects of the present invention have been described in detail. It should be understood that the purpose of the detailed description is for those skilled in the art to better understand the present invention, and it is not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An encapsulated chip for wire bonding, characterized in that, Comprising: A substrate, on which M substrate inductance pins are provided, where M≥1; A bare chip, mounted on the substrate, on which N chip inductance pads are provided, where N≥2; Wherein, the substrate inductance pins and the chip inductance pads are electrically connected through second bonding wires, and two adjacent chip inductance pads connected to different substrate inductance pins are electrically connected through the in-chip circuit of the bare chip. The second bonding wires and the in-chip circuit are electrically connected to form a bonding wire inductance that horizontally extends along the periphery of the bare chip.

2. The packaged chip according to claim 1, wherein For the m-th substrate inductance pin, it is electrically connected through a second bonding wire to: the (2m - 1)-th chip inductance pad and the 2m-th chip inductance pad; Except for the chip inductance pads at both the head and tail sides, for the 2m-th chip inductance pad, it is electrically connected through a second bonding wire to the m-th substrate inductance pin, and it is electrically connected through the in-chip circuit of the bare chip to the (2m + 1)-th chip inductance pad; Wherein, m = 1, 2, ……, M - 1.

3. The encapsulated chip according to claim 1, wherein N≥2M; The first chip inductance pad is connected to the first substrate inductance pin through a second bonding wire; The M-th substrate inductance pin is connected to the 2M-th chip inductance pad through a second bonding wire; There is an inductance section with a U section between the first substrate inductance pin and the M-th substrate inductance pin, where U≥1; The inductance section includes: The second bonding wire segment where the m-th substrate inductance pin is electrically connected to the 2m-th chip inductance pad; The in-chip circuit segment where the 2m-th chip inductance pad is electrically connected to the (2m + 1)-th chip inductance pad; The second bonding wire segment where the (2m + 1)-th chip inductance pad is electrically connected to the (m + 1)-th substrate inductance pin; Wherein, m = 1, 2, ……, M - 1.

4. The packaged chip according to claim 3, wherein U≥4； The bare chip is rectangular, and there is at least one inductance section on each side of its periphery.

5. The encapsulated chip according to claim 1, wherein The inductance value L of the bonding wire inductor bonding satisfies: Wherein, l is the total length of all the second bonding wires in the bonding wire inductance, r is the wire radius of the second bonding wire, h is the arc height of the second bonding wire, and μ0 is the magnetic permeability of vacuum.

6. The encapsulated chip according to claim 5, characterized in that, The packaged chip satisfies at least one of the following: 60μm≤h≤150μm; 10μm≤r≤100μm; 1mm≤l≤20mm.

7. The packaged chip according to claim 1, wherein S substrate signal pins are provided on the substrate, where S≥1; S chip signal pads are provided on the bare chip; the chip signal pads and the main substrate pads are electrically connected through first bonding wires; Wherein, the distance L between the second bonding wire and the adjacent first bonding wire satisfies: L≥6r, where r is the wire radius of the first bonding wire and the second bonding wire.

8. The encapsulated chip according to claim 7, wherein The packaged chip satisfies at least one of the following: Both the first bonding wire and the second bonding wire are gold wires; There is at least one substrate signal pin between adjacent substrate inductance pins; There is at least one chip signal pad between adjacent chip inductance pads; The first bonding wire and the second bonding wire are completed through the same wire bonding process; Further comprising: an encapsulation housing, which is buckled on the outside of the bare chip and the first and second bonding leads and fixed on the substrate.

9. The encapsulated chip according to claim 1, wherein the encapsulated chip is a QFN package; and / or, the substrate inductance pins are uniformly arranged on the periphery of the substrate; the chip inductance pads are uniformly arranged on the periphery of the bare chip.

10. The encapsulated chip according to claim 1, wherein the bonding lead inductance and the resonant capacitor formed inside the bare chip constitute an LC resonant circuit; the LC resonant circuit is a part of the voltage-controlled oscillator in the encapsulated chip; the voltage-controlled oscillator is a part of the frequency control circuit of the encapsulated chip; wherein, in the frequency control circuit, other parts except the bonding lead inductance are formed inside the bare chip.

11. The encapsulated chip according to claim 10, wherein The frequency control circuit includes: A frequency discriminator and phase detector, whose first input terminal and second input terminal are respectively connected to the reference voltage V of the frequency control circuit ref and the voltage V of the frequency divider div , for comparing the frequency and phase differences of the two signals and outputting a first control signal in digital form; a charge pump, whose input end is connected to the output end of the frequency discriminator and phase detector, and is used to convert the first control signal output by the frequency discriminator and phase detector from digital form to analog form; a low-pass filter, connected between the output end of the charge pump and the ground voltage, and is used to filter out high-frequency noise and interference signals in the analog form of the first control signal output by the charge pump; An automatic frequency control circuit, whose first end and second end are respectively connected to a frequency control circuit reference voltage V ref and a frequency divider voltage V div , is used to find a working frequency that needs to be locked by a voltage-controlled oscillator by using two signals and output a second control signal; a voltage-controlled oscillator, whose first input end and second input end respectively input the first control signal and the second control signal, and is used to control the output frequency of the LC resonant circuit by using the first and second control signals to obtain a signal with a required frequency; a frequency divider, whose input end is connected to the output end of the voltage-controlled oscillator, and is used to perform frequency division processing on the frequency of the signal output by the voltage-controlled oscillator; An N-divider, whose input terminal is connected to the output terminal of the frequency divider by two, and whose output terminal is connected to the divider voltage V div , is used to perform N-division processing on the signal output by the frequency divider by two, and feedback the signal after N-division processing to the frequency discriminator and phase discriminator; a Delta-Sigma modulator, whose input end and output end are connected to the N-frequency divider, and is used to adjust the frequency division coefficient of the N-frequency divider; wherein, the frequency discriminator and phase detector, the charge pump, the frequency divider, the N-frequency divider, and the Delta-Sigma modulator are all formed inside the bare chip.

12. The encapsulated chip according to claim 11, wherein Further comprising: a power amplifier, whose input end is connected to the frequency divider, and is used to perform power amplification on the signal output by the frequency divider; a mixer, whose input end is connected to the frequency divider, and is used to perform mixing processing on the signal output by the frequency divider to obtain new frequency components; wherein, the power amplifier and the mixer are both formed inside the bare chip.

13. A method for preparing a packaged chip with wire bonding, characterized in that, For preparing the encapsulated chip according to claim 7 or 8, including: Step A, obtaining a substrate, where M substrate inductance pins and S substrate signal pins are arranged on the substrate, M≥1, S≥1; Step B, obtaining a bare chip, where N chip inductance pads and S chip signal pads are arranged on the bare chip, and among them, two adjacent chip inductance pads preset to be connected to different substrate inductance pins are electrically connected through the in-chip circuit of the bare chip; Step C, mounting the bare chip on the substrate; Step D, performing a wire bonding process, including: performing a first wire bonding between the substrate signal pins and the chip signal pads; performing a second wire bonding between the substrate inductance pins and the chip inductance pads; Among them, the second bonding wire that electrically connects the substrate inductance pin and the chip inductance pad is electrically connected through the in-chip circuit between the corresponding chip inductance pads, forming a bonding wire inductance that horizontally extends along the periphery of the bare chip.

14. The preparation method according to claim 13, wherein, In the step of performing the second wire bonding between the substrate inductance pin and the chip inductance pad in the step D, at least one of the following is satisfied: 60μm ≤ h ≤ 150μm; 10μm ≤ r ≤ 100μm; 1mm ≤ l ≤ 20mm Among them, l is the length of all the second bonding wires in the bonding wire inductance, r is the wire radius of the second bonding wire, and h is the arc height of the second bonding wire.

15. The preparation method according to claim 13, wherein In the step of obtaining the bare chip, a resonant capacitor is further formed in the bare chip; After performing the step D, the bonding wire inductance and the resonant capacitor form an LC resonant circuit; the LC resonant circuit constitutes a part of a voltage-controlled oscillator; the voltage-controlled oscillator is a part of a frequency control circuit; Among them, in the frequency control circuit, all parts except the bonding wire inductance are formed inside the bare chip.

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