3D packaging optical engine and packaging method thereof

Abstract

The invention provides a 3D packaging optical engine and a packaging method thereof, the optical engine adopts a structure that an EIC is stacked on a PIC, and the EIC is located on the uppermost layer of the optical engine, has minimum thermal resistance and is beneficial to heat dissipation of the EIC. And the PIC is mounted on the 2.5 D EIC module in a surface mounting manner. The substrate is hollowed out or the TGV adapter plate is integrated on the same layer of the PIC, so that the PIC can support a larger thickness and even does not need to be thinned, and the low warping of the PIC can be realized. And the integration of passive devices is realized by adopting an integrated passive device (IPD) method.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic packaging, and particularly to a 3D packaged optical engine and its packaging method. Background Art

[0002] In the current field of communication technologies, co-packaged optics (CPO) and optical I / O (OIO) technologies have become the focus of the industry, attracting extensive attention from leading manufacturers such as Intel, Broadcom, Cisco, Marvell, Ayar Labs, and Ranovus. Among them, CPO switches are recognized as the future development direction that will replace traditional pluggable switches due to their significant advantages such as low cost, low power consumption, low latency, and low loss. Therefore, as the core component of CPO switches, the optical engine has naturally become the research focus in this field in recent years.

[0003] Currently, four main structural types have been proposed for optical engines in the industry: the first is a 3D fan-out packaged optical engine with a PIC stacked on an EIC; the second is a 3D fan-out packaged optical engine with an EIC stacked on a PIC; the third is a 3D integrated optical engine with a PIC integrated with TSVs; and the fourth is a 3D integrated optical engine with an EIC integrated with TSVs.

[0004] For the 3D fan-out packaged optical engine with a PIC stacked on an EIC, it faces the challenge of difficult heat dissipation. Moreover, since the aspect ratio of TMV (molded vias) is only 1:1.5, this makes TMV require a large area, which is not conducive to the miniaturization development of the module. In addition, the optical coupling packaging of the PIC must be completed before it is mounted on the substrate, otherwise the optical port is extremely easy to be blocked.

[0005] For the 3D fan-out packaged optical engine with an EIC stacked on a PIC, similarly, because the aspect ratio of TMV is only 1:1.5, the area overhead of TMV is relatively large, which is extremely unfavorable for the miniaturization of the module. At the same time, the thickness of TMV is usually no more than 300 μm, which will cause a large warpage of the PIC, seriously affecting the subsequent optical coupling effect. And during the plastic encapsulation process of the PIC, there is a risk of the optical port being contaminated.

[0006] In the 3D integrated optical engine with a PIC integrated with TSVs, when the single-channel rate reaches 100 Gbps and above, due to the large parasitic capacitance of TSVs (through-silicon vias), there will be a large link loss problem. In addition, the thickness of TMV is usually no more than 200 μm, which will cause a large warpage of the PIC, which is extremely unfavorable for the optical coupling of the PIC.

[0007] However, for a 3D integrated optical engine that adopts EIC integrated with TSV, in the case of a single-channel rate of 100 Gbps and above, there are also significant link loss problems due to the large parasitic capacitance of the TSV. Moreover, since EIC requires additional reserved area, this will undoubtedly increase the cost of EIC. Similarly, the optical coupling packaging of PIC must also be completed before it is mounted on the substrate to avoid blocking the optical port.

[0008] In summary, the existing publicly available technical solutions are difficult to simultaneously meet the requirements in multiple aspects such as the good heat dissipation performance of EIC, the low warping of PIC, the small size of the module, the low loss of high-speed lines, and the convenience of PIC optical coupling.

[0009] Therefore, to solve the above problems, the present invention provides a 3D packaged optical engine and a packaging method. The optical engine adopts a structure in which EIC is stacked on PIC. EIC is located at the top layer of the optical engine and has the smallest thermal resistance, which is beneficial to the heat dissipation of EIC. PIC is mounted on a 2.5D EIC module. By hollowing out the substrate or integrating a TGV adapter board on the same layer as PIC, PIC can support a relatively thick thickness, or even without thinning, which is beneficial to PIC achieving low warping. Summary of the Invention

[0010] The present invention provides a 3D packaged optical engine, which is characterized by comprising:

[0011] A PIC module, which is used to realize the emission, reception, and modulation of optical signals;

[0012] An EIC module, which is used to process electrical signals and cooperate with the PIC module to complete optoelectronic conversion. The PIC module is mounted on the EIC module;

[0013] A substrate, on which the EIC module is flip-chip mounted;

[0014] An adhesive layer, which is coated on the surface of the EIC module and is used to fix the cover plate on the top of the EIC module to form a sealed structure;

[0015] A cover plate, which has a transparent optical port area and is used to cover and protect the optical engine and isolate the external environment.

[0016] In an embodiment of the present invention, the substrate has a cavity area for accommodating the PIC module, so that the contact surface between the PIC module and the EIC module and the contact surface between the EIC module and the substrate are on the same horizontal plane.

[0017] In an embodiment of the present invention, the substrate has a hollowed-out area for accommodating the PIC module, so that the contact surface between the PIC module and the EIC module and the contact surface between the EIC module and the substrate are on the same horizontal plane.

[0018] In an embodiment of the present invention, it further includes a TGV adapter board, which is disposed on the substrate and used to connect the EIC module and the substrate. The TGV adapter board has the same thickness as the PIC module and is disposed on the same horizontal plane.

[0019] In an embodiment of the present invention, the EIC module includes:

[0020] Multiple wiring layers, where multiple metal and dielectric layers are alternately stacked to form circuits;

[0021] A chip, and the multiple wiring layers are disposed on the surface of the chip;

[0022] A plastic encapsulation layer that encapsulates the chip and the multiple wiring layers and exposes the top surface of the chip;

[0023] Solder balls, which are used to achieve electrical and mechanical connections between the EIC module and the outside;

[0024] Dummy chips, which are filled in the areas where no electronic chips are placed.

[0025] In an embodiment of the present invention, it further includes an IPD module, and the IPD module is disposed on the silicon substrate of the EIC module and the glass substrate of the TGV adapter board

[0026] The present invention also provides a 3D packaging optical engine packaging method, which is characterized by including:

[0027] Mount the PIC module on the EIC module to form mechanical and electrical connections;

[0028] Flip-chip mount the EIC module onto the substrate so that the EIC module is on the top layer and the PIC module is on the bottom layer;

[0029] Apply a bonding adhesive on the surface of the EIC module and bond the cover plate to the EIC module to form a sealed structure;

[0030] Couple and package the optical engine with external devices.

[0031] In an embodiment of the present invention, the step of flip-chip mounting the EIC module onto the substrate so that the EIC module is on the top layer and the PIC module is on the bottom layer further includes:

[0032] Hollow out or partially hollow out the substrate to accommodate the PIC module so that the contact surface between the PIC module and the EIC module and the contact surface between the EIC module and the substrate are on the same horizontal plane; or

[0033] Mount the TGV adapter board on the substrate using TCB, MR or hybrid bonding process so that the TGV adapter boards with the same thickness are assembled on the same layer as the PIC module.

[0034] In an embodiment of the present invention, it further includes:

[0035] Filling virtual chips in the chipless area of the EIC module;

[0036] Etching different patterns on the silicon substrate of the EIC module using lithography technology, and integrating different passive devices by means of thin film deposition process and forming deep trench capacitors.

[0037] In an embodiment of the present invention, the mounting of the TGV adapter board on the substrate using the TCB, MR or hybrid bonding process further includes:

[0038] Etching different patterns on the glass substrate of the TGV adapter board using lithography technology, and integrating different passive devices by means of thin film deposition process and forming deep trench capacitors.

[0039] The present invention has the following beneficial effects:

[0040] (1) The present invention adopts the structure of stacking EIC on PIC. The EIC is located on the top layer of the optical engine and has the smallest thermal resistance, which is beneficial to the heat dissipation of the EIC.

[0041] (2) By hollowing out the substrate in the present invention, the high-speed line has the shortest routing length, so the loss is the lowest and the process flow is simple. Or by integrating the TGV adapter board on the same layer of the PIC, and using the extremely small feature size (≤5μm) of the TGV, it is beneficial to the miniaturization of the optical engine. Thanks to the fact that the TGV can be fabricated in relatively thick (≥800μm) glass and the substrate is hollowed out, there is no need to thin the optical chip, which greatly alleviates the warping of the PIC.

[0042] (3) The present invention adopts the method of integrating passive devices (IPD) to realize the integration of passive devices. Here, the IPD can be realized on silicon or glass using thin film deposition technology. In addition, the capacitor can adopt deep trench capacitors (DTC). In the present invention, the TGV adapter board not only integrates the TGV, but can also include the IPD. Description of the Drawings

[0043] Figure 1 Shows the schematic diagram of the 3D packaged optical engine structure in an embodiment of the present invention;

[0044] Figure 2 Shows the schematic diagram of the EIC module structure in an embodiment of the present invention;

[0045] Figure 3 Shows the schematic diagram of the 3D packaged optical engine structure in another embodiment of the present invention;

[0046] Figure 4 Shows the flowchart of the 3D packaged optical engine packaging method in an embodiment of the present invention;

[0047] Figure 5 Shows the flowchart of the 3D package optical engine package method in another embodiment of the present invention;

[0048] Figure 6 Shows the flowchart of the 3D package optical engine package method in another embodiment of the present invention;

[0049] Figure 7 Shows the flowchart of the 3D package optical engine package method in another embodiment of the present invention;

[0050] Figure 8 Shows the flowchart of the 3D package optical engine package method in another embodiment of the present invention;

[0051] Figure 9 Shows the flowchart of the EIC module package in one embodiment of the present invention; and

[0052] Figure 10 Shows the flowchart of the EIC module package in another embodiment of the present invention;

[0053] Figure 11 Shows the flowchart of the EIC module package in another embodiment of the present invention;

[0054] Figure 12 Shows the plan view of the 3D package optical engine in one embodiment of the present invention; and

[0055] Figure 13 Shows the schematic diagram of the EIC module integrated IPD in one embodiment of the present invention. Detailed implementation manners

[0056] In the following description, the present invention is described with reference to the embodiments. However, those skilled in the art will recognize that the embodiments can be implemented without one or more specific details or in combination with other alternative and / or additional methods, materials, or components. In other cases, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the inventive points of the present invention. Similarly, for the purpose of explanation, specific quantities, materials, and configurations are set forth to provide a thorough understanding of the embodiments of the present invention. However, the present invention is not limited to these specific details.

[0057] In the present invention, the embodiments are only intended to illustrate the solutions of the present invention and should not be construed as restrictive.

[0058] In the description of the present application, it should be understood that the orientation or positional relationships indicated by the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than explicitly or implicitly indicating that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as explicitly or implicitly indicating relative importance.

[0059] In this specification, the reference to "an embodiment" or "the embodiment" means that the specific features, structures or characteristics described in connection with the embodiment are included in at least one embodiment of the present invention. The phrase "in an embodiment" appearing throughout this specification does not necessarily all refer to the same embodiment.

[0060] In addition, the numbering of the steps of each method of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps can be executed in different orders.

[0061] The present invention will be further described below in conjunction with the specific embodiments with reference to the drawings.

[0062] Figure 1 The schematic structural diagram of a 3D packaged optical engine in an embodiment of the present invention is shown.

[0063] As Figure 1 shown, in this embodiment, the 3D packaged optical engine includes:

[0064] A substrate 10, which undergoes local cavity excavation treatment. The depth of the cavity excavation area is adapted to the thickness of the PIC module. The high-speed lines have the shortest routing length, so the loss is the lowest. The substrate 10 can be formed of one or more of phenolic resin, epoxy resin, and polyimide. The substrate 10 can include, for example, one or more of FR4, tetrafunctional epoxy resin, polyphenylene ether, epoxy / polyphenylene oxide, bismaleimide triazine, polyamide short fiber mat, cyanate ester, polyimide, and liquid crystal polymer. The upper substrate pad, the lower substrate pad, the internal wiring line, and the substrate connection via hole can be formed of one or more of, for example, copper (Cu), nickel (Ni), aluminum (Al), or beryllium (Be) (for example, beryllium copper).

[0065] A PIC module 20, the core of which is a silicon photonics chip (PIC), including optoelectronic devices such as modulators and detectors, and is directly mounted in the cavity of the substrate 10 without thinning (thickness ≥ 800 μm).

[0066] The EIC module 30 integrates electronic chips such as TIA (transimpedance amplifier), Driver (driver chip), ADC / DAC, and MCU. It adopts a 2.5D packaging process (Chip first / die down, Chip first / die up, or Chip Last), with a thickness ≤ 300 μm. In an embodiment of the present invention, its non-chip area is filled with virtual chips to balance the stress distribution and reduce warping deformation caused by material non-uniformity. The EIC module 30 is used to process electrical signals (such as amplification and analog-to-digital conversion), and cooperate with the PIC module 20 to complete optoelectronic conversion. The EIC module 30 is located on the top layer of the optical engine, minimizing the thermal resistance and optimizing the heat dissipation performance.

[0067] The first bonding layer 40 is used to complete the mechanical and electrical connections between the EIC module 30, the substrate 10, and the PIC module 20.

[0068] The bonding adhesive layer 50 uses adhesives such as epoxy resin or silicone rubber, which is coated on the surface of the EIC module 30 to fix the cover plate 60 on the top of the EIC module 30, forming a sealed structure. It protects the internal chips from moisture and dust pollution and enhances the mechanical stability.

[0069] The cover plate 60 is made of metal, ceramic, or glass, and the optical port area is transparent (such as glass). It is used to cover and protect the optical engine and isolate the external environment. The optical port area allows optical signals to penetrate, and the non-optical port area provides electromagnetic shielding.

[0070] Figure 2 It shows a schematic structural diagram of the EIC module in an embodiment of the present invention.

[0071] As Figure 2 shown, in an embodiment of the present invention, the EIC module 30 includes:

[0072] The multi-layer wiring layer 31 is formed by alternately stacking multiple layers of metal (such as copper) and dielectric layers (such as polyimide) to form fine lines. The surface is coated with UBM (Under Bump Metallurgy) for connecting solder balls or bonding bumps.

[0073] The EIC chip 32 includes chips such as TIA, Driver, ADC, DAC, and MCU.

[0074] The plastic encapsulation layer 33 is used to encapsulate the multi-layer wiring layer 31 and the EIC chip 32.

[0075] The solder balls 34 are used to connect the EIC module 30 to other external devices.

[0076] Among them, different passive devices are also integrated on the silicon substrate of the EIC module 30.

[0077] Figure 3 The schematic diagram of the 3D packaging optical engine structure in another embodiment of the present invention is shown.

[0078] In this embodiment, the substrate 10 is not cavity - dug. As Figure 3 shown, the 3D packaging optical engine structure includes:

[0079] Substrate 10, which can be formed by one or more of phenolic resin, epoxy resin, and polyimide. Substrate 10 can include, for example, one or more of FR4, tetra - functional epoxy resin, polyphenylene ether, epoxy / polyphenylene oxide, bismaleimide triazine, polyamide short fiber mat, cyanate ester, polyimide, and liquid crystal polymer. The upper substrate pad, lower substrate pad, internal wiring line, and substrate connection through - hole can be formed by one or more of, for example, copper (Cu), nickel (Ni), aluminum (Al), or beryllium (Be) (for example, beryllium copper).

[0080] TGV interposer 21, including a glass substrate and glass through - vias (TGV). The glass substrate usually adopts high - quality borosilicate glass or quartz glass. The inner wall of the glass through - via is metallized (such as copper), and defect - free filling is achieved through Bottom - up electroplating or butterfly filling process. TGV interposer 21 also includes a stack of multiple layers of metal (copper) and dielectric layers (such as polyimide), supports wiring of more than 5 layers, and also integrates passive devices, resistors, capacitors (such as deep trench capacitors DTC), and inductors, which are integrated on the glass substrate through thin - film deposition process.

[0081] PIC module 20, with a silicon - photonic chip (PIC) as the core, containing optoelectronic devices such as modulators and detectors, directly mounted on substrate 10, and on the same layer as TGV interposer 21. Since TGV can be fabricated in relatively thick (≥800μm) glass, there is no need to thin the optical chip, which greatly alleviates the warping of PIC.

[0082] The second bonding layer 41 is used to bond the TGV interposer 21 and PIC module 20 to substrate 10 to complete mechanical and electrical connections.

[0083] EIC module 30 integrates electronic chips such as TIA (trans - impedance amplifier), Driver (driver chip), ADC / DAC, and MCU. It adopts a 2.5D packaging process (Chip first / die down, Chip first / die up, or Chip Last), with a thickness ≤300μm. Its non - chip area is filled with virtual chips to balance stress distribution and control warping. It is used to process electrical signals (such as amplification, analog - to - digital conversion), and cooperate with PIC module 20 to complete optoelectronic conversion. EIC module 30 is located at the top layer of the optical engine to minimize thermal resistance and optimize heat dissipation performance.

[0084] The bonding adhesive layer 50, made of adhesives such as epoxy resin or silicone rubber, is coated on the surface of the EIC module 30 to fix the cover plate 60 on the top of the EIC module 30, forming a sealed structure to protect the internal chips from moisture and dust pollution and enhance mechanical stability.

[0085] The cover plate 60, made of metal, ceramic or glass, is transparent in the optical port area (such as glass), used to cover and protect the optical engine and isolate the external environment. The optical port area allows optical signals to penetrate, and the non-optical port area provides electromagnetic shielding.

[0086] Figure 4 The flowchart of the 3D packaged optical engine packaging method in an embodiment of the present invention is shown.

[0087] As Figure 4 shown, in this embodiment, the 3D packaged optical engine packaging method is as follows:

[0088] EIC module packaging 100, packaging multiple chips to form an EIC module;

[0089] PIC module packaging 200, performing UBM electroplating and dicing on the silicon photonics chip to form a PIC module;

[0090] PIC module mounting 300, mounting the PIC module to the cavity area of the substrate to form mechanical and electrical connections;

[0091] EIC module mounting 400, mounting the EIC module to the substrate to form electrical connections with the substrate and the PIC module;

[0092] Firmware writing and testing 500, writing the firmware into the chip and performing tests;

[0093] Covering 600, applying a bonding adhesive on the surface of the EIC module and fitting the cover plate to the EIC module to form a sealed structure;

[0094] Coupling packaging 700, coupling and packaging the optical engine with external devices.

[0095] In this embodiment, the method of first mounting the PIC module to the substrate and then mounting the EIC module is adopted.

[0096] Figure 5 The flowchart of the 3D packaged optical engine packaging method in another embodiment of the present invention is shown.

[0097] In this embodiment, the method of first mounting the PIC module to the EIC module and then mounting the whole to the substrate is adopted. As Figure 5 shown, the 3D packaged optical engine packaging method is as follows:

[0098] EIC module packaging 100, packaging multiple chips to form an EIC module;

[0099] PIC module packaging 200, perform UBM electroplating and dicing on the silicon photonic chip to form a PIC module;

[0100] PIC module mounting 310, mount the PIC module onto the EIC module to form a mechanical and electrical connection;

[0101] Chip mounting 410, mount the EIC module together with the PIC module onto the substrate to form an electrical connection with the substrate and the PIC module, where the substrate is cavity-machined, and the cavity is used to accommodate the PIC module;

[0102] Firmware writing and testing 500, write the firmware into the chip and perform testing;

[0103] Covering 600, apply a bonding adhesive on the surface of the EIC module, and bond the cover plate onto the EIC module to form a sealed structure;

[0104] Coupling packaging 700, couple and package the optical engine with external devices.

[0105] In the above two embodiments, the substrate 10 is cavity-machined. Next, the 3D packaging method of the optical engine will be described for the embodiment using the TGV adapter board 21.

[0106] Figure 6 The flowchart of the 3D packaging method of the optical engine in another embodiment of the present invention is shown.

[0107] As Figure 6 shown, the 3D packaging method of the optical engine is as follows:

[0108] EIC module packaging 100, package multiple chips to form an EIC module;

[0109] PIC module packaging 200, perform UBM electroplating and dicing on the silicon photonic chip to form a PIC module;

[0110] PIC module and TGV adapter board mounting 320, mount the PIC module and the TGV adapter board onto the EIC module through a hybrid bonding process;

[0111] Chip mounting 420, mount the above-mounted EIC module onto the substrate, with the PIC module and the TGV adapter board at the bottom layer and the EIC module at the top layer;

[0112] Firmware writing and testing 500, write the firmware into the chip and perform testing;

[0113] Covering 600, apply a bonding adhesive on the surface of the EIC module, and bond the cover plate onto the EIC module to form a sealed structure;

[0114] Coupling encapsulation 700 couples and encapsulates the optical engine with external devices.

[0115] In step 320, the interconnection of the TGV adapter board, PIC, and EIC module can also be achieved through the TCB / MR process.

[0116] Figure 7 The flowchart of the 3D packaged optical engine packaging method in another embodiment of the present invention is shown.

[0117] As Figure 7 shown, the 3D packaged optical engine packaging method is as follows:

[0118] EIC module packaging 100 packages multiple chips to form an EIC module;

[0119] PIC module packaging 200 performs UBM electroplating and dicing on the silicon photonics chip to form a PIC module;

[0120] PIC module and TGV adapter board mounting 330 mounts the PIC module and TGV adapter board to the EIC module through the TCB / MR process;

[0121] Chip mounting 420 mounts the above-mounted EIC module on a substrate, with the PIC module and TGV adapter board at the bottom layer and the EIC module at the top layer;

[0122] Firmware writing and testing 500 writes firmware into the chip and conducts tests;

[0123] Covering 600 applies a bonding adhesive on the surface of the EIC module and bonds the cover plate to the EIC module to form a sealed structure;

[0124] Coupling encapsulation 700 couples and encapsulates the optical engine with external devices.

[0125] Figure 8 The flowchart of the 3D packaged optical engine packaging method in another embodiment of the present invention is shown.

[0126] Compared with Figure 4 and Figure 5 where the substrate is cavity-machined, in this embodiment, the substrate is directly hollowed out, which is also used to accommodate the PIC module.

[0127] EIC module packaging 100 packages multiple chips to form an EIC module;

[0128] PIC module packaging 200 performs UBM electroplating and dicing on the silicon photonics chip to form a PIC module;

[0129] PIC module mounting 310 mounts the PIC module on the EIC module to form mechanical and electrical connections;

[0130] The chip mounting 430 mounts the EIC module together with the PIC module onto the substrate, forming an electrical connection with the substrate and the PIC module. The substrate is hollowed out to accommodate the PIC module.

[0131] The firmware flashing and testing 500 writes the firmware into the chip and conducts tests.

[0132] The capping 600 applies a bonding adhesive on the surface of the EIC module and bonds the cover plate to the EIC module to form a sealed structure.

[0133] The coupling and encapsulation 700 couples and encapsulates the optical engine with external devices.

[0134] Figure 9 It shows the EIC module packaging flow chart in an embodiment of the present invention.

[0135] As Figure 9 shown, packaging multiple chips to form an EIC module includes:

[0136] The EIC mounting 110 bonds the EIC chip to the first temporary carrier.

[0137] The plastic encapsulation and thinning 120 plastic-encapsulates the EIC chip and thins it to expose the top surface of the EIC chip.

[0138] The debonding and bonding 130 debonds the EIC chip from the first temporary carrier and inverts and bonds it to the second temporary carrier.

[0139] The multi-layer RDL and UBM electroplating process 140 generates multiple wiring layers on the active surface of the EIC chip and conducts UBM electroplating.

[0140] The ball mounting 150 conducts ball mounting on the multiple wiring layers.

[0141] The debonding and dicing 160 debonds the EIC chip from the second temporary carrier and conducts dicing.

[0142] In the embodiment of the present invention, the temporary carrier is generally a glass carrier, and other materials can also be selected for the carrier, such as single-crystalline silicon wafers, organic substrates, metal substrates, ceramic substrates, substrates composed of a composite of an organic substrate and a metal substrate, or other similar materials. Those skilled in the art should understand that as long as it has a flat surface with specific strength, it can be used as the carrier of the present invention.

[0143] In this embodiment, the temporary bonding is performed through a temporary bonding film. The temporary bonding film is a thermoplastic or thermosetting organic material, or can also be an inorganic material containing components such as Cu, Ni, Cr, Co, etc. The temporary bonding film can be removed by heating, mechanical means, chemical means, laser, freezing, etc.

[0144] Figure 10 Shows the EIC module packaging flow chart in another embodiment of the present invention.

[0145] As Figure 10 shown, in this embodiment, the EIC module packaging process is as follows:

[0146] EIC mounting 111, mounting the EIC chip with copper pillars onto the first temporary carrier;

[0147] Molding 121, molding the EIC chip to form a molding layer;

[0148] Multi-layer RDL and UBM electroplating treatment 131, performing multi-layer RDL and UBM treatment to generate multiple wiring layers;

[0149] Ball planting 141, performing ball planting treatment on the multiple wiring layers;

[0150] Debonding and bonding 151, debonding from the first temporary carrier and inverting and bonding the chip to the second temporary carrier;

[0151] Thinning, debonding and dicing 161, thinning the molding layer to expose the top surface of the chip, debonding from the second temporary carrier and performing dicing treatment to complete the EIC module packaging.

[0152] Figure 11 Shows the EIC module packaging flow chart in another embodiment of the present invention.

[0153] As Figure 11 shown, in this embodiment, the EIC module packaging process is as follows:

[0154] Multi-layer RDL and UBM electroplating treatment 112, generating multiple wiring layers on the temporary carrier;

[0155] C2W chip mounting 122, mounting the EIC chip onto the multiple wiring layers through C2W;

[0156] Molding and thinning 132, molding the EIC chip and the multiple wiring layers and thinning to expose the top surface of the chip;

[0157] Debonding 142, debonding the molded chip from the temporary carrier;

[0158] Ball planting and dicing 152, performing ball planting on the multiple wiring layers and performing dicing treatment to complete the EIC module packaging.

[0159] Figure 12 Shows the plan view of a 3D packaged optical engine in an embodiment of the present invention.

[0160] As Figure 12As shown, the red area is the C4 bump area or the TGV adapter board, the blue area is the PIC module, and the green is the EIC module. The C4 bump area or the TGV adapter board is located on two or three sides of the 3D optical engine. The area without chips in the EIC module needs to be filled with Dumy Die virtual chips to control warping. This is just one implementation case. The actual layout of the EIC needs to consider factors such as chip size and the layout of devices inside the optical chip.

[0161] Figure 13 The figure shows a schematic diagram of the integration of IPD in the EIC module in an embodiment of the present invention.

[0162] As Figure 13 shown, in the EIC module, through the IPD chip, different patterns are etched on the silicon substrate using the process of a foundry, and photolithography technology is employed. Using the thin film deposition process, and the capacitor can be in the form of a deep trench capacitor (DTC) to form different devices, thus achieving high-density integration such as resistors, capacitors, and inductors, further reducing the volume of the module. The following is just an example of integrating the IPD chip in one of the above examples, and other layouts can also integrate the IPD chip. In addition, the number and size of the IPD can be adjusted according to needs. In addition, in the present invention, the TGV adapter board not only integrates TGV, but can also include IPD, and the TGV adapter board IPD is realized by using the thin film deposition process.

[0163] In this embodiment, the EIC module integrates IPD passive devices on the silicon substrate. In another embodiment of the present invention, different patterns can also be etched on the glass substrate of the TGV adapter board using photolithography technology, and different passive devices can be integrated by using the thin film deposition process and the method of forming deep trench capacitors.

[0164] Although the above describes various embodiments of the present invention, it should be understood that they are presented only as examples and not as limitations. It will be apparent to those skilled in the relevant art that various combinations, modifications, and changes can be made without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the above-disclosed exemplary embodiments, but should be defined only by the appended claims and their equivalents.

Claims

1. A 3D packaged optical engine, characterized in that, Comprising: A PIC module for realizing the emission, reception, and modulation of optical signals; An EIC module for processing electrical signals and collaborating with the PIC module to complete optoelectronic conversion, and the PIC module is mounted on the EIC module; A substrate, on which the EIC module is flip-chip mounted; An adhesive layer coated on the surface of the EIC module for fixing a cover plate on the top of the EIC module to form a sealed structure; A cover plate with a transparent optical port area for covering and protecting the optical engine and isolating the external environment.

2. The 3D packaged optical engine according to claim 1, wherein The substrate has a cavity area for accommodating the PIC module, so that the contact surface between the PIC module and the EIC module and the contact surface between the EIC module and the substrate are on the same horizontal plane.

3. The 3D packaged optical engine according to claim 1, wherein The substrate has a hollowed-out area for accommodating the PIC module, so that the contact surface between the PIC module and the EIC module and the contact surface between the EIC module and the substrate are on the same horizontal plane.

4. The 3D packaged optical engine according to claim 1, characterized in that, It further includes a TGV adapter board arranged on the substrate for connecting the EIC module and the substrate, and the TGV adapter board has the same thickness as the PIC module and is arranged on the same horizontal layer.

5. The 3D packaged optical engine according to claim 1, wherein, The EIC module includes: Multiple wiring layers, with multiple layers of metal and dielectric layers stacked alternately to form circuits; A chip, on the surface of which the multiple wiring layers are arranged; A plastic encapsulation layer covering the chip and the multiple wiring layers and exposing the top surface of the chip; Solder balls for realizing the electrical and mechanical connection between the EIC module and the outside; Virtual chips filled in the areas without electronic chips.

6. The 3D packaged optical engine according to claim 4 to 5, characterized in that, It further includes an IPD module, and the IPD module is arranged on the silicon substrate of the EIC module and the glass substrate of the TGV adapter board.

7. A 3D packaging method for an optical engine, characterized in that, Comprising: Mounting the PIC module onto the EIC module to form a mechanical and electrical connection; Flip-chip mounting the EIC module onto the substrate so that the EIC module is on the top layer and the PIC module is on the bottom layer; Coating an adhesive on the surface of the EIC module and fitting the cover plate onto the EIC module to form a sealed structure; Coupling and encapsulating the optical engine with external devices.

8. The 3D packaging optical engine packaging method according to claim 7, characterized in that, The step of flip-chip mounting the EIC module onto the substrate so that the EIC module is on the top layer and the PIC module is on the bottom layer further includes: Performing cavity digging or partial hollowing on the substrate to accommodate the PIC module, so that the contact surface between the PIC module and the EIC module and the contact surface between the EIC module and the substrate are on the same horizontal plane; or Mounting the TGV adapter board on the substrate by using TCB, MR, or hybrid bonding process, so that a TGV adapter board with the same thickness is assembled on the same layer as the PIC module.

9. The 3D package optical engine packaging method according to claim 7, characterized in that, It further includes: Filling virtual chips in the area without chips of the EIC module; Using photolithography technology to etch different patterns on the silicon substrate of the EIC module, and integrating different passive devices by using thin film deposition technology and the method of forming deep trench capacitors.

10. The 3D packaged optical engine packaging method according to claim 7, wherein The step of mounting the TGV adapter board on the substrate by using TCB, MR, or hybrid bonding process further includes: Using photolithography technology to etch different patterns on the glass substrate of the TGV adapter board, and integrating different passive devices by using thin film deposition technology and the method of forming deep trench capacitors.

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