A wafer-level inductor packaging structure and its preparation method

Abstract

The present invention provides a wafer-level inductor packaging structure and a method for manufacturing the same. The packaging structure includes an interposer, an electromagnetic bump, a plastic encapsulation body, a plastic encapsulation portion, and a third functional chip. Two plastic encapsulation bodies are provided. After being rotated 90 degrees, the plastic encapsulation bodies are perpendicularly positioned in front of the interposer and symmetrically arranged on either side of the electromagnetic bump, with the first and second left side wall metal layers facing the front of the interposer. The first and second left side wall metal layers in the plastic encapsulation bodies are electrically connected to the electromagnetic bump via the interposer. The plastic encapsulation portion covers the two plastic encapsulation bodies and the electromagnetic bump, and the third functional chip is integrated on the surfaces of the first and second right side wall metal layers. The wafer-level inductor packaging structure provided by the present invention achieves high-density integration of six chips within a limited space, significantly reducing the package size, and is simple to manufacture.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and more particularly to a wafer-level inductor packaging structure and a preparation method thereof. Background Art

[0002] In today's semiconductor industry, electronic packaging technology has become an indispensable and important aspect driving the development of the entire industry. After decades of continuous evolution, packaging technology has made significant progress, making high-density, high-performance packaging requirements gradually become the mainstream development trend in the packaging field.

[0003] Fan-out wafer-level packaging technology, an embedded packaging format implemented during wafer-level processing, not only represents a major innovation in packaging technology but also represents a key advanced packaging process offering high I / O counts and exceptional integration flexibility. With its unique technological advantages, it plays an increasingly important role in meeting the high-performance and miniaturization demands of modern electronic products.

[0004] In today's packaging technology landscape, achieving high levels of system integration and high-density interconnection to meet the increasingly complex functional requirements of semiconductor electronics, improve product performance, increase packaging density, and enhance electrical transmission efficiency have become the most critical and influential technical solutions for high-end semiconductor products. These solutions not only represent the latest developments in semiconductor packaging technology but also represent the technical challenges that semiconductor manufacturers are actively investing R&D resources to overcome. They are leading the direction of contemporary semiconductor research and providing a powerful impetus for the industry's continued progress and innovation.

[0005] Existing wafer-level inductor packaging is mostly a planar inductor structure, using wafer-level photolithography and electroplating processes to create a planar spiral coil on the wafer, or using high-permeability materials between layers. This method and structure are limited by area, making it difficult to increase inductance and dissipate heat. Summary of the Invention

[0006] In order to solve the above problems, the present invention provides a high-density wafer-level inductor packaging structure and a preparation method thereof, and the wafer-level inductor packaging structure can increase the inductance and has excellent heat dissipation performance.

[0007] In a first aspect, the present invention discloses a wafer-level inductor packaging structure, comprising:

[0008] an interposer having a front side and a back side for support and electrical connection;

[0009] The electromagnetic bump is provided on the front surface of the interposer;

[0010] A plastic package body having a substrate wafer, a first functional chip arranged on the front side of the substrate wafer, and a second functional chip arranged on the back side of the substrate wafer; a plurality of through-silicon vias are arranged in the substrate wafer; the first functional chip and the second functional chip are connected via the through-silicon vias; the first functional chip has a first left-side wall metal layer and a first right-side wall metal layer electrically connected to the outside; the second functional chip has a second left-side wall metal layer and a second right-side wall metal layer electrically connected to the outside; two plastic packages are provided, which are rotated 90 degrees and arranged perpendicularly on the front side of the interposer and symmetrically arranged on both sides of the electromagnetic bump, so that the first left-side wall metal layer and the second left-side wall metal layer face the front side of the interposer; the first left-side wall metal layer and the second left-side wall metal layer in the plastic package are electrically connected to the electromagnetic bump through the interposer;

[0011] A plastic sealing portion is formed on the front surface of the interposer, covering the two plastic sealing bodies and the electromagnetic bump, with the first right side wall metal layer and the second right side wall metal layer of the two plastic sealing bodies exposed; a second redistribution metal layer is formed on the surfaces of the first right side wall metal layer and the second right side wall metal layer;

[0012] The third functional chip is integrated on the surface of the first right side wall metal layer and the second right side wall metal layer of the two plastic packaging bodies, and is electrically connected to the first right side wall metal layer and the second right side wall metal layer through the second redistribution metal layer to form a wafer-level inductor packaging structure.

[0013] Preferably, solder balls are provided on the back side of the interposer for electrical connection with an external circuit.

[0014] Preferably, the interposer layer is a mixed structure of an organic medium and a rewiring metal layer.

[0015] Preferably, the electromagnetic bump is made of NiFe material having electromagnetic properties.

[0016] Preferably, the first function chip and the second function chip are memory chips with storage functions; and the third function chip is a chip with a SOC processor.

[0017] In a second aspect, the present invention further provides a method for preparing the above-mentioned wafer-level inductor packaging structure, which comprises the following steps:

[0018] S1. Providing an interposer, wherein the interposer has a front side and a back side, and the front side of the interposer has a first redistribution metal layer for electrical connection;

[0019] S2, electroplating a NiFe material having electromagnetic properties on the surface of the first redistribution metal layer to form an electromagnetic bump;

[0020] S3. Provide two plastic encapsulation bodies with the same structure. The plastic encapsulation bodies are rotated 90 degrees and vertically arranged on the first redistribution metal layer on the front side of the interposer, and are symmetrically arranged on both sides of the electromagnetic bump. The method for preparing the plastic encapsulation bodies is as follows:

[0021] A. Providing a substrate wafer having a plurality of through-silicon vias, connecting a first functional chip on the front side of the substrate wafer, and connecting a second functional chip on the back side of the substrate wafer;

[0022] B. A first left-side metal layer and a first right-side metal layer are formed on both sidewalls of the first functional chip for external electrical connection, and a second left-side metal layer and a second right-side metal layer are formed on both sidewalls of the second functional chip for external electrical connection;

[0023] Wherein, after the plastic package body is rotated 90 degrees, the first left side wall metal layer and the second left side wall metal layer in the plastic package body face the front of the interposer, and the first left side wall metal layer and the second left side wall metal layer are electrically connected to the electromagnetic bump through the first redistribution metal layer;

[0024] S4. Plastic-encapsulate the front side of the interposer, and use the plastic-encapsulation material to cover the two plastic-encapsulated bodies and the electromagnetic bump to form a plastic-encapsulated portion. Grind the top of the plastic-encapsulated portion to expose the first right side wall metal layer and the second right side wall metal layer of the plastic-encapsulated body.

[0025] S5. Form a second redistribution metal layer on the surfaces of the first right side wall metal layer and the second right side wall metal layer, connect a third functional chip on the surface of the second redistribution metal layer, perform a ball planting process on the back side of the interposer to form solder balls, and complete the preparation of the wafer-level inductor packaging structure.

[0026] Preferably, the molding material is epoxy molding material.

[0027] Preferably, the interposer is a glass interposer or a silicon interposer.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] 1. The plastic package of the present invention realizes double-sided functional chip integration, with high integration, making the package volume and floor space smaller; the first functional chip and the second functional chip are directly interconnected through silicon vias of the substrate wafer, which shortens the interconnection length, significantly reduces the signal transmission delay between the first functional chip and the second functional chip, and improves the stability of the connection;

[0030] 2. The present invention rotates the plastic package body 90 degrees and places it vertically on the front of the interposer. Together with the third functional chip on the top, it surrounds the electromagnetic bumps, thus realizing a vertical chip 3D inductor packaging structure and enhancing the performance of the inductor packaging structure.

[0031] 3. The wafer-level inductor packaging structure provided by the present invention achieves high-density integration of six chips in a limited space, significantly reducing the package size, and the preparation method is simple;

[0032] 4. Compared with traditional planar inductors, the three-dimensional inductor structure provided by the present invention increases the effective flux linkage by expanding the vertical dimension of the magnetic flux path, thereby improving the inductance;

[0033] 5. In the wafer-level inductor packaging structure provided by the present invention, each functional chip can achieve effective heat dissipation. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 Schematic diagram of the wafer-level inductor packaging structure in Example 1 of the present invention;

[0035] Figure 2 Schematic diagram of the structure of the glass interposer in Example 2 of the present invention;

[0036] Figure 3 For Figure 2 Schematic diagram of the structure in which the electromagnetic bumps are electroplated;

[0037] Figure 4 Schematic diagram of the structure of the plastic package body in Example 2 of the present invention;

[0038] Figure 5 Schematic diagram of the structure of the substrate wafer in Example 2 of the present invention;

[0039] Figure 6 For Figure 5 A schematic diagram of bonding the first functional chip in the structure shown;

[0040] Figure 7 For Figure 3 The structure shown is a schematic diagram of a plastic package body connected to the structure rotated 90 degrees;

[0041] Figure 8 For Figure 7 Schematic diagram of the structure after plastic packaging.

[0042] Explanation of the reference numerals: interposer 1; front surface 101; back surface 102; first redistribution metal layer 103; glass wafer 104; electromagnetic bump 2; plastic package 3; substrate wafer 31; through-silicon via 310; first functional chip 32; second functional chip 33; first left side wall metal layer 320; first right side wall metal layer 321; second left side wall metal layer 330; second right side wall metal layer 331; plastic package 4; second redistribution metal layer 5; third functional chip 6; solder ball 7. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0044] Example 1

[0045] like Figure 1 As shown, this embodiment discloses a wafer-level inductor packaging structure, which includes:

[0046] Interposer 1, having a front side 101 and a back side 102, for support and electrical connection;

[0047] The electromagnetic bump 2 is provided on the front surface 101 of the interposer 1;

[0048] The plastic package 3 comprises a substrate wafer 31, a first functional chip 32 disposed on the front surface of the substrate wafer 31, and a second functional chip 33 disposed on the back surface of the substrate wafer 31. The substrate wafer 31 is provided with a plurality of through-silicon vias 310, and the first functional chip 32 and the second functional chip 33 are connected via the through-silicon vias 310. The first functional chip 32 also comprises a first left-side metal layer 320 and a first right-side metal layer 321 for external electrical connection, and the second functional chip 33 comprises a second left-side metal layer 330 and a second right-side metal layer 331 for external electrical connection. The plastic package 3 is provided with two plastic packages. The plastic package 3 is rotated 90 degrees and is disposed perpendicularly to the front surface 101 of the interposer 1. The plastic packages are symmetrically arranged on both sides of the electromagnetic bump 2, so that the first left-side metal layer 320 and the second left-side metal layer 330 face the front surface 101 of the interposer 1. The first left-side metal layer 320 and the second left-side metal layer 330 in the plastic package 3 are electrically connected to the electromagnetic bump 2 via the interposer 1.

[0049] The plastic sealing portion 4 is formed on the front surface 101 of the interposer 1, covering the two plastic sealing bodies 3 and the electromagnetic bump 2, with the first right side wall metal layer 321 and the second right side wall metal layer 331 of the two plastic sealing bodies 3 exposed; a second redistribution metal layer 5 is formed on the surfaces of the first right side wall metal layer 321 and the second right side wall metal layer 331;

[0050] The third functional chip 6 is integrated on the surface of the first right side wall metal layer 321 and the second right side wall metal layer 331 of the two plastic packaging bodies 3, and is electrically connected to the first right side wall metal layer 321 and the second right side wall metal layer 331 through the second redistribution metal layer 5. A solder ball 7 is provided on the back side 102 of the interposer 1, forming a wafer-level inductor packaging structure.

[0051] The interposer 1 is a hybrid structure of an organic dielectric and a rewiring metal layer. This structure is a PI / RDL structure, where PI stands for polyimide and RDL stands for rewiring metal layer. The PI / RDL structure in this embodiment can be a multi-layer interposer 1 structure consisting of a layer of PI and a layer of metal alternating. The advantages of the PI / RDL structure are small size and good performance. For detailed information on the PI / RDL structure, please refer to relevant records in the prior art and will not be elaborated in this embodiment.

[0052] In this embodiment, the first function chip 32 and the second function chip 33 are memory chips with storage functions; and the third function chip 6 is a chip with a SOC processor.

[0053] In a specific implementation, the distance between the plastic package body 3 and the electromagnetic bump 2 is greater than 100 microns.

[0054] In a specific implementation, the two plastic packaging bodies 3 can each be connected to a third functional chip 6 , or can be jointly connected to a third functional chip 6 , which is not limited here.

[0055] In this embodiment, other circuits can be connected via the solder balls 7 on the back side 102 of the interposer 1. The wafer-level inductor packaging structure provided by the present invention achieves high-density integration of six chips in a limited space, significantly reducing the package size.

[0056] In this embodiment, the plastic package body 3 is rotated 90 degrees and then vertically arranged on the front surface 101 of the interposer 1, and the third functional chip 6 on the top surrounds the electromagnetic bump 2, thereby realizing a vertical chip inductor 3D packaging structure and enhancing the performance of the inductor packaging structure.

[0057] Example 2

[0058] This embodiment provides a method for preparing the wafer-level inductor packaging structure described in Example 1, which includes the following steps:

[0059] S1 . Provide an interposer 1 . The interposer 1 has a front side 101 and a back side 102 . The front side 101 of the interposer 1 has a first redistribution metal layer 103 for electrical connection.

[0060] S2 , electroplating a NiFe material with electromagnetic properties on the surface of the first redistribution metal layer 103 to form an electromagnetic bump 2 ; the electromagnetic bump 2 is used to subsequently form an inductor structure.

[0061] S3, providing two plastic packaging bodies 3 with the same structure, which are rotated 90 degrees and arranged vertically on the first redistribution metal layer 103 on the front surface 101 of the interposer 1, and symmetrically arranged on both sides of the electromagnetic bump 2;

[0062] Among them, after the plastic package body 3 is rotated 90 degrees, the first left side wall metal layer 320 and the second left side wall metal layer 330 in the plastic package body 3 face the front surface 101 of the interposer 1, and the first left side wall metal layer 320 and the second left side wall metal layer 330 are electrically connected to the electromagnetic bump 2 through the first redistribution metal layer 103; forming Figure 7 In this step, part of the I / O interfaces of the first function chip and the second function chip are creatively arranged on the sidewalls at both ends of the chip by rewiring.

[0063] S4, plastic-sealing the front side 101 of the intermediary layer 1, and coating the two plastic-sealed bodies 3 and the electromagnetic bump 2 with plastic-sealed materials to form a plastic-sealed portion 4, as shown in FIG. Figure 8 The plastic encapsulation part 4 can protect each chip from the external environment and ensure a reliable electrical connection between each chip and the interposer 1. The plastic encapsulation material is an epoxy plastic encapsulation material.

[0064] S5, grinding the top of the plastic sealing part 4 to expose the first right side wall metal layer 321 and the second right side wall metal layer 331 of the plastic sealing body 3, forming a second redistribution metal layer 5 on the surface of the first right side wall metal layer 321 and the second right side wall metal layer 331, and connecting the third functional chip 6 on the surface of the second redistribution metal layer 5; grinding the glass wafer 104 of the interposer 1 to expose the bottom surface of the first redistribution metal layer 103, and performing a ball planting process on the back surface 102 of the interposer 1 (i.e., the bottom surface of the first redistribution metal layer 103) to form a solder ball 7, and obtaining the following Figure 1 The wafer-level inductor packaging structure shown.

[0065] In step S1, the interposer 1 may be a glass interposer or a silicon interposer. In this embodiment, the glass interposer is taken as an example. Figure 2 A release layer (bonding glue) is applied on the glass wafer 104 , and then a first redistribution metal layer 103 is formed through processes such as sputtering, photolithography, electroplating, and cleaning, for connecting the vertical plastic package 3 and the electromagnetic bump 2 .

[0066] The surface of the first redistribution metal layer 103 is plated with the structure of the electromagnetic bump 2 as shown in FIG. Figure 3 shown.

[0067] In step S3, the structure of the plastic package body 3 is as follows Figure 4 As shown, it needs to be prepared in advance, and the preparation method is:

[0068] A. Provide a substrate wafer 31 having multiple through silicon vias 310 TSVs. Perform a copper reveal process on the substrate wafer 31, such as Si Etch (silicon etching), PECVD (plasma enhanced chemical vapor deposition), CMP (chemical polishing), and other fine steps to expose the silicon surface. Immerse the processed wafer in a plating solution containing copper, nickel, and gold plasma. Through the action of electric current, the copper ions are reduced to metallic copper on specific areas of the wafer and deposited to form metal bumps. Then perform plasma cleaning to remove residual plating solution and impurities on the surface, forming a metal bump. Figure 5 The structure shown;

[0069] Under high temperature and high pressure conditions, multiple first function chips 32 are bonded to the front side of the substrate wafer 31 through metal bumps to form a Figure 6The structure shown in the figure takes a single first functional chip 32 as an example. During the bonding process, the temperature and pressure need to be precisely controlled to ensure the bonding quality and efficiency. After the bonding is completed, appearance inspection and solder joint testing are required to ensure the bonding quality. Preheating and baking the first functional chip 32 can facilitate the fluidity of the filling glue. Use a dispensing machine to apply the bottom filling glue to the specified position of the first functional chip 32 according to the settings. Use the capillary effect to allow the bottom filling glue to naturally diffuse and fill the gap between the first functional chip 32 and the substrate wafer 31, and ensure that the filling is uniform and without omissions. Place the filled first functional chip 32 in a heating device and bake it at high temperature to accelerate the curing process of the glue. Using the same method, connect the second functional chip 33 to the back of the substrate wafer 31; finally, use a dicing machine to cut it into single pieces to form the following. Figure 4 The structure of the plastic package 3 is shown.

[0070] B. After cutting, the side walls of the first functional chip 32 at both ends form a first left wall metal layer 320 and a first right wall metal layer 321 for external electrical connection, and the side walls of the second functional chip 33 at both ends form a second left wall metal layer 330 and a second right wall metal layer 331 for external electrical connection; wherein, when designing RDL, the first functional chip 32 and the second functional chip 33 will exceed the chip boundary and be made on the cutting path, and when they are cut into single chips, chips with metal side walls will be formed. Other technical solutions that can form side walls with metal layers are also acceptable.

[0071] Two plastic packaging bodies 3 with the same structure are rotated 90 degrees and then vertically arranged on the first redistribution metal layer 103 on the front surface 101 of the interposer 1 and symmetrically arranged on both sides of the electromagnetic bump 2;

[0072] After the plastic package body 3 is rotated 90 degrees, the first left side wall metal layer 320 and the second left side wall metal layer 330 in the plastic package body 3 face the front surface 101 of the interposer 1, and the first left side wall metal layer 320 and the second left side wall metal layer 330 are electrically connected to the electromagnetic bump 2 through the first redistribution metal layer 103.

[0073] The plastic package body 3 in this embodiment realizes double-sided functional chip integration with high integration, making the package volume and footprint smaller; the first functional chip 32 and the second functional chip 33 are directly interconnected through the silicon via 310 of the substrate wafer 31, which reduces the interconnection length, significantly reduces the signal transmission delay between the first functional chip 32 and the second functional chip 33, and improves the stability of the connection.

[0074] The above are only some embodiments of the present invention. It should be pointed out that for ordinary technicians in this field, other variations and improvements can be made without departing from the creative concept of the present invention, and these all fall within the scope of protection of the present invention.

Claims

1. A wafer-level inductor packaging structure, characterized in that: include: an interposer having a front side and a back side for support and electrical connection; The electromagnetic bump is provided on the front surface of the interposer; A plastic package body having a substrate wafer, a first functional chip arranged on the front side of the substrate wafer, and a second functional chip arranged on the back side of the substrate wafer; a plurality of through-silicon vias are arranged in the substrate wafer; the first functional chip and the second functional chip are connected via the through-silicon vias; the first functional chip has a first left-side wall metal layer and a first right-side wall metal layer electrically connected to the outside; the second functional chip has a second left-side wall metal layer and a second right-side wall metal layer electrically connected to the outside; two plastic packages are provided, which are rotated 90 degrees and arranged perpendicularly on the front side of the interposer and symmetrically arranged on both sides of the electromagnetic bump, so that the first left-side wall metal layer and the second left-side wall metal layer face the front side of the interposer; the first left-side wall metal layer and the second left-side wall metal layer in the plastic package are electrically connected to the electromagnetic bump through the interposer; A plastic sealing portion is formed on the front side of the interposer, covering the two plastic sealing bodies and the electromagnetic bump, with the first right side wall metal layer and the second right side wall metal layer of the two plastic sealing bodies exposed; forming a second redistribution metal layer on surfaces of the first right side wall metal layer and the second right side wall metal layer; The third functional chip is integrated on the surface of the first right side wall metal layer and the second right side wall metal layer of the two plastic packaging bodies, and is electrically connected to the first right side wall metal layer and the second right side wall metal layer through the second redistribution metal layer to form a wafer-level inductor packaging structure.

2. The wafer-level inductor packaging structure according to claim 1, wherein: The back of the interposer is provided with solder balls for electrically connecting with an external circuit.

3. The wafer-level inductor packaging structure according to claim 2, wherein: The interposer is a mixed structure of an organic medium and a rewiring metal layer.

4. The wafer-level inductor packaging structure according to claim 3, wherein: The electromagnetic bump is made of NiFe material with electromagnetic properties.

5. The wafer-level inductor packaging structure according to claim 4, characterized in that: The first function chip and the second function chip are memory chips with storage functions; the third function chip is a chip with a SOC processor.

6. The method for preparing a wafer-level inductor packaging structure according to any one of claims 1 to 5, wherein: The following steps are involved: S1. Providing an interposer, wherein the interposer has a front side and a back side, and the front side of the interposer has a first redistribution metal layer for electrical connection; S2, electroplating a NiFe material having electromagnetic properties on the surface of the first redistribution metal layer to form an electromagnetic bump; S3. Provide two plastic encapsulation bodies with the same structure. The plastic encapsulation bodies are rotated 90 degrees and vertically arranged on the first redistribution metal layer on the front side of the interposer, and are symmetrically arranged on both sides of the electromagnetic bump. The method for preparing the plastic encapsulation bodies is as follows: A. Providing a substrate wafer having a plurality of through-silicon vias, connecting a first functional chip on the front side of the substrate wafer, and connecting a second functional chip on the back side of the substrate wafer; B. A first left-side metal layer and a first right-side metal layer are formed on both sidewalls of the first functional chip for external electrical connection, and a second left-side metal layer and a second right-side metal layer are formed on both sidewalls of the second functional chip for external electrical connection; Wherein, after the plastic package body is rotated 90 degrees, the first left side wall metal layer and the second left side wall metal layer in the plastic package body face the front of the interposer, and the first left side wall metal layer and the second left side wall metal layer are electrically connected to the electromagnetic bump through the first redistribution metal layer; S4. Plastic-encapsulate the front side of the interposer, and use the plastic-encapsulation material to cover the two plastic-encapsulated bodies and the electromagnetic bump to form a plastic-encapsulated portion. Grind the top of the plastic-encapsulated portion to expose the first right side wall metal layer and the second right side wall metal layer of the plastic-encapsulated body. S5. Form a second redistribution metal layer on the surfaces of the first right side wall metal layer and the second right side wall metal layer, connect a third functional chip on the surface of the second redistribution metal layer, perform a ball planting process on the back side of the interposer to form solder balls, and complete the preparation of the wafer-level inductor packaging structure.

7. The preparation method according to claim 6, characterized in that The plastic packaging material is an epoxy plastic packaging material.

8. The preparation method according to claim 7, characterized in that The interposer is a glass interposer or a silicon interposer.

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