Semiconductor packaging structure with glass substrate and packaging method thereof

Abstract

A semiconductor package structure is disclosed that includes a substrate structure including a glass substrate and a through-glass interconnect structure. The glass substrate has a bottom surface and a top surface opposite the bottom surface. The through-glass interconnect structure is located between the top surface of the glass substrate and the bottom surface of the glass substrate and passes through the glass substrate downward from the top surface of the glass substrate to the bottom surface of the glass substrate. The through glass interconnect structure has a flat bottom at the bottom surface of the glass substrate. The semiconductor structure also includes a redistribution layer (RDL) disposed over the top surface of the glass substrate and a semiconductor chip attached to and over the RDL.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and more particularly to a semiconductor package structure and a packaging method thereof. Background Art

[0002] In semiconductor manufacturing processes, the packaging process can encapsulate semiconductor components, such as one or more chips, to form a semiconductor package structure to protect the semiconductor components. Nowadays, the industry is making efforts to develop package structures with excellent characteristics. For example, in 3D semiconductor devices (such as 3D memory devices), it is desirable for the package structure to have many advantageous characteristics, such as low cost, small size, short design time, strong protection, and / or preferred electrical properties (e.g., short electrical connection distance). Summary of the Invention

[0003] Aspects of the present disclosure provide a semiconductor package structure. The semiconductor package structure includes a substrate structure that includes a glass substrate and a through-glass interconnect structure. The glass substrate has a bottom surface and a top surface opposite the bottom surface. The through-glass interconnect structure is located between the top surface and the bottom surface of the glass substrate and extends from the top surface of the glass substrate downward through the glass substrate to the bottom surface of the glass substrate. The through-glass interconnect structure has a flat bottom at the bottom surface of the glass substrate. The semiconductor structure further includes a redistribution layer (RDL) disposed on the top surface of the glass substrate and a semiconductor chip attached to the RDL and located above the RDL.

[0004] Aspects of the present disclosure provide a packaging method. The packaging method may include: providing a glass substrate having a first side and a second side; preprocessing the second side of the glass substrate to form a plurality of notches in the surface of the second side of the glass substrate; and encapsulating a semiconductor chip on the first side of the glass substrate. Hard particles at the interface between the surface of the second side of the glass substrate and the surface of the molding are included in a plurality of notches in the surface of the second side of the glass substrate.

[0005] Aspects of the present disclosure provide a semiconductor package system that includes a semiconductor package structure and a printed circuit board (PCB). The semiconductor package structure is attached to the PCB. Brief Description of the Drawings

[0006] Aspects of the present disclosure can be understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to the standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity in discussion, the dimensions of various features can be increased or decreased. The following drawings are only examples for illustrative purposes according to various disclosed embodiments and are not intended to limit the scope of the present disclosure.

[0007] Figure 1Shows a schematic cross-sectional view of a semiconductor package structure according to an embodiment of the present disclosure.

[0008] Figures 2A - 2G Shows a manufacturing process for fabricating a semiconductor package structure according to an embodiment of the present disclosure.

[0009] Figure 3 Shows a flowchart of a semiconductor packaging process according to an embodiment of the present disclosure. Detailed Description

[0010] Reference will now be made in detail to embodiments of the invention shown in the drawings. Whenever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0011] Although specific configurations and arrangements are discussed, it should be understood that this is for illustrative purposes only. Thus, other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. Additionally, those skilled in the relevant art will recognize that the present disclosure can also be used in a variety of other applications.

[0012] It should be noted that references in the specification to "an embodiment", "embodiments", "exemplary embodiments", "some embodiments", etc., indicate that the described embodiments may include a particular feature, structure, or characteristic, but not necessarily every embodiment includes that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, those skilled in the relevant art will know that such feature, structure, or characteristic can be implemented in connection with other embodiments (whether or not explicitly described).

[0013] Generally, terms can be understood, at least in part, from their usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a" or "the" can also be understood to convey a singular usage or a plural usage. Additionally, the term "based on" can be understood to not necessarily be intended to express a set of exclusive elements, but can allow for the existence of other elements that are not necessarily explicitly described, again depending at least in part on the context.

[0014] It should be readily understood that the meanings of "on", "above", and "over" in the present disclosure should be interpreted in the broadest manner such that "on" not only means "directly on something", but also includes "on something" with intermediate features or layers therebetween, and "above" or "over" not only means "above something" or "over something", but may also include "it is above something" or "it is over something" without intermediate features or layers therebetween (i.e., directly on something).

[0015] In addition, for ease of description, spatial relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (or other) element or feature. Except for the orientation shown in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0016] As used herein, the term "layer" refers to a portion of material including a region having a thickness. The layer may extend over the entire underlying or overlying structure, or may have a scope less than the scope of the underlying or overlying structure. In addition, the layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any horizontal planes at the top and bottom surfaces. The layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and contact layers (wherein interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0017] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter of a component or process step set during the design stage of a product or process, together with a range of values above and / or below the expected value. The range of values may be attributable to minor variations in the manufacturing process or tolerances. As used herein, the term "about" indicates a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" may indicate a value of a given quantity that varies, for example, within 10%–30% of that value (e.g., ±10%, ±20%, or ±30% of that value).

[0018] As used herein, the term "3D memory" refers to a semiconductor device having vertically oriented memory cell transistor strings (referred to herein as "memory strings", such as NAND memory strings) on a laterally oriented substrate such that the memory strings extend in a vertical direction with respect to the substrate. As used herein, the term "vertical / vertically" means nominally perpendicular to the lateral surface of the substrate.

[0019] Figure 1 FIG. shows a schematic cross-sectional view of a semiconductor package structure 100 in accordance with an embodiment of the present disclosure. The semiconductor package structure 100 includes a substrate structure 101, a redistribution layer 201, and an encapsulation layer 301.

[0020] The substrate structure 101 includes a glass substrate 102. The glass substrate 102 may include any suitable type of glass known in the art. Examples of types of glass include photosensitive glass, borosilicate glass, soda-lime glass, quartz, heat-resistant glass, fused quartz, glass-ceramics, or other glass materials. In various embodiments, the thickness of the glass substrate 102 may be in the range of 100 μm to 1500 μm. In some embodiments, the thickness of the glass substrate 102 may be greater than 1500 μm.

[0021] The glass substrate 102 may be formed of bulk transparent glass, which is different from the glass fibers in the reinforced epoxy resin core typically used for encapsulation substrates or printed circuit boards (PCBs). In some embodiments, the glass substrate 102 does not include organic materials. The glass substrate 102 may include any type of bulk amorphous or polycrystalline transparent, opaque, or translucent glass.

[0022] Compared with organic encapsulation substrates or silicon encapsulation substrates, using the glass substrate 102 has many technical advantages. For example, the glass substrate 102 is more rigid than an organic substrate, thus providing better support for the semiconductor package structure 100 and reducing warpage. Due to the high flatness of the glass panel of the glass substrate 102, the glass substrate 102 allows for finer line widths and line spacings in the redistribution layer 201. Compared with a silicon encapsulation substrate, the glass substrate 102 has a smaller dielectric constant and can thus allow high-frequency signal interconnections passing through the glass substrate 102 or located within the redistribution layer 201.

[0023] The substrate structure 101 further includes a plurality of through-glass interconnect structures 111. The glass substrate 102 may include a plurality of through-glass cavities 103. The plurality of through-glass interconnect structures 111 may be formed in the through-glass cavities 103. Each through-glass interconnect structure 111 corresponds to a respective through-glass cavity 103. The glass substrate 102 has a bottom surface 172 and a top surface 171 opposite to the bottom surface 172. The through-glass interconnect structures 111 are positioned between the top surface 171 and the bottom surface 172 of the glass substrate 102 and extend from the top surface 171 of the glass substrate 102 downward through the glass substrate 102 to the bottom surface 172 of the glass substrate 102. In some embodiments, the through-glass interconnect structures 111 may each have a flat bottom 119 at the bottom surface 172 of the glass substrate 102.

[0024] A plurality of conductive structures 132 may be disposed on the bottom surface 172 of the glass substrate 102 and below each through-glass interconnect structure 111. The conductive structures 132 are electrically coupled to the redistribution layer 201 via the through-glass interconnect structures 111.

[0025] The through-glass interconnect structure 111 may include a conductive layer 115 at the sidewall 118 and the flat bottom 119 of the through-glass interconnect structure 111. The conductive layer 115 may include two portions: a sidewall portion 113 formed on the sidewall of the respective through-glass cavity 103, and a bottom portion 114 formed on the bottom of the respective through-glass cavity 103. The sidewall portion 113 and the bottom portion 114 of the through-glass interconnect structure 111 are connected at the bottom edge of the sidewall of the through-glass cavity 103. The bottom encapsulation 114 is also referred to as the conductive pad 114. In some embodiments, the bottom surface of the bottom portion 114 is in the same plane as the bottom surface of the glass substrate 102.

[0026] In various embodiments, the conductive layer 115 may be formed of any suitable conductive material, such as copper, silver, nickel, gold, aluminum, other metals, or combinations thereof. In some embodiments, the thickness of the conductive layer 115 may be in the range of 1 μm to 20 μm. In other embodiments, the thickness of the conductive layer 115 may be thicker than 20 μm. In some examples, the sidewall portion 113 and the bottom portion 114 may have different thicknesses.

[0027] In Figure 1In the example, the sidewall 118 of the through-glass interconnect structure 111 (or the sidewall of the through-glass cavity 103) has a stepped shape. As shown in the cross-sectional view, the left-hand sidewall of the through-glass interconnect structure 111 has a stepped shape 141, and the right-hand sidewall of the through-glass interconnect structure 111 has a stepped shape 142. For example, in the cross-section of the through-glass interconnect structure 111, the upper part of the through-glass interconnect structure 111 has a wider lateral width than the lower part of the through-glass interconnect structure 111. For example, the upper part and the lower part may have different sizes but similar shapes, such as a cylinder, a rectangular prism, a frustum of a cone, etc. Alternatively, the upper part and the lower part may have different shapes. For example, the upper part of the cavity 103 has a cylindrical shape, and the lower part of the cavity 103 has a rectangular prism shape.

[0028] In some embodiments, the sidewall of the through-glass interconnect structure 111 may have a shape with multiple steps. In some embodiments, the sidewall of the through-glass interconnect structure 111 does not have a stepped shape. For example, the through-glass interconnect structure 111 as a whole has a shape such as a cylinder, a prism, a frustum of a cone, etc. In some embodiments, different through-glass interconnect structures 111 may have different sizes because those different through-glass interconnect structures 111 are used for different purposes, such as signal or power transmission. For example, some through-glass interconnect structures 111 are wider in the lateral direction than other through-glass interconnect structures 111.

[0029] In various embodiments, the conductive layer 115 is attached to the surface (including the sidewall and the bottom) of each through-glass cavity 103. For different possible shapes of the through-glass interconnect structure 111, the through-glass cavity 103 correspondingly has different shapes that are consistent with the shape of the through-glass interconnect structure 111.

[0030] According to one aspect of the present disclosure, the through-glass interconnect structure 111 (or the through-glass cavity 103) is designed to have a lower aspect ratio of height to width. For example, the height of the through-glass interconnect structure 111 may be the thickness of the glass substrate 102, and the width of the through-glass interconnect structure 111 may be represented by the width of the flat bottom 119 of the through-glass interconnect structure 111. For example, the width of the bottom may be the minimum dimension of the flat bottom 119 of the through-glass interconnect structure 111 at the bottom surface 172 of the glass substrate 102. For example, in some embodiments, the aspect ratio (height to width ratio) of the through-glass cavity 103 may be less than 4. In various embodiments, the minimum dimension of the flat bottom 119 of the through-glass structure 111 at the bottom surface 172 of the glass substrate 102 is greater than 100 μm.

[0031] In some examples, through-glass vias (TGVs) with a high aspect ratio are employed to provide through-glass interconnects. For example, the aspect ratio of the TGV can be in the range of 10:1 to 50:1. Compared with the high-aspect-ratio TGV, the low-aspect-ratio through-glass interconnect structure 111 can be formed using conventional etching processes and equipment, and avoids the expensive dedicated glass processing systems required for high-aspect-ratio TGVs. Thus, the low-aspect-ratio through-glass cavity 103 disclosed herein has a lower manufacturing cost and can be obtained through an easier manufacturing process.

[0032] In Figure 1 examples, the space 112 surrounded by the conductive layer 115 within the corresponding through-glass interconnect structure 111 can be filled with a dielectric material, such as a polymer dielectric material (e.g., epoxy resin dielectric). In other examples, the space 112 can be filled with a conductive material. For example, the space 112 can have the same conductive material as the conductive layer 115.

[0033] In various embodiments, the conductive structure 132 can be a solder ball, a conductive pillar, a conductive bump, etc. The semiconductor package structure 100 can be attached to a PCB or another package substrate by using the conductive structure 132.

[0034] In Figure 1 examples, the conductive structure 132 is coupled to the bottom portion 114 of the through-glass interconnect structure 111 through a conductive pad 131. The conductive pad 131 can include any suitable conductive material, such as, including copper, silver, nickel, gold, aluminum, other metals, or combinations thereof. The conductive pad 131 is optional. In some embodiments, the conductive pad 131 is not employed. In this case, the conductive structure 132 can be in direct contact with the bottom portion 114 of the conductive layer 115.

[0035] In some embodiments, the glass substrate 102 can further include a plurality of recesses 104 in the top surface of the glass substrate 102. The recesses 104 can be used to accommodate passive components (or passive devices) 121, and / or active components (or active devices) (not shown). Examples of passive components 121 include resistors, capacitors, inductors, diodes, transformers, or combinations thereof. Examples of active components can include circuits having transistors. The recesses 104 can have any suitable size or shape for accommodating the corresponding passive or active components.

[0036] Embedding active or passive components in the package substrate, rather than positioning them above the package substrate or the redistribution layer, can save package area, thereby reducing the package size. Moreover, in terms of manufacturing process complexity, embedding passive or active components in the glass substrate 102 is simpler than embedding them in an organic substrate. Thus, the manufacturing cost can be reduced by using the glass substrate 102.

[0037] The redistribution layer 201 is disposed between the substrate structure 101 and the encapsulation layer 301. The redistribution layer 201 provides wire metal interconnections between components (such as chips or circuit components) in the encapsulation layer 301 and between components in the encapsulation layer 301 and the through-glass interconnect structure 111. The redistribution layer 201 redistributes input / output (I / O) access to components in the encapsulation layer 301 to locations of the through-glass interconnect structure 111 and further redistributes to the conductive structure 132. The through-glass interconnect structure 111 and the conductive structure 132 can be arranged to their desired positions such that the semiconductor package structure 100 can be easily connected to the PCB through the conductive structure 132. The redistribution layer 201 can be appropriately designed based on the position of the through-glass interconnect structure 111.

[0038] The redistribution layer 201 can include at least one conductive layer and at least one insulating layer. The conductive layer can include any suitable conductive material, such as copper, silver, nickel, gold, aluminum, other metals, or combinations thereof. The insulating layer can include organic or inorganic dielectric materials. In Figure 1 an example, the redistribution layer 201 includes a plurality of conductive layers 202. The top conductive layer 202 can include a plurality of top contact pads 202C and 202D exposed from the surrounding insulating material. The bottom conductive layer 202 can include a plurality of bottom contact pads 202A and 202B. The bottom contact pad 202A can be disposed on top of a corresponding through-glass interconnect structure 111 and coupled to the conductive layer 115 of the corresponding through-glass interconnect structure 111. In various embodiments, one bottom contact pad 202A can completely or partially cover the top surface of the corresponding through-glass interconnect structure 111. Figure 1 An example shows the case where the bottom contact pad 202A completely covers the top surface of the corresponding through-glass interconnect structure 111. However, in other examples, one bottom contact pad 202A can partially cover the top surface of the corresponding through-glass interconnect structure 111. The bottom contact pads 202B can each be disposed in contact with at least one terminal of a corresponding passive component 121 or active component.

[0039] The encapsulation layer 301 includes a plurality of semiconductor chips encapsulated in an encapsulation material. In Figure 1 an example, the encapsulation layer 301 includes a set of semiconductor chips 311 and individual semiconductor chips 321. For example, the semiconductor chips 311 can be a set of 3D memory devices. The semiconductor chip 321 can be a memory controller coupled to the 3D memory devices. The 3D memory devices and the memory controller together form a memory system, such as a solid-state drive (SSD).

[0040] The set of semiconductor chips 311 is attached to the top surface of the redistribution layer 201. Each semiconductor chip 311 is attached to the redistribution layer 201 using an adhesive layer 312. The semiconductor chips 311 are vertically stacked on top of the redistribution layer 201. Further, the semiconductor chips 311 are shifted from each other such that the chip contact pads 313 disposed on the top surface of each semiconductor chip 311 can be exposed for wire bonding. Each chip contact pad 313 can be connected to the corresponding top contact pad 202C of the redistribution layer 201 by wire bonding using a metal wire 314. As shown, the chip contact pads 313 of the semiconductor chips 311 can be directly connected to the corresponding top contact pads 202C of the redistribution layer 201 or connected to the corresponding top contact pads 202C of the redistribution layer 201 via the chip contact pads 313 of another semiconductor chip 311. Figure 1 The example of Figure 1 shows four semiconductor chips 311 stacked together. However, based on actual needs, the number of semiconductor chips 311 can be different from four in other examples. Further, the semiconductor chips 311 can be vertically stacked and / or laterally spaced apart from each other.

[0041] The semiconductor chip 321 can have a conductive structure 322 (such as conductive pillars, contact pads, etc.), which are all electrically coupled to the corresponding top contact pads 202D of the redistribution layer 201 via a conductive structure 323 such as solder balls, conductive bumps, etc.

[0042] The encapsulation layer 301 can include an epoxy molding compound (EMC) to seal the semiconductor chips 311 and 321. The encapsulation layer 301 not only provides mechanical protection for the semiconductor package structure 100, but also prevents external moisture and dust from touching the semiconductor chips 311 and 321, the metal wires 314, the interconnect structures 322 and 323, and the top contact pads 202C and 202D.

[0043] In various embodiments, the plurality of chips encapsulated in the encapsulation layer 301 can be any type or number of semiconductor chips and can be arranged in any suitable manner. Examples of such semiconductor chips can include, but are not limited to, system-on-chip (SoC) die, processing chips (digital signal processor (DSP), application specific integrated circuit (ASIC), central processing unit (CPU), graphics processing unit (GPU)), memory chips (volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read only memory (ROM)), flash memory, solid state memory), and so on.

[0044] Figures 2A - 2GIllustrated is a manufacturing process for fabricating a semiconductor package structure 100 according to an embodiment of the present disclosure. Schematic cross-sectional views of a series of semiconductor structures are shown. Each semiconductor structure in the series corresponds to a stage of the manufacturing process. Several technical advantages associated with the manufacturing process are explained.

[0045] In Figure 2A , a glass substrate 150 is provided. The glass substrate 150 may include any suitable type of glass known in the art, including but not limited to photosensitive glass, borosilicate glass, soda-lime glass, quartz, or other glass materials. The glass substrate has a front (first side) 149 and a back (second side) 155. A pretreatment is performed at the back 155 of the glass substrate 150 to form a plurality of notches 152. An enlarged view of a portion 151 of the back surface of the glass substrate 150 is shown to display the notches 152.

[0046] According to one aspect of the present disclosure, the notches 152 can be used to prevent or reduce damage to the glass substrate 150 during a subsequent molding process. For example, during the molding process, the glass substrate 150 with a semiconductor chip attached thereto is disposed in a molding cavity between a top mold and a bottom mold. EMC is injected into the molding cavity. The back surface of the glass substrate 150 is pressed against the top surface of the bottom mold with high pressure. Hard particles present at the interface between the back surface of the glass substrate 150 and the top surface of the bottom mold may potentially damage the glass substrate 150. For example, microcracks and mechanical stress may be induced within the glass substrate 150, thereby having a negative impact on the yield. Measures can be taken to clean the mold or the glass substrate 150, but it is difficult to completely remove the hard particles. By pretreating the back 155 of the glass substrate 150, the resulting notches can contain the hard particles, thereby eliminating or reducing the pressure on the glass substrate 150 caused by the hard particles during the molding process. Therefore, the yield can be improved.

[0047] In various embodiments, the notches 152 can have various shapes (or profiles) and cross-sectional dimensions. In some examples, the width and depth of the notches 152 can be in the range of 5 μm to 15 μm. In some examples, the width and depth of the notches 152 can be in the range of 2 μm to 25 μm. In some examples, the width and depth of the notches 152 can be in a range different from the above ranges. The notches 152 can have shapes such as hemispherical, conical, frustoconical, cylindrical, tetrahedral, pyramidal, truncated conical, octagonal prism, truncated pyramidal, cuboid, hexagonal prism, etc. The notches 152 can have an irregular shape. The notches 152 can be pits, recesses, cavities, etc. The notches 152 can have an elongated shape. For example, the notches 152 can be slots, grooves, etc.

[0048] The notch 152 can be formed using any suitable glass processing technique, such as crack-free laser drilling, laser ablation techniques, media sandblasting or sandblasting techniques, ultrasonic drilling techniques, or etching techniques (such as chemical wet etching techniques or dry reactive ion etching techniques), or a combination of these techniques. In some embodiments, the notch 152 can be formed by exposing a photoimageable glass to ultraviolet (UV) light. For example, a mask material can be used to define the regions of the photoimageable glass that are exposed to ultraviolet light. The photoimageable glass with the mask can be exposed to ultraviolet light and heated to an elevated temperature, thereby causing changes in the structure and / or chemical properties of the regions exposed to ultraviolet light such that the exposed regions of the photoimageable glass can have a higher etching rate than the unexposed regions. An acid such as hydrofluoric acid (HF), ethylenediamine pyrocatechol, potassium hydroxide / isopropyl alcohol, tetramethylammonium hydroxide, etc. can be used to etch the notch 152 in the exposed regions of the photoimageable glass.

[0049] In Figure 2B , a plurality of blind cavities 153 and a plurality of recesses 104 are formed in the front surface of the glass substrate 150. The blind cavities 153 are subsequently transformed into Figure 1 the through-glass cavities 103 shown. Each blind cavity has a flat bottom 154. The blind cavities 153 and the recesses 104 can be arranged in desired positions. Any suitable glass processing technique (as described with reference to Figure 2A ) can be used to form the blind cavities 153 and the recesses 104. Figure 2B The glass substrate 150 in Figure 2A is flipped compared to

[0050] and the back surface 155 of the glass substrate 150 is now facing down.

[0051] The shape and size of the blind cavities 153 can vary in different embodiments. In some embodiments, the sidewalls 161 of the cross-section of the blind cavities 153 have a stepped shape. For example, to form a blind cavity 153 with stepped sidewalls 161, a first shallow cavity with a larger width 156 can first be formed in the front surface of the glass substrate 150, and subsequently a second shallow cavity with a smaller width 157 can be formed at the bottom of the first cavity. Forming the blind cavities 153 in this way (stacking multiple shallow cavities) simplifies the manufacturing process and reduces the requirements for expensive glass processing equipment, resulting in lower manufacturing costs.

[0052] Moreover, compared with the through-glass vias or blind vias structures adopted in the art, the aspect ratio (the ratio of the height 158 to the bottom width 159) of the blind cavity 153 is relatively high. The high aspect ratio reduces the manufacturing cost.

[0053] In Figure 2C , a plurality of through-glass interconnect structures 111 are formed in a plurality of blind cavities 153. Each through-glass interconnect structure 111 includes a conductive layer 115 (sidewall portion 113 and bottom portion 114) attached to the sidewall 161 and the flat bottom 154 of the corresponding blind cavity 153. The space 112 surrounded by the conductive layer 115 is filled with a polymer dielectric material, for example. In addition, a plurality of passive components 121 or active components are embedded in a plurality of recesses 104.

[0054] In an exemplary manufacturing process, the passive components 121 or active components can be embedded in the recesses 104. For example, the passive components 121 or active components can be pre-fabricated and ready to be placed in the recesses 104. (A variety of) bonding materials can be used to fix the passive components 121 or active components to the recesses 104. Subsequently, in order to form the through-glass interconnect structures 111, a seed layer can be first formed on the front surface of the glass substrate 150 to cover the inner surface of the blind cavity 153 as well as the front surface of the glass substrate 150. In an example, sputtered Ti-Cu is deposited as the seed layer (also used as a barrier layer).

[0055] Then a mask layer can be formed on top of the seed layer to expose the blind cavity 153 but cover other areas on the front surface of the glass substrate 150. Copper metallization can be performed, for example, by electroplating or any other suitable method to cover the sidewall and bottom of the blind cavity 153 with the conductive layer 115. The polymer dielectric material can be filled into the space 112 in the blind cavity 153. A chemical mechanical polishing (CMP) process can be performed to remove the excess polymer dielectric material, the deposited copper layer, and the mask above the front surface of the glass substrate 150. An etching process can be performed to remove the seed layer on the front surface of the glass substrate 150. The top surfaces of the passive components 121 or active components are also exposed.

[0056] In Figure 2D , a redistribution layer 201 is formed on top of the glass substrate 150. Any suitable manufacturing method known in the art can be used to form the redistribution layer 201.

[0057] In Figure 2E , an encapsulation layer 301 is formed on top of the redistribution layer 201. Any suitable manufacturing method known in the art can be used to form the encapsulation layer 301. For example, a semiconductor chip can be first attached to the top surface of the redistribution layer 201, and then a molding process can be performed to encapsulate the semiconductor chip with EMC.

[0058] In Figure 2F , the glass substrate 150 is thinned to expose the bottom portion 114 of the conductive layer 115 of each via glass interconnect structure 111. The glass substrate 150 is transformed into the glass substrate 102. The back surface 155 of the glass substrate 150 becomes the back surface 160 of the glass substrate 102. The blind cavity 153 is transformed into the through-glass cavity 103. The substrate structure 101 is created by the operation of thinning the glass substrate 150. In Figure 2F the Figure 2E semiconductor structure is flipped. The back surface 160 of the glass substrate 102 is now facing up.

[0059] In some embodiments, a grinding and / or polishing process, such as a CMP process, may be performed to remove the glass layer above the current back surface of the glass substrate 102 to expose the bottom portion 114 of the conductive layer. Other thinning methods, such as the wet or dry etching or glass processing techniques described in reference Figure 2A , may be used in some embodiments.

[0060] In the manufacturing process disclosed herein, a thick glass substrate 150 is initially used until the semiconductor chips 311 and 321 are encapsulated during the EMC molding process, and then the thick glass substrate 150 is transformed into the thin glass substrate 102 by removing the glass layer. The removed glass layer can act as a protective layer to prevent the substrate structure 101 from being damaged. For example, due to the additional thickness of the removed glass layer, the glass substrate 150 can have higher mechanical strength and better withstand external pressure and impact, thereby reducing the risk of cracking during the manufacturing process (including EMC molding). Moreover, the removed glass layer also prevents notches from being formed on the back surface 160, resulting in a smooth back surface of the semiconductor package structure 100. Therefore, the manufacturing process disclosed herein helps to improve the yield.

[0061] In Figure 2G , a plurality of conductive structures 132, such as solder balls, are injected at the back surface 160 of the glass substrate 102. The conductive structures 132 are electrically coupled to the conductive pads 114 of the corresponding via glass interconnect structures 111. In some embodiments, a plurality of conductive pads 131 are formed between the conductive pads 114 and the conductive structures 132. In the case where the grinding and / or polishing process performed in the previous step to expose the conductive pads 114 has completely or partially eliminated the conductive pads 114, the additional conductive pads 131 can act as intermediate interconnect structures to connect the conductive structures 132 to the sidewall portions 113 of the corresponding via glass interconnect structures 111. Such conductive pads 131 can relax the requirements of the grinding and / or polishing process. Moreover, such conductive pads 131 can improve the reliability of the interconnect structure. In some embodiments, no conductive pads are employed. At this stage, the semiconductor package structure 100 is formed.

[0062] In Figure 2G is shown additional manufacturing steps for forming a semiconductor package system. Specifically, the semiconductor package structure 100 is attached to the PCB 181. The resulting semiconductor package system includes the semiconductor package structure 100 and the PCB 181. Various types of PCBs can be employed to provide the PCB 181 in various embodiments. Depending on the conductive structure 132, various methods can be employed to bond the semiconductor package structure 100 to the PCB 181.

[0063] Figure 3 Shown is a flowchart of a semiconductor package structure manufacturing process 300 (or semiconductor packaging process 300) according to an embodiment of the present disclosure. The process 300 can be executed to manufacture the semiconductor package structure 100. In some examples, the steps in the process 300 can be performed in a different order or in parallel. In some examples, not all steps are performed. The process 300 can start at S301 and proceed to S310.

[0064] At S310, a glass substrate having a front side (first side) and a back side (second side) can be provided. The back side of the glass substrate is pre-treated to form a plurality of notches in the back surface of the glass substrate.

[0065] At S312, a plurality of cavities can be formed in the surface of the front side of the glass substrate. The cavities can be blind cavities and have a flat bottom. Additionally, a plurality of recesses can be formed in the surface of the front side of the glass substrate.

[0066] At S314, a conductive layer can be formed on the sidewalls and the flat bottom of each cavity. A portion of the conductive layer on the flat bottom of the corresponding cavity serves as a first conductive pad for implanting, for example, solder balls thereon. Moreover, a plurality of passive or active devices (components) can be respectively embedded in the plurality of recesses. In an example, the space within the conductive layer can be filled with a (plurality of) dielectric materials. The conductive layer and the (plurality of) dielectric materials form a through-glass interconnect structure in each blind cavity.

[0067] At S316, a redistribution layer can be formed on the front side of the glass substrate over the glass substrate.

[0068] At S318, a plurality of semiconductor chips can be mounted on the redistribution layer. A molding process can be performed at the front side of the glass substrate to encapsulate the semiconductor chips.

[0069] At S320, the glass substrate is thinned from the back side of the glass substrate to expose the first conductive pad at the back surface of the thinned glass substrate.

[0070] At S322, a plurality of second conductive pads are formed and respectively attached to the first conductive pads.

[0071] At S324, a plurality of conductive structures may be formed at the back surface of the thinned glass substrate. Each conductive structure is coupled to a corresponding first conductive pad through a corresponding second conductive pad. Examples of the conductive structures include solder balls, conductive pillars, conductive bumps, etc. Process 300 may proceed to S399 and end at S399.

[0072] Although aspects of the present disclosure have been described in connection with specific embodiments of the present disclosure presented as examples, substitutions, modifications, and variations of the examples may be made. Accordingly, the embodiments set forth herein are intended to be illustrative and not restrictive. Some changes may be made without departing from the scope of the appended claims.

Claims

1. A semiconductor package structure, comprising: A substrate structure, including a glass substrate and a through-glass interconnect structure. The glass substrate has a bottom surface and a top surface opposite to the bottom surface. The through-glass interconnect structure is located between the top surface and the bottom surface of the glass substrate and extends downward from the top surface of the glass substrate through the glass substrate to the bottom surface of the glass substrate. The through-glass interconnect structure has a flat bottom at the bottom surface of the glass substrate. A redistribution layer (RDL) disposed on the top surface of the glass substrate; And A semiconductor chip attached to the RDL and located above the RDL.

2. The semiconductor package structure according to claim 1, wherein, The minimum size of the flat bottom of the through-glass interconnect structure at the bottom surface of the glass substrate is greater than 100 μm.

3. The semiconductor package structure according to claim 1, wherein, The ratio of the minimum size of the flat bottom of the through-glass interconnect structure at the bottom surface of the glass substrate to the thickness of the glass substrate is greater than 1 / 4.

4. The semiconductor package structure according to claim 1, wherein, The through-glass interconnect structure includes a conductive layer covering the sidewalls and the outer surface of the flat bottom of the through-glass interconnect structure.

5. The semiconductor package structure according to claim 1, wherein, The through-glass interconnect structure has a stepped shape at each of a first side and a second side of the through-glass interconnect structure in a vertical cross-section of the through-glass interconnect structure, and the first side is opposite to the second side.

6. The semiconductor package structure according to claim 1, wherein, The through-glass interconnect structure has a lower portion and an upper portion stacked on top of the lower portion, and in a vertical cross-section of the through-glass interconnect structure, the upper portion is wider than the lower portion.

7. The semiconductor package structure according to claim 1, further comprising: A conductive pad attached to the flat bottom of the through-glass interconnect structure; And A conductive structure attached to the conductive pad.

8. The semiconductor package structure according to claim 1, further comprising: A conductive structure attached to the flat bottom of the through-glass interconnect structure, and the conductive structure includes one of a solder ball, a conductive pillar, and a conductive bump.

9. The semiconductor package structure according to claim 1, further comprising: A passive device embedded in the top surface of the glass substrate.

10. A packaging method, comprising: Providing a glass substrate having a first side and a second side; Preprocessing the second side of the glass substrate to form a plurality of notches in the surface of the second side of the glass substrate; And Encapsulating a semiconductor chip at the first side of the glass substrate.

11. The encapsulation method according to claim 10, wherein, Hard particles at the interface between the surface of the second side of the glass substrate and the surface of the molding are included in the plurality of notches in the surface of the second side of the glass substrate.

12. The packaging method according to claim 10, further comprising: Forming a cavity in the surface of the first side of the glass substrate, and the cavity has a flat bottom. A glass interconnection structure is formed in the cavity, the glass interconnection structure including a conductive layer formed on the sidewall of the cavity and the outer surface of the flat bottom, the glass interconnection structure having a flat bottom at the flat bottom of the cavity; and After encapsulating the semiconductor chip at the first side of the glass substrate, the glass substrate is thinned from the second side of the glass substrate to expose the flat bottom of the glass interconnection structure.

13. The encapsulation method according to claim 12, further comprising: After thinning the glass substrate from the second side of the glass substrate, a conductive structure is formed at the second side of the glass substrate, the conductive structure being coupled to the conductive layer of the glass interconnection structure at the flat bottom of the cavity, and the conductive structure including one of a solder ball, a conductive pillar, and a conductive bump.

14. The encapsulation method according to claim 13, further comprising: Forming a conductive pad attached to the flat bottom of the glass interconnection structure, the conductive structure being attached to the conductive pad.

15. The encapsulation method according to claim 12, wherein The minimum dimension of the flat bottom of the glass interconnection structure at the bottom surface of the glass substrate is greater than 100 μm.

16. The encapsulation method according to claim 12, wherein, The ratio of the minimum dimension of the flat bottom of the glass interconnection structure at the bottom surface of the glass substrate to the thickness of the glass substrate is greater than 1 / 4.

17. The encapsulation method according to claim 12, wherein, The glass interconnection structure has a stepped shape at opposite sides of the glass interconnection structure in a cross-section of the glass interconnection structure.

18. The encapsulation method according to claim 12, further comprising: Forming a recess in the surface of the first side of the glass substrate; And Setting a passive device into the recess.

19. The encapsulation method according to claim 10, wherein, The width or depth of the plurality of notches is in the range of 5 μm to 15 μm.

20. A semiconductor packaging system, comprising: A semiconductor packaging structure, the semiconductor packaging structure including: A substrate structure, including a glass substrate and a glass interconnection structure, the glass substrate having a bottom surface and a top surface opposite to the bottom surface, the glass interconnection structure being located between the top surface of the glass substrate and the bottom surface of the glass substrate and passing downward from the top surface of the glass substrate through the glass substrate to the bottom surface of the glass substrate, the glass interconnection structure having a flat bottom at the bottom surface of the glass substrate; A redistribution layer (RDL) disposed on the top surface of the glass substrate; and A semiconductor chip attached to the RDL and located above the RDL; and A printed circuit board (PCB), the semiconductor packaging structure being attached to the PCB.

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