A COT control circuit for switching power supply

Abstract

The present invention discloses a COT control circuit for a switching power supply, belonging to the technical field of switching power supplies. The COT control circuit for a switching power supply includes a voltage sampling module, which samples the input voltage and the output voltage through a proportional resistor, provides an input current proportional to the input voltage and an output current proportional to the output voltage, and forms two differential voltage signals according to the input current and the output current; a differential signal transmission module, which provides a differential voltage storing the proportional relationship between the input voltage and the output voltage according to the differential voltage signal; and a ripple voltage generation module, which converts the differential voltage into a proportional current proportional to the output voltage and inversely proportional to the input voltage, and uses the proportional current to charge a fixed capacitor to generate a ripple voltage. By superimposing a ripple voltage proportional to the output voltage and inversely proportional to the input voltage on the reference voltage, the problem of difficult ripple injection design for the feedback node is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, and in particular to a COT control circuit for a switching power supply. Background Art

[0002] COT (Constant On-Time) is a modulation control mode for switching power supplies. Its core feature is that the on-time Ton of each switch is fixed, while the off-time Toff is dynamically adjusted according to the feedback signal to achieve output voltage stability. Compared with the traditional voltage / current control mode, the COT control mode is simpler, such as Figure 1 As shown, the output voltage Vout is sampled through feedback resistors R10 and R20. The feedback voltage VFB is then input into a fixed comparator for comparison with the reference voltage Vref. When VFB falls below Vref, a fixed on-time pulse timer immediately initiates a fixed on-cycle, Ton, turning on switch Q10 and turning off Q20, charging inductor L1 and boosting the output voltage. When the on-time expires, the circuit enters the off-state, with Q10 turning off and Q20 turning on, discharging inductor L1. The off-time, Toff, is determined by the output load until VFB again falls below Vref, triggering a new Ton cycle.

[0003] The COT control mode eliminates the need for the compensation network found in traditional voltage / current mode DC / DC converters. This simplifies converter design, directly operating on the comparator and resulting in faster transient response. This also means that the output capacitor can be smaller to meet the given transient load response, saving both size and cost. Under light load, the output voltage in COT control mode drops more slowly, and the feedback voltage takes longer to fall below Vref. This reduces the frequency, maintaining high efficiency.

[0004] The traditional COT control mode also has the following drawbacks: 1. The switching frequency is not fixed, which may increase the difficulty of EMI (electromagnetic interference) filtering. 2. The ripple of the feedback voltage VFB must be kept to a minimum. If the ripple amplitude is insufficient, the controller may not be able to detect voltage drops. When designing a power supply, ceramic capacitors with low equivalent series resistance (ESR) are generally preferred as output capacitors to reduce output ripple and stabilize the output voltage. However, if the output ripple amplitude is too small, it can lead to false or missed touches. In extreme cases, it can even cause system instability and trigger output voltage oscillation.

[0005] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0006] The object of the present invention is to provide a COT control circuit for a switching power supply to solve the problems of difficulty in setting the ripple voltage and non-fixed switching frequency.

[0007] To solve the above technical problems, the present invention provides a COT control circuit for a switching power supply, comprising: a voltage sampling module configured to sample an input voltage and an output voltage through a proportional resistor, provide an input current proportional to the input voltage and an output current proportional to the output voltage, and form two differential voltage signals according to the input current and the output current;

[0008] a fixed on-time generating module, configured to generate a charging current proportional to the input current, for charging the charging capacitor, and generating a fixed on-time signal;

[0009] a differential signal transmission module configured to provide a differential voltage storing a proportional relationship between the input voltage and the output voltage according to the differential voltage signal;

[0010] a ripple voltage generating module configured to convert the differential voltage into a proportional current that is proportional to the output voltage and inversely proportional to the input voltage, and use the proportional current to charge the fixed capacitor to generate a ripple voltage;

[0011] The ripple current superposition module is configured to convert the ripple voltage into a ripple current and superimpose the ripple current on a reference current source to obtain a reference voltage superimposed with the ripple voltage.

[0012] Preferably, the voltage sampling module includes a first sampling unit and a second sampling unit. The first sampling unit is configured to sample the input voltage through a proportional resistor, generate an input current proportional to the input voltage, and transmit a first differential voltage signal to the differential signal transmission module through a switch tube. The second sampling unit is configured to sample the output voltage through a proportional resistor, generate an output current proportional to the output voltage, and transmit a second differential voltage signal to the differential signal transmission module through a switch tube. The first sampling unit and the second sampling unit have the same sampling ratio, and the switch tubes in the first sampling unit and the second sampling unit have the same size.

[0013] Preferably, the first sampling unit includes a first operational amplifier, a first resistor, a second resistor, a fifth resistor, a first NMOS transistor, a first current mirror, and a first switching transistor. The first end of the first resistor is connected to the input voltage, the second end of the first resistor is connected to the first end of the second resistor and is connected to the non-inverting input of the first operational amplifier, the second end of the second resistor is grounded, the output end of the first operational amplifier is connected to the control end of the first NMOS transistor, the output end of the first NMOS transistor is connected to the inverting input end of the first operational amplifier, the output end of the first NMOS transistor is further grounded through the fifth resistor, the input end of the first NMOS transistor is connected to the input end of the first current mirror, the output end of the first current mirror is connected to the input end of the first switching transistor, the control end and input end of the first switching transistor are interconnected, and the first differential voltage signal is output. The output end of the first switching transistor is grounded.

[0014] Preferably, the second sampling unit includes a second operational amplifier, a third resistor, a fourth resistor, a sixth resistor, a second NMOS transistor, a second current mirror, and a second switching transistor. The first end of the third resistor is connected to the output voltage, the second end of the third resistor is connected to the first end of the fourth resistor and connected to the non-inverting input of the second operational amplifier, the second end of the fourth resistor is grounded, the output end of the second operational amplifier is connected to the control end of the second NMOS transistor, the output end of the second NMOS transistor is connected to the inverting input end of the second operational amplifier, the output end of the second NMOS transistor is further grounded via the sixth resistor, the input end of the second NMOS transistor is connected to the input end of the second current mirror, the output end of the second current mirror is connected to the input end of the second switching transistor, the control end and input end of the second switching transistor are interconnected, and the second differential voltage signal is output. The output end of the second switching transistor is grounded.

[0015] Preferably, the differential signal transmission module includes a fully differential amplifier, a seventh resistor, an eighth resistor, a ninth resistor and a tenth resistor, the first differential voltage signal is connected to the non-inverting input terminal of the fully differential amplifier through the seventh resistor, the second differential voltage signal is connected to the inverting input terminal of the fully differential amplifier through the eighth resistor, a ninth resistor is connected between the first output terminal and the non-inverting input terminal of the fully differential amplifier, and a tenth resistor is connected between the second output terminal and the inverting input terminal of the fully differential amplifier, and the resistance values of the seventh resistor, the eighth resistor, the ninth resistor and the tenth resistor are equal.

[0016] Preferably, the ripple voltage generating module includes a bias current source, a third switching tube, a fourth switching tube, an eleventh resistor, a fixed capacitor, a fourth NMOS transistor, and a third current mirror. The third switching tube and the fourth switching tube have the same size. The input end of the bias current source is connected to the chip supply voltage, and the output end is connected to the input end of the third switching tube. The input end and the control end of the third switching tube are commonly connected and are also connected to the first end of the eleventh resistor and the first output end of the fully differential amplifier. The control end of the fourth switching tube is connected to the second end of the eleventh resistor and the second output end of the fully differential amplifier. The input end of the fourth switching tube is connected to the input end of the third current mirror. The output end of the third current mirror is connected to the first end of the fixed capacitor and the input end of the fourth NMOS transistor for providing a ripple voltage. The control end of the fourth NMOS transistor is used to receive a falling edge detection pulse signal provided by the chip SW port. The output end of the third switching tube, the output end of the fourth switching tube, the second end of the fixed capacitor, and the output end of the fourth NMOS transistor are all grounded.

[0017] Preferably, the ripple current superposition module includes a third operational amplifier, a fifth NMOS tube, a fourth current mirror, a reference current source, a twelfth resistor and a thirteenth resistor. The non-inverting input terminal of the third operational amplifier is used to access the ripple voltage, the control terminal of the fifth NMOS tube is connected to the output terminal of the third operational amplifier, and the output terminal is connected to the inverting input terminal of the third operational amplifier. The output terminal of the third operational amplifier is also grounded through the twelfth resistor. The input terminal of the fifth NMOS tube is connected to the input terminal of the fourth current mirror. The output terminal of the fourth current mirror is connected to the output terminal of the reference current source and the first terminal of the thirteenth resistor. The input terminal of the reference current source is connected to the chip power supply voltage, and the second terminal of the thirteenth resistor is grounded.

[0018] Preferably, the first current mirror includes a first PMOS tube and a second PMOS tube, the input end of the first PMOS tube and the input end of the second PMOS tube are both connected to the chip power supply voltage, the output end of the first PMOS tube is connected to the input end of the first NMOS tube, the output end and the control end of the first PMOS tube are interconnected, and the control end of the first PMOS tube is connected to the control end of the second PMOS tube, and the output end of the second PMOS tube is connected to the input end of the first switch tube.

[0019] Preferably, the fixed on-time generation module includes a fifth PMOS transistor, a charging capacitor, a third NMOS transistor and a comparator. The control end of the fifth PMOS transistor is connected to the control end of the first PMOS transistor, the input end of the fifth PMOS transistor is connected to the chip power supply voltage, the output end of the fifth PMOS transistor is commonly connected to the first end of the charging capacitor, the input end of the third NMOS transistor, and the non-inverting input end of the comparator, the inverting input end of the comparator is used to access the charging reference voltage, the output end of the comparator is used to provide a fixed on-time signal, the control end of the third NMOS transistor is used to receive the reverse signal of the switching frequency, and the second end of the charging capacitor and the output end of the third NMOS transistor are both grounded.

[0020] Preferably, the fifth PMOS transistor and the first PMOS transistor have the same length and width, but different m values, and are used to generate a charging current proportional to the input current.

[0021] The COT control circuit for a switching power supply provided by the present invention samples the input voltage and output voltage to generate a proportional current that is proportional to the output voltage and inversely proportional to the input voltage. The proportional current is converted into a ripple voltage that is proportional to the output voltage and inversely proportional to the input voltage. The ripple voltage is superimposed on a reference voltage Vref to achieve a ripple injection effect, thereby resolving the difficulty of designing ripple injection at the feedback node. Based on the input current generated in proportion to the input voltage, another current is formed to generate a fixed on-time inversely proportional to the input voltage, thereby achieving a fixed switching frequency FSW that is independent of changes in the input voltage under continuous conduction mode (CCM). BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0023] Figure 1 This is a schematic diagram of the BUCK COT architecture in the prior art;

[0024] Figure 2 is a circuit diagram of an embodiment of the present invention;

[0025] Figure 3 This is a waveform diagram of an embodiment of the present invention with a fixed output voltage of 5V and an input voltage increasing from 10V to 40V;

[0026] Figure 4 This is a waveform diagram of an embodiment of the present invention when the input voltage is fixed at 10V and the output voltage increases from 4V to 6V.

[0027] Attachment Figure 2 middle:

[0028] 100, voltage sampling module; 101, first current mirror; 102, second current mirror; 200, fixed on-time generation module; 300, differential signal transmission module; 400, ripple voltage generation module; 401, third current mirror; 500, ripple current superposition module; 501, fourth current mirror. DETAILED DESCRIPTION

[0029] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0030] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in a sense including "and / or", the term "several" is generally used in a sense including "at least one", and the term "at least two" is generally used in a sense including "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features. Therefore, features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of such features. The term "proximal end" generally refers to the end closest to the operator, and the term "distal end" generally refers to the end closest to the patient. "One end" and "the other end" as well as "proximal end" and "distal end" generally refer to two corresponding parts, which include not only endpoints. The terms "mounted", "connected", and "connected" should be understood in a broad sense. For example, they can be fixedly connected, detachably connected, or integrated; they can be mechanically connected or electrically connected; they can be directly connected or indirectly connected through an intermediate medium; they can be internal communication between two elements or an interactive relationship between two elements. In addition, as used in the present invention, "one element is arranged on another element" generally only means that there is a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element, and it should not be understood to indicate or imply a spatial positional relationship between the two elements, that is, one element can be in any position such as inside, outside, above, below, or to the side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0031] Research has found that there are three ripple injection methods in the existing COT control mode: Method 1, using the ripple voltage naturally generated by the output capacitor ESR; Method 2, connecting a capacitor (CFF) in parallel across the upper voltage divider resistor of the feedback resistor to couple the ripple signal to the feedback node (FB) through the capacitor; Method 3, using an RC network to generate a voltage ripple in phase with the inductor current across the inductor, and then coupling it to the feedback node (FB) through a capacitor.

[0032] All three methods have varying degrees of implementation challenges. Method 1, due to the low ESR of ceramic capacitors, is insufficient for ripple compensation. Electrolytic capacitors have sufficient ESR, but their larger size results in unacceptably high output ripple. Method 2, similar to Method 1, partially offsets the ripple attenuation problem of low-ESR capacitors, but still depends on the system's own output voltage ripple, which is insufficient for stable controller triggering. Method 3 offers adjustable injected ripple amplitude, but compensation generally requires resetting under different conditions, which is cumbersome. Both Methods 2 and 3 require additional components. Generally speaking, the lower the output voltage, the smaller the naturally generated ripple, and the larger the required ripple injection.

[0033] Further research has found that some existing COT control modes also introduce input voltage feedforward. Under continuous conduction (CCM) conditions, changes in input voltage will not cause changes in switching frequency (FSW). The formula for switching frequency (FSW) is as follows:

[0034]

[0035] Buck circuit duty cycle D:

[0036]

[0037] The above formulas can be combined to obtain:

[0038]

[0039] To fix the switching frequency, Vin needs to be inversely proportional to Ton.

[0040] According to the existing technology, if FSW is to be constant, Vin needs to be inversely proportional to Ton. A current Ion inversely proportional to the input voltage can be used to charge a charging capacitor Con to a certain voltage value Vt, that is, Ion can be obtained by sampling the input voltage VIN' and dividing it by a resistor R , it can be deduced that .

[0041] A ripple voltage inversely proportional to the output voltage and independent of the input voltage is superimposed on the reference voltage Vref. Alternatively, a current Ic can be used to charge a fixed capacitor Cc to generate a ripple voltage, which is then converted into a ripple current and superimposed on the reference current. The superimposed ripple voltage should begin to rise at the falling edge of SW and reset and rise again at the next falling edge of SW. The charging time is Toff + Ton', where Ton' is the on-time of the next cycle.

[0042]

[0043] Based on the BUCK CCM mode, the above formula shows that the larger Vin is, the larger Toff is. To keep the ripple voltage amplitude unchanged, the charging current Ic should be inversely proportional to Vin; the larger Vo is, the smaller Toff is, and the charging current Ic should be proportional to Vo, that is, .

[0044] Based on this, the core idea of the present invention is to generate a proportional current that is proportional to the output voltage and inversely proportional to the input voltage by sampling the input voltage and output voltage, convert the proportional current into a ripple voltage that is proportional to the output voltage and inversely proportional to the input voltage, and superimpose the ripple voltage on the reference voltage Vref to achieve the effect of ripple injection, thereby solving the difficult problem of ripple injection design for the feedback node. On the basis of the generated proportional current, another current is formed to generate a fixed on-time that is inversely proportional to the input voltage, thereby obtaining a fixed switching frequency FSW that does not change with the input voltage under continuous conduction (CCM) conditions.

[0045] For details, please refer to Figure 2 , which is a schematic diagram of an embodiment of the present invention. Figure 2 As shown, a COT control circuit for a switching power supply includes:

[0046] The voltage sampling module 100 is configured to sample the input voltage Vin and the output voltage Vo through a proportional resistor, provide an input current Iin proportional to the input voltage Vin and an output current Io proportional to the output voltage Vo, and form two differential voltage signals based on the input current Iin and the output current Io;

[0047] The fixed on-time generating module 200 is configured to generate a charging current Ion proportional to the input current Iin, for charging the charging capacitor Con, and generate a fixed on-time signal COT_on;

[0048] The differential signal transmission module 300 is configured to provide a differential voltage ΔV storing a proportional relationship between the input voltage Vin and the output voltage Vo according to the differential voltage signal;

[0049] The ripple voltage generating module 400 is configured to convert the differential voltage ΔV into a proportional current Ic that is proportional to the output voltage Vo and inversely proportional to the input voltage Vin, and use the proportional current Ic to charge the fixed capacitor Cc to generate a ripple voltage Vc;

[0050] The ripple current superposition module 500 is configured to convert the ripple voltage Vc into a ripple current ΔI and superimpose the ripple current on the reference current source Iref to obtain a reference voltage Vref superimposed with the ripple voltage Vc.

[0051] Exemplarily, in the voltage sampling module 100, the input voltage Vin and the output voltage Vo are sampled through a proportional resistor to generate an input current Iin proportional to the input voltage Vin and an output current Io proportional to the output voltage Vo. The current is processed to form two differential voltage signals containing information about the input voltage Vin and the output voltage Vo, respectively. A differential voltage ΔV is generated in the differential signal transmission module 300, and the value of the differential voltage ΔV is related to the ratio between the input voltage Vin and the output voltage Vo. The ripple voltage generation module 400 processes the differential voltage ΔV to form a proportional current Ic that is proportional to the output voltage Vo and inversely proportional to the input voltage Vin, thereby generating a ripple voltage Vc. In the ripple current superposition module 500, the ripple voltage Vc is first converted into a ripple current ΔI and superimposed on the reference current source Iref to obtain a reference voltage Vref superimposed with the ripple voltage Vc, thereby achieving the effect of ripple injection.

[0052] Furthermore, a fixed on-time generating module 200 is provided to generate a charging current Ion proportional to the input current Iin according to the provided input current Iin. The charging current Ion is also proportional to the input voltage Vin, and is used to generate a fixed on-time signal inversely proportional to the input voltage Vin, thereby obtaining a fixed switching frequency FSW that does not change with the input voltage under continuous conduction (CCM) conditions.

[0053] Specifically, the voltage sampling module 100 includes a first sampling unit (not labeled) and a second sampling unit (not labeled). The first sampling unit is configured to sample the input voltage Vin via a proportional resistor, generate an input current Iin proportional to the input voltage Vin, and transmit a first differential voltage signal to the differential signal transmission module via a switch. The second sampling unit is configured to sample the output voltage Vo via a proportional resistor, generate an output current Io proportional to the output voltage Vo, and transmit a second differential voltage signal to the differential signal transmission module 300 via a switch. The first and second sampling units have the same sampling ratio, and the switches in the first and second sampling units have the same size.

[0054] After sampling to form an input current Iin proportional to the input voltage Vin and an output current Io proportional to the output voltage Vo, a switching transistor is used to provide a differential voltage signal input to the subsequent stage. To ensure the proportional relationship, the first sampling unit and the second sampling unit have the same sampling ratio, and the switching transistors in the first and second sampling units are the same size. The proportional resistors in the first sampling unit are the first resistor R1 and the second resistor R2, and the proportional resistors in the second sampling unit are the third resistor R3 and the fourth resistor R4. Preferably, the first resistor R1 and the third resistor R3 have the same resistance value, and the second resistor R2 and the fourth resistor R4 have the same resistance value.

[0055] More preferably, the first sampling unit includes a first operational amplifier OP1, a first resistor R1, a second resistor R2, a fifth resistor R5, a first NMOS transistor NM1, a first current mirror 101, and a first switch transistor Q1. A first end of the first resistor R1 is connected to the input voltage Vin, a second end of the first resistor R1 is connected to the first end of the second resistor R2 and is connected to the non-inverting input terminal of the first operational amplifier OP1, a second end of the second resistor R2 is grounded, an output end of the first operational amplifier OP1 is connected to the control end of the first NMOS transistor NM1, an output end of the first NMOS transistor NM1 is connected to the inverting input terminal of the first operational amplifier OP1, an output end of the first NMOS transistor NM1 is further grounded through the fifth resistor R5, an input end of the first NMOS transistor NM1 is connected to the input end of the first current mirror 101, an output end of the first current mirror 101 is connected to the input end of the first switch transistor Q1, the control end and input end of the first switch transistor Q1 are interconnected, and the first differential voltage signal is outputted. The output end of the first switch transistor Q1 is grounded.

[0056] The input terminal of the first NMOS transistor NM1 is a drain terminal, the output terminal is a source terminal, and the control terminal is a gate terminal. The gate terminal of the first NMOS transistor NM1 is connected to the output terminal of the first operational amplifier OP1, the source terminal of the first NMOS transistor NM1 is connected to the inverting input terminal of the first operational amplifier OP1, the source terminal of the first NMOS transistor NM1 is also grounded through the fifth resistor R5, and the drain terminal of the first NMOS transistor NM1 is connected to the input terminal of the first current mirror 101. The NMOS transistor in this application can be replaced with a PMOS transistor. It should be noted that the arrangement of the replaced PMOS transistor needs to have the same current direction as the original NMOS transistor. Similarly, the first switch transistor Q1 can also be a PNP transistor or an NPN transistor. Exemplarily, the first switch transistor Q1 is an NPN transistor, the control terminal of the NPN transistor is the base, the input terminal is the collector, and the output terminal is the emitter. The base and collector of the first switch transistor Q1 are connected in common, and the first differential voltage signal is output at the base.

[0057] The first current mirror 101 includes a first PMOS transistor PM1 and a second PMOS transistor PM2. The input terminals of the first PMOS transistor PM1 and the second PMOS transistor PM2 are both connected to the chip power supply voltage Vcc. The output terminal of the first PMOS transistor PM1 is connected to the input terminal of the first NMOS transistor NM1. The output terminal and the control terminal of the first PMOS transistor PM1 are interconnected, and the control terminal of the first PMOS transistor PM1 is connected to the control terminal of the second PMOS transistor PM2. The output terminal of the second PMOS transistor PM2 is connected to the input terminal of the first switch transistor Q1. The input terminals of the first PMOS transistor PM1 and the second PMOS transistor PM2 are source terminals, the output terminals are drain terminals, and the control terminals are gate terminals. The source terminal of the first PMOS transistor PM1 and the source terminal of the second PMOS transistor PM2 are both connected to the chip power supply voltage Vcc, the drain terminal of the first PMOS transistor PM1 is connected to the drain terminal of the first NMOS transistor NM1, the drain terminal and gate terminal of the first PMOS transistor PM1 are interconnected, and the gate terminal of the first PMOS transistor PM1 is connected to the gate terminal of the second PMOS transistor PM2, and the drain terminal of the second PMOS transistor PM2 is connected to the collector of the first switch transistor Q1. The PMOS transistor in this application can also be replaced with an NMOS transistor. It should be noted that the arrangement of the replaced NMOS transistor needs to ensure that the current direction is the same as that of the original PMOS transistor.

[0058] Specifically, the second sampling unit includes a second operational amplifier OP2, a third resistor R3, a fourth resistor R4, a sixth resistor R6, a second NMOS transistor NM2, a second current mirror 102, and a second switch transistor Q2. A first end of the third resistor R3 is connected to the output voltage Vo, a second end of the third resistor R3 is connected to the first end of the fourth resistor R4 and is connected to the non-inverting input terminal of the second operational amplifier OP2, a second end of the fourth resistor R4 is grounded, an output end of the second operational amplifier OP2 is connected to the control end of the second NMOS transistor NM2, an output end of the second NMOS transistor NM2 is connected to the inverting input terminal of the second operational amplifier OP2, an output end of the second NMOS transistor NM2 is further grounded via the sixth resistor R6, an input end of the second NMOS transistor NM2 is connected to the input end of the second current mirror 102, an output end of the second current mirror 102 is connected to the input end of the second switch transistor Q2, the control end and input end of the second switch transistor Q2 are interconnected, and the second differential voltage signal is outputted. The output end of the second switch transistor Q2 is grounded.

[0059] As can be understood, the second switch transistor Q2 is an NPN transistor, with its base and collector connected in common, and a second differential voltage signal outputted at the base. The second current mirror 102 includes a third PMOS transistor PM3 and a fourth PMOS transistor PM4. The input terminals of the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are both connected to the chip power supply voltage Vcc. The output terminal of the third PMOS transistor PM3 is connected to the input terminal of the second NMOS transistor NM2. The control terminal and output terminal of the third PMOS transistor PM3 are interconnected, and the control terminal of the third PMOS transistor PM3 is connected to the control terminal of the fourth PMOS transistor PM4. The output terminal of the fourth PMOS transistor PM4 is connected to the input terminal of the second switch transistor Q2. The input terminal and control terminal of the second switch transistor Q2 are interconnected. The output terminal of the second switch transistor Q2 is grounded, and the control terminal of the second switch transistor Q2 is used to provide the second differential voltage signal to the differential signal transmission module.

[0060] Among them, the resistance values of the first resistor R1 and the third resistor R3 are equal, the resistance values of the second resistor R2 and the fourth resistor R4 are equal, the resistance values of the fifth resistor R5 and the sixth resistor R6 are equal, the sampling ratios of the input voltage Vin and the output voltage Vo are the same, the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are PMOS transistors of the same size and are used to build a current mirror; the first NMOS transistor NM1 and the second NMOS transistor NM2 are NMOS transistors of the same size and enhance the current output capability; the first switch transistor Q1 and the second switch transistor Q2 are NPN transistors of the same size and are used to generate the Vbe voltage.

[0061] Vcc is the internal power supply voltage of the chip, which is generally set to 3.3V. The first resistor R1 and the second resistor R2 are sampling resistors. The obtained sampling voltage is proportional to the input voltage Vin and is connected to the non-inverting input terminal of the first operational amplifier OP1. The output terminal of the first operational amplifier OP1 is connected to the gate of the first NMOS tube NM1, and the inverting input terminal of the first operational amplifier OP1 is connected to the source of the first NMOS tube NM1, so as to achieve voltage following and enhance the output current capability. The sampling voltage generates a current Iin proportional to the input voltage Vin through the fifth resistor R5. It is copied to the first switch tube Q1 through the current mirror composed of the first PMOS tube PM1 and the second PMOS tube PM2. The be of the first switch tube Q1 is short-circuited to ensure that it works in a saturated state, and it can be obtained , where I S is the reverse saturation current, V T At room temperature, it is approximately equal to 26mV. .

[0062] Specifically, the differential signal transmission module 300 includes a fully differential amplifier FD_OP, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a tenth resistor R10. The first differential voltage signal is connected to the non-inverting input terminal of the fully differential amplifier FD_OP through the seventh resistor R7, and the second differential voltage signal is connected to the inverting input terminal of the fully differential amplifier FD_OP through the eighth resistor R8. A ninth resistor R9 is connected between the first output terminal and the non-inverting input terminal of the fully differential amplifier FD_OP, and a tenth resistor R10 is connected between the second output terminal and the inverting input terminal of the fully differential amplifier FD_OP. The resistance values of the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, and the tenth resistor R10 are equal.

[0063] The fully differential amplifier FD_OP is used to suppress common-mode interference and output a stable differential voltage ΔV. R7 = R8 = R9 = R10, and the differential signal amplification factor is 1. This module is used to obtain a stable Vinbe-Vobe differential voltage, as shown in the following equation.

[0064]

[0065] Specifically, the ripple voltage generating module 400 includes a bias current source Ibias, a third switch tube Q3, a fourth switch tube Q4, an eleventh resistor R11, a fixed capacitor Cc, a fourth NMOS transistor NM4, and a third current mirror 401. The third switch tube Q3 and the fourth switch tube Q4 have the same size. The input terminal of the bias current source Ibias is connected to the chip power supply voltage Vcc, and the output terminal is connected to the input terminal of the third switch tube Q3. The input terminal and the control terminal of the third switch tube Q3 are connected in common, and are also connected to the first terminal of the eleventh resistor R11 and the first output terminal of the fully differential amplifier FD_OP. The fourth switch tube Q4 The control end of the fourth switch tube Q3 is connected to the second end of the eleventh resistor R11 and the second output end of the fully differential amplifier FD_OP. The input end of the fourth switch tube Q4 is connected to the input end of the third current mirror 401. The output end of the third current mirror 401 is connected to the first end of the fixed capacitor Cc and the input end of the fourth NMOS tube NM4, for providing a ripple voltage Vc. The control end of the fourth NMOS tube NM4 is used to access the falling edge detection pulse signal Rc provided by the chip SW port. The output end of the third switch tube Q3, the output end of the fourth switch tube Q4, the second end of the fixed capacitor Cc, and the output end of the fourth NMOS tube NM4 are all grounded.

[0066] In one embodiment, an input terminal of the bias current source Ibias is connected to the supply voltage Vcc of the switching power supply chip. The bias current source Ibias may be a current generated by an internal module of the chip or may be an externally provided current source.

[0067] The third current mirror 401 includes a sixth PMOS transistor PM6 and a seventh PMOS transistor PM7. The input end of the sixth PMOS transistor PM6 and the input end of the seventh PMOS transistor PM7 are both connected to the chip power supply voltage Vcc. The output end of the sixth PMOS transistor PM6 is connected to the input end of the fourth switch transistor Q4. The output end and the control end of the sixth PMOS transistor PM6 are interconnected, and the control end of the sixth PMOS transistor PM6 is connected to the control end of the seventh PMOS transistor PM7. The output end of the seventh PMOS transistor PM7 is connected to the first end of the fixed capacitor Cc.

[0068] The third and fourth switching transistors Q3 and Q4 are both NPN transistors. The sixth and seventh PMOS transistors PM6 and PM7 are PMOS transistors of the same size and are used for current replication. The third and fourth switching transistors Q3 and Q4 are NPN transistors of the same size. The voltage across the eleventh resistor R11 is the differential voltage ΔV output by the fully differential amplifier FD_OP, which is also the voltage difference between Vbbe and Vcbe. The bias current source Ibais is an internally generated fixed current, as shown in the following equation.

[0069]

[0070]

[0071]

[0072] The differential voltage ΔV transfers the proportional relationship between the input current Iin and the output current Io to the proportional relationship between the bias current source Ibais and the proportional current Ic. Since the input current Iin and the output current Io are obtained by sampling the input voltage Vin and the output voltage Vo, the proportional current Ic is inversely proportional to the input voltage Vin and directly proportional to the output voltage Vo. The resulting proportional current Ic is used to charge the fixed capacitor Cc, generating the ripple current Vc. The Rc signal is a pulse signal detected by the falling edge of the SW switch and is used to control the switching of the fourth NMOS transistor NM4, providing a discharge circuit for the fixed capacitor Cc.

[0073] Specifically, the ripple current superposition module 500 includes a third operational amplifier OP3, a fifth NMOS transistor NM5, a fourth current mirror 501, a reference current source Iref, a twelfth resistor R12, and a thirteenth resistor R13. The non-inverting input terminal of the third operational amplifier OP3 is used to connect to the ripple voltage Vc. The control terminal of the fifth NMOS transistor NM5 is connected to the output terminal of the third operational amplifier OP3, and the output terminal is connected to the inverting input terminal of the third operational amplifier OP3. The output terminal of the third operational amplifier OP3 is also grounded through the twelfth resistor R12. The input terminal of the fifth NMOS transistor NM5 is connected to the input terminal of the fourth current mirror 501. The output terminal of the fourth current mirror 501 is connected to the output terminal of the reference current source Iref and the first terminal of the thirteenth resistor R13. The input terminal of the reference current source Iref is connected to the chip power supply voltage Vcc. The second terminal of the thirteenth resistor R13 is grounded.

[0074] In one embodiment, the input end of the reference current source Iref is connected to the supply voltage Vcc of the switching power supply chip. The reference current source Iref can be a current generated by an internal module of the chip or a current source provided externally.

[0075] The fourth current mirror 501 includes an eighth PMOS transistor PM8 and a ninth PMOS transistor PM9. The input terminals of the eighth PMOS transistor PM8 and the ninth PMOS transistor PM9 are both connected to the chip power supply voltage Vcc. The output terminal of the eighth PMOS transistor PM8 is connected to the input terminal of the fifth NMOS transistor NM5. The output terminal and the control terminal of the eighth PMOS transistor PM8 are interconnected, and the control terminal of the eighth PMOS transistor PM8 is connected to the control terminal of the ninth PMOS transistor PM9. The output terminal of the ninth PMOS transistor PM9 is connected to the first terminal of the thirteenth resistor R13.

[0076] The ripple voltage Vc is connected to the non-inverting input of the third operational amplifier OP3. The output of the third operational amplifier OP3 is connected to the gate of the fifth NMOS transistor NM5, and the inverting input of the third operational amplifier OP3 is connected to the source of the fifth NMOS transistor NM5, achieving voltage following and enhancing output current capability. The ripple voltage Vc generates a ripple current ΔI through the twelfth resistor R12. The eighth and ninth PMOS transistors PM8 and PM9 are identical in size and are used to replicate the ripple current ΔI. The ripple current ΔI is superimposed on the reference current source Iref, and the reference voltage Vref, which is superimposed with the ripple signal, is generated by passing through the thirteenth resistor R13.

[0077] Specifically, the fixed on-time generating module 200 includes a fifth PMOS transistor PM5, a charging capacitor Con, a third NMOS transistor NM3, and a comparator COMP. The control terminal of the fifth PMOS transistor PM5 is connected to the control terminal of the first PMOS transistor PM1, the input terminal of the fifth PMOS transistor PM5 is connected to the chip power supply voltage Vcc, the output terminal of the fifth PMOS transistor PM5 is commonly connected to the first terminal of the charging capacitor Con, the input terminal of the third NMOS transistor NM3, and the non-inverting input terminal of the comparator COMP, the inverting input terminal of the comparator COMP is used to receive the charging reference voltage Vt, the output terminal of the comparator COMP is used to provide the fixed on-time signal COT_on, the control terminal of the third NMOS transistor NM3 is connected to the reverse switching frequency signal Ro, which is obtained, for example, by processing the signal output from the chip SW port, and the second terminal of the charging capacitor Con and the output terminal of the third NMOS transistor NM3 are both grounded. The fifth PMOS transistor PM5 and the first PMOS transistor PM1 have the same length and width, but different m values, and are configured to generate a charging current Ion proportional to the input current Iin. It is understood that the different m values mean that the number of MOS transistors connected in parallel in the fifth PMOS transistor PM5 and the first PMOS transistor PM1 differs on the layout.

[0078] The fifth PMOS transistor PM5 has the same length and width as the first PMOS transistor PM1, but a different m value. It generates a charging current Ion proportional to the input current Iin, which charges the charging capacitor Con. COMP is a comparator that compares the charging voltage Von with the charging reference voltage Vt to generate a COT_on pulse signal that reaches the fixed on-time. This is used to switch the drive to a mode where the upper tube is turned off and the lower tube is turned on. The duration of the square wave's high level is the fixed on-time. The Ro signal is the inverse of the switching frequency and is used to control the switching of the third NMOS transistor NM3, providing a discharge circuit for the charging capacitor Con. COT_on is a narrow pulse signal used for logic control in switching power supplies.

[0079] like Figure 3 、 Figure 4 is the waveform diagram of the circuit, Figure 3The waveform diagram shows that the output voltage Vo is fixed at 5V and the input voltage Vin increases from 10V to 40V. It can be seen from the SW (output port) waveform that when the input voltage Vin increases, the on-time Ton will decrease, but the frequency remains unchanged. The charging current Ion is proportional to the input voltage Vin. The increase in the charging current Ion enables the charging voltage to reach the charging reference voltage Vt faster, which reduces the on-time Ton. The proportional current Ic is inversely proportional to the input voltage Vin. Since the frequency remains unchanged and the on-time decreases, the off-time Toff will increase, and the charging time of the fixed capacitor Cc will increase. The charging current Ic decreases and the charging time increases, so the resulting ripple voltage Vc remains unchanged. The charging time of the fixed capacitor Cc is , charging voltage , the charging time of the fixed capacitor Cc is proportional to the input voltage Vin, and the charging current Ic is inversely proportional to the input voltage Vin, so the ripple voltage remains unchanged.

[0080] Figure 4 The following is a waveform diagram of the output voltage Vo changing from 4V to 6V when the input voltage Vin is fixed at 10V. As can be seen from the SW waveform, when the input voltage Vin remains unchanged, the on-time Ton remains unchanged. However, due to the change in the output voltage Vo, the duty cycle will change, and the time of one cycle is no longer fixed. The proportional current Ic is proportional to the output voltage Vo, the on-time Ton remains unchanged, and the off-time Toff is inversely proportional to the output voltage Vo, so the slope of the charging voltage change remains fixed. The charging time of the fixed capacitor Cc is , charging voltage At this time, the on-time Ton is a constant value, the proportional current Ic is inversely proportional to the output voltage Vo, so the ripple voltage Vc is inversely proportional to Vo.

[0081] In the COT control circuit for a switching power supply provided by the present invention, a ripple voltage that is inversely proportional to the output voltage and proportional to the input voltage is superimposed on the reference voltage Vref to solve the problem of difficult ripple injection design at the feedback node. A fixed on-time current is designed based on the input current that is proportional to the input voltage to generate a current, thereby generating an on-time Ton that is inversely proportional to Vin, thereby fixing the switching frequency in the CCM state and reducing EMI.

[0082] The above description is only a description of the preferred embodiment of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the technical solution of the present invention.

Claims

1. A COT control circuit for a switching power supply, characterized in that: include: a voltage sampling module configured to sample the input voltage and the output voltage through a proportional resistor, provide an input current proportional to the input voltage and an output current proportional to the output voltage, and form two differential voltage signals according to the input current and the output current; a fixed on-time generating module, configured to generate a charging current proportional to the input current, for charging the charging capacitor, and generating a fixed on-time signal; a differential signal transmission module configured to provide a differential voltage storing a proportional relationship between the input voltage and the output voltage according to the differential voltage signal; a ripple voltage generating module configured to convert the differential voltage into a proportional current that is proportional to the output voltage and inversely proportional to the input voltage, and use the proportional current to charge the fixed capacitor to generate a ripple voltage; The ripple current superposition module is configured to convert the ripple voltage into a ripple current and superimpose the ripple current on a reference current source to obtain a reference voltage superimposed with the ripple voltage.

2. The COT control circuit for a switching power supply according to claim 1, characterized in that: The voltage sampling module includes a first sampling unit and a second sampling unit. The first sampling unit is configured to sample the input voltage through a proportional resistor, generate an input current proportional to the input voltage, and transmit a first differential voltage signal to the differential signal transmission module through a switch tube. The second sampling unit is configured to sample the output voltage through a proportional resistor, generate an output current proportional to the output voltage, and transmit a second differential voltage signal to the differential signal transmission module through a switch tube. The first sampling unit and the second sampling unit have the same sampling ratio, and the switch tubes in the first sampling unit and the second sampling unit have the same size.

3. The COT control circuit for a switching power supply according to claim 2, characterized in that: The first sampling unit includes a first operational amplifier, a first resistor, a second resistor, a fifth resistor, a first NMOS transistor, a first current mirror, and a first switching transistor. The first end of the first resistor is connected to the input voltage, the second end of the first resistor is connected to the first end of the second resistor and is connected to the non-inverting input of the first operational amplifier, the second end of the second resistor is grounded, the output end of the first operational amplifier is connected to the control end of the first NMOS transistor, the output end of the first NMOS transistor is connected to the inverting input end of the first operational amplifier, the output end of the first NMOS transistor is also grounded through the fifth resistor, the input end of the first NMOS transistor is connected to the input end of the first current mirror, the output end of the first current mirror is connected to the input end of the first switching transistor, the control end and input end of the first switching transistor are interconnected and output the first differential voltage signal, and the output end of the first switching transistor is grounded.

4. The COT control circuit for a switching power supply according to claim 2, characterized in that: The second sampling unit includes a second operational amplifier, a third resistor, a fourth resistor, a sixth resistor, a second NMOS transistor, a second current mirror, and a second switch transistor. The first end of the third resistor is connected to the output voltage, the second end of the third resistor is connected to the first end of the fourth resistor and connected to the non-inverting input of the second operational amplifier, the second end of the fourth resistor is grounded, the output end of the second operational amplifier is connected to the control end of the second NMOS transistor, the output end of the second NMOS transistor is connected to the inverting input end of the second operational amplifier, the output end of the second NMOS transistor is further grounded via the sixth resistor, the input end of the second NMOS transistor is connected to the input end of the second current mirror, the output end of the second current mirror is connected to the input end of the second switch transistor, the control end and input end of the second switch transistor are interconnected, and the second differential voltage signal is output. The output end of the second switch transistor is grounded.

5. The COT control circuit for a switching power supply according to claim 2, characterized in that: The differential signal transmission module includes a fully differential amplifier, a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistor. The first differential voltage signal is connected to the non-inverting input terminal of the fully differential amplifier through the seventh resistor, and the second differential voltage signal is connected to the inverting input terminal of the fully differential amplifier through the eighth resistor. A ninth resistor is connected between the first output terminal and the non-inverting input terminal of the fully differential amplifier, and a tenth resistor is connected between the second output terminal and the inverting input terminal of the fully differential amplifier. The resistance values of the seventh resistor, the eighth resistor, the ninth resistor, and the tenth resistor are equal.

6. The COT control circuit for a switching power supply according to claim 5, characterized in that: The ripple voltage generating module includes a bias current source, a third switching tube, a fourth switching tube, an eleventh resistor, a fixed capacitor, a fourth NMOS transistor, and a third current mirror. The third switching tube and the fourth switching tube have the same size. The input end of the bias current source is connected to the chip power supply voltage, and the output end is connected to the input end of the third switching tube. The input end and the control end of the third switching tube are commonly connected and are also connected to the first end of the eleventh resistor and the first output end of the fully differential amplifier. The control end of the fourth switching tube is connected to the second end of the eleventh resistor and the second output end of the fully differential amplifier. The input end of the fourth switching tube is connected to the input end of the third current mirror. The output end of the third current mirror is connected to the first end of the fixed capacitor and the input end of the fourth NMOS transistor for providing a ripple voltage. The control end of the fourth NMOS transistor is used to receive a falling edge detection pulse signal provided by the chip SW port. The output end of the third switching tube, the output end of the fourth switching tube, the second end of the fixed capacitor, and the output end of the fourth NMOS transistor are all grounded.

7. The COT control circuit for a switching power supply according to claim 2, characterized in that: The ripple current superposition module includes a third operational amplifier, a fifth NMOS tube, a fourth current mirror, a reference current source, a twelfth resistor and a thirteenth resistor. The non-inverting input terminal of the third operational amplifier is used to access the ripple voltage, the control terminal of the fifth NMOS tube is connected to the output terminal of the third operational amplifier, and the output terminal is connected to the inverting input terminal of the third operational amplifier. The output terminal of the third operational amplifier is also grounded through the twelfth resistor. The input terminal of the fifth NMOS tube is connected to the input terminal of the fourth current mirror. The output terminal of the fourth current mirror is connected to the output terminal of the reference current source and the first terminal of the thirteenth resistor. The input terminal of the reference current source is connected to the chip power supply voltage, and the second terminal of the thirteenth resistor is grounded.

8. The COT control circuit for a switching power supply according to claim 3, characterized in that: The first current mirror includes a first PMOS transistor and a second PMOS transistor, wherein the input end of the first PMOS transistor and the input end of the second PMOS transistor are both connected to the chip power supply voltage, the output end of the first PMOS transistor is connected to the input end of the first NMOS transistor, the output end and the control end of the first PMOS transistor are interconnected, and the control end of the first PMOS transistor is connected to the control end of the second PMOS transistor, and the output end of the second PMOS transistor is connected to the input end of the first switch transistor.

9. The COT control circuit for a switching power supply according to claim 8, characterized in that: The fixed on-time generation module includes a fifth PMOS transistor, a charging capacitor, a third NMOS transistor, and a comparator. The control end of the fifth PMOS transistor is connected to the control end of the first PMOS transistor, the input end of the fifth PMOS transistor is connected to the chip power supply voltage, the output end of the fifth PMOS transistor is commonly connected to the first end of the charging capacitor, the input end of the third NMOS transistor, and the non-inverting input end of the comparator, the inverting input end of the comparator is used to access the charging reference voltage, the output end of the comparator is used to provide a fixed on-time signal, the control end of the third NMOS transistor is used to receive the reverse signal of the switching frequency, and the second end of the charging capacitor and the output end of the third NMOS transistor are both grounded.

10. The COT control circuit for a switching power supply according to claim 9, characterized in that: The fifth PMOS transistor and the first PMOS transistor have the same length and width, but different m values, and are used to generate a charging current proportional to the input current.

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