Power converter and operating method

Abstract

A power converter includes a first set of switching elements and a second set of switching elements communicatively coupled with a first capacitor and a second capacitor. The controller is configured to periodically command a first operation of the first set of switches to supply current to the first capacitor for a first duration, followed by terminating a first interval of current to the first capacitor. The controller is also configured to periodically command a second operation of the second set of switches to provide current to the second capacitor for a second duration, followed by terminating a second interval of current to the second capacitor.

Description

Cross - reference to related applications (one or more)

[0001] This application claims the priority and benefit of U.S. Patent Application No. 18 / 415,152, filed on January 17, 2024, the entire content of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to power converters and methods of operating power converters, and more particularly to active gate drive circuits for power converters. Background Art

[0003] In the power industry, direct current (DC) distribution systems, DC energy sources such as photovoltaic (PV) panels and fuel cells, and DC - based energy storage systems are increasingly being deployed in various applications that require enhanced performance and power density. In each of these technical fields, DC - DC converters with the ability to handle high voltages and high currents are required.

[0004] Many conventional DC - DC converters employ a set of switches to assist in power conversion. For example, some DC - DC converters employ silicon carbide (SiC) switches, such as SiC metal - oxide - semiconductor field - effect transistors (MOSFETs) or insulated - gate bipolar transistors (IGBTs). Each switch can be operated or toggled by a corresponding gate - drive circuit, which can selectively provide a control signal to the gate terminal of the switch to cause the switch to transition between an on - state and an off - state. Brief Description of the Drawings

[0005] This description, which includes the best mode for one of ordinary skill in the art, is set forth in the specification, which refers to the accompanying drawings, in which In the drawings:

[0006] FIG. 1 is a schematic diagram of a conventional power converter.

[0007] Figure 2 is a schematic diagram of a power converter according to aspects described herein.

[0008] Figure 3 is according to aspects described herein, representing Figure 2 an exemplary operation of the power converter in a balanced condition, a graphical representation of a set of waveforms designated 3a - 3d.

[0009] Figure 4 is according to aspects described herein, representing Figure 2Graphical representation of a set of waveforms designated 4a - 4c of an exemplary operation of a power converter under unbalanced conditions.

[0010] Figure 5 depicts, in accordance with aspects described herein, Figure 2 A set of simplified schematic diagrams designated 5a - 5d of possible operating phases of a power converter.

[0011] Figure 6 Is a flowchart of a method for operating a power converter in accordance with aspects described herein. Detailed Description

[0012] Aspects of the present disclosure may be implemented in any environment, device, or method in a circuit regardless of the function performed by the circuit.

[0013] As used herein, the term "collection" of elements or a "group" of elements may be any number of elements, including only one. Additionally, although terms such as "voltage", "current", and "power" may be used herein, it will be apparent to those skilled in the art that these terms may be interrelated when describing aspects of a circuit or circuit operation. Thus, as used herein, the term "power" may represent voltage, current, or both voltage and current.

[0014] As used herein, the term "duty cycle" refers to the ratio of the time that a switching device or other component in a circuit is conducting or "ON" compared to the time that the switching device or other component is non - conducting or "OFF".

[0015] Unless otherwise indicated, connection references (e.g., attached, coupled, connected, and joined) are to be interpreted broadly and may include intermediate members between sets of elements and relative movement between elements. Similarly, connection references do not necessarily infer that two elements are directly connected and in a fixed relationship to each other. In a non - limiting example, connection or disconnection may be selectively configured to provide, enable, disable, etc., an electrical connection between corresponding elements. A non - limiting example of a distribution bus connection or disconnection may be enabled or operated by a switch, bus connection logic, or any other connector configured to enable or disable the excitation of an electrical load applied to the bus. Additionally, as used herein, "electrical connection" or "electrical coupling" may include wired or wireless connections. Exemplary drawings are for illustrative purposes only, and the dimensions, positions, sequences, and relative sizes reflected in the accompanying drawings may vary.

[0016] As used herein, a "controller" or "module" (e.g., "controller module" or "switch module") can include components configured or adapted to provide instructions, control, operation, or any form of communication to an operable component to affect its operation. Such a controller or module can include any known processor, microcontroller, or logic device, including but not limited to: field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), application specific integrated circuits (ASICs), full authority digital engine controls (FADECs), proportional controllers (PCs), proportional-integral controllers (PI), proportional-derivative controllers (PD), proportional-integral-derivative controllers (PID), hardware acceleration logic controllers (e.g., for encoding, decoding, transcoding, etc.), and the like, or combinations thereof. Although described herein as including separate elements, in a non-limiting aspect, such controllers and modules can be combined on one or more devices including a common device such as a single processor or microcontroller. Non-limiting examples of such a controller or module can be configured or adapted to run, operate, or otherwise execute program code to achieve an operational or functional result, including performing various methods, functions, processing tasks, calculations, comparisons, sensing or measuring of values, etc., to enable or implement the technical operations or operations described herein. The operational or functional result can be based on one or more inputs, stored data values, sensed or measured values, true or false indications, etc. Although "program code" is described, non-limiting examples of sets of operable or executable instructions can include routines, programs, objects, components, data structures, algorithms, etc. having a technical effect of performing a particular task or implementing a particular abstract data type. In another non-limiting example, a controller module or switch module can also include a data storage component accessible by a processor, including memory, whether volatile, non-transient, or non-volatile memory. Additional non-limiting examples of memory can include random access memory (RAM), read only memory (ROM), flash memory, or one or more different types of portable electronic memory, such as disks, DVDs, CD-ROMs, flash drives, universal serial bus (USB) drives, etc., or any suitable combination of these types of memory. In one example, the program code can be stored in memory in a machine-readable format accessible by the processor. Additionally, as described herein, the memory can store various data, data types, sensed or measured data values, inputs, generated or processed data, etc. accessible by the processor when providing instructions, control, or operation to affect a function or operational result.

[0017] Although various non-limiting aspects have been depicted and described herein using various switching devices including MOSFETs or IGBTs or combinations thereof, other aspects are not so limited. Other non-limiting aspects may include any desired switching device that can switch states between a low-resistance state and a high-resistance state in response to an electrical signal. For example, the switching device of the various aspects may include, but is not limited to, any desired type of switching element, including, for example, transistors, gate-commutated thyristors, field-effect transistors (FETs), IGBTs, MOSFETs, gate-turn-off thyristors, static induction transistors, static induction thyristors, or combinations thereof and combinations thereof.

[0018] Exemplary figures are for illustrative purposes only, and the dimensions, positions, sequences, and relative sizes reflected in the figures attached thereto may vary. Additionally, the number and placement of the various components depicted in the figures are also non-limiting examples of aspects associated with the present disclosure. For example, although the various components have been shown in relative positions and the like, the aspects of the present disclosure are not limited thereto, and these components are not limited based on their schematic depictions to this.

[0019] A power converter is a power source or power processing circuit that converts an input voltage waveform into a specified output voltage waveform having a controllable frequency, phase, amplitude, or polarity. Power converters can be used to convert direct current (DC) to alternating current (AC), or from DC to DC (i.e., DC-DC), or from AC to DC (i.e., AC-DC), as well as voltage or frequency, or some combination of these. Conventional power converters typically consist of one or more conversion stages. For example, a DC-AC power converter (e.g., an inverter) may include two stages, a first DC-DC converter that supplies a DC voltage, followed by a DC-to-AC converter that supplies an AC voltage to the load. The conversion stages can also be arranged as a step-down or "buck" converter (e.g., a DC-DC power converter that steps down the voltage received at its input (supply) to its output (load)). Alternatively, the conversion stages can also be arranged as a "boost" or step-up converter (e.g., a DC-DC power converter that steps up the voltage from its input to its output). Still other converters can be arranged to selectively provide buck or boost modes. Multilevel DC-DC converters are commonly used in many applications, such as renewable energy systems, energy storage systems, uninterruptible power supply systems, and electric vehicle charging systems.

[0020] A conventional power converter includes a series of semiconductor switches and voltage sources (e.g., capacitors). A controller associated with the power converter manages its operation by selectively controlling the conduction periods of the switches employed therein. The switches employed in the power converter are typically semiconductor switching devices (e.g., MOSFETs, IGBTs, etc.). The switches are selectively operated to connect an electrical load to the voltage source.

[0021] In combination with the controller, a drive circuit (e.g., a gate drive circuit) is typically used to selectively supply a drive signal to the control terminal (e.g., the gate terminal) of each semiconductor switch to control its operation in response to a corresponding command signal (e.g., a pulse width modulation (PWM) signal) from the controller.

[0022] Typically, the controller supplies a PWM command signal (e.g., a gate drive signal) of a constant frequency based on a comparison of a reference signal with a carrier signal (e.g., using a conventional comparator circuit). For example, a conventional carrier signal may include a sawtooth carrier signal, an inverse sawtooth carrier signal, a triangular carrier signal, or a combination thereof. For example, a typical triangular carrier signal includes a cyclic triangular shape, and the leading and trailing edges of the PWM signal output are modulated. Further, the rising and falling edges of the triangular carrier signal are typically symmetric. In some digital applications (e.g., non - analog), the reference signal is sampled at a regular frequency, and the carrier signal is replaced by a counter or a timer. To avoid multiple switching transitions within the carrier signal period, the reference signal is sampled corresponding to the peak and / or valley of the carrier signal.

[0023] When high voltages need to be withstood, a typical DC - DC converter employs silicon carbide (SiC) switches such as MOSFETs. As will be appreciated, compared to other switches such as IGBTs, SiC MOSFETs switch relatively faster between the on and off states, resulting in relatively lower switching losses. Due to the switching frequency of the solid - state switches (e.g., SiC MOSFETs) used in the operation of power electronic circuits, low - frequency current and high - frequency ripple current will flow in the circuit. In a conventional power converter, the high - frequency ripple current is the AC component of the output current, which is independent of the load and is generally regarded as an undesirable part of the current. To reduce the high - frequency ripple current, some conventional systems employ various chokes and filters. Such passive filters are typically referred to as "LC filters" because they typically employ inductors (L) and capacitors (C) arranged to attenuate the ripple current.

[0024] As will be described in detail herein, various non-limiting aspects of apparatus and methods for operating a power converter, such as a DC-DC power converter, are presented. Using the apparatus and methods can result in improved operating efficiency and service life of the DC-DC power converter. More specifically, the apparatus and methods enable the DC-DC power converter to operate more efficiently, especially when providing a low load or output current.

[0025] A simplified topology of a conventional DC-DC power converter 10 is depicted in FIG. 1. A set of input terminals Y1, Z1, N1 are coupled to a DC bus or other charging device (e.g., a solar panel, not shown). For example, input terminal Y1 may be coupled to the positive DC bus, input terminal N1 may be coupled to the negative DC bus, and input terminal Z1 may be coupled to the neutral bus. The power converter 10 generally includes a set of switching devices S1, S2, S3, S4 and corresponding freewheeling diodes X1, X2, X3, X4. The power converter 10 also includes an upper input capacitor C1, a lower input capacitor C2, an output capacitor C3, and two output inductors L1, L2. As shown, switches S1-S4 are arranged to define a pair of internal switches S2, S3 and a pair of external switches S1, S4. In operation, depending on the respective duty cycles of switches S1-S4, switches S1 and S4 are cycled or repeatedly switched between ON and OFF states (e.g., conducting and non-conducting states, respectively) by a controller and gate drive circuit (not shown). The internal switches S2, S3 operate complementarily with their corresponding adjacent external switches S1, S4. During balanced load conditions (e.g., equal voltages across the upper and lower input capacitors C1, C2), the respective duty cycles of external switches S1 and S4 may be the same as each other.

[0026] During operation, an output voltage Vo is provided across the output capacitor C3. Depending on the respective operating states (e.g., ON or OFF) of the switching devices S1-S4, the charging current Io from the output capacitor C3 may flow to the upper input capacitor C1, or the lower input capacitor C2, or both.

[0027] In the operation of a conventional power converter 10, balanced power is maintained over time (e.g., equal capacitor voltages Vin across upper and lower input capacitors C1, C2) to reduce stress on the upper and lower input capacitors C1, C2 and enable efficient operation of the power converter 10. To maintain power balance or equal voltages across the upper and lower input capacitors C1, C2 over time, conventional methods typically manipulate or control the duration of the charging current Io flowing to the upper input capacitor C1 relative to the duration of the charging current Io flowing to the lower input capacitor C2. It is generally desirable to operate the power converter 10 in a balanced charging condition. A balanced charging condition or balanced operation is arranged when the charging currents Io flowing to the upper and lower input capacitors C1, C2 are balanced over time. Typically, such a balanced charging condition or balanced operation is achieved by extending or shortening the relative length or duration of the ON time of switches S1 - S4.

[0028] However, the charging current Io typically includes a non - load - related AC component (e.g., ripple) Iac and an average load - related DC component Idc, such that the charging current Io is equal to the sum of the AC component Iac and the DC component Idc (Io = Iac + Idc). Additionally, the direction of the charging current Io with respect to the neutral point Z1 to the upper input capacitor C1 may be opposite to the direction of the charging current Io with respect to the neutral point Z1 to the lower input capacitor C2. Typically, the AC component Iac of the charging current Io flowing to the upper and lower input capacitors C1, C2 is not considered or controlled in conventional methods, and the net charging current Io flowing to the upper and lower input capacitors C1, C2 is typically determined based on the DC component Idc of the charging current Io. This conventional technique requires determining the direction of the charging current Io with respect to time and adjusting the duration of the charging current Io in each direction to maintain a balanced charging current Io flowing to the upper and lower input capacitors C1, C2 over time.

[0029] For example, relative to the duration that the charging current Io flows to the lower input capacitor C2, the duration that the charging current Io flows to the upper input capacitor C1 is typically manipulated by extending or shortening the duration that the charging current Io flows to one of the upper or lower input capacitors C1, C2 to arrange equal voltages across the upper and lower input capacitors C1, C2. More specifically, if the instantaneous voltage at the positive terminal Y1 is lower than the voltage at the negative terminal N1, a conventional method arranges a relatively longer duration that the charging current Io flows to the upper input capacitor C1, and / or a relatively shorter duration that the charging current Io flows to the lower input capacitor C2, such that the power converter 10 draws more charge from the positive DC bus at the positive terminal Y1 to balance the power between the positive terminal Y1 and the negative terminal N1. Conversely, if the instantaneous voltage at the positive terminal Y1 is higher than the instantaneous voltage at the negative terminal N1, the conventional method arranges the opposite regulation, where the charging current Io flows to the upper input capacitor C1 for a relatively shorter duration and the charging current Io flows to the lower input capacitor C2 for a relatively longer duration.

[0030] These conventional techniques present several challenges in practice, particularly during operation under relatively light electrical load conditions (e.g., with a relatively low charging current Io). For example, determining the net charge flowing to the upper and lower input capacitors C1, C2 requires determining the current direction of the charging current Io. Under relatively light electrical load conditions, the determined net charge flowing to the upper and lower input capacitors C1, C2 may not be accurate because it is very challenging to determine the current direction of the charging current Io without delay, for example due to the oscillations and DC offsets present in current measurements.

[0031] Accordingly, aspects disclosed herein are directed to a power converter and a control method therefor. More specifically, the aspects disclosed herein provide a power converter configured to control the operation of a switch based on a fixed ON duration while shifting (e.g., advancing or delaying) the ON duration of the switch relative to time to achieve a balanced charging condition. Compared with conventional power converters and control methods, the aspects disclosed herein do not rely on the direction of the charging current Io. Moreover, the aspects described herein enable arranging a balanced operation (e.g., balanced voltages or a balanced charging condition across the upper and lower input capacitors C1, C2) without the need to determine the direction of the charging current Io, which enables balanced operation of the power converter even at very low power levels down to and including no-load operation.

[0032] Now referring to Figure 2, which shows a schematic diagram of an exemplary DC-DC power converter 200 for implementing various aspects of the present disclosure. The power converter 200 may include a set of input terminals, such as a first input terminal 201, a second input terminal 202, and a neutral input terminal 203. The power converter 200 may include a first output terminal 204 and a second output terminal 205. A set of input capacitors 220 including a first capacitor 221 and a second capacitor 222 may be serially electrically coupled between the first input terminal 201 and the second input terminal 202. The power converter 200 may further include a first set of switches 210a, a second set of switches 210b, a first output terminal 204, a second output terminal 205, and a set of sensors 270. An output capacitor 223 may be serially coupled between the first output terminal 204 and the second output terminal 205. Optionally, a first inductor 231 may be serially electrically coupled between the first set of switches 210a and the first output terminal 204, and a second inductor 232 may be serially electrically coupled between the second set of switches 210b and the second output terminal 205. The first input terminal 201 may be coupled to a positive DC bus (not shown), the second input terminal 202 may be coupled to a negative DC bus (not shown), and the neutral input terminal 203 may be coupled to a neutral bus (not shown). A first voltage V1 may be defined across the first capacitor 221 (e.g., between the first input terminal 201 and the neutral input terminal 203), and a second voltage V2 may be defined across the second capacitor C2 (e.g., between the second input terminal 202 and the neutral input terminal 203). A third voltage (e.g., an output voltage) may be defined across the output capacitor 223 (e.g., between the first output terminal 204 and the second output terminal 205).

[0033] The first set of switches 210a may include a first switch 211 and a second switch 212. The second set of switches 210b may include a third switch 213 and a fourth switch 214. The first switch 211, the second switch 212, the third switch 213, and the fourth switch 214 may hereinafter be collectively referred to as switches 211-214. Additionally, for ease of reference, the first switch 211 and the fourth switch 214 may be collectively referred to as external switches 211, 214 herein, and the second switch 212 and the third switch 213 may be collectively referred to as internal switches 212, 213 herein. Each of the switches 211-214 may further include a corresponding gate drive circuit 250. For example, the corresponding gate drive circuit 250 may be communicatively coupled to each of the switches 211-214.

[0034] The corresponding gate drive circuit 250 may be communicatively coupled to the gate terminals of each of the switches 211-214. In a non-limiting aspect, a modulator 227 may be communicatively coupled to the gate drive circuit 250. In Figure 2In the non-limiting aspects shown, the modulator 227 is depicted as part of the power converter 200. In other aspects, the modulator 227 may be deployed remote from the power converter 200. The modulator 227 may include a controller 226 configured to control the operation of switches 211 - 214 to facilitate the operation of the power converter 200. The controller 226 may include hardware elements such as a specially programmed general-purpose computer, an electronic processor such as a microprocessor, a digital signal processor, an FPGA, a microcontroller, or a combination thereof. Additionally, the controller 226 may include input / output (I / O) ports and a storage medium such as an electronic memory. Various examples of microprocessors include, but are not limited to, microprocessors of the reduced instruction set computing (RISC) architecture type or the complex instruction set computing (CISC) architecture type. Further, the microprocessor may be of the single-core type or the multi-core type. Alternatively, the controller 226 may be implemented using hardware elements such as a circuit board with a processor, logic gates, or as software running on a processor such as a personal computer (PC) or a microcontroller.

[0035] The controller 226 may be communicatively coupled to the gate drive circuit 250 and configured to selectively control the operation of switches 211 - 214. For example, the set of gate drive circuits 250 may receive command signals (e.g., PWM command signals) from the controller 226. In non-limiting aspects, the first set of switches 210a may be arranged to receive a first command signal 251 from the controller 226, and the second set of switches may be arranged to receive a second command signal 254 from the controller 226. The controller 226 may be further communicatively coupled to the set of sensors 270.

[0036] The set of sensors 270 may be configured to detect, measure, or otherwise sense corresponding electrical parameters (e.g., voltage) associated with the operation of the power converter 200. Each sensor 270 may include any desired conventional sensor type, including but not limited to a voltage sensor, a current sensor, or a combination thereof. Each sensor 270 may be arranged to provide a corresponding sensor signal 270a (e.g., a voltage signal) indicative of the value of the corresponding electrical parameter to the controller 226. The value of the corresponding electrical parameter may directly or indirectly at least partially indicate the first voltage V1 across the first capacitor 221, or the second voltage V2 across the second capacitor 222, or both. For example, a particular sensor 270 may provide a first corresponding sensor signal 270a indicative of the first voltage V1 across the first capacitor 221 to the controller 226, and another sensor 270 may provide a second corresponding sensor signal 270a indicative of the second voltage V2 across the second capacitor 222 to the controller 226.

[0037] The controller 226 may be communicatively coupled to the set of sensors 270 via a suitable wired or wireless communication line. The controller 226 may be configured to determine the value of at least one corresponding electrical parameter based on the respective sensor signals 270a. The controller 226 may be configured to selectively activate or energize the first set of switches 210a or the second set of switches 210b or both, at least in part based on the respective sensor signals 270a. It will be appreciated that the set of sensors 270 may include any desired number of sensors 270.

[0038] For ease of description and understanding, the first set of switches 210a and the second set of switches 210b are depicted in Figure 2 the exemplary non-limiting aspects as each having two switches. However, aspects having any number of switches are also contemplated, including more than two switches in the first set of switches 210a and the second set of switches 210b. Additionally, the switches 211-214 are discussed and described herein as including SiC MOSFETs. Other aspects are not so limited, and the power converter 200 may include other types of switches as needed. Other non-limiting examples of the switches 211-214 may include transistors, gate-commutated thyristors, FETs, MOSFETs, IGBTs, gate turn-off thyristors, static induction transistors, static induction thyristors, or combinations thereof. Additionally, the materials used to form the switches 211-214 may include, but are not limited to, silicon (Si), germanium (Ge), SiC, gallium nitride (GaN), or combinations thereof.

[0039] As will be appreciated, a SiC switch module (e.g., a MOSFET) may include more than one switch. Thus, in some non-limiting aspects, two such SiC modules may be used to form Figure 2 the power converter 200. For example, a first SiC switch module (not shown) may include a first switch 211 and a second switch 212, while a second SiC switch module (not shown) may include a third switch 213 and a fourth switch 214. It will be appreciated that other types of switch modules may also be used without limiting the scope of the present disclosure.

[0040] As Figure 2 depicted in the non-limiting aspects, the first switch 211, the second switch 212, the third switch 213, and the fourth switch 214 may be electrically coupled in series. More specifically, the first switch 211, the second switch 212, the third switch 213, and the fourth switch 214 may be electrically coupled in series such that the source terminal of the first switch 211 is connected to the drain terminal of the second switch 212, the source terminal of the second switch 212 is connected to the drain terminal of the third switch 213, and the source terminal of the third switch 213 is connected to the drain terminal of the fourth switch 214.

[0041] In addition, the first switch 211 is operably coupled to the first input terminal 201, and the fourth switch 214 is operably coupled to the second input terminal 202. More specifically, as Figure 2 depicted, the drain terminal of the first switch 211 can be connected to the first input terminal 201, while the source terminal of the fourth switch 214 can be connected to the second input terminal 202.

[0042] In addition, a first node 241 is provided as the interconnection point of the second switch 212 and the third switch 213. The first node 241 is communicatively coupled to the neutral input terminal 203. In addition, a second node 242 is provided as the interconnection point of the first switch 211 and the second switch 212. In addition, a third node 243 is provided as the interconnection point of the third switch 213 and the fourth switch 214.

[0043] In a non-limiting aspect, the first inductor 231 is electrically coupled in series between the second node 242 and the first output terminal 204. The second inductor 232 is electrically coupled in series between the third node 243 and the second output terminal 205. Additionally, the first capacitor 221 is electrically connected between the first input terminal 201 and the neutral input terminal 203. In addition, the second capacitor 222 is electrically connected between the second input terminal 202 and the neutral input terminal 203.

[0044] In operation, the controller 226 can be configured to selectively command one or more of the switches 211 - 214 to be in a conducting state (e.g., ON state) and operate the remaining switches in a non-conducting state (e.g., OFF state). As will be appreciated, the switches 211 - 214 operating in the conducting state allow current to pass, while the switches 211 - 214 operating in the non-conducting state prevent current from flowing. In a non-limiting aspect, the controller 226 can be configured to periodically command a first operation of the first set of switches 210a (e.g., based on a predetermined duty cycle). In addition, the controller 226 is further configured to periodically command a second operation of the second set of switches 210b (e.g., based on a predetermined duty cycle).

[0045] Based on the respective operating states (e.g., ON state or OFF state) of the switches 211 - 214, a charging current Ic can be provided from the third capacitor C3. As will be described in more detail herein, the charging current Ic can flow in a first direction (relative to the neutral input terminal 203) to the first capacitor 221 for a fixed first duration or in a second direction (relative to the neutral input terminal 203) to the second capacitor 222 for a fixed second duration.

[0046] The controller 226 can be configured to selectively supply a first command signal 251 or a second command signal 254 to the respective gate drive circuits 250 of each of the switches 211-214, so as to cause the gate drive circuits 250 to trigger the respective operations of the switches 211-214, thereby independently commanding the first operation or the second operation of the switches 211-214 in the on state or the off state respectively. For example, the controller 226 can be configured to selectively supply the respective first command signal 251 to the first set of switches 210a. In addition, the controller 226 can be configured to selectively supply the respective second command signal 254 to the second set of switches 210b.

[0047] In Figure 2 In a non-limiting aspect, the switches 211-214 are depicted as N-channel SiC MOSFETs. Therefore, in order to operate any of the switches 211-214 in the on state, it is desirable to supply the respective first or second command signal 251, 254 with a higher amplitude (H) to the corresponding gate terminal. It can be noted that the first or second command signal 251, 254 with a higher amplitude represents the respective first or second command signal 251, 254 having an amplitude greater than the amplitude of the signal supplied to the corresponding source or emitter terminal. Similarly, in order to operate any of the switches 211-214 in the off state, it is desirable to supply the respective first or second command signal 251, 254 with a lower amplitude (L) to the corresponding gate terminal. It can be noted that the respective first or second command signal 251, 254 with a lower amplitude represents the first or second command signal 251, 254 having an amplitude lower than the amplitude of the signal supplied to the corresponding source or emitter terminal. In addition, it can be noted that if P-channel SiC MOSFETs are used as the switches 211-214, the levels of the respective first and second command signals 251, 254 can be interchanged.

[0048] Therefore, in order to operate any of the switches 211-214 in the on state, the controller 226 can be configured to supply the respective command signal 251, 254 with a higher amplitude to the respective gate terminals of the switches 211-214 via the respective gate drive circuits 250. Similarly, in order to operate any of the switches 211-214 in the off state, the controller 226 can be configured to supply the command signal 251, 254 with a lower amplitude (L) to the respective gate terminals of the switches 211-214 via the gate drive circuits 250.

[0049] The controller 226 may also receive from the set of sensors 270 one or more sensor signals 270a indicative of values of one or more sensed electrical parameters (such as voltage). The controller 226 may determine the magnitude or value of one or more electrical parameters based on the corresponding sensor signals 270a. For example, the controller 226 may receive from a sensor 270 (such as a voltage sensor) a sensor signal 270a indicative of the magnitude or value of a first voltage V1 across a first capacitor 221, and may further receive from another sensor 270 (such as a voltage sensor) another sensor signal 270a indicative of the magnitude or value of a second voltage V2 across a second capacitor 222. The controller 226 may be configured to determine the magnitude of the first voltage V1 and the magnitude of the second voltage V2 based on the sensor signals 270a from the sensors 270. The controller 226 may be further configured to determine the difference between the magnitude of the first voltage V1 and the magnitude of the second voltage V2.

[0050] The controller 226 may further determine when an imbalance condition exists with respect to the first and second capacitors 221, 222. For example, the controller 226 may determine the existence of an imbalance condition based on the magnitude of the first voltage V1 and the magnitude of the second voltage V2 or the difference therebetween. In one non-limiting example, the controller 226 may be configured to determine the existence of an imbalance condition when the magnitude of the first voltage V1 across the first capacitor 221 is not equal to the magnitude of the second voltage V2 across the second capacitor 222. In another non-limiting example, the controller 226 may be configured to determine the existence of an imbalance condition when the difference between the magnitude of the first voltage V1 across the first capacitor 221 and the magnitude of the second voltage V2 across the second capacitor 222 is greater than a predetermined range or a predetermined magnitude.

[0051] If the controller 226 determines that an imbalance condition exists, the controller 226 may be configured to cause a phase shift or a timing advance of the first command signal 251. For example, in a non-limiting aspect, based on the determination that an imbalance condition exists, the controller 226 may be configured to advance the first operation of the first set of switches 210a by supplying the first command signal 251 to the first set of switches 210a at a time point earlier than the time point at which it would be supplied during a balanced charging condition. The magnitude (such as time) of the advance of the first operation of the first set of switches 210a may be based on (such as proportional to) the magnitude of the difference between the first voltage V1 and the second voltage V2.

[0052] Alternatively, in a non-limiting aspect, based on the determination of the presence of an imbalance condition, the controller 226 may be configured to delay the first operation of the first set of switches 210a by supplying the first command signal 251 to the first set of switches 210a at a time point later than the time point at which it would be supplied during a balanced charging condition. The magnitude (e.g., time) of the delay of the first operation of the first set of switches 210a may be based on (e.g., proportional to) the magnitude of the difference between the first voltage V1 and the second voltage V2.

[0053] In addition, or alternatively, in a non-limiting aspect, based on the determination of the presence of an imbalance condition, the controller 226 may be configured to advance the second operation of the second set of switches 210b by supplying the second command signal 254 to the second set of switches 210b at a time point earlier than the time point at which it would be supplied during a balanced charging condition. The magnitude (e.g., time) of the advancement of the second operation of the second set of switches 210b may be based on or proportional to the magnitude of the difference between the first voltage V1 and the second voltage V2.

[0054] In other non-limiting aspects, based on the determination of the presence of an imbalance condition, the controller 226 may be configured to delay the second operation of the second set of switches 210b by supplying the second command signal 254 to the second set of switches 210b at a time point later than the time point at which it would be supplied during a balanced charging condition. The magnitude (e.g., time) of the delay of the second operation of the second set of switches 210b may be based on or proportional to the magnitude of the difference between the first voltage V1 and the second voltage V2.

[0055] Reference will be made simultaneously to Figure 2-3 and Figure 5 to discuss a more detailed example of the exemplary operation of one aspect of the power converter 200 during a balanced charging condition (e.g., with respect to the first and second capacitors 221, 222). In addition, reference will then be made simultaneously to Figure 2 and Figure 2 and Figure 4 to discuss an example of the exemplary operation of an aspect of the power converter 200 during an unbalanced charging condition (e.g., with respect to the first and second capacitors 221, 222). Figure 2 An example of the exemplary operation of an aspect of the power converter 200 during an unbalanced charging condition (e.g., with respect to the first and second capacitors 221, 222).

[0056] Figure 3 A set of timing diagrams (designated as Charts 3a - 3d) is shown, which depict, over time, in a balanced operating condition (e.g., with respect to the first and second capacitors 221, 222), the relationship with Figure 2Concurrent waveforms associated with an exemplary operation of the power converter 200. Chart 3a shows the respective common duty cycles D1, D4 (shown as respective reference signals D1, D4) of the external switches 211, 214 that are less than or equal to 0.5 (e.g., 0.4). Chart 3b depicts the binary operating state (e.g., ON / OFF) of the first switch 211 over time relative to Chart 3a. Chart 3c depicts the binary operating state (e.g., ON / OFF) of the fourth switch 214 over time relative to Chart 3a. Chart 3d depicts the magnitude of the charging current Ic over time based on the operation of the external switches 211, 214 as indicated in Charts 3a - 3c.

[0057] The duty cycles D1, D4 depicted in Chart 3a can be predetermined duty cycles. While the specific example depicted in Chart 3a depicts external switches 211, 214 having equal duty cycles less than 0.5, other aspects are not limited thereto, and it is contemplated that the external switches 211, 214 can be arranged to have any desired respective duty cycles (including greater than 0.5 and equal to 0.5), and the respective duty cycles need not be equal. Additionally, Chart 3a depicts respective carrier signals designated as a first carrier signal CS1 and a second carrier signal CS4, where the first and second carrier signals CS1, CS4 correspond to the external switches 211, 214, respectively. The respective first and second carrier signals CS1, CS4 are 180 - degree interleaved and symmetric with each other. Based on the comparison of the duty - cycle reference signals D1, D4 with the interleaved first and second carrier signals CS1, CS4, respectively (e.g., using a conventional comparator circuit), the controller 226 can supply first and second command signals 251, 254 to the external switches 211, 214, respectively. While the example shown in Chart 3a depicts the first and second carrier signals CS1, CS4 as 180 - degree interleaved triangular carrier signals, it will be appreciated that other aspects are not limited thereto, and other carrier - signal waveforms, such as sawtooth, inverse - sawtooth, etc., can be employed and can be interleaved in any desired phase direction. In still other aspects, non - analog duty - cycle reference signals D1, D4 can be sampled by the controller 226 at a regular frequency, and the first and second carrier signals CS1, CS4 can be replaced by a counter or timer (not shown) without departing from the scope of the present disclosure.

[0058] In operation, the controller 226 is configured to selectively command one or more of the switches 211 - 214 to be in an on - state (e.g., ON state) operation and cause the remaining switches to be in an off - state (e.g., OFF state) operation. In non - limiting aspects, the controller 226 can be configured to periodically command a first operation of the first set of switches 210a (e.g., based on the respective duty cycle D1), and is also configured to periodically command a second operation of the second set of switches 210b (e.g., based on the respective duty cycle D4).

[0059] For example, the first operation may include periodically operating the first switch 211 based on a duty cycle D1 to be in an ON state for a fixed first duration T1, followed by a predetermined first interval P1 in an OFF state. The first duration T1 includes a start point T1a and an end point T1b, where the duration of T1 is the time elapsed between T1a and T1b. Similarly, the first interval P1 includes a start point P1a and an end point P1b, where the duration of P1 is the time elapsed between P1a and P1b. Conversely, the first operation may include periodically operating the second switch 212 to be in an OFF state for the first duration T1, followed by an ON state in a predetermined first interval P1. In the specific example shown, the first switch 211 is shown to be in an ON state at t = t0 on the horizontal axis (e.g., during the first duration T1). At the end point T1b (where t = t1 on the horizontal axis), the first switch 211 is switched to an OFF state at the start point P1a to start the first interval P1. Then, at the end point P1b, the first interval P1 ends at t = t4 on the horizontal axis, and the first switch 211 cycles back to the ON state at the start point T1a to start the first duration T1.

[0060] Similarly, the second operation may include periodically operating the fourth switch 214 based on a predetermined duty cycle D4 to be in an ON state for a fixed second duration T2, followed by a predetermined second interval P2 in an OFF state. The second duration T2 includes a start point T2a and an end point T2b, where the duration of T2 is the time elapsed between T2a and T2b. Similarly, the second interval P2 includes a start point P2a and an end point P2b, where the duration of P2 is the time elapsed between P2a and P2b. Conversely, the second operation may include periodically operating the third switch 213 to be in an OFF state for the second duration T2, followed by a predetermined second interval P2. For example, the fourth switch 214 is shown to be in an OFF state at t = t0 on the horizontal axis (i.e., during the second interval P2), until reaching the start point at T2a (where t = t2 on the horizontal axis), when the fourth switch 214 is switched to an ON state for the second duration T2 that ends at t = t3 on the horizontal axis when the fourth switch 214 cycles back to an OFF state at the start point P2a for the second interval P2. The fixed first duration T1 and the fixed second duration T2 may be based on the predetermined respective duty cycles of the first and second sets of switches 210a, 210b.

[0061] Figure 5 is depicted Figure 2Four possible operating phases of the power converter 200, and the corresponding equivalent circuits (shown as operating phases: (5a) 212-213, (5b) 211-213, (5c) 212-214, and (5d) 211-214), where the corresponding numbers indicate which of the switches 211-214 are turned on during the respective operating phases ((5a) 212-213, (5b) 211-213, (5c) 212-214, and (5d) 211-214). For ease of description and understanding, and for clarity, the controller 226 is omitted in Figure 5 The polarity of the charging current Ic is depicted as positive, and the first and second capacitors 221, 222, and the output capacitor 223 are depicted as corresponding ideal voltage sources, providing the respective first and second voltages V1, V2.

[0062] In operation, the external switches 211, 214 respond to the respective first command signal 251 or second command signal 254 provided by the controller 226 (as Figure 2 shown) and cycle between the ON and OFF states according to the respective duty cycles (e.g., 40%) indicated by the duty cycle reference signals D1, D4 (as Figure 3 shown). As shown in the diagram 3a of Figure 3 , the timing of the first command signal 251 and the second command signal 254 can be based on the comparison by the controller 226 of the respective reference signals D1, D4 for the external switches 211, 214 with the first and second carrier signals (designated as CS1, CS4). In a non-limiting aspect, the first (external) switch 211 can operate complementarily to the second (internal) switch 212. For example, the first switch 211 can cycle between the ON and OFF states in response to the respective first command signal 251 ( Figure 2 ), while the second switch 212 can operate in response to the NOT or opposite signal of the first command signal 251. Similarly, in a non-limiting aspect, the fourth (external) switch 214 can operate complementarily to the third (internal) switch 213. For example, the fourth switch 214 can cycle between the ON and OFF states in response to the respective first command signal 251 ( Figure 2 ), while the third switch 213 can operate in response to the NOT or opposite signal of the first command signal 251. Thus, in a non-limiting aspect, the internal switches 212, 213 can be actuated complementarily to their corresponding adjacent external switches 211, 214.

[0063] Referring simultaneously to Figure 3 and Figure 5, starting from a time reference equal to zero (e.g., at t = t0 on the horizontal axis), the first switch 211 is in the ON or conducting state, and the fourth switch 214 is in the OFF or non-conducting state, corresponding to the operation phase (5b) 211 - 213. As time increases, when the rising edge of the first carrier signal CS1 is equal to or crosses the reference signal D1 (e.g., at t = t1), the controller 226 supplies a first command signal 251 to trigger the first switch 211 to switch to the OFF or non-conducting state, thereby transitioning the power converter 200 to the operation phase (5a) 212 - 213. Next, as time increases, when the falling edge of the second carrier signal CS4 is equal to or crosses the reference signal D4 (e.g., at t = t2), the controller 226 supplies a second command signal 254 to trigger the fourth switch 214 to switch to the ON or conducting state, transitioning the power converter 200 to the operation phase (5c) 212 - 214.

[0064] As time increases, when the rising edge of the second carrier signal CS4 is again equal to or crosses the reference signal D4 (e.g., at t = t3), the controller 226 supplies the second command signal 254 to trigger the fourth switch 214 to switch to the OFF or non-conducting state, transitioning the power converter 200 back to the operation phase (5a) 212 - 213.

[0065] Next, as time increases, when the falling edge of the first carrier signal CS1 is again equal to or crosses the reference signal D1 (e.g., at t = t4), the controller 226 supplies the first command signal 251 to trigger the first switch 211 to switch to the ON or conducting state, converting the power converter 200 back to the operation phase (5b) 211 - 213.

[0066] However, in operation, the controller 226 ( Figure 2) is also configured to determine when there is an imbalance condition regarding the first and second capacitors 221, 222. For example, when the magnitude of the first voltage V1 across the first capacitor 221 is not equal to the magnitude of the second voltage V2 across the second capacitor 222, or when the difference between the magnitude of the first voltage V1 across the first capacitor 221 and the magnitude of the second voltage V2 across the second capacitor 222 is greater than a predetermined range or magnitude, the controller 226 may determine that an imbalance condition exists. When the controller 226 determines that an imbalance condition exists, the controller 226 is configured to advance or delay the start of at least one or both of the first interval T1 or the second interval T2. In a non-limiting aspect, the advancement or delay of the start of at least one or both of the first interval T1 or the second interval T2 may include a phase shift (e.g., timing advance or timing delay) of the first or second carrier signal CS1, CS4, or both, such that the first and second carrier signals CS1, CS4 are asymmetric with respect to each other. This phase shift of the first carrier signal CS1 or the second carrier signal CS4, or both, causes the controller 226 to supply the first command signal 251 or the second command signal 254, or both, at one of the time points earlier or later than the time point at which they would be supplied in a balanced charging condition, without modifying the length of the first duration T1 or the second duration T2. The magnitude of the advancement or delay (e.g., time) may be based on (e.g., proportional to) the magnitude of the difference between the first voltage V1 and the second voltage V2.

[0067] Reference will now be made simultaneously to Figure 4 discuss an example of exemplary operation of the power converter 200 during an Figure 2 imbalanced charging condition (e.g., regarding the first and second capacitors 221, 222). For the purpose of concise description, a specific instance of an imbalanced charging condition where the second voltage V2 is less than the first voltage V1 will be described by way of one non-limiting example. Other aspects are not limited thereto, and it is contemplated that in other instances, the imbalanced charging condition may be based on other operating conditions, such as the first voltage V1 being less than the second voltage V2.

[0068] Figure 4 A set of timing diagrams (designated as FIGS. 4a - 4d) is shown, which depict the concurrent waveforms associated with Figure 2 the exemplary operation of the power converter 200. FIGS. 4a - 4d are similar to Figure 3 the FIGS. 3a - 3d depicted in Figure 3 However, although Figure 2 the FIGS. 3a - 3d of Figure 4 depict the waveforms associated with the operation of the power converter 200 of Figure 2Waveforms associated with the operation over time of the power converter 200 in an unbalanced condition with respect to the first and second capacitors 221, 222, e.g., when the second voltage V2 is less than the first voltage V1.

[0069] Chart 4a shows the respective common duty cycles (indicated by the reference signals D1, D4) of the external switches 211, 214 that are less than or equal to 0.5 (e.g., 0.4). Chart 4b depicts the binary operating state (e.g., ON / OFF) of the first switch 211 over time with respect to Chart 4a. Chart 4c depicts the binary operating state (e.g., ON / OFF) of the fourth switch 214 over time with respect to Chart 4a. Chart 4d depicts the magnitude of the charging current Ic over time based on the operation of the external switches 211, 214 in response to the unbalanced condition as indicated in Charts 4a - 4c. For purposes of clarity and ease of understanding, the waveform of the charging current Ic over time based on the operation of the external switches 211, 214 when operating in a balanced condition (as Figure 3 shown in Chart 3d of Figure 4 d) is overlapped as a dashed line on the

[0070] charging current waveform Ic of d. Figure 4 Although the specific example shown in Chart 4a depicts the external switches 211, 214 having equal duty cycles less than 0.5, other aspects are not so limited, and the external switches 211, 214 can be arranged to have any desired respective duty cycles (including greater than 0.5 as well as less than 0.5), and the respective duty cycles need not be equal. Additionally, although Figure 3 Chart 4a depicts the respective first and second carrier signals CS1, CS4 corresponding to the external switches 211, 214, it will be appreciated that the controller 226 can supply the first and second command signals 251, 254 to the external switches 211, 214 respectively based on the comparison of the reference signals D1, D4 with the interleaved first and second carrier signals CS1, CS4 respectively (e.g., using a conventional comparator circuit). It is noted that although in Figure 4 the exemplary instance depicted in Chart 3a of Figure 2 depicts a balanced operating condition where the first and second carrier signals CS1, CS4 are symmetric with respect to each other, in contrast, the instance depicted in Chart 4a of

[0071] depicts an unbalanced operating condition where the controller 226 ( Figure 4As shown in Chart 4a, the carrier signal CS4 intersects with the duty cycle reference signal D4 at time t = t2 on the horizontal axis, and triggers the controller 226 to supply the second command signal 254 to the fourth switch 214. Figure 4 The exemplary instance shown in Chart 4a of [document] shows the phase shift of the second carrier signal CS4. More specifically, in an exemplary instance where the controller 226 determines an imbalance condition (e.g., the first voltage V1 is greater than the second voltage V2), the controller 226 changes (e.g., shifts earlier in time) the second carrier signal CS4 such that the second carrier signal CS4 intersects with the reference signal D4 earlier in time (e.g., at t1.8 on the horizontal axis) than in the previous example in the balanced condition of Chart 3a (e.g., at t = t2). The magnitude (e.g., time) of the phase shift of the second carrier signal CS4 may be based on or proportional to the magnitude of the difference between the first voltage V1 and the second voltage V2. Although Figure 4 the specific example depicted in [document] shows the exemplary phase shift of the second carrier signal CS4 when the first voltage V1 is greater than the second voltage V2, other aspects are not limited thereto. For example, aspects are envisioned where the controller 226 delays or phase-shifts the second carrier signal CS4 to intersect with the reference signal D4 later in time based on the determination that the first voltage V1 is less than the second voltage V2. Additionally or alternatively, in other aspects, the controller may similarly advance or delay the first carrier signal CS1 based on the difference between the first voltage V1 and the second voltage V2 to intersect with the duty cycle reference signal D1 earlier or later in time. The magnitude (e.g., time) of the phase shift of the first carrier signal CS1 may be based on or proportional to the magnitude of the difference between the first voltage V1 and the second voltage V2.

[0072] The phase shift of the second carrier signal CS4 depicted in Chart 4a may further cause the controller 226 to advance or otherwise supply the second command signal 254 to operate the fourth switch 214 earlier in time than in the balanced condition without modifying the duration of the second duration T2.

[0073] While the example shown in Chart 4a depicts the first and second carrier signals CS1, CS4 as interleaved triangular carrier signals, it will be appreciated that other aspects are not limited thereto, and other carrier signals, such as sawtooth, anti-aliasing, etc., may be employed and interleaved in any desired phase direction. In still other aspects, the non-analog duty cycle reference signals D1, D4 may be sampled by the controller 226 at a regular frequency, and the first and second carrier signals CS1, CS4 may be replaced by a counter or timer (not shown). Additionally, while non-limiting aspects are described herein for ease of description and understanding with reference to a duty cycle less than or equal to 0.5, other aspects are not limited thereto, and the power converter 200 may operate the first set of switches 210a and the second set of switches 210b using any desired duty cycle (including equal to, greater than, or less than 0.5) without departing from the scope of the present disclosure.

[0074] As shown in Chart 4b, based on a predetermined duty cycle, the first switch 211 is periodically operated to be in an ON state during a first duration T1, followed by a first interval P1 in an OFF state. The first duration T1 includes a starting point T1a and an ending point T1b, where the duration of T1 is the time elapsed between T1a and T1b. Similarly, the first interval P1 includes a starting point P1a and an ending point P1b, where the duration of P1 is the time elapsed between P1a and P1b. Conversely, the first operation may include periodically operating the second switch 212 to be in an OFF state during the first duration T1, followed by an ON state within a predetermined first interval P1.

[0075] For example, during the first duration T1, the first switch 211 is shown to be in an ON state at t = t0 on the horizontal axis, and at the ending point T1b (where t = t1 on the horizontal axis), the first switch 211 is switched to an OFF state at the starting point P1a to begin the first interval P1. Then, at the ending point P1b, the first interval P1 ends at t = t4 on the horizontal axis, and the first switch 211 cycles back to an ON state at the starting point T1a to begin the first duration T1.

[0076] Referring to Figure 4c, the fourth switch 214 is periodically operated to be in the non-conducting (OFF) state within the second interval P2 based on a predetermined duty cycle, followed by a second duration T2 in the conducting (ON) state. The second duration T2 includes a starting point T2a and an ending point T2b, where the duration of T2 is the time elapsed between T2a and T2b. Similarly, the second interval P2 includes a starting point P2a and an ending point P2b, where the duration of P2 is the time elapsed between P2a and P2b. Conversely, the second operation may include periodically operating the third switch 213 to be in the non-conducting (OFF) state within the second duration T2, followed by a predetermined second interval P2. More specifically, during the second interval P2, the fourth switch 214 is shown to be in the non-conducting state at t = t0 on the horizontal axis until reaching the starting point at T2a (where t = t1.8 on the horizontal axis), when the fourth switch 214 cycles back to the non-conducting state at the starting point P2a for the second interval P2, and the fourth switch 214 is switched to the conducting state for the second duration T2, which ends at t = t2.8 on the horizontal axis.

[0077] It is noted that in Figure 4 the depicted example, due to the unbalanced operating condition, the second duration T2 is advanced in time (e.g., from Figure 3 t = t2 in the depicted balanced condition) to t = t1.8, but the duration or the length of the second duration T2 with respect to time remains unchanged. As depicted, by advancing the second duration T2 in time, more charging current Ic flows out of the second capacitor 222 (e.g., from the positive terminal as shown) in the unbalanced operating condition compared to the balanced operating condition, without the need to modify the length of the second duration T2 with respect to time.

[0078] Figure 6 A method 700 of operating a power converter 200 is depicted. Although described in terms of a power converter, it will be appreciated that the method 700 may be applied to any electronic device. While the method 700 will be described herein, for ease of understanding, with reference to Figure 2-5 the described power converter 200, other aspects are not limited thereto, and the method 700 may be implemented with any power converter without departing from the scope of the present disclosure. In a non-limiting aspect, the power converter 200 may be arranged as a DC-DC power converter.

[0079] The power converter 200 may include the set of input terminals, such as a first input terminal 201, a second input terminal 202, and a neutral input terminal 203. The power converter 200 may include a first output terminal 204 and a second output terminal 205. The set of input capacitors 220 includes a first capacitor 221 and a second capacitor 222, and may be electrically coupled in series between the first input terminal 201 and the second input terminal 202. The power converter 200 may further include a first set of switches 210a, a second set of switches 210b, a first output terminal 204, and a second output terminal 205. An output capacitor 223 may be coupled in series between the first output terminal 204 and the second output terminal 205. The first input terminal 201 may be coupled to a positive DC bus (not shown), the second input terminal 202 may be coupled to a negative DC bus (not shown), and the neutral input terminal 203 may be coupled to a neutral bus (not shown). A first voltage V1 may be defined across the first capacitor 221, and a second voltage V2 may be defined across the second capacitor C2. A third voltage V3 (e.g., the output voltage) may be defined across the output capacitor 223.

[0080] The first set of switches 210a may include a first switch 211 and a second switch 212. The second set of switches 210b may include a third switch 213 and a fourth switch 214. Each of the switches 211 - 214 may further include a corresponding gate drive circuit 250. The set of gate drive circuits 250 may be communicatively coupled to a controller 226 to receive one of a first command signal 251 or a second command signal 254 from the controller 226. In a non - limiting aspect, the controller 226 may include the controller 226. The controller 226 may be further communicatively coupled to the set of sensors 270.

[0081] The set of sensors 270 may be configured to detect, measure, or otherwise sense corresponding electrical parameters (e.g., voltage) associated with the operation of the power converter 200. Each sensor 270 may be arranged to provide a corresponding sensor signal 270a indicative of a value of the corresponding electrical parameter to the controller 226. The value of the corresponding electrical parameter may directly or indirectly at least partially indicate the first voltage V1 across the first capacitor 221, or the second voltage V2 across the second capacitor 222, or both.

[0082] The first switch 211, the second switch 212, the third switch 213, and the fourth switch 214 may be electrically coupled in series. Based on the corresponding operating states (e.g., ON or OFF) of the switches 211 - 214, a charging current Ic is provided from a third capacitor C3. The charging current Ic may flow in a first direction (relative to the neutral input terminal 203) to the first capacitor 221, or in a second direction (relative to the neutral input terminal 203) to the second capacitor 222.

[0083] At 710, method 700 begins with the controller 226 periodically commanding a first operation of the first set of switches 210a to supply a charging current Ic to the first capacitor 221 for a fixed first duration T1, followed by a first interval P1 during which the charging current Ic to the first capacitor 221 is terminated. The method includes, at 720, the controller 226 periodically commanding a second operation of the second set of switches 210b to provide a charging current Ic to the second capacitor 222 for a fixed second duration T2, followed by a second interval P2 during which the charging current Ic to the second capacitor 222 is terminated. The fixed first duration T1 and the fixed second duration T2 may be based on the respective predetermined duty cycles of the first and second sets of switches 210a, 210b. In a non-limiting aspect, periodically commanding the first operation includes the controller 226 supplying a first command signal 251 to the first set of switches 210a. Additionally, in a non-limiting aspect, commanding the second operation includes the controller 226 supplying a second command signal 254 to the second set of switches 210b.

[0084] Method 700 may include, at 730, determining whether an imbalance condition exists based on a comparison of the magnitude of a first voltage V1 across the first capacitor 221 and the magnitude of a second voltage V2 across the second capacitor 222. For example, the controller 226 determining whether an imbalance condition exists may include the controller 226 determining the magnitude of the first voltage V1 and the magnitude of the second voltage V2 based on a sensor signal 270a received from the sensor 270. In a non-limiting aspect, the controller 226 determining that an imbalance condition exists may include determining that the magnitude of the first voltage V1 across the first capacitor 221 is not equal to the magnitude of the second voltage V2 across the second capacitor 222. In another non-limiting example, the controller 226 determining that an imbalance condition exists may include determining that the difference between the magnitude of the first voltage V1 across the first capacitor 221 and the magnitude of the second voltage V2 across the second capacitor 222 is greater than a predetermined range or predetermined magnitude.

[0085] In the case where an imbalance condition is determined to exist, method 700 may include, at 740, advancing or delaying the start of one or both of a first duration T1 and a second duration T2. In a non - limiting aspect, advancing or delaying the start of the first duration T1 may include a phase shift or timing advance of a first command signal 251. In a non - limiting aspect, advancing or delaying the start of the second duration T2 may include a phase shift or timing advance of a second command signal 254. For example, in a non - limiting aspect, based on the determination of the existence of an imbalance condition, the controller 226 may be configured to advance the first duration T1 of the first set of switches 210a by advancing or supplying the first command signal 251 to the first set of switches 210a at a time point earlier than the time point at which it would be supplied during a balanced charging condition, without changing the length of the first duration T1. The magnitude of the advance (e.g., time) may be based on or proportional to the magnitude of the difference between the first voltage V1 and the second voltage V2.

[0086] Alternatively, in a non - limiting aspect, based on the determination of the existence of an imbalance condition, the controller 226 may be configured to delay the first duration T1 of the first set of switches 210a by delaying or supplying the first command signal 251 to the first set of switches 210a at a time point later than the time point at which it would be supplied during a balanced charging condition, without changing the length of the first duration T1. The magnitude of the delay (e.g., time) may be based on or proportional to the magnitude of the difference between the first voltage V1 and the second voltage V2.

[0087] In addition, or alternatively, in a non - limiting aspect, based on the determination of the existence of an imbalance condition, the controller 226 may be configured to advance the second duration T2 of the second set of switches 210b by advancing or supplying the second command signal 254 to the second set of switches 210b at a time point earlier than the time point at which it would be supplied during a balanced charging condition, without changing the length of the second duration T2. The magnitude of the advance (e.g., time) may be based on or proportional to the magnitude of the difference between the first voltage V1 and the second voltage V2.

[0088] In other non - limiting aspects, based on the determination of the existence of an imbalance condition, the controller 226 may be configured to delay the second duration T2 of the second set of switches 210b by delaying or supplying the second command signal 254 to the second set of switches 210b at a time point later than the time point at which it would be supplied during a balanced charging condition, without changing the length of the second duration T2. The magnitude of the delay (e.g., time) may be based on or proportional to the magnitude of the difference between the first voltage V1 and the second voltage V2.

[0089] For example, in a case where an imbalance condition is determined based on the magnitude of a first voltage V1 that is greater than the magnitude of a second voltage V2, advancing or delaying the start of one of a first duration T1 or a second duration T2 may include advancing the first command signal 251 or delaying the second command signal 254, or both. Alternatively, in a case where an imbalance condition is determined based on the magnitude of a first voltage V1 that is less than the magnitude of a second voltage V2, advancing or delaying the start of one of the first or second durations T1, T2 includes delaying the first command signal 251 or advancing the second command signal 254, or both.

[0090] The sequences depicted are for illustrative purposes only and are not meant to limit method 700 in any way, as it should be understood that portions of the method may proceed in a different logical order, may include additional or intermediate portions, or the described portions of the method may be divided into multiple portions, or the described portions of the method may be omitted without detracting from the method.

[0091] For ranges that have not been described, the different features and structures of the various aspects may be used in combination with each other as needed. That a feature is not illustrated in all aspects does not mean it cannot be, but rather it is done for brevity of description. Thus, the various features of the different aspects may be mixed and matched as needed to form new aspects, whether or not the new aspects are explicitly described. Combinations or permutations of the features described herein are covered by this disclosure.

[0092] Additional aspects are provided by the subject matter of the following clauses:

[0093] A power converter, comprising: a first set of switches serially coupled to a second set of switches; a first capacitor arranged to receive current from the first set of switches; a second capacitor arranged to receive current from the second set of switches; and a controller communicatively coupled to the first set of switches and the second set of switches and configured to periodically command a first operation of the first set of switches to supply current to the first capacitor for a first duration and terminate the current to the first capacitor within a first interval, the controller further configured to periodically command a second operation of the second set of switches to supply current to the second capacitor for a second duration and terminate the current to the second capacitor within a second interval, the controller further configured to determine that an imbalance condition exists based on a comparison of a first voltage across the first capacitor and a second voltage across the second capacitor, and wherein when the imbalance condition exists, the controller is configured to do one of the following: advance or delay the start of one or both of the first duration or the second duration.

[0094] The power converter of any of the preceding clauses, wherein the first duration and the second duration are based on respective duty cycles of the first set of switches and the second set of switches.

[0095] A power converter according to any of the preceding clauses, wherein the controller commands a first operation based on a comparison of a first carrier signal with the respective duty cycles of a first set of switches, and further commands a second operation based on a comparison of a second carrier signal with the respective duty cycles of a second set of switches.

[0096] A power converter according to any of the preceding clauses, wherein when an imbalance condition exists, the controller is configured to do one of the following: advance or delay one or both of the first carrier signal and the second carrier signal such that the first carrier signal and the second carrier signal are asymmetric with respect to each other.

[0097] A power converter according to any of the preceding clauses, wherein the controller commands the first operation by supplying a first command signal to the first set of switches and commands the second operation by supplying a second command signal to the second set of switches.

[0098] A power converter according to any of the preceding clauses, wherein advancing or delaying the start of one or both of the first duration or the second duration is respectively based on advancing or delaying at least one of the first command signal or the second command signal.

[0099] A power converter according to any of the preceding clauses, further comprising a set of sensors communicatively coupled to the controller, the set of sensors being arranged to detect a first voltage across a first capacitor and a second voltage across a second capacitor, the set of sensors being configured to supply corresponding sensor signals to the controller indicating the magnitudes of the first voltage and the second voltage.

[0100] A power converter according to any of the preceding clauses, wherein the controller is configured to determine the magnitude of the first voltage and the magnitude of the second voltage based on the first corresponding sensor signal, determine the magnitude of the second voltage based on the corresponding sensor signal, and further determine that an imbalance condition exists based on the difference between the first voltage and the second voltage.

[0101] A power converter according to any of the preceding clauses, wherein the magnitude of the advance or delay of the start of one or both of the first duration or the second duration is proportional to the magnitude of the difference between the first voltage and the second voltage.

[0102] A power converter according to any of the preceding clauses, wherein when an imbalance condition is determined based on the magnitude of the first voltage being greater than the magnitude of the second voltage, the advance or delay of the start of one or both of the first duration or the second duration includes advancing the first command signal or delaying the second command signal, or both.

[0103] A power converter according to any of the preceding clauses, wherein, when determining an imbalance condition based on the magnitude of a first voltage that is less than the magnitude of a second voltage, an advancement or a delay of the start of one or both of the first duration or the second duration includes one of a delay of the first command signal or an advancement of the second command signal.

[0104] A method of operating a power converter, the power converter including a first set of switches serially coupled to a second set of switches, a first capacitor arranged to receive current from the first set of switches, and a second capacitor arranged to receive current from the second set of switches; the first set of switches and the second set of switches being communicatively coupled to a controller, the method including: periodically commanding, by the controller, a first operation of the first set of switches to supply current to the first capacitor for a first duration and terminate the current to the first capacitor within a first interval; periodically commanding, by the controller, a second operation of the second set of switches to supply current to the second capacitor for a second duration and subsequently terminate the current to the second capacitor within a second interval; determining, by the controller, that an imbalance condition exists based on a comparison of a first voltage across the first capacitor and a second voltage across the second capacitor; and when the imbalance condition exists, performing one of: advancing or delaying the start of one of the first duration or the second duration.

[0105] A method according to any of the preceding clauses, wherein the first duration and the second duration are based on the respective duty cycles of the first set of switches and the second set of switches.

[0106] A method according to any of the preceding clauses, wherein a set of sensors is communicatively coupled to the controller, the set of sensors being arranged to detect the first voltage across the first capacitor and the second voltage across the second capacitor, the set of sensors being configured to supply respective sensor signals indicative of the magnitude of the first voltage and the magnitude of the second voltage to the controller.

[0107] A method according to any of the preceding clauses, further including: determining, by the controller, the magnitude of the first voltage and the magnitude of the second voltage based on the respective sensor signals; wherein determining that an imbalance condition exists includes determining a difference between the first voltage and the second voltage.

[0108] A method according to any of the preceding clauses, wherein commanding the first operation includes the controller supplying a first command signal to the first set of switches, and wherein commanding the second operation includes the controller supplying a second command signal to the second set of switches.

[0109] A method according to any of the preceding clauses, wherein advancing or delaying one of the start of the first duration or the second duration includes one of advancing or delaying at least one of the first command signal or the second command signal, respectively.

[0110] A method according to any of the preceding clauses, wherein an amplitude of an advancement or a delay of at least one of the first command signal or the second command signal is proportional to an amplitude of a difference between the first voltage and the second voltage.

[0111] A method according to any of the preceding clauses, wherein when an imbalance condition is determined based on an amplitude of the first voltage that is greater than an amplitude of the second voltage, an advancement or a delay of a start of one of the first duration or the second duration includes one of a corresponding advancement of the first command signal or a delay of the second command signal.

[0112] A method according to any of the preceding clauses, wherein when an imbalance condition is determined based on an amplitude of the first voltage that is less than an amplitude of the second voltage, an advancement or a delay of a start of one of the first duration or the second duration includes one of a corresponding delay of the first command signal or an advancement of the second command signal.

[0113] As described herein, aspects of a power converter include a first set of switching elements and a second set of switching elements communicatively coupled to a first capacitor and a second capacitor. A controller is configured to periodically command a first operation of the first set of switches to supply current to the first capacitor for a first duration, followed by a first interval in which current to the first capacitor is terminated. The controller is further configured to periodically command a second operation of the second set of switches to supply current to the second capacitor for a second duration, followed by a second interval in which current to the second capacitor is terminated. The controller is further configured to determine that an imbalance condition exists based on a comparison of a first voltage across the first capacitor and a second voltage across the second capacitor. When the imbalance condition exists, the controller is configured to do one of the following: advance or delay a start of at least one of the first duration and the second duration.

[0114] Aspects disclosed herein provide a power converter and a control method to control the operation of switches based on a fixed ON duration while offsetting (e.g., advancing or delaying) the ON duration of the switches with respect to time to achieve a balanced charging condition. Compared to conventional power converters and control methods, aspects disclosed herein do not rely on the direction of the charging current Io. Additionally, aspects described herein enable the arrangement of a balancing operation (e.g., balanced voltage or balanced charging condition across upper and lower input capacitors C1, C2) without the need to determine the direction of the charging current Io, which enables balanced operation of the power converter even at very low power levels down to and including no-load operation.

Claims

1. A power converter, comprising: a first set of switches, the first set of switches being serially coupled to a second set of switches; a first capacitor, the first capacitor being arranged to receive current from the first set of switches; a second capacitor, the second capacitor being arranged to receive the current from the second set of switches; and a controller, the controller being communicatively coupled to the first set of switches and the second set of switches and being configured to periodically command a first operation of the first set of switches to supply the current to the first capacitor for a first duration and to terminate the current to the first capacitor within a first interval, the controller further being configured to periodically command a second operation of the second set of switches to supply the current to the second capacitor for a second duration and to terminate the current to the second capacitor within a second interval, the controller further being configured to determine that an imbalance condition exists based on a comparison of a first voltage across the first capacitor with a second voltage across the second capacitor, wherein, when the imbalance condition exists, the controller is configured to do one of the following: advance or delay the start of at least one of the first duration and the second duration.

2. The power converter according to claim 1, wherein, The first duration and the second duration are based on respective duty cycles of the first set of switches and the second set of switches.

3. The power converter according to claim 2, wherein, The controller commands the first operation based on a comparison of a first carrier signal with the respective duty cycle of the first set of switches and also commands the second operation based on a comparison of a second carrier signal with the respective duty cycle of the second set of switches.

4. The power converter according to claim 3, wherein, When the imbalance condition exists, the controller is configured to do one of the following: advance or delay one or both of the first carrier signal and the second carrier signal such that the first carrier signal and the second carrier signal are asymmetric with respect to each other.

5. The power converter according to claim 1, wherein, The controller commands the first operation by supplying a first command signal to the first set of switches and commands the second operation by supplying a second command signal to the second set of switches.

6. The power converter according to claim 5, wherein, Advancing or delaying one of the start of the first duration or the second duration or both is respectively based on an advance or delay of at least one of the first command signal or the second command signal.

7. A method of operating a power converter, the power converter including a first set of switches series-coupled with a second set of switches, a first capacitor arranged to receive a current from the first set of switches, and a second capacitor arranged to receive the current from the second set of switches; The first set of switches and the second set of switches are communicatively coupled to a controller, the method comprising: periodically commanding, by the controller, a first operation of the first set of switches to supply the current to the first capacitor for a first duration and to terminate the current to the first capacitor within a first interval; periodically commanding, by the controller, a second operation of the second set of switches to supply the current to the second capacitor for a second duration and subsequently to terminate the current to the second capacitor within a second interval; determining, by the controller, that an imbalance condition exists based on a comparison of a first voltage across the first capacitor with a second voltage across the second capacitor; and When an imbalance condition exists, perform one of the following: advance or delay the start of one of the first duration or the second duration.

8. The method according to claim 7, wherein The first duration and the second duration are based on the respective duty cycles of the first set of switches and the second set of switches.

9. The method according to claim 7, wherein A set of sensors is communicatively coupled to the controller, the set of sensors being arranged to detect the first voltage across the first capacitor and the second voltage across the second capacitor, the set of sensors being configured to supply respective sensor signals indicative of the magnitudes of the first voltage and the second voltage to the controller.

10. The method according to claim 9, further comprising: Determining, by the controller, the magnitudes of the first voltage and the second voltage based on the respective sensor signals; Among them, Determining that the imbalance condition exists includes determining a difference between the first voltage and the second voltage.

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