Gallium nitride power amplifier switching circuit

Abstract

The embodiment of the invention discloses a gallium nitride power amplifier switching circuit. Comprising the steps that an input matching network processes a radio frequency signal and a first voltage signal to obtain a first radio frequency signal; the first amplification unit processes the first radio frequency signal to obtain a second radio frequency signal; the first inter-stage matching network processes the second radio frequency signal, the first voltage signal and the second voltage signal to obtain a third radio frequency signal; the second amplification unit processes the third radio frequency signal to obtain a fourth radio frequency signal; the second inter-stage matching network processes the fourth radio frequency signal, the first voltage signal and the second voltage signal to obtain a fifth radio frequency signal; the third amplification unit processes the fifth radio frequency signal to obtain a sixth radio frequency signal; the output matching network receives the sixth radio frequency signal and the third voltage signal and processes the sixth radio frequency signal and the third voltage signal to obtain a seventh radio frequency signal; the switch circuit processes the seventh radio frequency signal, the fourth voltage signal, the fifth voltage signal and the sixth voltage signal to obtain an eighth radio frequency signal.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies. More specifically, it relates to a gallium nitride power amplifier switching circuit. Background Art

[0002] The gallium nitride (GaN) power amplifier switching circuit is an important part of the transceiver system. The power level and efficiency of the power amplifier switch have a great impact on the performance of the transceiver system. For traditional power amplifier switches, assembling appropriate power amplifier chips and switch chips is difficult to avoid disadvantages such as large size, high cost, and low efficiency. Summary of the Invention

[0003] An object of the present invention is to provide a gallium nitride power amplifier switching circuit to solve at least one of the problems existing in the prior art.

[0004] To achieve the above object, the present invention adopts the following technical solutions:

[0005] In a first aspect of the present invention, a gallium nitride power amplifier switching circuit is provided, and the circuit includes:

[0006] An input matching network unit for receiving a radio frequency signal and a first voltage signal and performing signal processing to obtain a first radio frequency signal;

[0007] A first amplification unit for receiving the first radio frequency signal and performing signal processing to obtain a second radio frequency signal;

[0008] A first inter-stage matching network unit for receiving the second radio frequency signal, the first voltage signal, and a second voltage signal and performing signal processing to obtain a third radio frequency signal;

[0009] A second amplification unit for receiving the third radio frequency signal and performing signal processing to obtain a fourth radio frequency signal;

[0010] A second inter-stage matching network unit for receiving the fourth radio frequency signal, the first voltage signal, and the second voltage signal and performing signal processing to obtain a fifth radio frequency signal;

[0011] A third amplification unit for receiving the fifth radio frequency signal and performing signal processing to obtain a sixth radio frequency signal;

[0012] An output matching network unit for receiving the sixth radio frequency signal and a third voltage signal and performing signal processing to obtain a seventh radio frequency signal;

[0013] A switching circuit unit for receiving the seventh radio frequency signal, a fourth voltage signal, a fifth voltage signal, and a sixth voltage signal and performing signal processing to obtain an eighth radio frequency signal.

[0014] Optionally, the first input end of the input matching network unit receives the radio frequency signal, the second input end of the input matching network unit receives the first voltage signal, and the output end of the input matching network unit is connected to the input end of the first amplification unit;

[0015] The output end of the first amplification unit is connected to the first input end of the first inter-stage matching network unit, and the grounding end of the first amplification unit is grounded;

[0016] The second input end of the first inter-stage matching network unit receives the first voltage signal, the third input end of the first inter-stage matching network unit receives the second voltage signal, and the output end of the first inter-stage matching network unit is connected to the input end of the second amplification unit;

[0017] The output end of the second amplification unit is connected to the first input end of the second inter-stage matching network unit, and the grounding end of the second amplification unit is grounded;

[0018] The second input end of the second inter-stage matching network unit receives the first voltage signal, the third input end of the second inter-stage matching network unit receives the second voltage signal, and the output end of the second inter-stage matching network unit is connected to the input end of the third amplification unit;

[0019] The output end of the third amplification unit is connected to the first input end of the output matching network unit, and the grounding end of the third amplification unit is grounded;

[0020] The second input end of the output matching network unit receives the third voltage signal, and the output end of the output matching network unit is connected to the first input end of the switch circuit unit;

[0021] The second input end of the switch circuit unit receives the fourth voltage signal, the third input end of the switch circuit unit receives the fifth voltage signal, the fourth input end of the switch circuit unit receives the sixth voltage signal, and the output end of the switch circuit unit outputs the eighth radio frequency signal.

[0022] Optionally, the input matching network unit includes:

[0023] The first end of the first capacitor is the first input end of the input matching network unit, and the second end of the first capacitor is connected to the first end of the first resistor, the first end of the second capacitor, and the first end of the first inductor;

[0024] The second end of the first resistor is connected to the second end of the second capacitor and serves as the output end of the input matching network unit;

[0025] The second end of the first inductor is connected to the first end of the second resistor;

[0026] The second terminal of the second resistor is connected to the first terminal of the third capacitor and serves as the second input terminal of the input matching network unit;

[0027] The second terminal of the third capacitor is grounded.

[0028] Optionally, the first amplification unit includes a first transistor;

[0029] The first pole of the first transistor is the input terminal of the first amplification unit;

[0030] The second pole of the first transistor is the output terminal of the first amplification unit;

[0031] The third pole of the first transistor is the ground terminal of the first amplification unit.

[0032] Optionally, the first inter-stage matching network unit includes:

[0033] The first terminal of the second inductor is the first input terminal of the first inter-stage matching network unit, and the second terminal of the second inductor is connected to the first terminal of the third inductor and the first terminal of the fourth capacitor;

[0034] The second terminal of the fourth capacitor is connected to the first terminal of the fourth inductor and the first terminal of the fifth inductor;

[0035] The second terminal of the fourth inductor is the output terminal of the first inter-stage matching network unit;

[0036] The second terminal of the fifth inductor is connected to the first terminal of the third resistor;

[0037] The second terminal of the third resistor is connected to the first terminal of the fifth capacitor and serves as the second input terminal of the first inter-stage matching network unit;

[0038] The second terminal of the fifth capacitor is grounded;

[0039] The second terminal of the third inductor is connected to the first terminal of the sixth capacitor and serves as the third input terminal of the first inter-stage matching network unit;

[0040] The second terminal of the sixth capacitor is grounded.

[0041] Optionally, the second amplification unit includes a second transistor;

[0042] The first pole of the second transistor is the input terminal of the second amplification unit;

[0043] The second pole of the second transistor is the output terminal of the second amplification unit;

[0044] The third pole of the second transistor is the ground terminal of the second amplification unit.

[0045] Optionally, the second inter-stage matching network unit includes:

[0046] The first end of the sixth inductor is the first input end of the second inter-stage matching network unit, and the second end of the sixth inductor is connected to the first end of the seventh inductor and the first end of the seventh capacitor;

[0047] The second end of the seventh capacitor is connected to the first end of the eighth inductor;

[0048] The second end of the eighth inductor is connected to the first end of the ninth inductor and the first end of the eighth capacitor;

[0049] The second end of the ninth inductor is grounded;

[0050] The second end of the eighth capacitor is connected to the first end of the ninth capacitor and the first end of the tenth inductor and serves as the output end of the second inter-stage matching network unit;

[0051] The second end of the ninth capacitor is grounded;

[0052] The second end of the tenth inductor is connected to the first end of the fourth resistor;

[0053] The second end of the fourth resistor is connected to the first end of the tenth capacitor and serves as the second input end of the second inter-stage matching network unit;

[0054] The second end of the tenth capacitor is grounded;

[0055] The second end of the seventh inductor is connected to the first end of the eleventh capacitor and serves as the third input end of the second inter-stage matching network unit;

[0056] The second end of the eleventh capacitor is grounded.

[0057] Optionally, the third amplification unit includes a third transistor;

[0058] The first pole of the third transistor is the input end of the third amplification unit;

[0059] The second pole of the third transistor is the output end of the third amplification unit;

[0060] The third pole of the third transistor is the ground end of the third amplification unit.

[0061] Optionally, the output matching network unit includes:

[0062] The first end of the eleventh inductor is the first input end of the output matching network unit;

[0063] The second end of the eleventh inductor is connected to the first end of the twelfth inductor and the first end of the twelfth capacitor;

[0064] The second terminal of the twelfth capacitor is the output terminal of the output matching network unit;

[0065] The second terminal of the twelfth inductor is connected to the first terminal of the thirteenth capacitor and serves as the second input terminal of the output matching network unit.

[0066] Optionally, the switch circuit unit includes:

[0067] The first terminal of the thirteenth inductor is the first input terminal of the switch circuit unit. The second terminal of the thirteenth inductor is connected to the second pole of the fourth transistor and the first terminal of the fourteenth inductor;

[0068] The first pole of the fourth transistor is connected to the first terminal of the fifth resistor, and the third pole of the fourth transistor is grounded;

[0069] The second terminal of the fifth resistor is the second input terminal of the switch circuit unit;

[0070] The first terminal of the fifteenth inductor is connected to the second terminal of the fourteenth inductor and serves as the output terminal of the switch circuit unit;

[0071] The second terminal of the fifteenth inductor is connected to the first terminal of the sixteenth inductor and the second pole of the fifth transistor;

[0072] The third pole of the fifth transistor is grounded. The first pole of the fifth transistor is connected to the first terminal of the sixth resistor, and the second terminal of the sixth resistor is the third input terminal of the switch circuit unit;

[0073] The second terminal of the sixteenth inductor is the fourth input terminal of the switch circuit unit.

[0074] The beneficial effects of the present invention are as follows:

[0075] In the technical solution of the present invention, the power amplifier circuit and the switch circuit are monolithically integrated by using the GaN HEMT process, so that the monolithic GaN power amplifier switch circuit has the advantages of small size, high power, high efficiency, good consistency, etc., and can further improve the performance of the transceiver system; due to the wide bandgap characteristic of the GaN material, the use of GaN monolithic integrated power amplifier switches can achieve high-power output and meet the requirements of system miniaturization and high performance; for every 0.1 dB reduction in the insertion loss of the power amplifier output matching circuit (including the switch circuit), the power added efficiency (PAE) can be increased by 1%. Monolithic integration of the power amplifier and the switch can rematch the interconnected part of the two, effectively improving the output power and the emission state efficiency; only by monolithic integrating the power amplifier and the switch, a lower-cost GaAs chip can be selected for the low-noise amplifier required in the receiving state, achieving a double improvement in the performance and cost of the whole machine. Description of the Drawings

[0076] The following further details the specific embodiments of the present invention in conjunction with the drawings.

[0077] Figure 1 The schematic diagram of the GaN power amplifier switch circuit provided by the embodiment of the present invention is shown.

[0078] Figure 2 The schematic diagram of the comparison of the simulation results of the improvement of the circuit performance by the re-matching circuit of the GaN power amplifier switch circuit provided by the embodiment of the present invention is shown.

[0079] Figure 3 The schematic diagram of the simulation results of the S-parameters in the transmitting state of the GaN power amplifier switch circuit provided by the embodiment of the present invention is shown.

[0080] Figure 4 The schematic diagram of the simulation results of the output power and power added efficiency in the transmitting state of the GaN power amplifier switch circuit provided by the embodiment of the present invention is shown.

[0081] Figure 5 The schematic diagram of the simulation results of the S-parameters in the receiving state of the GaN power amplifier switch circuit provided by the embodiment of the present invention is shown. Detailed implementation manners

[0082] In order to illustrate the present invention more clearly, the present invention will be further described below in conjunction with embodiments and drawings. Similar components in the drawings are denoted by the same reference numerals. Those skilled in the art should understand that the content specifically described below is illustrative rather than restrictive, and should not be used to limit the protection scope of the present invention.

[0083] The GaN (Gallium Nitride) power amplifier switch circuit is an important part of the transceiver system. The power level and efficiency of the power amplifier switch have a great impact on the performance of the transceiver system. For traditional power amplifier switches, assembling appropriate power amplifier chips and switch chips is difficult to avoid disadvantages such as large size, high cost, and low efficiency.

[0084] In view of this, as Figure 1As shown in the figure, an embodiment of the present invention provides a GaN power amplifier switching circuit, which includes: an input matching network unit for receiving a radio frequency signal and a first voltage signal and performing signal processing to obtain a first radio frequency signal; a first amplification unit for receiving the first radio frequency signal and performing signal processing to obtain a second radio frequency signal; a first inter-stage matching network unit for receiving the second radio frequency signal, the first voltage signal and a second voltage signal and performing signal processing to obtain a third radio frequency signal; a second amplification unit for receiving the third radio frequency signal and performing signal processing to obtain a fourth radio frequency signal; a second inter-stage matching network unit for receiving the fourth radio frequency signal, the first voltage signal and the second voltage signal and performing signal processing to obtain a fifth radio frequency signal; a third amplification unit for receiving the fifth radio frequency signal and performing signal processing to obtain a sixth radio frequency signal; an output matching network unit for receiving the sixth radio frequency signal and a third voltage signal and performing signal processing to obtain a seventh radio frequency signal; and a switching circuit unit for receiving the seventh radio frequency signal, a fourth voltage signal, a fifth voltage signal and a sixth voltage signal and performing signal processing to obtain an eighth radio frequency signal.

[0085] In a specific example, the GaN power amplifier switching circuit includes an input matching network, a first transistor M1, an inter-stage matching network 1, a second transistor M2, an inter-stage matching network 2, a third transistor M3, an output matching network, and a switching circuit, which are sequentially connected between a signal input terminal PA_in and a signal output terminal SW_COM.

[0086] This embodiment uses the GaN HEMT process to monolithically integrate the power amplifier circuit and the switching circuit, enabling the monolithic GaN power amplifier switching circuit to have advantages such as small size, high power, high efficiency, and good consistency, which can further improve the system performance. Due to the wide bandgap characteristic of the GaN material, using a GaN monolithic integrated power amplifier switch can achieve high-power output and meet the requirements of system miniaturization and high performance. Generally, for every 0.1 dB reduction in the insertion loss of the power amplifier output matching circuit (including the switching circuit), the power added efficiency (PAE) can be increased by 1%. Monolithically integrating the power amplifier and the switch can rematch the interconnected part of the two, effectively improving the output power and the emission state efficiency. At the same time, by only monolithically integrating the power amplifier and the switch, a lower-cost GaAs chip can be selected for the low-noise amplifier required in the receive state, achieving a dual improvement in the overall machine performance and cost.

[0087] In a possible implementation, the first input end of the input matching network unit receives the radio frequency signal, the second input end of the input matching network unit receives the first voltage signal, and the output end of the input matching network unit is connected to the input end of the first amplification unit; the output end of the first amplification unit is connected to the first input end of the first inter-stage matching network unit, and the grounding end of the first amplification unit is grounded; the second input end of the first inter-stage matching network unit receives the first voltage signal, the third input end of the first inter-stage matching network unit receives the second voltage signal, and the output end of the first inter-stage matching network unit is connected to the input end of the second amplification unit; the output end of the second amplification unit is connected to the first input end of the second inter-stage matching network unit, and the grounding end of the second amplification unit is grounded; the second input end of the second inter-stage matching network unit receives the first voltage signal, the third input end of the second inter-stage matching network unit receives the second voltage signal, and the output end of the second inter-stage matching network unit is connected to the input end of the third amplification unit; the output end of the third amplification unit is connected to the first input end of the output matching network unit, and the grounding end of the third amplification unit is grounded; the second input end of the output matching network unit receives the third voltage signal, and the output end of the output matching network unit is connected to the first input end of the switch circuit unit; the second input end of the switch circuit unit receives the fourth voltage signal, the third input end of the switch circuit unit receives the fifth voltage signal, the fourth input end of the switch circuit unit receives the sixth voltage signal, and the output end of the switch circuit unit outputs the eighth radio frequency signal.

[0088] In a specific example, the GaN power amplifier switch circuit includes three cascaded common-source amplifier circuits and a switch circuit. The input end of the amplifier circuit adopts a parallel RC structure to increase stability, and the output end of the amplifier circuit and the input end of the switch circuit are rematched to improve the overall efficiency of the circuit. The GaN power amplifier switch circuit has characteristics such as high gain, high power, high flatness, and high efficiency, and can be used in X-band transceiver systems.

[0089] In a possible implementation, the input matching network unit includes: the first end of the first capacitor C1 is the first input end of the input matching network unit, the second end of the first capacitor C1 is connected to the first end of the first resistor R1, the first end of the second capacitor C2, and the first end of the first inductor GL1; the second end of the first resistor R1 is connected to the second end of the second capacitor C2 and serves as the output end of the input matching network unit; the second end of the first inductor GL1 is connected to the first end of the second resistor GR1; the second end of the second resistor GR1 is connected to the first end of the third capacitor GC1 and serves as the second input end of the input matching network unit; the second end of the third capacitor GC1 is grounded.

[0090] In a specific example, the input matching network includes a series-connected capacitor C1, a series-connected capacitor C2, a series-connected resistor R1, a series-connected gate bias inductor GL1, a series-connected gate bias resistor GR1, and a gate bias capacitor GC1 connected to ground in parallel. The input terminal of capacitor C1 is connected to the signal input terminal PA_in. The output terminal of capacitor C1 is connected to the input terminal of capacitor C2. The output terminal of capacitor C2 is connected to the gate of transistor M1. The input terminal of resistor R1 is connected to the input terminal of capacitor C2. The output terminal of resistor R1 is connected to the output terminal of capacitor C2. The input terminal of gate bias inductor GL1 is connected to the output terminal of capacitor C1. The output terminal of gate bias inductor GL1 is connected to the input terminal of gate bias resistor GR1. The output terminal of gate bias resistor GR1 is connected to the input terminal of gate bias capacitor GC1. The output terminal of gate bias capacitor GC1 is connected to ground. The input terminal of gate bias capacitor GC1 is connected to the gate bias voltage VG;

[0091] In this embodiment, the series-connected resistor R1 can reduce the DC supply voltage, thereby improving the circuit stability. The capacitor C2 connected in parallel with the resistor R1 functions as a filter and allows RF signals to pass through. The combined action of the two can improve the circuit stability without degrading the RF characteristics of the circuit.

[0092] In a possible implementation, the first amplification unit includes a first transistor M1; the first pole of the first transistor M1 is the input terminal of the first amplification unit; the second pole of the first transistor M1 is the output terminal of the first amplification unit; the third pole of the first transistor M1 is the ground terminal of the first amplification unit.

[0093] In a specific example, the gate of the first transistor M1 is connected to the output terminal of capacitor C2, the drain of the first transistor M1 is connected to the input terminal of inductor L1, and the source of the first transistor M1 is connected to ground.

[0094] In a possible implementation, the first inter-stage matching network unit includes: the first end of the second inductor L1 is the first input terminal of the first inter-stage matching network unit, the second end of the second inductor L1 is connected to the first end of the third inductor DL1 and the first end of the fourth capacitor C3; the second end of the fourth capacitor C3 is connected to the first end of the fourth inductor L2 and the first end of the fifth inductor GL2; the second end of the fourth inductor L2 is the output terminal of the first inter-stage matching network unit; the second end of the fifth inductor GL2 is connected to the first end of the third resistor GR2; the second end of the third resistor GR2 is connected to the first end of the fifth capacitor GC2 and serves as the second input terminal of the first inter-stage matching network unit; the second end of the fifth capacitor GC2 is grounded; the second end of the third inductor DL1 is connected to the first end of the sixth capacitor DC1 and serves as the third input terminal of the first inter-stage matching network unit; the second end of the sixth capacitor DC1 is grounded.

[0095] In a specific example, the inter-stage matching network 1 includes an inductor L1 connected in series, a capacitor C3 connected in series, an inductor L2 connected in series, a drain bias inductor DL1 connected in series, a drain bias capacitor DC1 connected to ground in parallel, a gate bias inductor GL2 connected in series, a gate bias resistor GR2 connected in series, a gate bias capacitor GC2 connected to ground in parallel. The input end of the inductor L1 is connected to the drain of the first transistor M1, the output end of the inductor L1 is connected to the input end of the capacitor C3, the output end of the capacitor C3 is connected to the input end of the inductor L2, the output end of the inductor L2 is connected to the gate of the transistor M2, the input end of the drain bias inductor DL1 is connected to the output end of the inductor L1, the output end of the drain bias inductor DL1 is connected to the input end of the drain bias capacitor DC1, the output end of the drain bias capacitor DC1 is connected to ground, the input end of the drain bias capacitor DC1 is connected to the drain bias voltage VD1, the input end of the gate bias inductor GL2 is connected to the output end of the capacitor C3, the output end of the gate bias inductor GL2 is connected to the input end of the gate bias resistor GR2, the output end of the gate bias resistor GR2 is connected to the input end of the gate bias capacitor GC2, the output end of the gate bias capacitor GC2 is connected to ground, and the input end of the gate bias capacitor GC2 is connected to the gate bias voltage VG;

[0096] In this embodiment, the capacitor C3 has the function of matching and filtering, avoiding the crosstalk between the drain bias voltage of the first transistor M1 and the gate bias voltage of the second transistor M2. The inductor L1 and the inductor L2 can be replaced by long wire microstrip lines, and using wire-wound inductors can effectively reduce the circuit area. Other inductors in the circuit also have similar functions;

[0097] In a possible implementation manner, the second amplification unit includes a second transistor M2; the first pole of the second transistor M2 is the input end of the second amplification unit; the second pole of the second transistor M2 is the output end of the second amplification unit; and the third pole of the second transistor M2 is the ground end of the second amplification unit.

[0098] In a specific example, the gate of the second transistor M2 is connected to the output end of the inductor L2, the drain of the second transistor M2 is connected to the input end of the inductor L3, and the source of the second transistor M2 is connected to ground;

[0099] In a possible implementation, the second inter-stage matching network unit includes: the first end of a sixth inductor L3 is the first input end of the second inter-stage matching network unit, and the second end of the sixth inductor L3 is connected to the first end of a seventh inductor DL2 and the first end of a seventh capacitor C4; the second end of the seventh capacitor C4 is connected to the first end of an eighth inductor L4; the second end of the eighth inductor L4 is connected to the first end of a ninth inductor L5 and the first end of an eighth capacitor C5; the second end of the ninth inductor L5 is grounded; the second end of the eighth capacitor C5 is connected to the first end of a ninth capacitor C6 and the first end of a tenth inductor GL3 and serves as the output end of the second inter-stage matching network unit; the second end of the ninth capacitor C6 is grounded; the second end of the tenth inductor GL3 is connected to the first end of a fourth resistor GR3; the second end of the fourth resistor GR3 is connected to the first end of a tenth capacitor GC3 and serves as the second input end of the second inter-stage matching network unit; the second end of the tenth capacitor GC3 is grounded; the second end of the seventh inductor DL2 is connected to the first end of an eleventh capacitor DC2 and serves as the third input end of the second inter-stage matching network unit; the second end of the eleventh capacitor DC2 is grounded.

[0100] In a specific example, the inter-stage matching network 2 includes a series inductor L3, a series capacitor C4, a series inductor L4, a shunt-grounded inductor L5, a series capacitor C5, a shunt-grounded capacitor C6, a series drain bias inductor DL2, a shunt-grounded drain bias capacitor DC2, a series gate bias inductor GL3, a series gate bias resistor GR3, and a shunt-grounded gate bias capacitor GC3. The input end of the inductor L3 is connected to the drain of the second transistor M2, the output end of the inductor L3 is connected to the input end of the capacitor C4, the output end of the capacitor C4 is connected to the input end of the inductor L4, the output end of the inductor L4 is connected to the input end of the inductor L5, the output end of the inductor L5 is grounded, the input end of the inductor L5 is connected to the input end of the capacitor C5, the output end of the capacitor C5 is connected to the input end of the capacitor C6, the output end of the capacitor C6 is grounded, the input end of the capacitor C6 is connected to the gate of the third transistor M3, the input end of the drain bias inductor DL2 is connected to the output end of the inductor L3, the output end of the drain bias inductor DL2 is connected to the input end of the drain bias capacitor DC2, the output end of the drain bias capacitor DC2 is grounded, the input end of the drain bias capacitor DC2 is connected to the drain bias voltage VD1, the input end of the gate bias inductor GL3 is connected to the output end of the capacitor C5, the output end of the gate bias inductor GL32 is connected to the input end of the gate bias resistor GR3, the output end of the gate bias resistor GR3 is connected to the input end of the gate bias capacitor GC3, the output end of the gate bias capacitor GC3 is grounded, and the input end of the gate bias capacitor GC3 is connected to the gate bias voltage VG;

[0101] In this embodiment, the inductor L5 and the capacitor C6 play a major filtering and matching role, which can greatly improve the gain flatness. A capacitor C5 is added between the inductor L5 and the capacitor C6 for filtering to prevent the gate bias voltage of the third transistor M3 from directly grounding through the inductor L5.

[0102] In a possible implementation, the third amplification unit includes a third transistor M3; the first pole of the third transistor M3 is the input end of the third amplification unit; the second pole of the third transistor M3 is the output end of the third amplification unit; the third pole of the third transistor M3 is the grounding end of the third amplification unit.

[0103] In a specific example, the gate of the third transistor M3 is connected to the input end of the capacitor C6, the drain of the third transistor M3 is connected to the input end of the inductor L6, and the source of the third transistor M3 is connected to the ground.

[0104] In a possible implementation, the output matching network unit includes: the first end of the eleventh inductor L6 is the first input end of the output matching network unit; the second end of the eleventh inductor L6 is connected to the first end of the twelfth inductor DL3 and the first end of the twelfth capacitor C7; the second end of the twelfth capacitor C7 is the output end of the output matching network unit; the second end of the twelfth inductor DL3 is connected to the first end of the thirteenth capacitor DC3 and serves as the second input end of the output matching network unit.

[0105] In a specific example, the output matching network includes a series-connected inductor L6, a series-connected capacitor C7, a series-connected drain bias inductor DL3, and a drain bias capacitor DC3 connected in parallel to the ground. The input end of the inductor L6 is connected to the drain of the third transistor M3, the output end of the inductor L6 is connected to the input end of the capacitor C7, the output end of the capacitor C7 is connected to the input end of the inductor L7, the input end of the drain bias inductor DL3 is connected to the output end of the inductor L6, the output end of the drain bias inductor DL3 is connected to the input end of the drain bias capacitor DC3, the output end of the drain bias capacitor DC3 is connected to the ground, and the input end of the drain bias capacitor DC3 is connected to the drain bias voltage VD2.

[0106] Furthermore, the inductor L7 is a part of the conduction path of the switching circuit, and a re-matching network is formed by the inductor L6, the capacitor C7, the drain bias inductor DL3 in the output matching network and the inductor L7 in the switching circuit.

[0107] This embodiment optimizes the design of this re-matching network, which can effectively improve the matching characteristics between the amplification circuit and the switching circuit, reduce the final-stage insertion loss, and thus improve the output power and efficiency of the power amplifier switching circuit. The improvement effect of the re-matching network on the circuit is as Figure 2 shown.

[0108] In a possible implementation, the switch circuit unit includes: the first end of the thirteenth inductor L7 is the first input end of the switch circuit unit, the second end of the thirteenth inductor L7 is connected to the second pole of the fourth transistor SM1 and the first end of the fourteenth inductor L8; the first pole of the fourth transistor SM1 is connected to the first end of the fifth resistor R2, and the third pole of the fourth transistor SM1 is grounded; the second end of the fifth resistor R2 is the second input end of the switch circuit unit; the first end of the fifteenth inductor L9 is connected to the second end of the fourteenth inductor L8 and serves as the output end of the switch circuit unit; the second end of the fifteenth inductor L9 is connected to the first end of the sixteenth inductor L10 and the second pole of the fifth transistor SM2; the third pole of the fifth transistor SM2 is grounded, the first pole of the fifth transistor SM2 is connected to the first end of the sixth resistor R3, and the second end of the sixth resistor R3 is the third input end of the switch circuit unit; the second end of the sixteenth inductor L10 is the fourth input end of the switch circuit unit.

[0109] In a specific example, the switch circuit includes a series of inductor L7, a series of inductor L8, a series of inductor L9, a series of inductor L10, a parallel first switching transistor (i.e., the fourth transistor) SM1, a parallel second switching transistor (i.e., the fifth transistor) SM2, a series of resistor R2, a series of resistor R3. The input end of inductor L7 is connected to the output end of capacitor C7, the output end of inductor L7 is connected to the input end of inductor L8, the output end of inductor L8 is connected to the input end of inductor L9, the output end of inductor L9 is connected to the input end of inductor L10, the drain of the first switching transistor SM1 is connected to the output end of inductor L7, the source of the first switching transistor SM1 is connected to the ground, the gate of the first switching transistor SM1 is connected to the input end of resistor R2, the output end of resistor R2 is connected to the control port SW1, the drain of the second switching transistor SM2 is connected to the output end of inductor L9, the source of the second switching transistor SM2 is connected to the ground, the gate of the second switching transistor SM2 is connected to the input end of resistor R3, the output end of resistor R3 is connected to the control port SW2, the output end of inductor L8 is connected to the signal output end SW_COM, and the output end of inductor L10 is connected to the switch cut-off state port LNA_in; wherein, due to the influence of the re-matching network optimization, inductor L7 and inductor L10 are not equal.

[0110] In a specific example, the simulation results of the improvement of the circuit performance by the re-matching circuit of the gallium nitride power amplifier switch circuit are compared as Figure 2 shown. In the range of 7 - 13 GHz, the maximum insertion loss of the re-matching circuit can be improved by 1.1 dB;

[0111] In a specific example, the simulation results of the S parameters in the transmitting state of the gallium nitride power amplifier switch circuit are as Figure 3As shown, the maximum gain is 34.8 dB, the 3 dB bandwidth is 8.5 - 10.9 GHz. In the range of 7 - 13 GHz, the input reflection coefficient (PA_in port) is less than -15 dB, the output reflection coefficient (SW_COM port) is less than -5 dB, and the switch forward transmission coefficient (LNA_in to SW_COM) is approximately -1.1 dB;

[0112] In a specific example, the simulation results of the output power and power added efficiency of the gallium nitride power amplifier switch circuit in the transmit state are as Figure 4 shown. In the range of 8.5 - 10.5 GHz, the output power is 34.9 ± 0.1 dBm, the power gain is greater than 27 dB, and the power added efficiency is greater than 41%;

[0113] In a specific example, the simulation results of the S parameters of the gallium nitride power amplifier switch circuit in the receive state are as Figure 5 shown. In the range of 8 - 13 GHz, the maximum insertion loss is 1.0 dB, the minimum insertion loss is 0.8 dB, and both the output reflection coefficient (SW_COM port) and the switch forward transmission coefficient [LNA_in to SW_COM] are less than -15 dB.

[0114] In summary, the present invention monolithically integrates the power amplifier circuit and the switch circuit using GaN HEMT technology to realize a monolithic GaN power amplifier switch circuit, which has the advantages of small size, high power, high efficiency, and good consistency, and can further improve the performance of the transceiver system. Due to the wide bandgap characteristic of GaN material, using a monolithic integrated GaN power amplifier switch can achieve high-power output and meet the requirements of system miniaturization and high performance. Generally, for every 0.1 dB reduction in the insertion loss of the power amplifier output matching circuit (including the switch circuit), the power added efficiency PAE can be increased by 1%. Monolithically integrating the power amplifier and the switch can rematch the interconnected part of the two, effectively improving the output power and the transmit state efficiency. At the same time, only by monolithically integrating the power amplifier and the switch, a lower-cost GaAs chip can be selected for the low-noise amplifier required in the receive state to achieve a double improvement in the performance and cost of the whole machine.

[0115] In the description of the present application, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0116] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, rather than limitations on the implementation manners of the present invention. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. It is impossible to enumerate all implementation manners here. Any obvious changes or variations derived from the technical solutions of the present invention still fall within the protection scope of the present invention.

Claims

1. A gallium nitride power amplifier switching circuit, characterized in that The circuit includes: An input matching network unit for receiving a radio frequency signal and a first voltage signal and performing signal processing to obtain a first radio frequency signal; A first amplification unit for receiving the first radio frequency signal and performing signal processing to obtain a second radio frequency signal; A first inter-stage matching network unit for receiving the second radio frequency signal, the first voltage signal and a second voltage signal and performing signal processing to obtain a third radio frequency signal; A second amplification unit for receiving the third radio frequency signal and performing signal processing to obtain a fourth radio frequency signal; A second inter-stage matching network unit for receiving the fourth radio frequency signal, the first voltage signal and the second voltage signal and performing signal processing to obtain a fifth radio frequency signal; A third amplification unit for receiving the fifth radio frequency signal and performing signal processing to obtain a sixth radio frequency signal; An output matching network unit for receiving the sixth radio frequency signal and a third voltage signal and performing signal processing to obtain a seventh radio frequency signal; A switch circuit unit for receiving the seventh radio frequency signal, a fourth voltage signal, a fifth voltage signal and a sixth voltage signal and performing signal processing to obtain an eighth radio frequency signal.

2. The gallium nitride power amplifier switch circuit according to claim 1, wherein The first input end of the input matching network unit receives the radio frequency signal, the second input end of the input matching network unit receives the first voltage signal, and the output end of the input matching network unit is connected to the input end of the first amplification unit; The output end of the first amplification unit is connected to the first input end of the first inter-stage matching network unit, and the grounding end of the first amplification unit is grounded; The second input end of the first inter-stage matching network unit receives the first voltage signal, the third input end of the first inter-stage matching network unit receives the second voltage signal, and the output end of the first inter-stage matching network unit is connected to the input end of the second amplification unit; The output end of the second amplification unit is connected to the first input end of the second inter-stage matching network unit, and the grounding end of the second amplification unit is grounded; The second input end of the second inter-stage matching network unit receives the first voltage signal, the third input end of the second inter-stage matching network unit receives the second voltage signal, and the output end of the second inter-stage matching network unit is connected to the input end of the third amplification unit; The output end of the third amplification unit is connected to the first input end of the output matching network unit, and the grounding end of the third amplification unit is grounded; The second input end of the output matching network unit receives the third voltage signal, and the output end of the output matching network unit is connected to the first input end of the switch circuit unit; The second input end of the switch circuit unit receives the fourth voltage signal, the third input end of the switch circuit unit receives the fifth voltage signal, the fourth input end of the switch circuit unit receives the sixth voltage signal, and the output end of the switch circuit unit outputs the eighth radio frequency signal.

3. The gallium nitride power amplifier switch circuit according to claim 2, wherein The input matching network unit includes: The first end of the first capacitor is the first input end of the input matching network unit, and the second end of the first capacitor is connected to the first end of the first resistor, the first end of the second capacitor, and the first end of the first inductor; The second end of the first resistor is connected to the second end of the second capacitor and serves as the output end of the input matching network unit; The second end of the first inductor is connected to the first end of the second resistor; The second end of the second resistor is connected to the first end of the third capacitor and serves as the second input end of the input matching network unit; The second end of the third capacitor is grounded.

4. The gallium nitride power amplifier switching circuit according to claim 3, wherein The first amplifying unit includes a first transistor; The first pole of the first transistor is the input end of the first amplifying unit; The second pole of the first transistor is the output end of the first amplifying unit; The third pole of the first transistor is the grounding end of the first amplifying unit.

5. The gallium nitride power amplifier switching circuit according to claim 4, wherein The first inter-stage matching network unit includes: The first end of the second inductor is the first input end of the first inter-stage matching network unit, and the second end of the second inductor is connected to the first end of the third inductor and the first end of the fourth capacitor; The second end of the fourth capacitor is connected to the first end of the fourth inductor and the first end of the fifth inductor; The second end of the fourth inductor is the output end of the first inter-stage matching network unit; The second end of the fifth inductor is connected to the first end of the third resistor; The second end of the third resistor is connected to the first end of the fifth capacitor and serves as the second input end of the first inter-stage matching network unit; The second end of the fifth capacitor is grounded; The second end of the third inductor is connected to the first end of the sixth capacitor and serves as the third input end of the first inter-stage matching network unit; The second end of the sixth capacitor is grounded.

6. The gallium nitride power amplifier switching circuit according to claim 5, wherein The second amplifying unit includes a second transistor; The first pole of the second transistor is the input end of the second amplifying unit; The second pole of the second transistor is the output end of the second amplifying unit; The third pole of the second transistor is the grounding end of the second amplifying unit.

7. The gallium nitride power amplifier switching circuit according to claim 6, characterized in that, The second inter-stage matching network unit includes: The first end of the sixth inductor is the first input end of the second inter-stage matching network unit, and the second end of the sixth inductor is connected to the first end of the seventh inductor and the first end of the seventh capacitor; The second end of the seventh capacitor is connected to the first end of the eighth inductor; The second end of the eighth inductor is connected to the first end of the ninth inductor and the first end of the eighth capacitor; The second end of the ninth inductor is grounded; The second end of the eighth capacitor is connected to the first end of the ninth capacitor and the first end of the tenth inductor and serves as the output end of the second inter-stage matching network unit; The second end of the ninth capacitor is grounded; The second end of the tenth inductor is connected to the first end of the fourth resistor; The second end of the fourth resistor is connected to the first end of the tenth capacitor and serves as the second input end of the second inter-stage matching network unit; The second end of the tenth capacitor is grounded; The second end of the seventh inductor is connected to the first end of the eleventh capacitor and serves as the third input end of the second inter-stage matching network unit; The second end of the eleventh capacitor is grounded.

8. The gallium nitride power amplifier switching circuit according to claim 7, characterized in that, The third amplifying unit includes a third transistor; The first pole of the third transistor is the input end of the third amplifying unit; The second pole of the third transistor is the output end of the third amplifying unit; The third pole of the third transistor is the grounding end of the third amplifying unit.

9. The gallium nitride power amplifier switching circuit according to claim 8, characterized in that The output matching network unit includes: The first end of the eleventh inductor is the first input end of the output matching network unit; The second end of the eleventh inductor is connected to the first end of the twelfth inductor and the first end of the twelfth capacitor; The second end of the twelfth capacitor is the output end of the output matching network unit; The second end of the twelfth inductor is connected to the first end of the thirteenth capacitor and serves as the second input end of the output matching network unit.

10. The gallium nitride power amplifier switching circuit according to claim 9, wherein, The switch circuit unit includes: The first end of the thirteenth inductor is the first input end of the switch circuit unit, and the second end of the thirteenth inductor is connected to the second pole of the fourth transistor and the first end of the fourteenth inductor; The first pole of the fourth transistor is connected to the first end of the fifth resistor, and the third pole of the fourth transistor is grounded; The second end of the fifth resistor is the second input end of the switch circuit unit; The first end of the fifteenth inductor is connected to the second end of the fourteenth inductor and serves as the output end of the switch circuit unit; The second end of the fifteenth inductor is connected to the first end of the sixteenth inductor and the second pole of the fifth transistor; The third pole of the fifth transistor is grounded, the first pole of the fifth transistor is connected to the first end of the sixth resistor, and the second end of the sixth resistor is the third input end of the switch circuit unit; The second end of the sixteenth inductor is the fourth input end of the switch circuit unit.

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